1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2021 Intel Corporation
4 #ifndef _RTE_IDXD_RAWDEV_FNS_H_
5 #define _RTE_IDXD_RAWDEV_FNS_H_
9 * This header file contains the implementation of the various ioat
10 * rawdev functions for DSA hardware. The API specification and key
11 * public structures are defined in "rte_ioat_rawdev.h".
13 * This file should not be included directly, but instead applications should
14 * include "rte_ioat_rawdev.h", which then includes this file - and the
15 * IOAT/CBDMA equivalent header - in turn.
21 * Defines used in the data path for interacting with IDXD hardware.
23 #define IDXD_CMD_OP_SHIFT 24
32 #define IDXD_FLAG_FENCE (1 << 0)
33 #define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2)
34 #define IDXD_FLAG_REQUEST_COMPLETION (1 << 3)
35 #define IDXD_FLAG_CACHE_CONTROL (1 << 8)
37 #define IOAT_COMP_UPDATE_SHIFT 3
38 #define IOAT_CMD_OP_SHIFT 24
40 ioat_op_copy = 0, /* Standard DMA Operation */
41 ioat_op_fill /* Block Fill */
45 * Hardware descriptor used by DSA hardware, for both bursts and
46 * for individual operations.
48 struct rte_idxd_hw_desc {
51 rte_iova_t completion;
55 rte_iova_t src; /* source address for copy ops etc. */
56 rte_iova_t desc_addr; /* descriptor pointer for batch */
60 uint32_t size; /* length of data for op, or batch size */
62 uint16_t intr_handle; /* completion interrupt handle */
64 /* remaining 26 bytes are reserved */
65 uint16_t __reserved[13];
69 * Completion record structure written back by DSA
71 struct rte_idxd_completion {
74 /* 16-bits pad here */
75 uint32_t completed_size; /* data length, or descriptors for batch */
77 rte_iova_t fault_address;
78 uint32_t invalid_flags;
82 * structure used to save the "handles" provided by the user to be
83 * returned to the user on job completion.
85 struct rte_idxd_user_hdl {
92 * Structure representing an IDXD device instance
94 struct rte_idxd_rawdev {
95 enum rte_ioat_dev_type type;
96 struct rte_ioat_xstats xstats;
98 void *portal; /* address to write the batch descriptor */
100 struct rte_ioat_rawdev_config cfg;
101 rte_iova_t desc_iova; /* base address of desc ring, needed for completions */
103 /* counters to track the batches */
104 unsigned short max_batches;
105 unsigned short batch_idx_read;
106 unsigned short batch_idx_write;
107 unsigned short *batch_idx_ring; /* store where each batch ends */
109 /* track descriptors and handles */
110 unsigned short desc_ring_mask;
111 unsigned short hdls_avail; /* handles for ops completed */
112 unsigned short hdls_read; /* the read pointer for hdls/desc rings */
113 unsigned short batch_start; /* start+size == write pointer for hdls/desc */
114 unsigned short batch_size;
116 struct rte_idxd_hw_desc *desc_ring;
117 struct rte_idxd_user_hdl *hdl_ring;
118 /* flags to indicate handle validity. Kept separate from ring, to avoid
119 * using 8 bytes per flag. Upper 8 bits holds error code if any.
121 uint16_t *hdl_ring_flags;
124 #define RTE_IDXD_HDL_NORMAL 0
125 #define RTE_IDXD_HDL_INVALID (1 << 0) /* no handle stored for this element */
126 #define RTE_IDXD_HDL_OP_FAILED (1 << 1) /* return failure for this one */
127 #define RTE_IDXD_HDL_OP_SKIPPED (1 << 2) /* this op was skipped */
129 static __rte_always_inline uint16_t
130 __idxd_burst_capacity(int dev_id)
132 struct rte_idxd_rawdev *idxd =
133 (struct rte_idxd_rawdev *)rte_rawdevs[dev_id].dev_private;
134 uint16_t write_idx = idxd->batch_start + idxd->batch_size;
137 /* Check for space in the batch ring */
138 if ((idxd->batch_idx_read == 0 && idxd->batch_idx_write == idxd->max_batches) ||
139 idxd->batch_idx_write + 1 == idxd->batch_idx_read)
142 /* for descriptors, check for wrap-around on write but not read */
143 if (idxd->hdls_read > write_idx)
144 write_idx += idxd->desc_ring_mask + 1;
145 used_space = write_idx - idxd->hdls_read;
147 /* Return amount of free space in the descriptor ring
148 * subtract 1 for space for batch descriptor and 1 for possible null desc
150 return idxd->desc_ring_mask - used_space - 2;
153 static __rte_always_inline rte_iova_t
154 __desc_idx_to_iova(struct rte_idxd_rawdev *idxd, uint16_t n)
156 return idxd->desc_iova + (n * sizeof(struct rte_idxd_hw_desc));
159 static __rte_always_inline int
160 __idxd_write_desc(int dev_id,
161 const uint32_t op_flags,
162 const rte_iova_t src,
163 const rte_iova_t dst,
165 const struct rte_idxd_user_hdl *hdl)
167 struct rte_idxd_rawdev *idxd =
168 (struct rte_idxd_rawdev *)rte_rawdevs[dev_id].dev_private;
169 uint16_t write_idx = idxd->batch_start + idxd->batch_size;
170 uint16_t mask = idxd->desc_ring_mask;
172 /* first check batch ring space then desc ring space */
173 if ((idxd->batch_idx_read == 0 && idxd->batch_idx_write == idxd->max_batches) ||
174 idxd->batch_idx_write + 1 == idxd->batch_idx_read)
176 /* for descriptor ring, we always need a slot for batch completion */
177 if (((write_idx + 2) & mask) == idxd->hdls_read)
180 /* write desc and handle. Note, descriptors don't wrap */
181 idxd->desc_ring[write_idx].pasid = 0;
182 idxd->desc_ring[write_idx].op_flags = op_flags | IDXD_FLAG_COMPLETION_ADDR_VALID;
183 idxd->desc_ring[write_idx].completion = __desc_idx_to_iova(idxd, write_idx & mask);
184 idxd->desc_ring[write_idx].src = src;
185 idxd->desc_ring[write_idx].dst = dst;
186 idxd->desc_ring[write_idx].size = size;
189 idxd->hdl_ring_flags[write_idx & mask] = RTE_IDXD_HDL_INVALID;
191 idxd->hdl_ring[write_idx & mask] = *hdl;
194 idxd->xstats.enqueued++;
196 rte_prefetch0_write(&idxd->desc_ring[write_idx + 1]);
200 idxd->xstats.enqueue_failed++;
205 static __rte_always_inline int
206 __idxd_enqueue_fill(int dev_id, uint64_t pattern, rte_iova_t dst,
207 unsigned int length, uintptr_t dst_hdl)
209 const struct rte_idxd_user_hdl hdl = {
212 return __idxd_write_desc(dev_id,
213 (idxd_op_fill << IDXD_CMD_OP_SHIFT) | IDXD_FLAG_CACHE_CONTROL,
214 pattern, dst, length, &hdl);
217 static __rte_always_inline int
218 __idxd_enqueue_copy(int dev_id, rte_iova_t src, rte_iova_t dst,
219 unsigned int length, uintptr_t src_hdl, uintptr_t dst_hdl)
221 const struct rte_idxd_user_hdl hdl = {
225 return __idxd_write_desc(dev_id,
226 (idxd_op_memmove << IDXD_CMD_OP_SHIFT) | IDXD_FLAG_CACHE_CONTROL,
227 src, dst, length, &hdl);
230 static __rte_always_inline int
231 __idxd_fence(int dev_id)
233 /* only op field needs filling - zero src, dst and length */
234 return __idxd_write_desc(dev_id, IDXD_FLAG_FENCE, 0, 0, 0, NULL);
237 static __rte_always_inline void
238 __idxd_movdir64b(volatile void *dst, const struct rte_idxd_hw_desc *src)
240 asm volatile (".byte 0x66, 0x0f, 0x38, 0xf8, 0x02"
242 : "a" (dst), "d" (src)
246 static __rte_always_inline int
247 __idxd_perform_ops(int dev_id)
249 struct rte_idxd_rawdev *idxd =
250 (struct rte_idxd_rawdev *)rte_rawdevs[dev_id].dev_private;
252 if (!idxd->cfg.no_prefetch_completions)
253 rte_prefetch1(&idxd->desc_ring[idxd->batch_idx_ring[idxd->batch_idx_read]]);
255 if (idxd->batch_size == 0)
258 if (idxd->batch_size == 1)
259 /* use a fence as a null descriptor, so batch_size >= 2 */
260 if (__idxd_fence(dev_id) != 1)
263 /* write completion beyond last desc in the batch */
264 uint16_t comp_idx = (idxd->batch_start + idxd->batch_size) & idxd->desc_ring_mask;
265 *((uint64_t *)&idxd->desc_ring[comp_idx]) = 0; /* zero start of desc */
266 idxd->hdl_ring_flags[comp_idx] = RTE_IDXD_HDL_INVALID;
268 const struct rte_idxd_hw_desc batch_desc = {
269 .op_flags = (idxd_op_batch << IDXD_CMD_OP_SHIFT) |
270 IDXD_FLAG_COMPLETION_ADDR_VALID |
271 IDXD_FLAG_REQUEST_COMPLETION,
272 .desc_addr = __desc_idx_to_iova(idxd, idxd->batch_start),
273 .completion = __desc_idx_to_iova(idxd, comp_idx),
274 .size = idxd->batch_size,
277 _mm_sfence(); /* fence before writing desc to device */
278 __idxd_movdir64b(idxd->portal, &batch_desc);
279 idxd->xstats.started += idxd->batch_size;
281 idxd->batch_start += idxd->batch_size + 1;
282 idxd->batch_start &= idxd->desc_ring_mask;
283 idxd->batch_size = 0;
285 idxd->batch_idx_ring[idxd->batch_idx_write++] = comp_idx;
286 if (idxd->batch_idx_write > idxd->max_batches)
287 idxd->batch_idx_write = 0;
292 static __rte_always_inline int
293 __idxd_completed_ops(int dev_id, uint8_t max_ops, uint32_t *status, uint8_t *num_unsuccessful,
294 uintptr_t *src_hdls, uintptr_t *dst_hdls)
296 struct rte_idxd_rawdev *idxd =
297 (struct rte_idxd_rawdev *)rte_rawdevs[dev_id].dev_private;
298 unsigned short n, h_idx;
300 while (idxd->batch_idx_read != idxd->batch_idx_write) {
301 uint16_t idx_to_chk = idxd->batch_idx_ring[idxd->batch_idx_read];
302 volatile struct rte_idxd_completion *comp_to_chk =
303 (struct rte_idxd_completion *)&idxd->desc_ring[idx_to_chk];
304 uint8_t batch_status = comp_to_chk->status;
305 if (batch_status == 0)
307 comp_to_chk->status = 0;
308 if (unlikely(batch_status > 1)) {
309 /* error occurred somewhere in batch, start where last checked */
310 uint16_t desc_count = comp_to_chk->completed_size;
311 uint16_t batch_start = idxd->hdls_avail;
312 uint16_t batch_end = idx_to_chk;
314 if (batch_start > batch_end)
315 batch_end += idxd->desc_ring_mask + 1;
316 /* go through each batch entry and see status */
317 for (n = 0; n < desc_count; n++) {
318 uint16_t idx = (batch_start + n) & idxd->desc_ring_mask;
319 volatile struct rte_idxd_completion *comp =
320 (struct rte_idxd_completion *)&idxd->desc_ring[idx];
321 if (comp->status != 0 &&
322 idxd->hdl_ring_flags[idx] == RTE_IDXD_HDL_NORMAL) {
323 idxd->hdl_ring_flags[idx] = RTE_IDXD_HDL_OP_FAILED;
324 idxd->hdl_ring_flags[idx] |= (comp->status << 8);
325 comp->status = 0; /* clear error for next time */
328 /* if batch is incomplete, mark rest as skipped */
329 for ( ; n < batch_end - batch_start; n++) {
330 uint16_t idx = (batch_start + n) & idxd->desc_ring_mask;
331 if (idxd->hdl_ring_flags[idx] == RTE_IDXD_HDL_NORMAL)
332 idxd->hdl_ring_flags[idx] = RTE_IDXD_HDL_OP_SKIPPED;
335 /* avail points to one after the last one written */
336 idxd->hdls_avail = (idx_to_chk + 1) & idxd->desc_ring_mask;
337 idxd->batch_idx_read++;
338 if (idxd->batch_idx_read > idxd->max_batches)
339 idxd->batch_idx_read = 0;
342 if (idxd->cfg.hdls_disable && status == NULL) {
343 n = (idxd->hdls_avail < idxd->hdls_read) ?
344 (idxd->hdls_avail + idxd->desc_ring_mask + 1 - idxd->hdls_read) :
345 (idxd->hdls_avail - idxd->hdls_read);
346 idxd->hdls_read = idxd->hdls_avail;
351 h_idx = idxd->hdls_read;
352 while (h_idx != idxd->hdls_avail) {
353 uint16_t flag = idxd->hdl_ring_flags[h_idx];
354 if (flag != RTE_IDXD_HDL_INVALID) {
355 if (!idxd->cfg.hdls_disable) {
356 src_hdls[n] = idxd->hdl_ring[h_idx].src;
357 dst_hdls[n] = idxd->hdl_ring[h_idx].dst;
359 if (unlikely(flag != RTE_IDXD_HDL_NORMAL)) {
361 status[n] = flag == RTE_IDXD_HDL_OP_SKIPPED ?
362 RTE_IOAT_OP_SKIPPED :
363 /* failure case, return err code */
364 idxd->hdl_ring_flags[h_idx] >> 8;
365 if (num_unsuccessful != NULL)
366 *num_unsuccessful += 1;
370 idxd->hdl_ring_flags[h_idx] = RTE_IDXD_HDL_NORMAL;
371 if (++h_idx > idxd->desc_ring_mask)
377 /* skip over any remaining blank elements, e.g. batch completion */
378 while (idxd->hdl_ring_flags[h_idx] == RTE_IDXD_HDL_INVALID && h_idx != idxd->hdls_avail) {
379 idxd->hdl_ring_flags[h_idx] = RTE_IDXD_HDL_NORMAL;
380 if (++h_idx > idxd->desc_ring_mask)
383 idxd->hdls_read = h_idx;
386 idxd->xstats.completed += n;