1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Intel Corporation
4 #ifndef _RTE_IOAT_RAWDEV_FNS_H_
5 #define _RTE_IOAT_RAWDEV_FNS_H_
8 #include <rte_rawdev.h>
9 #include <rte_memzone.h>
10 #include <rte_prefetch.h>
14 * Structure representing a device descriptor
16 struct rte_ioat_generic_hw_desc {
21 uint32_t int_enable: 1;
22 uint32_t src_snoop_disable: 1;
23 uint32_t dest_snoop_disable: 1;
24 uint32_t completion_update: 1;
26 uint32_t reserved2: 1;
27 uint32_t src_page_break: 1;
28 uint32_t dest_page_break: 1;
32 uint32_t reserved: 13;
39 uint64_t op_specific[4];
44 * Identify the data path to use.
45 * Must be first field of rte_ioat_rawdev and rte_idxd_rawdev structs
47 enum rte_ioat_dev_type {
54 * Structure representing an IOAT device instance
56 struct rte_ioat_rawdev {
57 enum rte_ioat_dev_type type;
58 struct rte_rawdev *rawdev;
59 const struct rte_memzone *mz;
60 const struct rte_memzone *desc_mz;
62 volatile uint16_t *doorbell;
63 phys_addr_t status_addr;
64 phys_addr_t ring_addr;
66 unsigned short ring_size;
68 struct rte_ioat_generic_hw_desc *desc_ring;
69 __m128i *hdls; /* completion handles for returning to user */
72 unsigned short next_read;
73 unsigned short next_write;
75 /* some statistics for tracking, if added/changed update xstats fns*/
76 uint64_t enqueue_failed __rte_cache_aligned;
81 /* to report completions, the device will write status back here */
82 volatile uint64_t status __rte_cache_aligned;
84 /* pointer to the register bar */
85 volatile struct rte_ioat_registers *regs;
88 #define RTE_IOAT_CHANSTS_IDLE 0x1
89 #define RTE_IOAT_CHANSTS_SUSPENDED 0x2
90 #define RTE_IOAT_CHANSTS_HALTED 0x3
91 #define RTE_IOAT_CHANSTS_ARMED 0x4
94 * Defines used in the data path for interacting with hardware.
96 #define IDXD_CMD_OP_SHIFT 24
105 #define IDXD_FLAG_FENCE (1 << 0)
106 #define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2)
107 #define IDXD_FLAG_REQUEST_COMPLETION (1 << 3)
108 #define IDXD_FLAG_CACHE_CONTROL (1 << 8)
111 * Hardware descriptor used by DSA hardware, for both bursts and
112 * for individual operations.
114 struct rte_idxd_hw_desc {
117 rte_iova_t completion;
121 rte_iova_t src; /* source address for copy ops etc. */
122 rte_iova_t desc_addr; /* descriptor pointer for batch */
126 uint32_t size; /* length of data for op, or batch size */
128 /* 28 bytes of padding here */
132 * Completion record structure written back by DSA
134 struct rte_idxd_completion {
137 /* 16-bits pad here */
138 uint32_t completed_size; /* data length, or descriptors for batch */
140 rte_iova_t fault_address;
141 uint32_t invalid_flags;
144 #define BATCH_SIZE 64
147 * Structure used inside the driver for building up and submitting
148 * a batch of operations to the DSA hardware.
150 struct rte_idxd_desc_batch {
151 struct rte_idxd_completion comp; /* the completion record for batch */
157 struct rte_idxd_hw_desc batch_desc;
159 /* batches must always have 2 descriptors, so put a null at the start */
160 struct rte_idxd_hw_desc null_desc;
161 struct rte_idxd_hw_desc ops[BATCH_SIZE];
165 * structure used to save the "handles" provided by the user to be
166 * returned to the user on job completion.
168 struct rte_idxd_user_hdl {
175 * Structure representing an IDXD device instance
177 struct rte_idxd_rawdev {
178 enum rte_ioat_dev_type type;
179 void *portal; /* address to write the batch descriptor */
181 /* counters to track the batches and the individual op handles */
182 uint16_t batch_ring_sz; /* size of batch ring */
183 uint16_t hdl_ring_sz; /* size of the user hdl ring */
185 uint16_t next_batch; /* where we write descriptor ops */
186 uint16_t next_completed; /* batch where we read completions */
187 uint16_t next_ret_hdl; /* the next user hdl to return */
188 uint16_t last_completed_hdl; /* the last user hdl that has completed */
189 uint16_t next_free_hdl; /* where the handle for next op will go */
190 uint16_t hdls_disable; /* disable tracking completion handles */
192 struct rte_idxd_user_hdl *hdl_ring;
193 struct rte_idxd_desc_batch *batch_ring;
197 * Enqueue a copy operation onto the ioat device
200 rte_ioat_enqueue_copy(int dev_id, phys_addr_t src, phys_addr_t dst,
201 unsigned int length, uintptr_t src_hdl, uintptr_t dst_hdl)
203 struct rte_ioat_rawdev *ioat =
204 (struct rte_ioat_rawdev *)rte_rawdevs[dev_id].dev_private;
205 unsigned short read = ioat->next_read;
206 unsigned short write = ioat->next_write;
207 unsigned short mask = ioat->ring_size - 1;
208 unsigned short space = mask + read - write;
209 struct rte_ioat_generic_hw_desc *desc;
212 ioat->enqueue_failed++;
216 ioat->next_write = write + 1;
219 desc = &ioat->desc_ring[write];
221 /* set descriptor write-back every 16th descriptor */
222 desc->u.control_raw = (uint32_t)((!(write & 0xF)) << 3);
223 desc->src_addr = src;
224 desc->dest_addr = dst;
226 if (!ioat->hdls_disable)
227 ioat->hdls[write] = _mm_set_epi64x((int64_t)dst_hdl,
229 rte_prefetch0(&ioat->desc_ring[ioat->next_write & mask]);
235 /* add fence to last written descriptor */
237 rte_ioat_fence(int dev_id)
239 struct rte_ioat_rawdev *ioat =
240 (struct rte_ioat_rawdev *)rte_rawdevs[dev_id].dev_private;
241 unsigned short write = ioat->next_write;
242 unsigned short mask = ioat->ring_size - 1;
243 struct rte_ioat_generic_hw_desc *desc;
245 write = (write - 1) & mask;
246 desc = &ioat->desc_ring[write];
248 desc->u.control.fence = 1;
253 * Trigger hardware to begin performing enqueued operations
256 rte_ioat_perform_ops(int dev_id)
258 struct rte_ioat_rawdev *ioat =
259 (struct rte_ioat_rawdev *)rte_rawdevs[dev_id].dev_private;
260 ioat->desc_ring[(ioat->next_write - 1) & (ioat->ring_size - 1)].u
261 .control.completion_update = 1;
262 rte_compiler_barrier();
263 *ioat->doorbell = ioat->next_write;
264 ioat->started = ioat->enqueued;
269 * Returns the index of the last completed operation.
272 rte_ioat_get_last_completed(struct rte_ioat_rawdev *ioat, int *error)
274 uint64_t status = ioat->status;
276 /* lower 3 bits indicate "transfer status" : active, idle, halted.
277 * We can ignore bit 0.
279 *error = status & (RTE_IOAT_CHANSTS_SUSPENDED | RTE_IOAT_CHANSTS_ARMED);
280 return (status - ioat->ring_addr) >> 6;
284 * Returns details of operations that have been completed
287 rte_ioat_completed_ops(int dev_id, uint8_t max_copies,
288 uintptr_t *src_hdls, uintptr_t *dst_hdls)
290 struct rte_ioat_rawdev *ioat =
291 (struct rte_ioat_rawdev *)rte_rawdevs[dev_id].dev_private;
292 unsigned short mask = (ioat->ring_size - 1);
293 unsigned short read = ioat->next_read;
294 unsigned short end_read, count;
298 end_read = (rte_ioat_get_last_completed(ioat, &error) + 1) & mask;
299 count = (end_read - (read & mask)) & mask;
306 if (ioat->hdls_disable) {
311 if (count > max_copies)
314 for (; i < count - 1; i += 2, read += 2) {
315 __m128i hdls0 = _mm_load_si128(&ioat->hdls[read & mask]);
316 __m128i hdls1 = _mm_load_si128(&ioat->hdls[(read + 1) & mask]);
318 _mm_storeu_si128((__m128i *)&src_hdls[i],
319 _mm_unpacklo_epi64(hdls0, hdls1));
320 _mm_storeu_si128((__m128i *)&dst_hdls[i],
321 _mm_unpackhi_epi64(hdls0, hdls1));
323 for (; i < count; i++, read++) {
324 uintptr_t *hdls = (uintptr_t *)&ioat->hdls[read & mask];
325 src_hdls[i] = hdls[0];
326 dst_hdls[i] = hdls[1];
330 ioat->next_read = read;
331 ioat->completed += count;
336 __rte_deprecated_msg("use rte_ioat_perform_ops() instead")
337 rte_ioat_do_copies(int dev_id) { rte_ioat_perform_ops(dev_id); }
340 __rte_deprecated_msg("use rte_ioat_completed_ops() instead")
341 rte_ioat_completed_copies(int dev_id, uint8_t max_copies,
342 uintptr_t *src_hdls, uintptr_t *dst_hdls)
344 return rte_ioat_completed_ops(dev_id, max_copies, src_hdls, dst_hdls);
347 #endif /* _RTE_IOAT_RAWDEV_FNS_H_ */