common/mlx5: share MR management
[dpdk.git] / drivers / regex / mlx5 / mlx5_regex.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2020 Mellanox Technologies, Ltd
3  */
4
5 #include <rte_malloc.h>
6 #include <rte_log.h>
7 #include <rte_errno.h>
8 #include <rte_pci.h>
9 #include <rte_regexdev.h>
10 #include <rte_regexdev_core.h>
11 #include <rte_regexdev_driver.h>
12 #include <rte_bus_pci.h>
13
14 #include <mlx5_common.h>
15 #include <mlx5_common_mr.h>
16 #include <mlx5_glue.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_prm.h>
19
20 #include "mlx5_regex.h"
21 #include "mlx5_regex_utils.h"
22 #include "mlx5_rxp_csrs.h"
23
24 #define MLX5_REGEX_DRIVER_NAME regex_mlx5
25
26 int mlx5_regex_logtype;
27
28 const struct rte_regexdev_ops mlx5_regexdev_ops = {
29         .dev_info_get = mlx5_regex_info_get,
30         .dev_configure = mlx5_regex_configure,
31         .dev_db_import = mlx5_regex_rules_db_import,
32         .dev_qp_setup = mlx5_regex_qp_setup,
33         .dev_start = mlx5_regex_start,
34         .dev_stop = mlx5_regex_stop,
35         .dev_close = mlx5_regex_close,
36 };
37
38 int
39 mlx5_regex_start(struct rte_regexdev *dev __rte_unused)
40 {
41         return 0;
42 }
43
44 int
45 mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)
46 {
47         return 0;
48 }
49
50 int
51 mlx5_regex_close(struct rte_regexdev *dev __rte_unused)
52 {
53         return 0;
54 }
55
56 static int
57 mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines)
58 {
59         uint32_t fpga_ident = 0;
60         int err;
61         int i;
62
63         for (i = 0; i < num_engines; i++) {
64                 err = mlx5_devx_regex_register_read(ctx, i,
65                                                     MLX5_RXP_CSR_IDENTIFIER,
66                                                     &fpga_ident);
67                 fpga_ident = (fpga_ident & (0x0000FFFF));
68                 if (err || fpga_ident != MLX5_RXP_IDENTIFIER) {
69                         DRV_LOG(ERR, "Failed setup RXP %d err %d database "
70                                 "memory 0x%x", i, err, fpga_ident);
71                         if (!err)
72                                 err = EINVAL;
73                         return err;
74                 }
75         }
76         return 0;
77 }
78
79 static void
80 mlx5_regex_get_name(char *name, struct rte_device *dev)
81 {
82         sprintf(name, "mlx5_regex_%s", dev->name);
83 }
84
85 static int
86 mlx5_regex_dev_probe(struct mlx5_common_device *cdev)
87 {
88         struct mlx5_regex_priv *priv = NULL;
89         struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
90         char name[RTE_REGEXDEV_NAME_MAX_LEN];
91         int ret;
92         uint32_t val;
93
94         if ((!attr->regex && !attr->mmo_regex_sq_en && !attr->mmo_regex_qp_en)
95             || attr->regexp_num_of_engines == 0) {
96                 DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe "
97                         "old FW/OFED version?");
98                 rte_errno = ENOTSUP;
99                 return -rte_errno;
100         }
101         if (mlx5_regex_engines_status(cdev->ctx, 2)) {
102                 DRV_LOG(ERR, "RegEx engine error.");
103                 rte_errno = ENOMEM;
104                 return -rte_errno;
105         }
106         priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv),
107                            RTE_CACHE_LINE_SIZE);
108         if (!priv) {
109                 DRV_LOG(ERR, "Failed to allocate private memory.");
110                 rte_errno = ENOMEM;
111                 return -rte_errno;
112         }
113         priv->mmo_regex_qp_cap = attr->mmo_regex_qp_en;
114         priv->mmo_regex_sq_cap = attr->mmo_regex_sq_en;
115         priv->cdev = cdev;
116         priv->nb_engines = 2; /* attr.regexp_num_of_engines */
117         ret = mlx5_devx_regex_register_read(priv->cdev->ctx, 0,
118                                             MLX5_RXP_CSR_IDENTIFIER, &val);
119         if (ret) {
120                 DRV_LOG(ERR, "CSR read failed!");
121                 goto dev_error;
122         }
123         if (val == MLX5_RXP_BF2_IDENTIFIER)
124                 priv->is_bf2 = 1;
125         /* Default RXP programming mode to Shared. */
126         priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE;
127         mlx5_regex_get_name(name, cdev->dev);
128         priv->regexdev = rte_regexdev_register(name);
129         if (priv->regexdev == NULL) {
130                 DRV_LOG(ERR, "Failed to register RegEx device.");
131                 rte_errno = rte_errno ? rte_errno : EINVAL;
132                 goto dev_error;
133         }
134         /*
135          * This PMD always claims the write memory barrier on UAR
136          * registers writings, it is safe to allocate UAR with any
137          * memory mapping type.
138          */
139         priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
140         if (!priv->uar) {
141                 DRV_LOG(ERR, "can't allocate uar.");
142                 rte_errno = ENOMEM;
143                 goto error;
144         }
145         priv->regexdev->dev_ops = &mlx5_regexdev_ops;
146         priv->regexdev->enqueue = mlx5_regexdev_enqueue;
147 #ifdef HAVE_MLX5_UMR_IMKEY
148         if (!attr->umr_indirect_mkey_disabled &&
149             !attr->umr_modify_entity_size_disabled)
150                 priv->has_umr = 1;
151         if (priv->has_umr)
152                 priv->regexdev->enqueue = mlx5_regexdev_enqueue_gga;
153 #endif
154         priv->regexdev->dequeue = mlx5_regexdev_dequeue;
155         priv->regexdev->device = cdev->dev;
156         priv->regexdev->data->dev_private = priv;
157         priv->regexdev->state = RTE_REGEXDEV_READY;
158         DRV_LOG(INFO, "RegEx GGA is %s.",
159                 priv->has_umr ? "supported" : "unsupported");
160         return 0;
161
162 error:
163         if (priv->uar)
164                 mlx5_glue->devx_free_uar(priv->uar);
165         if (priv->regexdev)
166                 rte_regexdev_unregister(priv->regexdev);
167 dev_error:
168         if (priv)
169                 rte_free(priv);
170         return -rte_errno;
171 }
172
173 static int
174 mlx5_regex_dev_remove(struct mlx5_common_device *cdev)
175 {
176         char name[RTE_REGEXDEV_NAME_MAX_LEN];
177         struct rte_regexdev *dev;
178         struct mlx5_regex_priv *priv = NULL;
179
180         mlx5_regex_get_name(name, cdev->dev);
181         dev = rte_regexdev_get_device_by_name(name);
182         if (!dev)
183                 return 0;
184         priv = dev->data->dev_private;
185         if (priv) {
186                 if (priv->uar)
187                         mlx5_glue->devx_free_uar(priv->uar);
188                 if (priv->regexdev)
189                         rte_regexdev_unregister(priv->regexdev);
190                 rte_free(priv);
191         }
192         return 0;
193 }
194
195 static const struct rte_pci_id mlx5_regex_pci_id_map[] = {
196         {
197                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
198                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
199         },
200         {
201                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
202                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
203         },
204         {
205                 .vendor_id = 0
206         }
207 };
208
209 static struct mlx5_class_driver mlx5_regex_driver = {
210         .drv_class = MLX5_CLASS_REGEX,
211         .name = RTE_STR(MLX5_REGEX_DRIVER_NAME),
212         .id_table = mlx5_regex_pci_id_map,
213         .probe = mlx5_regex_dev_probe,
214         .remove = mlx5_regex_dev_remove,
215 };
216
217 RTE_INIT(rte_mlx5_regex_init)
218 {
219         mlx5_common_init();
220         if (mlx5_glue)
221                 mlx5_class_driver_register(&mlx5_regex_driver);
222 }
223
224 RTE_LOG_REGISTER_DEFAULT(mlx5_regex_logtype, NOTICE)
225 RTE_PMD_EXPORT_NAME(MLX5_REGEX_DRIVER_NAME, __COUNTER__);
226 RTE_PMD_REGISTER_PCI_TABLE(MLX5_REGEX_DRIVER_NAME, mlx5_regex_pci_id_map);
227 RTE_PMD_REGISTER_KMOD_DEP(MLX5_REGEX_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");