1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
7 #include <sys/eventfd.h>
9 #include <rte_malloc.h>
10 #include <rte_errno.h>
11 #include <rte_lcore.h>
12 #include <rte_atomic.h>
13 #include <rte_common.h>
15 #include <rte_alarm.h>
17 #include <mlx5_common.h>
19 #include "mlx5_vdpa_utils.h"
20 #include "mlx5_vdpa.h"
23 #define MLX5_VDPA_DEFAULT_TIMER_DELAY_US 500u
24 #define MLX5_VDPA_NO_TRAFFIC_TIME_S 2LLU
27 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
30 mlx5_glue->devx_free_uar(priv->uar);
33 #ifdef HAVE_IBV_DEVX_EVENT
36 struct mlx5dv_devx_async_event_hdr event_resp;
37 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
41 /* Clean all pending events. */
42 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
44 (ssize_t)sizeof(out.event_resp.cookie))
46 mlx5_glue->devx_destroy_event_channel(priv->eventc);
53 /* Prepare all the global resources for all the event objects.*/
55 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
61 lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
62 if (mlx5_glue->devx_query_eqn(priv->ctx, lcore, &priv->eqn)) {
64 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
67 priv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,
68 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
71 DRV_LOG(ERR, "Failed to create event channel %d.",
75 priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
78 DRV_LOG(ERR, "Failed to allocate UAR.");
83 mlx5_vdpa_event_qp_global_release(priv);
88 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
91 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
93 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
95 rte_free((void *)(uintptr_t)cq->umem_buf);
96 memset(cq, 0, sizeof(*cq));
99 static inline void __rte_unused
100 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
102 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
103 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
104 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
105 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
106 uint64_t db_be = rte_cpu_to_be_64(doorbell);
107 uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
110 cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
113 *(uint64_t *)addr = db_be;
115 *(uint32_t *)addr = db_be;
117 *((uint32_t *)addr + 1) = db_be >> 32;
124 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
125 int callfd, struct mlx5_vdpa_cq *cq)
127 struct mlx5_devx_cq_attr attr;
128 size_t pgsize = sysconf(_SC_PAGESIZE);
130 uint16_t event_nums[1] = {0};
131 uint16_t cq_size = 1 << log_desc_n;
134 cq->log_desc_n = log_desc_n;
135 umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
136 cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
138 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
142 cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
143 (void *)(uintptr_t)cq->umem_buf,
145 IBV_ACCESS_LOCAL_WRITE);
147 DRV_LOG(ERR, "Failed to register umem for CQ.");
150 attr.q_umem_valid = 1;
151 attr.db_umem_valid = 1;
152 attr.use_first_only = 1;
153 attr.overrun_ignore = 0;
154 attr.uar_page_id = priv->uar->page_id;
155 attr.q_umem_id = cq->umem_obj->umem_id;
156 attr.q_umem_offset = 0;
157 attr.db_umem_id = cq->umem_obj->umem_id;
158 attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
159 attr.eqn = priv->eqn;
160 attr.log_cq_size = log_desc_n;
161 attr.log_page_size = rte_log2_u32(pgsize);
162 cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
165 cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
167 rte_spinlock_init(&cq->sl);
168 /* Subscribe CQ event to the event channel controlled by the driver. */
169 ret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
172 (uint64_t)(uintptr_t)cq);
174 DRV_LOG(ERR, "Failed to subscribe CQE event.");
179 ret = mlx5_glue->devx_subscribe_devx_event_fd(priv->eventc,
183 DRV_LOG(ERR, "Failed to subscribe CQE event fd.");
189 /* Init CQ to ones to be in HW owner in the start. */
190 cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
191 cq->cqes[0].wqe_counter = rte_cpu_to_be_16(cq_size - 1);
193 mlx5_vdpa_cq_arm(priv, cq);
196 mlx5_vdpa_cq_destroy(cq);
200 static inline uint32_t
201 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
203 struct mlx5_vdpa_event_qp *eqp =
204 container_of(cq, struct mlx5_vdpa_event_qp, cq);
205 const unsigned int cq_size = 1 << cq->log_desc_n;
206 const unsigned int cq_mask = cq_size - 1;
209 uint16_t wqe_counter;
215 uint16_t next_wqe_counter = cq->cq_ci & cq_mask;
216 uint16_t cur_wqe_counter;
219 last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
220 cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
221 comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
224 MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
225 MLX5_CQE_OWNER(last_word.op_own));
226 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
228 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
230 MLX5_CQE_OPCODE(last_word.op_own) ==
234 /* Ring CQ doorbell record. */
235 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
237 /* Ring SW QP doorbell record. */
238 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
244 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
246 struct mlx5_vdpa_cq *cq;
249 for (i = 0; i < priv->nr_virtqs; i++) {
250 cq = &priv->virtqs[i].eqp.cq;
251 if (cq->cq && !cq->armed)
252 mlx5_vdpa_cq_arm(priv, cq);
257 mlx5_vdpa_poll_handle(void *arg)
259 struct mlx5_vdpa_priv *priv = arg;
261 struct mlx5_vdpa_cq *cq;
263 uint64_t current_tic;
265 pthread_mutex_lock(&priv->timer_lock);
266 while (!priv->timer_on)
267 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
268 pthread_mutex_unlock(&priv->timer_lock);
271 for (i = 0; i < priv->nr_virtqs; i++) {
272 cq = &priv->virtqs[i].eqp.cq;
273 if (cq->cq && !cq->armed) {
274 uint32_t comp = mlx5_vdpa_cq_poll(cq);
277 /* Notify guest for descs consuming. */
278 if (cq->callfd != -1)
279 eventfd_write(cq->callfd,
285 current_tic = rte_rdtsc();
287 /* No traffic ? stop timer and load interrupts. */
288 if (current_tic - priv->last_traffic_tic >=
289 rte_get_timer_hz() * MLX5_VDPA_NO_TRAFFIC_TIME_S) {
290 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
291 priv->vdev->device->name);
292 mlx5_vdpa_arm_all_cqs(priv);
293 pthread_mutex_lock(&priv->timer_lock);
295 while (!priv->timer_on)
296 pthread_cond_wait(&priv->timer_cond,
298 pthread_mutex_unlock(&priv->timer_lock);
302 priv->last_traffic_tic = current_tic;
304 usleep(priv->timer_delay_us);
310 mlx5_vdpa_interrupt_handler(void *cb_arg)
312 struct mlx5_vdpa_priv *priv = cb_arg;
313 #ifdef HAVE_IBV_DEVX_EVENT
315 struct mlx5dv_devx_async_event_hdr event_resp;
316 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
319 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
321 (ssize_t)sizeof(out.event_resp.cookie)) {
322 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
323 (uintptr_t)out.event_resp.cookie;
324 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
325 struct mlx5_vdpa_event_qp, cq);
326 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
327 struct mlx5_vdpa_virtq, eqp);
329 mlx5_vdpa_cq_poll(cq);
330 /* Don't arm again - timer will take control. */
331 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
332 " Timer is %s, cq ci is %u.\n",
333 priv->vdev->device->name,
334 (int)virtq->index, cq->cq->id,
335 priv->timer_on ? "on" : "off", cq->cq_ci);
340 /* Traffic detected: make sure timer is on. */
341 priv->last_traffic_tic = rte_rdtsc();
342 pthread_mutex_lock(&priv->timer_lock);
343 if (!priv->timer_on) {
345 pthread_cond_signal(&priv->timer_cond);
347 pthread_mutex_unlock(&priv->timer_lock);
351 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
357 /* All virtqs are in poll mode. */
359 pthread_mutex_init(&priv->timer_lock, NULL);
360 pthread_cond_init(&priv->timer_cond, NULL);
362 priv->timer_delay_us = MLX5_VDPA_DEFAULT_TIMER_DELAY_US;
363 ret = pthread_create(&priv->timer_tid, NULL, mlx5_vdpa_poll_handle,
366 DRV_LOG(ERR, "Failed to create timer thread.");
369 flags = fcntl(priv->eventc->fd, F_GETFL);
370 ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
372 DRV_LOG(ERR, "Failed to change event channel FD.");
375 priv->intr_handle.fd = priv->eventc->fd;
376 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
377 if (rte_intr_callback_register(&priv->intr_handle,
378 mlx5_vdpa_interrupt_handler, priv)) {
379 priv->intr_handle.fd = 0;
380 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
385 mlx5_vdpa_cqe_event_unset(priv);
390 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
392 int retries = MLX5_VDPA_INTR_RETRIES;
396 if (priv->intr_handle.fd) {
397 while (retries-- && ret == -EAGAIN) {
398 ret = rte_intr_callback_unregister(&priv->intr_handle,
399 mlx5_vdpa_interrupt_handler,
401 if (ret == -EAGAIN) {
402 DRV_LOG(DEBUG, "Try again to unregister fd %d "
403 "of CQ interrupt, retries = %d.",
404 priv->intr_handle.fd, retries);
408 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
410 if (priv->timer_tid) {
411 pthread_cancel(priv->timer_tid);
412 pthread_join(priv->timer_tid, &status);
418 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
421 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
423 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
425 rte_free(eqp->umem_buf);
427 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
428 mlx5_vdpa_cq_destroy(&eqp->cq);
429 memset(eqp, 0, sizeof(*eqp));
433 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
435 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
437 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
441 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
443 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
447 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
449 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
453 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
455 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
459 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
461 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
465 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
467 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
475 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
476 int callfd, struct mlx5_vdpa_event_qp *eqp)
478 struct mlx5_devx_qp_attr attr = {0};
479 uint16_t log_desc_n = rte_log2_u32(desc_n);
480 uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
481 sizeof(*eqp->db_rec) * 2;
483 if (mlx5_vdpa_event_qp_global_prepare(priv))
485 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
488 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
490 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
493 eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
494 if (!eqp->umem_buf) {
495 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
499 eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
500 (void *)(uintptr_t)eqp->umem_buf,
502 IBV_ACCESS_LOCAL_WRITE);
503 if (!eqp->umem_obj) {
504 DRV_LOG(ERR, "Failed to register umem for SW QP.");
507 attr.uar_index = priv->uar->page_id;
508 attr.cqn = eqp->cq.cq->id;
509 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
510 attr.rq_size = 1 << log_desc_n;
511 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
512 attr.sq_size = 0; /* No need SQ. */
513 attr.dbr_umem_valid = 1;
514 attr.wq_umem_id = eqp->umem_obj->umem_id;
515 attr.wq_umem_offset = 0;
516 attr.dbr_umem_id = eqp->umem_obj->umem_id;
517 attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
518 eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
520 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
523 eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
524 if (mlx5_vdpa_qps2rts(eqp))
527 rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
530 mlx5_vdpa_event_qp_destroy(eqp);