drivers/vdpa/mlx5/mlx5_vdpa_event.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2019 Mellanox Technologies, Ltd
   3  */
   4 #include <unistd.h>
   5 #include <stdint.h>
   6 #include <fcntl.h>
   7 #include <sys/eventfd.h>
   8
   9 #include <rte_malloc.h>
  10 #include <rte_errno.h>
  11 #include <rte_lcore.h>
  12 #include <rte_atomic.h>
  13 #include <rte_common.h>
  14 #include <rte_io.h>
  15 #include <rte_alarm.h>
  16
  17 #include <mlx5_common.h>
  18
  19 #include "mlx5_vdpa_utils.h"
  20 #include "mlx5_vdpa.h"
  21
  22
  23 void
  24 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
  25 {
  26         if (priv->uar) {
  27                 mlx5_glue->devx_free_uar(priv->uar);
  28                 priv->uar = NULL;
  29         }
  30 #ifdef HAVE_IBV_DEVX_EVENT
  31         if (priv->eventc) {
  32                 union {
  33                         struct mlx5dv_devx_async_event_hdr event_resp;
  34                         uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
  35                                                                          + 128];
  36                 } out;
  37
  38                 /* Clean all pending events. */
  39                 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
  40                        sizeof(out.buf)) >=
  41                        (ssize_t)sizeof(out.event_resp.cookie))
  42                         ;
  43                 mlx5_glue->devx_destroy_event_channel(priv->eventc);
  44                 priv->eventc = NULL;
  45         }
  46 #endif
  47         priv->eqn = 0;
  48 }
  49
  50 /* Prepare all the global resources for all the event objects.*/
  51 static int
  52 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
  53 {
  54         int flags, ret;
  55
  56         if (priv->eventc)
  57                 return 0;
  58         if (mlx5_glue->devx_query_eqn(priv->ctx, 0, &priv->eqn)) {
  59                 rte_errno = errno;
  60                 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
  61                 return -1;
  62         }
  63         priv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,
  64                            MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
  65         if (!priv->eventc) {
  66                 rte_errno = errno;
  67                 DRV_LOG(ERR, "Failed to create event channel %d.",
  68                         rte_errno);
  69                 goto error;
  70         }
  71         flags = fcntl(priv->eventc->fd, F_GETFL);
  72         ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
  73         if (ret) {
  74                 DRV_LOG(ERR, "Failed to change event channel FD.");
  75                 goto error;
  76         }
  77         priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
  78         if (!priv->uar) {
  79                 rte_errno = errno;
  80                 DRV_LOG(ERR, "Failed to allocate UAR.");
  81                 goto error;
  82         }
  83         return 0;
  84 error:
  85         mlx5_vdpa_event_qp_global_release(priv);
  86         return -1;
  87 }
  88
  89 static void
  90 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
  91 {
  92         if (cq->cq)
  93                 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
  94         if (cq->umem_obj)
  95                 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
  96         if (cq->umem_buf)
  97                 rte_free((void *)(uintptr_t)cq->umem_buf);
  98         memset(cq, 0, sizeof(*cq));
  99 }
 100
 101 static inline void __rte_unused
 102 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
 103 {
 104         uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
 105         uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
 106         uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
 107         uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
 108         uint64_t db_be = rte_cpu_to_be_64(doorbell);
 109         uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
 110
 111         rte_io_wmb();
 112         cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 113         rte_wmb();
 114 #ifdef RTE_ARCH_64
 115         *(uint64_t *)addr = db_be;
 116 #else
 117         *(uint32_t *)addr = db_be;
 118         rte_io_wmb();
 119         *((uint32_t *)addr + 1) = db_be >> 32;
 120 #endif
 121         cq->arm_sn++;
 122         cq->armed = 1;
 123 }
 124
 125 static int
 126 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
 127                     int callfd, struct mlx5_vdpa_cq *cq)
 128 {
 129         struct mlx5_devx_cq_attr attr = {0};
 130         size_t pgsize = sysconf(_SC_PAGESIZE);
 131         uint32_t umem_size;
 132         uint16_t event_nums[1] = {0};
 133         uint16_t cq_size = 1 << log_desc_n;
 134         int ret;
 135
 136         cq->log_desc_n = log_desc_n;
 137         umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
 138         cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
 139         if (!cq->umem_buf) {
 140                 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
 141                 rte_errno = ENOMEM;
 142                 return -ENOMEM;
 143         }
 144         cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
 145                                                 (void *)(uintptr_t)cq->umem_buf,
 146                                                 umem_size,
 147                                                 IBV_ACCESS_LOCAL_WRITE);
 148         if (!cq->umem_obj) {
 149                 DRV_LOG(ERR, "Failed to register umem for CQ.");
 150                 goto error;
 151         }
 152         attr.q_umem_valid = 1;
 153         attr.db_umem_valid = 1;
 154         attr.use_first_only = 1;
 155         attr.overrun_ignore = 0;
 156         attr.uar_page_id = priv->uar->page_id;
 157         attr.q_umem_id = cq->umem_obj->umem_id;
 158         attr.q_umem_offset = 0;
 159         attr.db_umem_id = cq->umem_obj->umem_id;
 160         attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
 161         attr.eqn = priv->eqn;
 162         attr.log_cq_size = log_desc_n;
 163         attr.log_page_size = rte_log2_u32(pgsize);
 164         cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
 165         if (!cq->cq)
 166                 goto error;
 167         cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
 168         cq->cq_ci = 0;
 169         rte_spinlock_init(&cq->sl);
 170         /* Subscribe CQ event to the event channel controlled by the driver. */
 171         ret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
 172                                                    sizeof(event_nums),
 173                                                    event_nums,
 174                                                    (uint64_t)(uintptr_t)cq);
 175         if (ret) {
 176                 DRV_LOG(ERR, "Failed to subscribe CQE event.");
 177                 rte_errno = errno;
 178                 goto error;
 179         }
 180         cq->callfd = callfd;
 181         /* Init CQ to ones to be in HW owner in the start. */
 182         cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
 183         cq->cqes[0].wqe_counter = rte_cpu_to_be_16(cq_size - 1);
 184         /* First arming. */
 185         mlx5_vdpa_cq_arm(priv, cq);
 186         return 0;
 187 error:
 188         mlx5_vdpa_cq_destroy(cq);
 189         return -1;
 190 }
 191
 192 static inline uint32_t
 193 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
 194 {
 195         struct mlx5_vdpa_event_qp *eqp =
 196                                 container_of(cq, struct mlx5_vdpa_event_qp, cq);
 197         const unsigned int cq_size = 1 << cq->log_desc_n;
 198         const unsigned int cq_mask = cq_size - 1;
 199         union {
 200                 struct {
 201                         uint16_t wqe_counter;
 202                         uint8_t rsvd5;
 203                         uint8_t op_own;
 204                 };
 205                 uint32_t word;
 206         } last_word;
 207         uint16_t next_wqe_counter = cq->cq_ci & cq_mask;
 208         uint16_t cur_wqe_counter;
 209         uint16_t comp;
 210
 211         last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
 212         cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
 213         comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
 214         if (comp) {
 215                 cq->cq_ci += comp;
 216                 MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
 217                             MLX5_CQE_OWNER(last_word.op_own));
 218                 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
 219                             MLX5_CQE_INVALID);
 220                 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
 221                                MLX5_CQE_RESP_ERR ||
 222                                MLX5_CQE_OPCODE(last_word.op_own) ==
 223                                MLX5_CQE_REQ_ERR)))
 224                         cq->errors++;
 225                 rte_io_wmb();
 226                 /* Ring CQ doorbell record. */
 227                 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 228                 rte_io_wmb();
 229                 /* Ring SW QP doorbell record. */
 230                 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
 231         }
 232         return comp;
 233 }
 234
 235 static void
 236 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
 237 {
 238         struct mlx5_vdpa_cq *cq;
 239         int i;
 240
 241         for (i = 0; i < priv->nr_virtqs; i++) {
 242                 cq = &priv->virtqs[i].eqp.cq;
 243                 if (cq->cq && !cq->armed)
 244                         mlx5_vdpa_cq_arm(priv, cq);
 245         }
 246 }
 247
 248 static void
 249 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
 250 {
 251         if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
 252                 switch (max) {
 253                 case 0:
 254                         priv->timer_delay_us += priv->event_us;
 255                         break;
 256                 case 1:
 257                         break;
 258                 default:
 259                         priv->timer_delay_us /= max;
 260                         break;
 261                 }
 262         }
 263         usleep(priv->timer_delay_us);
 264 }
 265
 266 static void *
 267 mlx5_vdpa_poll_handle(void *arg)
 268 {
 269         struct mlx5_vdpa_priv *priv = arg;
 270         int i;
 271         struct mlx5_vdpa_cq *cq;
 272         uint32_t max;
 273         uint64_t current_tic;
 274
 275         pthread_mutex_lock(&priv->timer_lock);
 276         while (!priv->timer_on)
 277                 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
 278         pthread_mutex_unlock(&priv->timer_lock);
 279         priv->timer_delay_us = priv->event_mode ==
 280                                             MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
 281                                               MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
 282                                                                  priv->event_us;
 283         while (1) {
 284                 max = 0;
 285                 pthread_mutex_lock(&priv->vq_config_lock);
 286                 for (i = 0; i < priv->nr_virtqs; i++) {
 287                         cq = &priv->virtqs[i].eqp.cq;
 288                         if (cq->cq && !cq->armed) {
 289                                 uint32_t comp = mlx5_vdpa_cq_poll(cq);
 290
 291                                 if (comp) {
 292                                         /* Notify guest for descs consuming. */
 293                                         if (cq->callfd != -1)
 294                                                 eventfd_write(cq->callfd,
 295                                                               (eventfd_t)1);
 296                                         if (comp > max)
 297                                                 max = comp;
 298                                 }
 299                         }
 300                 }
 301                 current_tic = rte_rdtsc();
 302                 if (!max) {
 303                         /* No traffic ? stop timer and load interrupts. */
 304                         if (current_tic - priv->last_traffic_tic >=
 305                             rte_get_timer_hz() * priv->no_traffic_time_s) {
 306                                 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
 307                                         priv->vdev->device->name);
 308                                 mlx5_vdpa_arm_all_cqs(priv);
 309                                 pthread_mutex_unlock(&priv->vq_config_lock);
 310                                 pthread_mutex_lock(&priv->timer_lock);
 311                                 priv->timer_on = 0;
 312                                 while (!priv->timer_on)
 313                                         pthread_cond_wait(&priv->timer_cond,
 314                                                           &priv->timer_lock);
 315                                 pthread_mutex_unlock(&priv->timer_lock);
 316                                 priv->timer_delay_us = priv->event_mode ==
 317                                             MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
 318                                               MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
 319                                                                  priv->event_us;
 320                                 continue;
 321                         }
 322                 } else {
 323                         priv->last_traffic_tic = current_tic;
 324                 }
 325                 pthread_mutex_unlock(&priv->vq_config_lock);
 326                 mlx5_vdpa_timer_sleep(priv, max);
 327         }
 328         return NULL;
 329 }
 330
 331 static void
 332 mlx5_vdpa_interrupt_handler(void *cb_arg)
 333 {
 334         struct mlx5_vdpa_priv *priv = cb_arg;
 335 #ifdef HAVE_IBV_DEVX_EVENT
 336         union {
 337                 struct mlx5dv_devx_async_event_hdr event_resp;
 338                 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
 339         } out;
 340
 341         pthread_mutex_lock(&priv->vq_config_lock);
 342         while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
 343                                          sizeof(out.buf)) >=
 344                                        (ssize_t)sizeof(out.event_resp.cookie)) {
 345                 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
 346                                                (uintptr_t)out.event_resp.cookie;
 347                 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
 348                                                  struct mlx5_vdpa_event_qp, cq);
 349                 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
 350                                                    struct mlx5_vdpa_virtq, eqp);
 351
 352                 if (!virtq->enable)
 353                         continue;
 354                 mlx5_vdpa_cq_poll(cq);
 355                 /* Notify guest for descs consuming. */
 356                 if (cq->callfd != -1)
 357                         eventfd_write(cq->callfd, (eventfd_t)1);
 358                 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
 359                         mlx5_vdpa_cq_arm(priv, cq);
 360                         pthread_mutex_unlock(&priv->vq_config_lock);
 361                         return;
 362                 }
 363                 /* Don't arm again - timer will take control. */
 364                 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
 365                         " Timer is %s, cq ci is %u.\n",
 366                         priv->vdev->device->name,
 367                         (int)virtq->index, cq->cq->id,
 368                         priv->timer_on ? "on" : "off", cq->cq_ci);
 369                 cq->armed = 0;
 370         }
 371 #endif
 372
 373         /* Traffic detected: make sure timer is on. */
 374         priv->last_traffic_tic = rte_rdtsc();
 375         pthread_mutex_lock(&priv->timer_lock);
 376         if (!priv->timer_on) {
 377                 priv->timer_on = 1;
 378                 pthread_cond_signal(&priv->timer_cond);
 379         }
 380         pthread_mutex_unlock(&priv->timer_lock);
 381         pthread_mutex_unlock(&priv->vq_config_lock);
 382 }
 383
 384 int
 385 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
 386 {
 387         int ret;
 388
 389         if (!priv->eventc)
 390                 /* All virtqs are in poll mode. */
 391                 return 0;
 392         if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
 393                 pthread_mutex_init(&priv->timer_lock, NULL);
 394                 pthread_cond_init(&priv->timer_cond, NULL);
 395                 priv->timer_on = 0;
 396                 ret = pthread_create(&priv->timer_tid, NULL,
 397                                      mlx5_vdpa_poll_handle, (void *)priv);
 398                 if (ret) {
 399                         DRV_LOG(ERR, "Failed to create timer thread.");
 400                         return -1;
 401                 }
 402         }
 403         priv->intr_handle.fd = priv->eventc->fd;
 404         priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
 405         if (rte_intr_callback_register(&priv->intr_handle,
 406                                        mlx5_vdpa_interrupt_handler, priv)) {
 407                 priv->intr_handle.fd = 0;
 408                 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
 409                 goto error;
 410         }
 411         return 0;
 412 error:
 413         mlx5_vdpa_cqe_event_unset(priv);
 414         return -1;
 415 }
 416
 417 void
 418 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
 419 {
 420         int retries = MLX5_VDPA_INTR_RETRIES;
 421         int ret = -EAGAIN;
 422         void *status;
 423
 424         if (priv->intr_handle.fd) {
 425                 while (retries-- && ret == -EAGAIN) {
 426                         ret = rte_intr_callback_unregister(&priv->intr_handle,
 427                                                     mlx5_vdpa_interrupt_handler,
 428                                                     priv);
 429                         if (ret == -EAGAIN) {
 430                                 DRV_LOG(DEBUG, "Try again to unregister fd %d "
 431                                         "of CQ interrupt, retries = %d.",
 432                                         priv->intr_handle.fd, retries);
 433                                 rte_pause();
 434                         }
 435                 }
 436                 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
 437         }
 438         if (priv->timer_tid) {
 439                 pthread_cancel(priv->timer_tid);
 440                 pthread_join(priv->timer_tid, &status);
 441         }
 442         priv->timer_tid = 0;
 443 }
 444
 445 void
 446 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
 447 {
 448         if (eqp->sw_qp)
 449                 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
 450         if (eqp->umem_obj)
 451                 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
 452         if (eqp->umem_buf)
 453                 rte_free(eqp->umem_buf);
 454         if (eqp->fw_qp)
 455                 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
 456         mlx5_vdpa_cq_destroy(&eqp->cq);
 457         memset(eqp, 0, sizeof(*eqp));
 458 }
 459
 460 static int
 461 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
 462 {
 463         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
 464                                           eqp->sw_qp->id)) {
 465                 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
 466                         rte_errno);
 467                 return -1;
 468         }
 469         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
 470                                           eqp->fw_qp->id)) {
 471                 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
 472                         rte_errno);
 473                 return -1;
 474         }
 475         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
 476                                           eqp->sw_qp->id)) {
 477                 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
 478                         rte_errno);
 479                 return -1;
 480         }
 481         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
 482                                           eqp->fw_qp->id)) {
 483                 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
 484                         rte_errno);
 485                 return -1;
 486         }
 487         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
 488                                           eqp->sw_qp->id)) {
 489                 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
 490                         rte_errno);
 491                 return -1;
 492         }
 493         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
 494                                           eqp->fw_qp->id)) {
 495                 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
 496                         rte_errno);
 497                 return -1;
 498         }
 499         return 0;
 500 }
 501
 502 int
 503 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
 504                           int callfd, struct mlx5_vdpa_event_qp *eqp)
 505 {
 506         struct mlx5_devx_qp_attr attr = {0};
 507         uint16_t log_desc_n = rte_log2_u32(desc_n);
 508         uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
 509                                                        sizeof(*eqp->db_rec) * 2;
 510
 511         if (mlx5_vdpa_event_qp_global_prepare(priv))
 512                 return -1;
 513         if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
 514                 return -1;
 515         attr.pd = priv->pdn;
 516         eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
 517         if (!eqp->fw_qp) {
 518                 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
 519                 goto error;
 520         }
 521         eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
 522         if (!eqp->umem_buf) {
 523                 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
 524                 rte_errno = ENOMEM;
 525                 goto error;
 526         }
 527         eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
 528                                                (void *)(uintptr_t)eqp->umem_buf,
 529                                                umem_size,
 530                                                IBV_ACCESS_LOCAL_WRITE);
 531         if (!eqp->umem_obj) {
 532                 DRV_LOG(ERR, "Failed to register umem for SW QP.");
 533                 goto error;
 534         }
 535         attr.uar_index = priv->uar->page_id;
 536         attr.cqn = eqp->cq.cq->id;
 537         attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
 538         attr.rq_size = 1 << log_desc_n;
 539         attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
 540         attr.sq_size = 0; /* No need SQ. */
 541         attr.dbr_umem_valid = 1;
 542         attr.wq_umem_id = eqp->umem_obj->umem_id;
 543         attr.wq_umem_offset = 0;
 544         attr.dbr_umem_id = eqp->umem_obj->umem_id;
 545         attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
 546         eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
 547         if (!eqp->sw_qp) {
 548                 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
 549                 goto error;
 550         }
 551         eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
 552         if (mlx5_vdpa_qps2rts(eqp))
 553                 goto error;
 554         /* First ringing. */
 555         rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
 556         return 0;
 557 error:
 558         mlx5_vdpa_event_qp_destroy(eqp);
 559         return -1;
 560 }