4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <sys/types.h>
40 #include <sys/queue.h>
45 #include <rte_common.h>
46 #include <rte_byteorder.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_per_lcore.h>
53 #include <rte_launch.h>
54 #include <rte_atomic.h>
55 #include <rte_cycles.h>
56 #include <rte_prefetch.h>
57 #include <rte_lcore.h>
58 #include <rte_per_lcore.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_interrupts.h>
62 #include <rte_random.h>
63 #include <rte_debug.h>
64 #include <rte_ether.h>
65 #include <rte_ethdev.h>
67 #include <rte_mempool.h>
70 #include <rte_string_fns.h>
75 #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
76 #define NB_MBUF (32 * 1024)
79 * RX and TX Prefetch, Host, and Write-back threshold values should be
80 * carefully set for optimal performance. Consult the network
81 * controller's datasheet and supporting DPDK documentation for guidance
82 * on how these parameters should be set.
84 #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */
85 #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */
86 #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */
89 * These default values are optimized for use with the Intel(R) 82599 10 GbE
90 * Controller and the DPDK ixgbe PMD. Consider using other values for other
91 * network controllers and/or network drivers.
93 #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */
94 #define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */
95 #define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */
97 #define MAX_PKT_BURST 32
98 #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
100 #define TX_QUEUE_FLUSH_MASK 0xFFFFFFFF
101 #define TSC_COUNT_LIMIT 1000
103 #define ACTION_ENCRYPT 1
104 #define ACTION_DECRYPT 2
107 * Configurable number of RX/TX ring descriptors
109 #define RTE_TEST_RX_DESC_DEFAULT 128
110 #define RTE_TEST_TX_DESC_DEFAULT 512
111 static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;
112 static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
114 /* ethernet addresses of ports */
115 static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
117 /* mask of enabled ports */
118 static unsigned enabled_port_mask = 0;
119 static int promiscuous_on = 1; /**< Ports set in promiscuous mode on by default. */
121 /* list of enabled ports */
122 static uint32_t dst_ports[RTE_MAX_ETHPORTS];
126 struct rte_mbuf *m_table[MAX_PKT_BURST];
129 struct lcore_rx_queue {
134 #define MAX_RX_QUEUE_PER_LCORE 16
136 #define MAX_LCORE_PARAMS 1024
137 struct lcore_params {
143 static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
144 static struct lcore_params lcore_params_array_default[] = {
156 static struct lcore_params * lcore_params = lcore_params_array_default;
157 static uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
158 sizeof(lcore_params_array_default[0]);
160 static struct rte_eth_conf port_conf = {
162 .mq_mode = ETH_MQ_RX_RSS,
164 .header_split = 0, /**< Header Split disabled */
165 .hw_ip_checksum = 1, /**< IP checksum offload enabled */
166 .hw_vlan_filter = 0, /**< VLAN filtering disabled */
167 .jumbo_frame = 0, /**< Jumbo Frame Support disabled */
168 .hw_strip_crc = 0, /**< CRC stripped by hardware */
173 .rss_hf = ETH_RSS_IPV4 | ETH_RSS_IPV6,
177 .mq_mode = ETH_MQ_TX_NONE,
181 static const struct rte_eth_rxconf rx_conf = {
183 .pthresh = RX_PTHRESH,
184 .hthresh = RX_HTHRESH,
185 .wthresh = RX_WTHRESH,
189 static const struct rte_eth_txconf tx_conf = {
191 .pthresh = TX_PTHRESH,
192 .hthresh = TX_HTHRESH,
193 .wthresh = TX_WTHRESH,
195 .tx_free_thresh = 0, /* Use PMD default values */
196 .tx_rs_thresh = 0, /* Use PMD default values */
199 static struct rte_mempool * pktmbuf_pool[RTE_MAX_NUMA_NODES];
206 uint16_t rx_queue_list_pos;
207 struct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];
208 uint16_t tx_queue_id[RTE_MAX_ETHPORTS];
209 struct mbuf_table rx_mbuf;
210 uint32_t rx_mbuf_pos;
211 uint32_t rx_curr_queue;
212 struct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];
213 } __rte_cache_aligned;
215 static struct lcore_conf lcore_conf[RTE_MAX_LCORE];
217 static inline struct rte_mbuf *
218 nic_rx_get_packet(struct lcore_conf *qconf)
220 struct rte_mbuf *pkt;
222 if (unlikely(qconf->n_rx_queue == 0))
225 /* Look for the next queue with packets; return if none */
226 if (unlikely(qconf->rx_mbuf_pos == qconf->rx_mbuf.len)) {
229 qconf->rx_mbuf_pos = 0;
230 for (i = 0; i < qconf->n_rx_queue; i++) {
231 qconf->rx_mbuf.len = rte_eth_rx_burst(
232 qconf->rx_queue_list[qconf->rx_curr_queue].port_id,
233 qconf->rx_queue_list[qconf->rx_curr_queue].queue_id,
234 qconf->rx_mbuf.m_table, MAX_PKT_BURST);
236 qconf->rx_curr_queue++;
237 if (unlikely(qconf->rx_curr_queue == qconf->n_rx_queue))
238 qconf->rx_curr_queue = 0;
239 if (likely(qconf->rx_mbuf.len > 0))
242 if (unlikely(i == qconf->n_rx_queue))
246 /* Get the next packet from the current queue; if last packet, go to next queue */
247 pkt = qconf->rx_mbuf.m_table[qconf->rx_mbuf_pos];
248 qconf->rx_mbuf_pos++;
254 nic_tx_flush_queues(struct lcore_conf *qconf)
258 for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {
259 struct rte_mbuf **m_table = NULL;
260 uint16_t queueid, len;
263 if (likely((qconf->tx_mask & (1 << portid)) == 0))
266 len = qconf->tx_mbufs[portid].len;
267 if (likely(len == 0))
270 queueid = qconf->tx_queue_id[portid];
271 m_table = qconf->tx_mbufs[portid].m_table;
273 n = rte_eth_tx_burst(portid, queueid, m_table, len);
274 for (i = n; i < len; i++){
275 rte_pktmbuf_free(m_table[i]);
278 qconf->tx_mbufs[portid].len = 0;
281 qconf->tx_mask = TX_QUEUE_FLUSH_MASK;
285 nic_tx_send_packet(struct rte_mbuf *pkt, uint8_t port)
287 struct lcore_conf *qconf;
291 if (unlikely(pkt == NULL)) {
295 lcoreid = rte_lcore_id();
296 qconf = &lcore_conf[lcoreid];
298 len = qconf->tx_mbufs[port].len;
299 qconf->tx_mbufs[port].m_table[len] = pkt;
302 /* enough pkts to be sent */
303 if (unlikely(len == MAX_PKT_BURST)) {
307 queueid = qconf->tx_queue_id[port];
308 n = rte_eth_tx_burst(port, queueid, qconf->tx_mbufs[port].m_table, MAX_PKT_BURST);
309 for (i = n; i < MAX_PKT_BURST; i++){
310 rte_pktmbuf_free(qconf->tx_mbufs[port].m_table[i]);
313 qconf->tx_mask &= ~(1 << port);
317 qconf->tx_mbufs[port].len = len;
320 /* main processing loop */
321 static __attribute__((noreturn)) int
322 main_loop(__attribute__((unused)) void *dummy)
325 struct lcore_conf *qconf;
326 const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
328 lcoreid = rte_lcore_id();
329 qconf = &lcore_conf[lcoreid];
331 printf("Thread %u starting...\n", lcoreid);
334 struct rte_mbuf *pkt;
335 uint32_t pkt_from_nic_rx = 0;
338 /* Flush TX queues */
340 if (unlikely(qconf->tsc_count == TSC_COUNT_LIMIT)) {
341 uint64_t tsc, diff_tsc;
345 diff_tsc = tsc - qconf->tsc;
346 if (unlikely(diff_tsc > drain_tsc)) {
347 nic_tx_flush_queues(qconf);
348 crypto_flush_tx_queue(lcoreid);
352 qconf->tsc_count = 0;
356 * Check the Intel QuickAssist queues first
359 pkt = (struct rte_mbuf *) crypto_get_next_response();
361 pkt = nic_rx_get_packet(qconf);
366 /* Send packet to either QAT encrypt, QAT decrypt or NIC TX */
367 if (pkt_from_nic_rx) {
368 struct ipv4_hdr *ip = (struct ipv4_hdr *) (rte_pktmbuf_mtod(pkt, unsigned char *) +
369 sizeof(struct ether_hdr));
370 if (ip->src_addr & rte_cpu_to_be_32(ACTION_ENCRYPT)) {
371 if (CRYPTO_RESULT_FAIL == crypto_encrypt(pkt,
372 (enum cipher_alg)((ip->src_addr >> 16) & 0xFF),
373 (enum hash_alg)((ip->src_addr >> 8) & 0xFF)))
374 rte_pktmbuf_free(pkt);
378 if (ip->src_addr & rte_cpu_to_be_32(ACTION_DECRYPT)) {
379 if(CRYPTO_RESULT_FAIL == crypto_decrypt(pkt,
380 (enum cipher_alg)((ip->src_addr >> 16) & 0xFF),
381 (enum hash_alg)((ip->src_addr >> 8) & 0xFF)))
382 rte_pktmbuf_free(pkt);
387 port = dst_ports[pkt->pkt.in_port];
389 /* Transmit the packet */
390 nic_tx_send_packet(pkt, (uint8_t)port);
394 static inline unsigned
395 get_port_max_rx_queues(uint8_t port_id)
397 struct rte_eth_dev_info dev_info;
399 rte_eth_dev_info_get(port_id, &dev_info);
400 return dev_info.max_rx_queues;
403 static inline unsigned
404 get_port_max_tx_queues(uint8_t port_id)
406 struct rte_eth_dev_info dev_info;
408 rte_eth_dev_info_get(port_id, &dev_info);
409 return dev_info.max_tx_queues;
413 check_lcore_params(void)
417 for (i = 0; i < nb_lcore_params; ++i) {
418 if (lcore_params[i].queue_id >= get_port_max_rx_queues(lcore_params[i].port_id)) {
419 printf("invalid queue number: %hhu\n", lcore_params[i].queue_id);
422 if (!rte_lcore_is_enabled(lcore_params[i].lcore_id)) {
423 printf("error: lcore %hhu is not enabled in lcore mask\n",
424 lcore_params[i].lcore_id);
432 check_port_config(const unsigned nb_ports)
437 for (i = 0; i < nb_lcore_params; ++i) {
438 portid = lcore_params[i].port_id;
439 if ((enabled_port_mask & (1 << portid)) == 0) {
440 printf("port %u is not enabled in port mask\n", portid);
443 if (portid >= nb_ports) {
444 printf("port %u is not present on the board\n", portid);
452 get_port_n_rx_queues(const uint8_t port)
457 for (i = 0; i < nb_lcore_params; ++i) {
458 if (lcore_params[i].port_id == port && lcore_params[i].queue_id > queue)
459 queue = lcore_params[i].queue_id;
461 return (uint8_t)(++queue);
465 init_lcore_rx_queues(void)
467 uint16_t i, nb_rx_queue;
470 for (i = 0; i < nb_lcore_params; ++i) {
471 lcore = lcore_params[i].lcore_id;
472 nb_rx_queue = lcore_conf[lcore].n_rx_queue;
473 if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {
474 printf("error: too many queues (%u) for lcore: %u\n",
475 (unsigned)nb_rx_queue + 1, (unsigned)lcore);
478 lcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =
479 lcore_params[i].port_id;
480 lcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =
481 lcore_params[i].queue_id;
482 lcore_conf[lcore].n_rx_queue++;
489 print_usage(const char *prgname)
491 printf ("%s [EAL options] -- -p PORTMASK [--no-promisc]"
492 " [--config '(port,queue,lcore)[,(port,queue,lcore)]'\n"
493 " -p PORTMASK: hexadecimal bitmask of ports to configure\n"
494 " --no-promisc: disable promiscuous mode (default is ON)\n"
495 " --config '(port,queue,lcore)': rx queues configuration\n",
500 parse_portmask(const char *portmask)
505 /* parse hexadecimal string */
506 pm = strtoul(portmask, &end, 16);
507 if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
514 parse_config(const char *q_arg)
517 const char *p, *p_end = q_arg;
525 unsigned long int_fld[_NUM_FLD];
526 char *str_fld[_NUM_FLD];
532 while ((p = strchr(p_end,'(')) != NULL) {
533 if (nb_lcore_params >= MAX_LCORE_PARAMS) {
534 printf("exceeded max number of lcore params: %hu\n",
539 if((p_end = strchr(p,')')) == NULL)
543 if(size >= sizeof(s))
546 rte_snprintf(s, sizeof(s), "%.*s", size, p);
547 if (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)
549 for (i = 0; i < _NUM_FLD; i++) {
551 int_fld[i] = strtoul(str_fld[i], &end, 0);
552 if (errno != 0 || end == str_fld[i] || int_fld[i] > 255)
555 lcore_params_array[nb_lcore_params].port_id = (uint8_t)int_fld[FLD_PORT];
556 lcore_params_array[nb_lcore_params].queue_id = (uint8_t)int_fld[FLD_QUEUE];
557 lcore_params_array[nb_lcore_params].lcore_id = (uint8_t)int_fld[FLD_LCORE];
560 lcore_params = lcore_params_array;
564 /* Parse the argument given in the command line of the application */
566 parse_args(int argc, char **argv)
571 char *prgname = argv[0];
572 static struct option lgopts[] = {
574 {"no-promisc", 0, 0, 0},
580 while ((opt = getopt_long(argc, argvopt, "p:",
581 lgopts, &option_index)) != EOF) {
586 enabled_port_mask = parse_portmask(optarg);
587 if (enabled_port_mask == 0) {
588 printf("invalid portmask\n");
589 print_usage(prgname);
596 if (strcmp(lgopts[option_index].name, "config") == 0) {
597 ret = parse_config(optarg);
599 printf("invalid config\n");
600 print_usage(prgname);
604 if (strcmp(lgopts[option_index].name, "no-promisc") == 0) {
605 printf("Promiscuous mode disabled\n");
610 print_usage(prgname);
615 if (enabled_port_mask == 0) {
616 printf("portmask not specified\n");
617 print_usage(prgname);
622 argv[optind-1] = prgname;
625 optind = 0; /* reset getopt lib */
630 print_ethaddr(const char *name, const struct ether_addr *eth_addr)
632 printf ("%s%02X:%02X:%02X:%02X:%02X:%02X", name,
633 eth_addr->addr_bytes[0],
634 eth_addr->addr_bytes[1],
635 eth_addr->addr_bytes[2],
636 eth_addr->addr_bytes[3],
637 eth_addr->addr_bytes[4],
638 eth_addr->addr_bytes[5]);
644 const unsigned flags = 0;
649 RTE_LCORE_FOREACH(lcoreid) {
650 socketid = rte_lcore_to_socket_id(lcoreid);
651 if (socketid >= RTE_MAX_NUMA_NODES) {
652 printf("Socket %d of lcore %u is out of range %d\n",
653 socketid, lcoreid, RTE_MAX_NUMA_NODES);
656 if (pktmbuf_pool[socketid] == NULL) {
657 rte_snprintf(s, sizeof(s), "mbuf_pool_%d", socketid);
658 pktmbuf_pool[socketid] =
659 rte_mempool_create(s, NB_MBUF, MBUF_SIZE, 32,
660 sizeof(struct rte_pktmbuf_pool_private),
661 rte_pktmbuf_pool_init, NULL,
662 rte_pktmbuf_init, NULL,
664 if (pktmbuf_pool[socketid] == NULL) {
665 printf("Cannot init mbuf pool on socket %d\n", socketid);
668 printf("Allocated mbuf pool on socket %d\n", socketid);
675 MAIN(int argc, char **argv)
677 struct lcore_conf *qconf;
678 struct rte_eth_link link;
683 uint32_t nb_tx_queue;
684 uint8_t portid, nb_rx_queue, queue, socketid, last_port;
685 unsigned nb_ports_in_mask = 0;
688 ret = rte_eal_init(argc, argv);
694 /* parse application arguments (after the EAL ones) */
695 ret = parse_args(argc, argv);
700 #ifdef RTE_LIBRTE_IXGBE_PMD
701 if (rte_ixgbe_pmd_init() < 0)
702 rte_panic("Cannot init ixgbe pmd\n");
705 if (rte_eal_pci_probe() < 0)
706 rte_panic("Cannot probe PCI\n");
708 if (check_lcore_params() < 0)
709 rte_panic("check_lcore_params failed\n");
711 ret = init_lcore_rx_queues();
719 nb_ports = rte_eth_dev_count();
720 if (nb_ports > RTE_MAX_ETHPORTS)
721 nb_ports = RTE_MAX_ETHPORTS;
723 if (check_port_config(nb_ports) < 0)
724 rte_panic("check_port_config failed\n");
726 /* reset dst_ports */
727 for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)
728 dst_ports[portid] = 0;
732 * Each logical core is assigned a dedicated TX queue on each port.
734 for (portid = 0; portid < nb_ports; portid++) {
735 /* skip ports that are not enabled */
736 if ((enabled_port_mask & (1 << portid)) == 0)
739 if (nb_ports_in_mask % 2) {
740 dst_ports[portid] = last_port;
741 dst_ports[last_port] = portid;
748 if (nb_ports_in_mask % 2) {
749 printf("Notice: odd number of ports in portmask.\n");
750 dst_ports[last_port] = last_port;
753 /* initialize all ports */
754 for (portid = 0; portid < nb_ports; portid++) {
755 /* skip ports that are not enabled */
756 if ((enabled_port_mask & (1 << portid)) == 0) {
757 printf("\nSkipping disabled port %d\n", portid);
762 printf("Initializing port %d ... ", portid );
765 nb_rx_queue = get_port_n_rx_queues(portid);
766 if (nb_rx_queue > get_port_max_rx_queues(portid))
767 rte_panic("Number of rx queues %d exceeds max number of rx queues %u"
768 " for port %d\n", nb_rx_queue, get_port_max_rx_queues(portid),
770 nb_tx_queue = rte_lcore_count();
771 if (nb_tx_queue > get_port_max_tx_queues(portid))
772 rte_panic("Number of lcores %u exceeds max number of tx queues %u"
773 " for port %d\n", nb_tx_queue, get_port_max_tx_queues(portid),
775 printf("Creating queues: nb_rxq=%d nb_txq=%u... ",
776 nb_rx_queue, (unsigned)nb_tx_queue );
777 ret = rte_eth_dev_configure(portid, nb_rx_queue,
778 (uint16_t)nb_tx_queue, &port_conf);
780 rte_panic("Cannot configure device: err=%d, port=%d\n",
783 rte_eth_macaddr_get(portid, &ports_eth_addr[portid]);
784 print_ethaddr(" Address:", &ports_eth_addr[portid]);
787 /* init one TX queue per couple (lcore,port) */
789 RTE_LCORE_FOREACH(lcoreid) {
790 socketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);
791 printf("txq=%u,%d,%d ", lcoreid, queueid, socketid);
793 ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,
796 rte_panic("rte_eth_tx_queue_setup: err=%d, "
797 "port=%d\n", ret, portid);
799 qconf = &lcore_conf[lcoreid];
800 qconf->tx_queue_id[portid] = queueid;
806 RTE_LCORE_FOREACH(lcoreid) {
807 qconf = &lcore_conf[lcoreid];
808 printf("\nInitializing rx queues on lcore %u ... ", lcoreid );
811 for(queue = 0; queue < qconf->n_rx_queue; ++queue) {
812 portid = qconf->rx_queue_list[queue].port_id;
813 queueid = qconf->rx_queue_list[queue].queue_id;
814 socketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);
815 printf("rxq=%d,%d,%d ", portid, queueid, socketid);
818 ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,
819 socketid, &rx_conf, pktmbuf_pool[socketid]);
821 rte_panic("rte_eth_rx_queue_setup: err=%d,"
822 "port=%d\n", ret, portid);
829 for (portid = 0; portid < nb_ports; portid++) {
830 if ((enabled_port_mask & (1 << portid)) == 0)
833 ret = rte_eth_dev_start(portid);
835 rte_panic("rte_eth_dev_start: err=%d, port=%d\n",
838 printf("done: Port %d ", portid);
840 /* get link status */
841 rte_eth_link_get(portid, &link);
842 if (link.link_status)
843 printf(" Link Up - speed %u Mbps - %s\n",
844 (unsigned) link.link_speed,
845 (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
846 ("full-duplex") : ("half-duplex\n"));
848 printf(" Link Down\n");
850 * If enabled, put device in promiscuous mode.
851 * This allows IO forwarding mode to forward packets
852 * to itself through 2 cross-connected ports of the
856 rte_eth_promiscuous_enable(portid);
858 printf("Crypto: Initializing Crypto...\n");
859 if (crypto_init() != 0)
862 RTE_LCORE_FOREACH(lcoreid) {
863 if (per_core_crypto_init(lcoreid) != 0) {
864 printf("Crypto: Cannot init lcore crypto on lcore %u\n", (unsigned)lcoreid);
868 printf("Crypto: Initialization complete\n");
869 /* launch per-lcore init on every lcore */
870 rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);
871 RTE_LCORE_FOREACH_SLAVE(lcoreid) {
872 if (rte_eal_wait_lcore(lcoreid) < 0)