examples/ip_pipeline/pipeline_ipv4_frag.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
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  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
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  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <stdint.h>
  37
  38 #include <rte_common.h>
  39 #include <rte_byteorder.h>
  40 #include <rte_log.h>
  41 #include <rte_malloc.h>
  42 #include <rte_ethdev.h>
  43 #include <rte_mbuf.h>
  44 #include <rte_ether.h>
  45 #include <rte_ip.h>
  46
  47 #include <rte_port_ethdev.h>
  48 #include <rte_port_ring.h>
  49 #include <rte_port_frag.h>
  50 #include <rte_table_stub.h>
  51 #include <rte_pipeline.h>
  52
  53 #include "main.h"
  54
  55 void
  56 app_main_loop_pipeline_ipv4_frag(void) {
  57         struct rte_pipeline *p;
  58         uint32_t port_in_id[APP_MAX_PORTS];
  59         uint32_t port_out_id[APP_MAX_PORTS];
  60         uint32_t table_id[APP_MAX_PORTS];
  61         uint32_t i;
  62
  63         uint32_t core_id = rte_lcore_id();
  64         struct app_core_params *core_params = app_get_core_params(core_id);
  65
  66         if ((core_params == NULL) ||
  67                 (core_params->core_type != APP_CORE_IPV4_FRAG))
  68                 rte_panic("Core %u misconfiguration\n", core_id);
  69
  70         RTE_LOG(INFO, USER1, "Core %u is doing IPv4 fragmentation\n", core_id);
  71
  72         /* Pipeline configuration */
  73         struct rte_pipeline_params pipeline_params = {
  74                 .name = "pipeline",
  75                 .socket_id = rte_socket_id(),
  76         };
  77
  78         p = rte_pipeline_create(&pipeline_params);
  79         if (p == NULL)
  80                 rte_panic("%s: Unable to configure the pipeline\n", __func__);
  81
  82         /* Input port configuration */
  83         for (i = 0; i < app.n_ports; i++) {
  84                 struct rte_port_ring_reader_ipv4_frag_params
  85                         port_frag_params = {
  86                         .ring = app.rings[core_params->swq_in[i]],
  87                         .mtu = 1500,
  88                         .metadata_size = sizeof(struct app_pkt_metadata),
  89                         .pool_direct = app.pool,
  90                         .pool_indirect = app.indirect_pool,
  91                 };
  92
  93                 struct rte_pipeline_port_in_params port_params = {
  94                         .ops = &rte_port_ring_reader_ipv4_frag_ops,
  95                         .arg_create = (void *) &port_frag_params,
  96                         .f_action = NULL,
  97                         .arg_ah = NULL,
  98                         .burst_size = app.bsz_swq_rd,
  99                 };
 100
 101                 if (rte_pipeline_port_in_create(p, &port_params,
 102                         &port_in_id[i]))
 103                         rte_panic("%s: Unable to configure input port %i\n",
 104                                 __func__, i);
 105         }
 106
 107         /* Output port configuration */
 108         for (i = 0; i < app.n_ports; i++) {
 109                 struct rte_port_ring_writer_params port_ring_params = {
 110                         .ring = app.rings[core_params->swq_out[i]],
 111                         .tx_burst_sz = app.bsz_swq_wr,
 112                 };
 113
 114                 struct rte_pipeline_port_out_params port_params = {
 115                         .ops = &rte_port_ring_writer_ops,
 116                         .arg_create = (void *) &port_ring_params,
 117                         .f_action = NULL,
 118                         .f_action_bulk = NULL,
 119                         .arg_ah = NULL,
 120                 };
 121
 122                 if (rte_pipeline_port_out_create(p, &port_params,
 123                         &port_out_id[i]))
 124                         rte_panic("%s: Unable to configure output port %i\n",
 125                                 __func__, i);
 126         }
 127
 128         /* Table configuration */
 129         for (i = 0; i < app.n_ports; i++) {
 130                 struct rte_pipeline_table_params table_params = {
 131                         .ops = &rte_table_stub_ops,
 132                         .arg_create = NULL,
 133                         .f_action_hit = NULL,
 134                         .f_action_miss = NULL,
 135                         .arg_ah = NULL,
 136                         .action_data_size = 0,
 137                 };
 138
 139                 if (rte_pipeline_table_create(p, &table_params, &table_id[i]))
 140                         rte_panic("%s: Unable to configure table %u\n",
 141                                 __func__, table_id[i]);
 142         }
 143
 144         /* Interconnecting ports and tables */
 145         for (i = 0; i < app.n_ports; i++)
 146                 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
 147                         table_id[i]))
 148                         rte_panic("%s: Unable to connect input port %u to "
 149                                 "table %u\n", __func__, port_in_id[i],
 150                                 table_id[i]);
 151
 152         /* Add entries to tables */
 153         for (i = 0; i < app.n_ports; i++) {
 154                 struct rte_pipeline_table_entry default_entry = {
 155                         .action = RTE_PIPELINE_ACTION_PORT,
 156                         {.port_id = port_out_id[i]},
 157                 };
 158
 159                 struct rte_pipeline_table_entry *default_entry_ptr;
 160
 161                 if (rte_pipeline_table_default_entry_add(p, table_id[i],
 162                         &default_entry, &default_entry_ptr))
 163                         rte_panic("%s: Unable to add default entry to "
 164                                 "table %u\n", __func__, table_id[i]);
 165         }
 166
 167         /* Enable input ports */
 168         for (i = 0; i < app.n_ports; i++)
 169                 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
 170                         rte_panic("Unable to enable input port %u\n",
 171                                 port_in_id[i]);
 172
 173         /* Check pipeline consistency */
 174         if (rte_pipeline_check(p) < 0)
 175                 rte_panic("%s: Pipeline consistency check failed\n", __func__);
 176
 177         /* Run-time */
 178         for (i = 0; ; i++) {
 179                 rte_pipeline_run(p);
 180
 181                 if ((i & APP_FLUSH) == 0)
 182                         rte_pipeline_flush(p);
 183         }
 184 }