examples/ip_pipeline/pipeline_ipv4_ras.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
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  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
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  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <stdint.h>
  37
  38 #include <rte_common.h>
  39 #include <rte_byteorder.h>
  40 #include <rte_log.h>
  41 #include <rte_malloc.h>
  42 #include <rte_ethdev.h>
  43 #include <rte_mbuf.h>
  44 #include <rte_ether.h>
  45 #include <rte_ip.h>
  46
  47 #include <rte_port_ethdev.h>
  48 #include <rte_port_ring.h>
  49 #include <rte_port_ras.h>
  50 #include <rte_table_stub.h>
  51 #include <rte_pipeline.h>
  52
  53 #include "main.h"
  54
  55 void
  56 app_main_loop_pipeline_ipv4_ras(void) {
  57         struct rte_pipeline *p;
  58         uint32_t port_in_id[APP_MAX_PORTS];
  59         uint32_t port_out_id[APP_MAX_PORTS];
  60         uint32_t table_id[APP_MAX_PORTS];
  61         uint32_t i;
  62
  63         uint32_t core_id = rte_lcore_id();
  64         struct app_core_params *core_params = app_get_core_params(core_id);
  65
  66         if ((core_params == NULL) ||
  67                 (core_params->core_type != APP_CORE_IPV4_RAS)) {
  68                 rte_panic("Core %u misconfiguration\n", core_id);
  69         }
  70
  71         RTE_LOG(INFO, USER1, "Core %u is doing IPv4 reassembly\n", core_id);
  72
  73         /* Pipeline configuration */
  74         struct rte_pipeline_params pipeline_params = {
  75                 .name = "pipeline",
  76                 .socket_id = rte_socket_id(),
  77         };
  78
  79         p = rte_pipeline_create(&pipeline_params);
  80         if (p == NULL)
  81                 rte_panic("%s: Unable to configure the pipeline\n", __func__);
  82
  83         /* Input port configuration */
  84         for (i = 0; i < app.n_ports; i++) {
  85                 struct rte_port_ring_reader_params port_ring_params = {
  86                         .ring = app.rings[core_params->swq_in[i]],
  87                 };
  88
  89                 struct rte_pipeline_port_in_params port_params = {
  90                         .ops = &rte_port_ring_reader_ops,
  91                         .arg_create = (void *) &port_ring_params,
  92                         .f_action = NULL,
  93                         .arg_ah = NULL,
  94                         .burst_size = app.bsz_swq_rd,
  95                 };
  96
  97                 if (rte_pipeline_port_in_create(p, &port_params,
  98                         &port_in_id[i]))
  99                         rte_panic("%s: Unable to configure input port %i\n",
 100                                 __func__, i);
 101         }
 102
 103         /* Output port configuration */
 104         for (i = 0; i < app.n_ports; i++) {
 105                 struct rte_port_ring_writer_params port_ring_ipv4_ras_params = {
 106                         .ring = app.rings[core_params->swq_out[i]],
 107                         .tx_burst_sz = app.bsz_swq_wr,
 108                 };
 109
 110                 struct rte_pipeline_port_out_params port_params = {
 111                         .ops = &rte_port_ring_writer_ipv4_ras_ops,
 112                         .arg_create = (void *) &port_ring_ipv4_ras_params,
 113                         .f_action = NULL,
 114                         .f_action_bulk = NULL,
 115                         .arg_ah = NULL,
 116                 };
 117
 118                 if (rte_pipeline_port_out_create(p, &port_params,
 119                         &port_out_id[i]))
 120                         rte_panic("%s: Unable to configure output port %i\n",
 121                                 __func__, i);
 122         }
 123
 124         /* Table configuration */
 125         for (i = 0; i < app.n_ports; i++) {
 126                 struct rte_pipeline_table_params table_params = {
 127                         .ops = &rte_table_stub_ops,
 128                         .arg_create = NULL,
 129                         .f_action_hit = NULL,
 130                         .f_action_miss = NULL,
 131                         .arg_ah = NULL,
 132                         .action_data_size = 0,
 133                 };
 134
 135                 if (rte_pipeline_table_create(p, &table_params, &table_id[i]))
 136                         rte_panic("%s: Unable to configure table %u\n",
 137                                 __func__, table_id[i]);
 138         }
 139
 140         /* Interconnecting ports and tables */
 141         for (i = 0; i < app.n_ports; i++)
 142                 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
 143                         table_id[i]))
 144                         rte_panic("%s: Unable to connect input port %u to "
 145                                 "table %u\n", __func__, port_in_id[i],
 146                                 table_id[i]);
 147
 148         /* Add entries to tables */
 149         for (i = 0; i < app.n_ports; i++) {
 150                 struct rte_pipeline_table_entry default_entry = {
 151                         .action = RTE_PIPELINE_ACTION_PORT,
 152                         {.port_id = port_out_id[i]},
 153                 };
 154
 155                 struct rte_pipeline_table_entry *default_entry_ptr;
 156
 157                 if (rte_pipeline_table_default_entry_add(p, table_id[i],
 158                         &default_entry,
 159                         &default_entry_ptr))
 160                         rte_panic("%s: Unable to add default entry to "
 161                                 "table %u\n", __func__, table_id[i]);
 162         }
 163
 164         /* Enable input ports */
 165         for (i = 0; i < app.n_ports; i++)
 166                 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
 167                         rte_panic("Unable to enable input port %u\n",
 168                                 port_in_id[i]);
 169
 170         /* Check pipeline consistency */
 171         if (rte_pipeline_check(p) < 0)
 172                 rte_panic("%s: Pipeline consistency check failed\n", __func__);
 173
 174         /* Run-time */
 175         for (i = 0; ; i++) {
 176                 rte_pipeline_run(p);
 177
 178                 if ((i & APP_FLUSH) == 0)
 179                         rte_pipeline_flush(p);
 180         }
 181 }