4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef APP_MAX_SOCKETS
40 #define APP_MAX_SOCKETS 2
43 #ifndef APP_MAX_LCORES
44 #define APP_MAX_LCORES RTE_MAX_LCORE
47 #ifndef APP_MAX_NIC_PORTS
48 #define APP_MAX_NIC_PORTS RTE_MAX_ETHPORTS
51 #ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT
52 #define APP_MAX_RX_QUEUES_PER_NIC_PORT 128
55 #ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT
56 #define APP_MAX_TX_QUEUES_PER_NIC_PORT 128
59 #ifndef APP_MAX_IO_LCORES
60 #define APP_MAX_IO_LCORES 16
62 #if (APP_MAX_IO_LCORES > APP_MAX_LCORES)
63 #error "APP_MAX_IO_LCORES is too big"
66 #ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE
67 #define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16
70 #ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE
71 #define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16
73 #if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)
74 #error "APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big"
77 #ifndef APP_MAX_WORKER_LCORES
78 #define APP_MAX_WORKER_LCORES 16
80 #if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)
81 #error "APP_MAX_WORKER_LCORES is too big"
86 #ifndef APP_DEFAULT_MBUF_SIZE
87 #define APP_DEFAULT_MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
90 #ifndef APP_DEFAULT_MEMPOOL_BUFFERS
91 #define APP_DEFAULT_MEMPOOL_BUFFERS 8192 * 4
94 #ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE
95 #define APP_DEFAULT_MEMPOOL_CACHE_SIZE 256
99 #ifndef APP_MAX_LPM_RULES
100 #define APP_MAX_LPM_RULES 1024
104 #ifndef APP_DEFAULT_NIC_RX_RING_SIZE
105 #define APP_DEFAULT_NIC_RX_RING_SIZE 1024
109 * RX and TX Prefetch, Host, and Write-back threshold values should be
110 * carefully set for optimal performance. Consult the network
111 * controller's datasheet and supporting DPDK documentation for guidance
112 * on how these parameters should be set.
114 #ifndef APP_DEFAULT_NIC_RX_PTHRESH
115 #define APP_DEFAULT_NIC_RX_PTHRESH 8
118 #ifndef APP_DEFAULT_NIC_RX_HTHRESH
119 #define APP_DEFAULT_NIC_RX_HTHRESH 8
122 #ifndef APP_DEFAULT_NIC_RX_WTHRESH
123 #define APP_DEFAULT_NIC_RX_WTHRESH 4
126 #ifndef APP_DEFAULT_NIC_RX_FREE_THRESH
127 #define APP_DEFAULT_NIC_RX_FREE_THRESH 64
130 #ifndef APP_DEFAULT_NIC_RX_DROP_EN
131 #define APP_DEFAULT_NIC_RX_DROP_EN 0
135 #ifndef APP_DEFAULT_NIC_TX_RING_SIZE
136 #define APP_DEFAULT_NIC_TX_RING_SIZE 1024
140 * These default values are optimized for use with the Intel(R) 82599 10 GbE
141 * Controller and the DPDK ixgbe PMD. Consider using other values for other
142 * network controllers and/or network drivers.
144 #ifndef APP_DEFAULT_NIC_TX_PTHRESH
145 #define APP_DEFAULT_NIC_TX_PTHRESH 36
148 #ifndef APP_DEFAULT_NIC_TX_HTHRESH
149 #define APP_DEFAULT_NIC_TX_HTHRESH 0
152 #ifndef APP_DEFAULT_NIC_TX_WTHRESH
153 #define APP_DEFAULT_NIC_TX_WTHRESH 0
156 #ifndef APP_DEFAULT_NIC_TX_FREE_THRESH
157 #define APP_DEFAULT_NIC_TX_FREE_THRESH 0
160 #ifndef APP_DEFAULT_NIC_TX_RS_THRESH
161 #define APP_DEFAULT_NIC_TX_RS_THRESH 0
165 #ifndef APP_DEFAULT_RING_RX_SIZE
166 #define APP_DEFAULT_RING_RX_SIZE 1024
169 #ifndef APP_DEFAULT_RING_TX_SIZE
170 #define APP_DEFAULT_RING_TX_SIZE 1024
174 #ifndef APP_MBUF_ARRAY_SIZE
175 #define APP_MBUF_ARRAY_SIZE 512
178 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ
179 #define APP_DEFAULT_BURST_SIZE_IO_RX_READ 144
181 #if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)
182 #error "APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big"
185 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE
186 #define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE 144
188 #if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)
189 #error "APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big"
192 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ
193 #define APP_DEFAULT_BURST_SIZE_IO_TX_READ 144
195 #if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)
196 #error "APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big"
199 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE
200 #define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE 144
202 #if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)
203 #error "APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big"
206 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ
207 #define APP_DEFAULT_BURST_SIZE_WORKER_READ 144
209 #if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)
210 #error "APP_DEFAULT_BURST_SIZE_WORKER_READ is too big"
213 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE
214 #define APP_DEFAULT_BURST_SIZE_WORKER_WRITE 144
216 #if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)
217 #error "APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big"
220 /* Load balancing logic */
221 #ifndef APP_DEFAULT_IO_RX_LB_POS
222 #define APP_DEFAULT_IO_RX_LB_POS 29
224 #if (APP_DEFAULT_IO_RX_LB_POS >= 64)
225 #error "APP_DEFAULT_IO_RX_LB_POS is too big"
228 struct app_mbuf_array {
229 struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
233 enum app_lcore_type {
234 e_APP_LCORE_DISABLED = 0,
239 struct app_lcore_params_io {
246 } nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
247 uint32_t n_nic_queues;
250 struct rte_ring *rings[APP_MAX_WORKER_LCORES];
253 /* Internal buffers */
254 struct app_mbuf_array mbuf_in;
255 struct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];
256 uint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];
259 uint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
260 uint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
261 uint32_t rings_count[APP_MAX_WORKER_LCORES];
262 uint32_t rings_iters[APP_MAX_WORKER_LCORES];
268 struct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
271 uint8_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
272 uint32_t n_nic_ports;
274 /* Internal buffers */
275 struct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
276 uint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
279 uint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
280 uint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
281 uint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
282 uint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
286 struct app_lcore_params_worker {
288 struct rte_ring *rings_in[APP_MAX_IO_LCORES];
290 struct rte_ring *rings_out[APP_MAX_NIC_PORTS];
293 struct rte_lpm *lpm_table;
296 /* Internal buffers */
297 struct app_mbuf_array mbuf_in;
298 struct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];
299 uint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];
302 uint32_t rings_in_count[APP_MAX_IO_LCORES];
303 uint32_t rings_in_iters[APP_MAX_IO_LCORES];
304 uint32_t rings_out_count[APP_MAX_NIC_PORTS];
305 uint32_t rings_out_iters[APP_MAX_NIC_PORTS];
308 struct app_lcore_params {
310 struct app_lcore_params_io io;
311 struct app_lcore_params_worker worker;
313 enum app_lcore_type type;
314 struct rte_mempool *pool;
315 } __rte_cache_aligned;
317 struct app_lpm_rule {
325 struct app_lcore_params lcore_params[APP_MAX_LCORES];
328 uint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];
329 uint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];
332 struct rte_mempool *pools[APP_MAX_SOCKETS];
335 struct rte_lpm *lpm_tables[APP_MAX_SOCKETS];
336 struct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];
337 uint32_t n_lpm_rules;
340 uint32_t nic_rx_ring_size;
341 uint32_t nic_tx_ring_size;
342 uint32_t ring_rx_size;
343 uint32_t ring_tx_size;
346 uint32_t burst_size_io_rx_read;
347 uint32_t burst_size_io_rx_write;
348 uint32_t burst_size_io_tx_read;
349 uint32_t burst_size_io_tx_write;
350 uint32_t burst_size_worker_read;
351 uint32_t burst_size_worker_write;
355 } __rte_cache_aligned;
357 extern struct app_params app;
359 int app_parse_args(int argc, char **argv);
360 void app_print_usage(void);
362 int app_lcore_main_loop(void *arg);
364 int app_get_nic_rx_queues_per_port(uint8_t port);
365 int app_get_lcore_for_nic_rx(uint8_t port, uint8_t queue, uint32_t *lcore_out);
366 int app_get_lcore_for_nic_tx(uint8_t port, uint32_t *lcore_out);
367 int app_is_socket_used(uint32_t socket);
368 uint32_t app_get_lcores_io_rx(void);
369 uint32_t app_get_lcores_worker(void);
370 void app_print_params(void);
372 #ifdef RTE_EXEC_ENV_BAREMETAL
378 int MAIN(int argc, char **argv);
380 #endif /* _MAIN_H_ */