2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER0B_AVAILABLE
69 #define TIMER1_AVAILABLE
70 #define TIMER1A_AVAILABLE
71 #define TIMER1B_AVAILABLE
73 /* overflow interrupt number */
74 #define SIG_OVERFLOW0_NUM 0
75 #define SIG_OVERFLOW1_NUM 1
76 #define SIG_OVERFLOW_TOTAL_NUM 2
78 /* output compare interrupt number */
79 #define SIG_OUTPUT_COMPARE0_NUM 0
80 #define SIG_OUTPUT_COMPARE0B_NUM 1
81 #define SIG_OUTPUT_COMPARE1A_NUM 2
82 #define SIG_OUTPUT_COMPARE1B_NUM 3
83 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
90 #define PWM_TOTAL_NUM 4
92 /* input capture interrupt number */
93 #define SIG_INPUT_CAPTURE1_NUM 0
94 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
98 #define EUDR0_REG EUDR
99 #define EUDR1_REG EUDR
100 #define EUDR2_REG EUDR
101 #define EUDR3_REG EUDR
102 #define EUDR4_REG EUDR
103 #define EUDR5_REG EUDR
104 #define EUDR6_REG EUDR
105 #define EUDR7_REG EUDR
108 #define MUX0_REG ADMUX
109 #define MUX1_REG ADMUX
110 #define MUX2_REG ADMUX
111 #define MUX3_REG ADMUX
112 #define ADLAR_REG ADMUX
113 #define REFS0_REG ADMUX
114 #define REFS1_REG ADMUX
117 #define OCR2SB_8_REG OCR2SBH
118 #define OCR2SB_9_REG OCR2SBH
119 #define OCR2SB_10_REG OCR2SBH
120 #define OCR2SB_11_REG OCR2SBH
123 #define OCR2SB_0_REG OCR2SBL
124 #define OCR2SB_1_REG OCR2SBL
125 #define OCR2SB_2_REG OCR2SBL
126 #define OCR2SB_3_REG OCR2SBL
127 #define OCR2SB_4_REG OCR2SBL
128 #define OCR2SB_5_REG OCR2SBL
129 #define OCR2SB_6_REG OCR2SBL
130 #define OCR2SB_7_REG OCR2SBL
133 #define WDP0_REG WDTCSR
134 #define WDP1_REG WDTCSR
135 #define WDP2_REG WDTCSR
136 #define WDE_REG WDTCSR
137 #define WDCE_REG WDTCSR
138 #define WDP3_REG WDTCSR
139 #define WDIE_REG WDTCSR
140 #define WDIF_REG WDTCSR
143 #define EEDR0_REG EEDR
144 #define EEDR1_REG EEDR
145 #define EEDR2_REG EEDR
146 #define EEDR3_REG EEDR
147 #define EEDR4_REG EEDR
148 #define EEDR5_REG EEDR
149 #define EEDR6_REG EEDR
150 #define EEDR7_REG EEDR
153 /* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
154 /* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
155 /* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
156 /* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
157 /* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
158 /* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
159 /* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
160 /* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
163 #define OCR0SA_0_REG OCR0SAL
164 #define OCR0SA_1_REG OCR0SAL
165 #define OCR0SA_2_REG OCR0SAL
166 #define OCR0SA_3_REG OCR0SAL
167 #define OCR0SA_4_REG OCR0SAL
168 #define OCR0SA_5_REG OCR0SAL
169 #define OCR0SA_6_REG OCR0SAL
170 #define OCR0SA_7_REG OCR0SAL
173 #define SPDR0_REG SPDR
174 #define SPDR1_REG SPDR
175 #define SPDR2_REG SPDR
176 #define SPDR3_REG SPDR
177 #define SPDR4_REG SPDR
178 #define SPDR5_REG SPDR
179 #define SPDR6_REG SPDR
180 #define SPDR7_REG SPDR
183 #define SPI2X_REG SPSR
184 #define WCOL_REG SPSR
185 #define SPIF_REG SPSR
198 #define MPCM_REG UCSRA
199 #define U2X_REG UCSRA
200 #define UPE_REG UCSRA
201 #define DOR_REG UCSRA
203 #define UDRE_REG UCSRA
204 #define TXC_REG UCSRA
205 #define RXC_REG UCSRA
208 #define TXB8_REG UCSRB
209 #define RXB8_REG UCSRB
210 #define UCSZ2_REG UCSRB
211 #define TXEN_REG UCSRB
212 #define RXEN_REG UCSRB
213 #define UDRIE_REG UCSRB
214 #define TXCIE_REG UCSRB
215 #define RXCIE_REG UCSRB
218 #define UCPOL_REG UCSRC
219 #define UCSZ0_REG UCSRC
220 #define UCSZ1_REG UCSRC
221 #define USBS_REG UCSRC
222 #define UPM0_REG UCSRC
223 #define UPM1_REG UCSRC
224 #define UMSEL0_REG UCSRC
237 #define AC1M0_REG AC1CON
238 #define AC1M1_REG AC1CON
239 #define AC1M2_REG AC1CON
240 #define AC1ICE_REG AC1CON
241 #define AC1IS0_REG AC1CON
242 #define AC1IS1_REG AC1CON
243 #define AC1IE_REG AC1CON
244 #define AC1EN_REG AC1CON
247 #define PRADC_REG PRR
248 #define PRUSART0_REG PRR
249 #define PRSPI_REG PRR
250 #define PRTIM0_REG PRR
251 #define PRTIM1_REG PRR
252 #define PRPSC0_REG PRR
253 #define PRPSC1_REG PRR
254 #define PRPSC2_REG PRR
257 #define PCLKSEL0_REG PCNF0
258 #define POP0_REG PCNF0
259 #define PMODE00_REG PCNF0
260 #define PMODE01_REG PCNF0
261 #define PLOCK0_REG PCNF0
262 #define PALOCK0_REG PCNF0
263 #define PFIFTY0_REG PCNF0
266 #define POME2_REG PCNF2
267 #define PCLKSEL2_REG PCNF2
268 #define POP2_REG PCNF2
269 #define PMODE20_REG PCNF2
270 #define PMODE21_REG PCNF2
271 #define PLOCK2_REG PCNF2
272 #define PALOCK2_REG PCNF2
273 #define PFIFTY2_REG PCNF2
276 #define TCNT1L0_REG TCNT1L
277 #define TCNT1L1_REG TCNT1L
278 #define TCNT1L2_REG TCNT1L
279 #define TCNT1L3_REG TCNT1L
280 #define TCNT1L4_REG TCNT1L
281 #define TCNT1L5_REG TCNT1L
282 #define TCNT1L6_REG TCNT1L
283 #define TCNT1L7_REG TCNT1L
286 #define PORTD0_REG PORTD
287 #define PORTD1_REG PORTD
288 #define PORTD2_REG PORTD
289 #define PORTD3_REG PORTD
290 #define PORTD4_REG PORTD
291 #define PORTD5_REG PORTD
292 #define PORTD6_REG PORTD
293 #define PORTD7_REG PORTD
296 #define PORTE0_REG PORTE
297 #define PORTE1_REG PORTE
298 #define PORTE2_REG PORTE
301 #define TCNT1H0_REG TCNT1H
302 #define TCNT1H1_REG TCNT1H
303 #define TCNT1H2_REG TCNT1H
304 #define TCNT1H3_REG TCNT1H
305 #define TCNT1H4_REG TCNT1H
306 #define TCNT1H5_REG TCNT1H
307 #define TCNT1H6_REG TCNT1H
308 #define TCNT1H7_REG TCNT1H
311 #define AMP1TS0_REG AMP1CSR
312 #define AMP1TS1_REG AMP1CSR
313 #define AMP1G0_REG AMP1CSR
314 #define AMP1G1_REG AMP1CSR
315 #define AMP1IS_REG AMP1CSR
316 #define AMP1EN_REG AMP1CSR
319 #define AC2M0_REG AC2CON
320 #define AC2M1_REG AC2CON
321 #define AC2M2_REG AC2CON
322 #define AC2IS0_REG AC2CON
323 #define AC2IS1_REG AC2CON
324 #define AC2IE_REG AC2CON
325 #define AC2EN_REG AC2CON
328 #define INT0_REG EIMSK
329 #define INT1_REG EIMSK
330 #define INT2_REG EIMSK
333 #define PRFM0A0_REG PFRC0A
334 #define PRFM0A1_REG PFRC0A
335 #define PRFM0A2_REG PFRC0A
336 #define PRFM0A3_REG PFRC0A
337 #define PFLTE0A_REG PFRC0A
338 #define PELEV0A_REG PFRC0A
339 #define PISEL0A_REG PFRC0A
340 #define PCAE0A_REG PFRC0A
343 #define PRFM0B0_REG PFRC0B
344 #define PRFM0B1_REG PFRC0B
345 #define PRFM0B2_REG PFRC0B
346 #define PRFM0B3_REG PFRC0B
347 #define PFLTE0B_REG PFRC0B
348 #define PELEV0B_REG PFRC0B
349 #define PISEL0B_REG PFRC0B
350 #define PCAE0B_REG PFRC0B
353 #define ISC00_REG EICRA
354 #define ISC01_REG EICRA
355 #define ISC10_REG EICRA
356 #define ISC11_REG EICRA
357 #define ISC20_REG EICRA
358 #define ISC21_REG EICRA
361 #define ADC0D_REG DIDR0
362 #define ADC1D_REG DIDR0
363 #define ADC2D_REG DIDR0
364 #define ADC3D_REG DIDR0
365 #define ADC4D_REG DIDR0
366 #define ADC5D_REG DIDR0
367 #define ADC6D_REG DIDR0
368 #define ADC7D_REG DIDR0
371 #define ADC8D_REG DIDR1
372 #define ADC9D_REG DIDR1
373 #define ADC10D_REG DIDR1
374 #define AMP0ND_REG DIDR1
375 #define AMP0PD_REG DIDR1
376 #define ACMP0D_REG DIDR1
379 #define CLKPS0_REG CLKPR
380 #define CLKPS1_REG CLKPR
381 #define CLKPS2_REG CLKPR
382 #define CLKPS3_REG CLKPR
383 #define CLKPCE_REG CLKPR
386 #define OCR0RB_8_REG OCR0RBH
387 #define OCR0RB_9_REG OCR0RBH
388 #define OCR0RB_00_REG OCR0RBH
389 #define OCR0RB_01_REG OCR0RBH
390 #define OCR0RB_02_REG OCR0RBH
391 #define OCR0RB_03_REG OCR0RBH
392 #define OCR0RB_04_REG OCR0RBH
393 #define OCR0RB_05_REG OCR0RBH
406 #define DDB0_REG DDRB
407 #define DDB1_REG DDRB
408 #define DDB2_REG DDRB
409 #define DDB3_REG DDRB
410 #define DDB4_REG DDRB
411 #define DDB5_REG DDRB
412 #define DDB6_REG DDRB
413 #define DDB7_REG DDRB
416 #define PEOPE2_REG PIM2
417 #define PEVE2A_REG PIM2
418 #define PEVE2B_REG PIM2
419 #define PSEIE2_REG PIM2
422 #define WGM10_REG TCCR1A
423 #define WGM11_REG TCCR1A
424 #define COM1B0_REG TCCR1A
425 #define COM1B1_REG TCCR1A
426 #define COM1A0_REG TCCR1A
427 #define COM1A1_REG TCCR1A
430 #define FOC1B_REG TCCR1C
431 #define FOC1A_REG TCCR1C
434 #define CS10_REG TCCR1B
435 #define CS11_REG TCCR1B
436 #define CS12_REG TCCR1B
437 #define WGM12_REG TCCR1B
438 #define WGM13_REG TCCR1B
439 #define ICES1_REG TCCR1B
440 #define ICNC1_REG TCCR1B
443 #define CAL0_REG OSCCAL
444 #define CAL1_REG OSCCAL
445 #define CAL2_REG OSCCAL
446 #define CAL3_REG OSCCAL
447 #define CAL4_REG OSCCAL
448 #define CAL5_REG OSCCAL
449 #define CAL6_REG OSCCAL
452 #define OCR0RA_0_REG OCR0RAL
453 #define OCR0RA_1_REG OCR0RAL
454 #define OCR0RA_2_REG OCR0RAL
455 #define OCR0RA_3_REG OCR0RAL
456 #define OCR0RA_4_REG OCR0RAL
457 #define OCR0RA_5_REG OCR0RAL
458 #define OCR0RA_6_REG OCR0RAL
459 #define OCR0RA_7_REG OCR0RAL
462 #define GPIOR10_REG GPIOR1
463 #define GPIOR11_REG GPIOR1
464 #define GPIOR12_REG GPIOR1
465 #define GPIOR13_REG GPIOR1
466 #define GPIOR14_REG GPIOR1
467 #define GPIOR15_REG GPIOR1
468 #define GPIOR16_REG GPIOR1
469 #define GPIOR17_REG GPIOR1
472 #define GPIOR00_REG GPIOR0
473 #define GPIOR01_REG GPIOR0
474 #define GPIOR02_REG GPIOR0
475 #define GPIOR03_REG GPIOR0
476 #define GPIOR04_REG GPIOR0
477 #define GPIOR05_REG GPIOR0
478 #define GPIOR06_REG GPIOR0
479 #define GPIOR07_REG GPIOR0
482 #define GPIOR30_REG GPIOR3
483 #define GPIOR31_REG GPIOR3
484 #define GPIOR32_REG GPIOR3
485 #define GPIOR33_REG GPIOR3
486 #define GPIOR34_REG GPIOR3
487 #define GPIOR35_REG GPIOR3
488 #define GPIOR36_REG GPIOR3
489 #define GPIOR37_REG GPIOR3
492 #define GPIOR20_REG GPIOR2
493 #define GPIOR21_REG GPIOR2
494 #define GPIOR22_REG GPIOR2
495 #define GPIOR23_REG GPIOR2
496 #define GPIOR24_REG GPIOR2
497 #define GPIOR25_REG GPIOR2
498 #define GPIOR26_REG GPIOR2
499 #define GPIOR27_REG GPIOR2
502 #define PEOP0_REG PIFR0
503 #define PRN00_REG PIFR0
504 #define PRN01_REG PIFR0
505 #define PEV0A_REG PIFR0
506 #define PEV0B_REG PIFR0
507 #define PSEI0_REG PIFR0
508 #define POAC0A_REG PIFR0
509 #define POAC0B_REG PIFR0
512 #define DDE0_REG DDRE
513 #define DDE1_REG DDRE
514 #define DDE2_REG DDRE
517 #define TCNT0_0_REG TCNT0
518 #define TCNT0_1_REG TCNT0
519 #define TCNT0_2_REG TCNT0
520 #define TCNT0_3_REG TCNT0
521 #define TCNT0_4_REG TCNT0
522 #define TCNT0_5_REG TCNT0
523 #define TCNT0_6_REG TCNT0
524 #define TCNT0_7_REG TCNT0
527 #define CS00_REG TCCR0B
528 #define CS01_REG TCCR0B
529 #define CS02_REG TCCR0B
530 #define WGM02_REG TCCR0B
531 #define FOC0B_REG TCCR0B
532 #define FOC0A_REG TCCR0B
535 #define WGM00_REG TCCR0A
536 #define WGM01_REG TCCR0A
537 #define COM0B0_REG TCCR0A
538 #define COM0B1_REG TCCR0A
539 #define COM0A0_REG TCCR0A
540 #define COM0A1_REG TCCR0A
543 #define PRFM2B0_REG PFRC2B
544 #define PRFM2B1_REG PFRC2B
545 #define PRFM2B2_REG PFRC2B
546 #define PRFM2B3_REG PFRC2B
547 #define PFLTE2B_REG PFRC2B
548 #define PELEV2B_REG PFRC2B
549 #define PISEL2B_REG PFRC2B
550 #define PCAE2B_REG PFRC2B
553 #define PRFM2A0_REG PFRC2A
554 #define PRFM2A1_REG PFRC2A
555 #define PRFM2A2_REG PFRC2A
556 #define PRFM2A3_REG PFRC2A
557 #define PFLTE2A_REG PFRC2A
558 #define PELEV2A_REG PFRC2A
559 #define PISEL2A_REG PFRC2A
560 #define PCAE2A_REG PFRC2A
563 #define OCR2SA_0_REG OCR2SAL
564 #define OCR2SA_1_REG OCR2SAL
565 #define OCR2SA_2_REG OCR2SAL
566 #define OCR2SA_3_REG OCR2SAL
567 #define OCR2SA_4_REG OCR2SAL
568 #define OCR2SA_5_REG OCR2SAL
569 #define OCR2SA_6_REG OCR2SAL
570 #define OCR2SA_7_REG OCR2SAL
573 #define URxS0_REG EUCSRA
574 #define URxS1_REG EUCSRA
575 #define URxS2_REG EUCSRA
576 #define URxS3_REG EUCSRA
577 #define UTxS0_REG EUCSRA
578 #define UTxS1_REG EUCSRA
579 #define UTxS2_REG EUCSRA
580 #define UTxS3_REG EUCSRA
583 #define BODR_REG EUCSRB
584 #define EMCH_REG EUCSRB
585 #define EUSBS_REG EUCSRB
586 #define EUSART_REG EUCSRB
589 #define STP0_REG EUCSRC
590 #define STP1_REG EUCSRC
591 #define F1617_REG EUCSRC
592 #define FEM_REG EUCSRC
595 #define PRUN0_REG PCTL0
596 #define PCCYC0_REG PCTL0
597 #define PARUN0_REG PCTL0
598 #define PAOC0A_REG PCTL0
599 #define PAOC0B_REG PCTL0
600 #define PBFM0_REG PCTL0
601 #define PPRE00_REG PCTL0
602 #define PPRE01_REG PCTL0
605 #define PRUN2_REG PCTL2
606 #define PCCYC2_REG PCTL2
607 #define PARUN2_REG PCTL2
608 #define PAOC2A_REG PCTL2
609 #define PAOC2B_REG PCTL2
610 #define PBFM2_REG PCTL2
611 #define PPRE20_REG PCTL2
612 #define PPRE21_REG PCTL2
615 #define SPR0_REG SPCR
616 #define SPR1_REG SPCR
617 #define CPHA_REG SPCR
618 #define CPOL_REG SPCR
619 #define MSTR_REG SPCR
620 #define DORD_REG SPCR
622 #define SPIE_REG SPCR
625 #define TOV1_REG TIFR1
626 #define OCF1A_REG TIFR1
627 #define OCF1B_REG TIFR1
628 #define ICF1_REG TIFR1
631 #define PSR10_REG GTCCR
632 #define ICPSEL1_REG GTCCR
633 #define TSM_REG GTCCR
634 #define PSRSYNC_REG GTCCR
637 #define ICR1H0_REG ICR1H
638 #define ICR1H1_REG ICR1H
639 #define ICR1H2_REG ICR1H
640 #define ICR1H3_REG ICR1H
641 #define ICR1H4_REG ICR1H
642 #define ICR1H5_REG ICR1H
643 #define ICR1H6_REG ICR1H
644 #define ICR1H7_REG ICR1H
647 #define POMV2A0_REG POM2
648 #define POMV2A1_REG POM2
649 #define POMV2A2_REG POM2
650 #define POMV2A3_REG POM2
651 #define POMV2B0_REG POM2
652 #define POMV2B1_REG POM2
653 #define POMV2B2_REG POM2
654 #define POMV2B3_REG POM2
657 #define OCR2RB_0_REG OCR2RBL
658 #define OCR2RB_1_REG OCR2RBL
659 #define OCR2RB_2_REG OCR2RBL
660 #define OCR2RB_3_REG OCR2RBL
661 #define OCR2RB_4_REG OCR2RBL
662 #define OCR2RB_5_REG OCR2RBL
663 #define OCR2RB_6_REG OCR2RBL
664 #define OCR2RB_7_REG OCR2RBL
667 #define PICR2_8_REG PICR2H
668 #define PICR2_9_REG PICR2H
669 #define PICR2_10_REG PICR2H
670 #define PICR2_11_REG PICR2H
671 #define PCST2_REG PICR2H
674 #define OCR2RB_8_REG OCR2RBH
675 #define OCR2RB_9_REG OCR2RBH
676 #define OCR2RB_10_REG OCR2RBH
677 #define OCR2RB_11_REG OCR2RBH
678 #define OCR2RB_12_REG OCR2RBH
679 #define OCR2RB_13_REG OCR2RBH
680 #define OCR2RB_14_REG OCR2RBH
681 #define OCR2RB_15_REG OCR2RBH
684 #define PICR2_0_REG PICR2L
685 #define PICR2_1_REG PICR2L
686 #define PICR2_2_REG PICR2L
687 #define PICR2_3_REG PICR2L
688 #define PICR2_4_REG PICR2L
689 #define PICR2_5_REG PICR2L
690 #define PICR2_6_REG PICR2L
691 #define PICR2_7_REG PICR2L
694 #define OCR1BL0_REG OCR1BL
695 #define OCR1BL1_REG OCR1BL
696 #define OCR1BL2_REG OCR1BL
697 #define OCR1BL3_REG OCR1BL
698 #define OCR1BL4_REG OCR1BL
699 #define OCR1BL5_REG OCR1BL
700 #define OCR1BL6_REG OCR1BL
701 #define OCR1BL7_REG OCR1BL
704 #define OCR1BH0_REG OCR1BH
705 #define OCR1BH1_REG OCR1BH
706 #define OCR1BH2_REG OCR1BH
707 #define OCR1BH3_REG OCR1BH
708 #define OCR1BH4_REG OCR1BH
709 #define OCR1BH5_REG OCR1BH
710 #define OCR1BH6_REG OCR1BH
711 #define OCR1BH7_REG OCR1BH
714 #define ICR1L0_REG ICR1L
715 #define ICR1L1_REG ICR1L
716 #define ICR1L2_REG ICR1L
717 #define ICR1L3_REG ICR1L
718 #define ICR1L4_REG ICR1L
719 #define ICR1L5_REG ICR1L
720 #define ICR1L6_REG ICR1L
721 #define ICR1L7_REG ICR1L
724 #define PORF_REG MCUSR
725 #define EXTRF_REG MCUSR
726 #define BORF_REG MCUSR
727 #define WDRF_REG MCUSR
730 #define EERE_REG EECR
731 #define EEWE_REG EECR
732 #define EEMWE_REG EECR
733 #define EERIE_REG EECR
742 #define PLOCK_REG PLLCSR
743 #define PLLE_REG PLLCSR
744 #define PLLF_REG PLLCSR
747 #define OCR2RA_8_REG OCR2RAH
748 #define OCR2RA_9_REG OCR2RAH
749 #define OCR2RA_10_REG OCR2RAH
750 #define OCR2RA_11_REG OCR2RAH
753 #define OCR2RA_0_REG OCR2RAL
754 #define OCR2RA_1_REG OCR2RAL
755 #define OCR2RA_2_REG OCR2RAL
756 #define OCR2RA_3_REG OCR2RAL
757 #define OCR2RA_4_REG OCR2RAL
758 #define OCR2RA_5_REG OCR2RAL
759 #define OCR2RA_6_REG OCR2RAL
760 #define OCR2RA_7_REG OCR2RAL
763 #define OCR0RB_0_REG OCR0RBL
764 #define OCR0RB_1_REG OCR0RBL
765 #define OCR0RB_2_REG OCR0RBL
766 #define OCR0RB_3_REG OCR0RBL
767 #define OCR0RB_4_REG OCR0RBL
768 #define OCR0RB_5_REG OCR0RBL
769 #define OCR0RB_6_REG OCR0RBL
770 #define OCR0RB_7_REG OCR0RBL
773 #define OCR0SA_8_REG OCR0SAH
774 #define OCR0SA_9_REG OCR0SAH
775 #define OCR0SA_00_REG OCR0SAH
776 #define OCR0SA_01_REG OCR0SAH
779 #define EEAR8_REG EEARH
780 #define EEAR9_REG EEARH
781 #define EEAR10_REG EEARH
782 #define EEAR11_REG EEARH
785 #define EEARL0_REG EEARL
786 #define EEARL1_REG EEARL
787 #define EEARL2_REG EEARL
788 #define EEARL3_REG EEARL
789 #define EEARL4_REG EEARL
790 #define EEARL5_REG EEARL
791 #define EEARL6_REG EEARL
792 #define EEARL7_REG EEARL
795 #define IVCE_REG MCUCR
796 #define IVSEL_REG MCUCR
797 #define PUD_REG MCUCR
798 #define SPIPS_REG MCUCR
801 #define PICR0_8_REG PICR0H
802 #define PICR0_9_REG PICR0H
803 #define PICR0_10_REG PICR0H
804 #define PICR0_11_REG PICR0H
805 #define PCST0_REG PICR0H
808 #define INTF0_REG EIFR
809 #define INTF1_REG EIFR
810 #define INTF2_REG EIFR
813 #define MUBRR0_REG MUBRRL
814 #define MUBRR1_REG MUBRRL
815 #define MUBRR2_REG MUBRRL
816 #define MUBRR3_REG MUBRRL
817 #define MUBRR4_REG MUBRRL
818 #define MUBRR5_REG MUBRRL
819 #define MUBRR6_REG MUBRRL
820 #define MUBRR7_REG MUBRRL
823 #define MUBRR8_REG MUBRRH
824 #define MUBRR9_REG MUBRRH
825 #define MUBRR10_REG MUBRRH
826 #define MUBRR11_REG MUBRRH
827 #define MUBRR12_REG MUBRRH
828 #define MUBRR13_REG MUBRRH
829 #define MUBRR14_REG MUBRRH
830 #define MUBRR15_REG MUBRRH
833 #define OCR2SA_8_REG OCR2SAH
834 #define OCR2SA_9_REG OCR2SAH
835 #define OCR2SA_10_REG OCR2SAH
836 #define OCR2SA_11_REG OCR2SAH
839 #define OCR0SB_0_REG OCR0SBL
840 #define OCR0SB_1_REG OCR0SBL
841 #define OCR0SB_2_REG OCR0SBL
842 #define OCR0SB_3_REG OCR0SBL
843 #define OCR0SB_4_REG OCR0SBL
844 #define OCR0SB_5_REG OCR0SBL
845 #define OCR0SB_6_REG OCR0SBL
846 #define OCR0SB_7_REG OCR0SBL
849 #define OCR0SB_8_REG OCR0SBH
850 #define OCR0SB_9_REG OCR0SBH
851 #define OCR0SB_00_REG OCR0SBH
852 #define OCR0SB_01_REG OCR0SBH
855 #define PICR0_0_REG PICR0L
856 #define PICR0_1_REG PICR0L
857 #define PICR0_2_REG PICR0L
858 #define PICR0_3_REG PICR0L
859 #define PICR0_4_REG PICR0L
860 #define PICR0_5_REG PICR0L
861 #define PICR0_6_REG PICR0L
862 #define PICR0_7_REG PICR0L
865 #define ADPS0_REG ADCSRA
866 #define ADPS1_REG ADCSRA
867 #define ADPS2_REG ADCSRA
868 #define ADIE_REG ADCSRA
869 #define ADIF_REG ADCSRA
870 #define ADATE_REG ADCSRA
871 #define ADSC_REG ADCSRA
872 #define ADEN_REG ADCSRA
875 #define POEN0A_REG PSOC0
876 #define POEN0B_REG PSOC0
877 #define PSYNC00_REG PSOC0
878 #define PSYNC01_REG PSOC0
881 #define ADTS0_REG ADCSRB
882 #define ADTS1_REG ADCSRB
883 #define ADTS2_REG ADCSRB
884 #define ADTS3_REG ADCSRB
885 #define ADASCR_REG ADCSRB
886 #define ADHSM_REG ADCSRB
889 /* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
890 /* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
891 /* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
892 /* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
893 /* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
894 /* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
895 /* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
896 /* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
899 #define AC0O_REG ACSR
900 #define AC1O_REG ACSR
901 #define AC2O_REG ACSR
902 #define AC0IF_REG ACSR
903 #define AC1IF_REG ACSR
904 #define AC2IF_REG ACSR
905 #define ACCKDIV_REG ACSR
908 #define DDD0_REG DDRD
909 #define DDD1_REG DDRD
910 #define DDD2_REG DDRD
911 #define DDD3_REG DDRD
912 #define DDD4_REG DDRD
913 #define DDD5_REG DDRD
914 #define DDD6_REG DDRD
915 #define DDD7_REG DDRD
918 #define UBRR8_REG UBRRH
919 #define UBRR9_REG UBRRH
920 #define UBRR10_REG UBRRH
921 #define UBRR11_REG UBRRH
924 #define DACL0_REG DACL
925 #define DACL1_REG DACL
926 #define DACL2_REG DACL
927 #define DACL3_REG DACL
928 #define DACL4_REG DACL
929 #define DACL5_REG DACL
930 #define DACL6_REG DACL
931 #define DACL7_REG DACL
934 #define UBRR0_REG UBRRL
935 #define UBRR1_REG UBRRL
936 #define UBRR2_REG UBRRL
937 #define UBRR3_REG UBRRL
938 #define UBRR4_REG UBRRL
939 #define UBRR5_REG UBRRL
940 #define UBRR6_REG UBRRL
941 #define UBRR7_REG UBRRL
944 #define DACH0_REG DACH
945 #define DACH1_REG DACH
946 #define DACH2_REG DACH
947 #define DACH3_REG DACH
948 #define DACH4_REG DACH
949 #define DACH5_REG DACH
950 #define DACH6_REG DACH
951 #define DACH7_REG DACH
954 #define OCR0RA_8_REG OCR0RAH
955 #define OCR0RA_9_REG OCR0RAH
956 #define OCR0RA_00_REG OCR0RAH
957 #define OCR0RA_01_REG OCR0RAH
960 #define SPMEN_REG SPMCSR
961 #define PGERS_REG SPMCSR
962 #define PGWRT_REG SPMCSR
963 #define BLBSET_REG SPMCSR
964 #define RWWSRE_REG SPMCSR
965 #define RWWSB_REG SPMCSR
966 #define SPMIE_REG SPMCSR
969 #define PEOPE0_REG PIM0
970 #define PEVE0A_REG PIM0
971 #define PEVE0B_REG PIM0
972 #define PSEIE0_REG PIM0
975 #define PEOP2_REG PIFR2
976 #define PRN20_REG PIFR2
977 #define PRN21_REG PIFR2
978 #define PEV2A_REG PIFR2
979 #define PEV2B_REG PIFR2
980 #define PSEI2_REG PIFR2
981 #define POAC2A_REG PIFR2
982 #define POAC2B_REG PIFR2
985 #define PORTB0_REG PORTB
986 #define PORTB1_REG PORTB
987 #define PORTB2_REG PORTB
988 #define PORTB3_REG PORTB
989 #define PORTB4_REG PORTB
990 #define PORTB5_REG PORTB
991 #define PORTB6_REG PORTB
992 #define PORTB7_REG PORTB
995 #define ADCL0_REG ADCL
996 #define ADCL1_REG ADCL
997 #define ADCL2_REG ADCL
998 #define ADCL3_REG ADCL
999 #define ADCL4_REG ADCL
1000 #define ADCL5_REG ADCL
1001 #define ADCL6_REG ADCL
1002 #define ADCL7_REG ADCL
1005 #define ADCH0_REG ADCH
1006 #define ADCH1_REG ADCH
1007 #define ADCH2_REG ADCH
1008 #define ADCH3_REG ADCH
1009 #define ADCH4_REG ADCH
1010 #define ADCH5_REG ADCH
1011 #define ADCH6_REG ADCH
1012 #define ADCH7_REG ADCH
1015 #define POEN2A_REG PSOC2
1016 #define POEN2C_REG PSOC2
1017 #define POEN2B_REG PSOC2
1018 #define POEN2D_REG PSOC2
1019 #define PSYNC2_0_REG PSOC2
1020 #define PSYNC2_1_REG PSOC2
1021 #define POS22_REG PSOC2
1022 #define POS23_REG PSOC2
1025 #define TOIE0_REG TIMSK0
1026 #define OCIE0A_REG TIMSK0
1027 #define OCIE0B_REG TIMSK0
1030 #define TOIE1_REG TIMSK1
1031 #define OCIE1A_REG TIMSK1
1032 #define OCIE1B_REG TIMSK1
1033 #define ICIE1_REG TIMSK1
1036 #define AMP0TS0_REG AMP0CSR
1037 #define AMP0TS1_REG AMP0CSR
1038 #define AMP0G0_REG AMP0CSR
1039 #define AMP0G1_REG AMP0CSR
1040 #define AMP0IS_REG AMP0CSR
1041 #define AMP0EN_REG AMP0CSR
1044 #define UDR0_REG UDR
1045 #define UDR1_REG UDR
1046 #define UDR2_REG UDR
1047 #define UDR3_REG UDR
1048 #define UDR4_REG UDR
1049 #define UDR5_REG UDR
1050 #define UDR6_REG UDR
1051 #define UDR7_REG UDR
1054 #define DAEN_REG DACON
1055 #define DALA_REG DACON
1056 #define DATS0_REG DACON
1057 #define DATS1_REG DACON
1058 #define DATS2_REG DACON
1059 #define DAATE_REG DACON
1062 #define PINB0_REG PINB
1063 #define PINB1_REG PINB
1064 #define PINB2_REG PINB
1065 #define PINB3_REG PINB
1066 #define PINB4_REG PINB
1067 #define PINB5_REG PINB
1068 #define PINB6_REG PINB
1069 #define PINB7_REG PINB
1072 #define AC0M0_REG AC0CON
1073 #define AC0M1_REG AC0CON
1074 #define AC0M2_REG AC0CON
1075 #define AC0IS0_REG AC0CON
1076 #define AC0IS1_REG AC0CON
1077 #define AC0IE_REG AC0CON
1078 #define AC0EN_REG AC0CON
1081 #define PINE0_REG PINE
1082 #define PINE1_REG PINE
1083 #define PINE2_REG PINE
1086 #define PIND0_REG PIND
1087 #define PIND1_REG PIND
1088 #define PIND2_REG PIND
1089 #define PIND3_REG PIND
1090 #define PIND4_REG PIND
1091 #define PIND5_REG PIND
1092 #define PIND6_REG PIND
1093 #define PIND7_REG PIND
1096 #define OCR1AH0_REG OCR1AH
1097 #define OCR1AH1_REG OCR1AH
1098 #define OCR1AH2_REG OCR1AH
1099 #define OCR1AH3_REG OCR1AH
1100 #define OCR1AH4_REG OCR1AH
1101 #define OCR1AH5_REG OCR1AH
1102 #define OCR1AH6_REG OCR1AH
1103 #define OCR1AH7_REG OCR1AH
1106 #define OCR1AL0_REG OCR1AL
1107 #define OCR1AL1_REG OCR1AL
1108 #define OCR1AL2_REG OCR1AL
1109 #define OCR1AL3_REG OCR1AL
1110 #define OCR1AL4_REG OCR1AL
1111 #define OCR1AL5_REG OCR1AL
1112 #define OCR1AL6_REG OCR1AL
1113 #define OCR1AL7_REG OCR1AL
1116 #define TOV0_REG TIFR0
1117 #define OCF0A_REG TIFR0
1118 #define OCF0B_REG TIFR0
1121 #define MISO_PORT PORTB
1123 #define PSCOUT20_PORT PORTB
1124 #define PSCOUT20_BIT 0
1126 #define MOSI_PORT PORTB
1128 #define PSCOUT21_PORT PORTB
1129 #define PSCOUT21_BIT 1
1131 #define ADC5_PORT PORTB
1133 #define INT1_PORT PORTB
1136 #define AMP0-_PORT PORTB
1139 #define AMP0+_PORT PORTB
1142 #define ADC6_PORT PORTB
1144 #define INT2_PORT PORTB
1147 #define ADC7_PORT PORTB
1149 #define PSCOUT11_PORT PORTB
1150 #define PSCOUT11_BIT 6
1151 #define ICP1B_PORT PORTB
1154 #define ADC4_PORT PORTB
1156 #define PSCOUT01_PORT PORTB
1157 #define PSCOUT01_BIT 7
1158 #define SCK_PORT PORTB
1161 #define PSCOUT00_PORT PORTD
1162 #define PSCOUT00_BIT 0
1163 #define XCK_PORT PORTD
1165 #define SSA_PORT PORTD
1168 #define PSCIN0_PORT PORTD
1169 #define PSCIN0_BIT 1
1170 #define CLK0_PORT PORTD
1173 #define PSCIN2_PORT PORTD
1174 #define PSCIN2_BIT 2
1175 #define OC1A_PORT PORTD
1177 #define MISO_A_PORT PORTD
1178 #define MISO_A_BIT 2
1180 #define TXD_PORT PORTD
1182 #define DALI_PORT PORTD
1184 #define OC0A_PORT PORTD
1186 #define SS_PORT PORTD
1188 #define MOSI_A_PORT PORTD
1189 #define MOSI_A_BIT 3
1191 #define ADC1_PORT PORTD
1193 #define RXD_PORT PORTD
1195 #define DALI_PORT PORTD
1197 #define ICP1_PORT PORTD
1199 #define SCK_A_PORT PORTD
1202 #define ADC2_PORT PORTD
1204 #define ACMP2_PORT PORTD
1207 #define ADC3_PORT PORTD
1209 #define ACMPM_PORT PORTD
1211 #define INT0_PORT PORTD
1214 #define ACMP0_PORT PORTD
1217 #define RESET_PORT PORTE
1219 #define OCD_PORT PORTE
1222 #define OC0B_PORT PORTE
1224 #define XTAL1_PORT PORTE
1227 #define ADC0_PORT PORTE
1229 #define XTAL2_PORT PORTE