2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
50 /* available timers */
51 #define TIMER0_AVAILABLE
52 #define TIMER1_AVAILABLE
53 #define TIMER1A_AVAILABLE
54 #define TIMER1B_AVAILABLE
56 /* overflow interrupt number */
57 #define SIG_OVERFLOW0_NUM 0
58 #define SIG_OVERFLOW1_NUM 1
59 #define SIG_OVERFLOW_TOTAL_NUM 2
61 /* output compare interrupt number */
62 #define SIG_OUTPUT_COMPARE1A_NUM 0
63 #define SIG_OUTPUT_COMPARE1B_NUM 1
64 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 2
69 #define PWM_TOTAL_NUM 2
71 /* input capture interrupt number */
72 #define SIG_INPUT_CAPTURE1_NUM 0
73 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
77 #define WDP0_REG WDTCR
78 #define WDP1_REG WDTCR
79 #define WDP2_REG WDTCR
81 #define WDTOE_REG WDTCR
84 #define INT0_REG GIMSK
85 #define INT1_REG GIMSK
88 #define ICR1H0_REG ICR1H
89 #define ICR1H1_REG ICR1H
90 #define ICR1H2_REG ICR1H
91 #define ICR1H3_REG ICR1H
92 #define ICR1H4_REG ICR1H
93 #define ICR1H5_REG ICR1H
94 #define ICR1H6_REG ICR1H
95 #define ICR1H7_REG ICR1H
98 #define CS00_REG TCCR0
99 #define CS01_REG TCCR0
100 #define CS02_REG TCCR0
113 #define DDB0_REG DDRB
114 #define DDB1_REG DDRB
115 #define DDB2_REG DDRB
116 #define DDB3_REG DDRB
117 #define DDB4_REG DDRB
118 #define DDB5_REG DDRB
119 #define DDB6_REG DDRB
120 #define DDB7_REG DDRB
130 #define EEDR0_REG EEDR
131 #define EEDR1_REG EEDR
132 #define EEDR2_REG EEDR
133 #define EEDR3_REG EEDR
134 #define EEDR4_REG EEDR
135 #define EEDR5_REG EEDR
136 #define EEDR6_REG EEDR
137 #define EEDR7_REG EEDR
140 #define DDC0_REG DDRC
141 #define DDC1_REG DDRC
142 #define DDC2_REG DDRC
143 #define DDC3_REG DDRC
144 #define DDC4_REG DDRC
145 #define DDC5_REG DDRC
146 #define DDC6_REG DDRC
147 #define DDC7_REG DDRC
150 #define DDA0_REG DDRA
151 #define DDA1_REG DDRA
152 #define DDA2_REG DDRA
153 #define DDA3_REG DDRA
154 #define DDA4_REG DDRA
155 #define DDA5_REG DDRA
156 #define DDA6_REG DDRA
157 #define DDA7_REG DDRA
160 #define PWM10_REG TCCR1A
161 #define PWM11_REG TCCR1A
162 #define COM1B0_REG TCCR1A
163 #define COM1B1_REG TCCR1A
164 #define COM1A0_REG TCCR1A
165 #define COM1A1_REG TCCR1A
168 #define DDD0_REG DDRD
169 #define DDD1_REG DDRD
170 #define DDD2_REG DDRD
171 #define DDD3_REG DDRD
172 #define DDD4_REG DDRD
173 #define DDD5_REG DDRD
174 #define DDD6_REG DDRD
175 #define DDD7_REG DDRD
178 #define CS10_REG TCCR1B
179 #define CS11_REG TCCR1B
180 #define CS12_REG TCCR1B
181 #define CTC1_REG TCCR1B
182 #define ICES1_REG TCCR1B
183 #define ICNC1_REG TCCR1B
186 #define INTF0_REG GIFR
187 #define INTF1_REG GIFR
190 #define TICIE1_REG TIMSK
191 #define OCIE1B_REG TIMSK
192 #define OCIE1A_REG TIMSK
193 #define TOIE1_REG TIMSK
194 #define TOIE0_REG TIMSK
202 #define UDRIE_REG UCR
203 #define TXCIE_REG UCR
204 #define RXCIE_REG UCR
207 #define SPDR0_REG SPDR
208 #define SPDR1_REG SPDR
209 #define SPDR2_REG SPDR
210 #define SPDR3_REG SPDR
211 #define SPDR4_REG SPDR
212 #define SPDR5_REG SPDR
213 #define SPDR6_REG SPDR
214 #define SPDR7_REG SPDR
217 #define WCOL_REG SPSR
218 #define SPIF_REG SPSR
221 #define ACIS0_REG ACSR
222 #define ACIS1_REG ACSR
223 #define ACIC_REG ACSR
224 #define ACIE_REG ACSR
240 #define OCR1BL0_REG OCR1BL
241 #define OCR1BL1_REG OCR1BL
242 #define OCR1BL2_REG OCR1BL
243 #define OCR1BL3_REG OCR1BL
244 #define OCR1BL4_REG OCR1BL
245 #define OCR1BL5_REG OCR1BL
246 #define OCR1BL6_REG OCR1BL
247 #define OCR1BL7_REG OCR1BL
250 #define ICR1L0_REG ICR1L
251 #define ICR1L1_REG ICR1L
252 #define ICR1L2_REG ICR1L
253 #define ICR1L3_REG ICR1L
254 #define ICR1L4_REG ICR1L
255 #define ICR1L5_REG ICR1L
256 #define ICR1L6_REG ICR1L
257 #define ICR1L7_REG ICR1L
260 #define OCR1BH0_REG OCR1BH
261 #define OCR1BH1_REG OCR1BH
262 #define OCR1BH2_REG OCR1BH
263 #define OCR1BH3_REG OCR1BH
264 #define OCR1BH4_REG OCR1BH
265 #define OCR1BH5_REG OCR1BH
266 #define OCR1BH6_REG OCR1BH
267 #define OCR1BH7_REG OCR1BH
270 #define PIND0_REG PIND
271 #define PIND1_REG PIND
272 #define PIND2_REG PIND
273 #define PIND3_REG PIND
274 #define PIND4_REG PIND
275 #define PIND5_REG PIND
276 #define PIND6_REG PIND
277 #define PIND7_REG PIND
290 #define EERE_REG EECR
291 #define EEWE_REG EECR
292 #define EEMWE_REG EECR
295 #define TCNT1L0_REG TCNT1L
296 #define TCNT1L1_REG TCNT1L
297 #define TCNT1L2_REG TCNT1L
298 #define TCNT1L3_REG TCNT1L
299 #define TCNT1L4_REG TCNT1L
300 #define TCNT1L5_REG TCNT1L
301 #define TCNT1L6_REG TCNT1L
302 #define TCNT1L7_REG TCNT1L
305 #define PORTB0_REG PORTB
306 #define PORTB1_REG PORTB
307 #define PORTB2_REG PORTB
308 #define PORTB3_REG PORTB
309 #define PORTB4_REG PORTB
310 #define PORTB5_REG PORTB
311 #define PORTB6_REG PORTB
312 #define PORTB7_REG PORTB
315 #define PORTD0_REG PORTD
316 #define PORTD1_REG PORTD
317 #define PORTD2_REG PORTD
318 #define PORTD3_REG PORTD
319 #define PORTD4_REG PORTD
320 #define PORTD5_REG PORTD
321 #define PORTD6_REG PORTD
322 #define PORTD7_REG PORTD
325 #define EEAR0_REG EEAR
326 #define EEAR1_REG EEAR
327 #define EEAR2_REG EEAR
328 #define EEAR3_REG EEAR
329 #define EEAR4_REG EEAR
330 #define EEAR5_REG EEAR
331 #define EEAR6_REG EEAR
332 #define EEAR7_REG EEAR
335 #define TCNT1H0_REG TCNT1H
336 #define TCNT1H1_REG TCNT1H
337 #define TCNT1H2_REG TCNT1H
338 #define TCNT1H3_REG TCNT1H
339 #define TCNT1H4_REG TCNT1H
340 #define TCNT1H5_REG TCNT1H
341 #define TCNT1H6_REG TCNT1H
342 #define TCNT1H7_REG TCNT1H
345 #define PORTC0_REG PORTC
346 #define PORTC1_REG PORTC
347 #define PORTC2_REG PORTC
348 #define PORTC3_REG PORTC
349 #define PORTC4_REG PORTC
350 #define PORTC5_REG PORTC
351 #define PORTC6_REG PORTC
352 #define PORTC7_REG PORTC
355 #define PORTA0_REG PORTA
356 #define PORTA1_REG PORTA
357 #define PORTA2_REG PORTA
358 #define PORTA3_REG PORTA
359 #define PORTA4_REG PORTA
360 #define PORTA5_REG PORTA
361 #define PORTA6_REG PORTA
362 #define PORTA7_REG PORTA
365 #define TCNT00_REG TCNT0
366 #define TCNT01_REG TCNT0
367 #define TCNT02_REG TCNT0
368 #define TCNT03_REG TCNT0
369 #define TCNT04_REG TCNT0
370 #define TCNT05_REG TCNT0
371 #define TCNT06_REG TCNT0
372 #define TCNT07_REG TCNT0
375 #define UBRR0_REG UBRR
376 #define UBRR1_REG UBRR
377 #define UBRR2_REG UBRR
378 #define UBRR3_REG UBRR
379 #define UBRR4_REG UBRR
380 #define UBRR5_REG UBRR
381 #define UBRR6_REG UBRR
382 #define UBRR7_REG UBRR
385 #define ICF1_REG TIFR
386 #define OCF1B_REG TIFR
387 #define OCF1A_REG TIFR
388 #define TOV1_REG TIFR
389 #define TOV0_REG TIFR
402 #define PINC0_REG PINC
403 #define PINC1_REG PINC
404 #define PINC2_REG PINC
405 #define PINC3_REG PINC
406 #define PINC4_REG PINC
407 #define PINC5_REG PINC
408 #define PINC6_REG PINC
409 #define PINC7_REG PINC
412 #define PINB0_REG PINB
413 #define PINB1_REG PINB
414 #define PINB2_REG PINB
415 #define PINB3_REG PINB
416 #define PINB4_REG PINB
417 #define PINB5_REG PINB
418 #define PINB6_REG PINB
419 #define PINB7_REG PINB
422 #define PINA0_REG PINA
423 #define PINA1_REG PINA
424 #define PINA2_REG PINA
425 #define PINA3_REG PINA
426 #define PINA4_REG PINA
427 #define PINA5_REG PINA
428 #define PINA6_REG PINA
429 #define PINA7_REG PINA
432 #define ISC00_REG MCUCR
433 #define ISC01_REG MCUCR
434 #define ISC10_REG MCUCR
435 #define ISC11_REG MCUCR
438 #define SRW_REG MCUCR
439 #define SRE_REG MCUCR
442 #define OCR1AH0_REG OCR1AH
443 #define OCR1AH1_REG OCR1AH
444 #define OCR1AH2_REG OCR1AH
445 #define OCR1AH3_REG OCR1AH
446 #define OCR1AH4_REG OCR1AH
447 #define OCR1AH5_REG OCR1AH
448 #define OCR1AH6_REG OCR1AH
449 #define OCR1AH7_REG OCR1AH
452 #define OCR1AL0_REG OCR1AL
453 #define OCR1AL1_REG OCR1AL
454 #define OCR1AL2_REG OCR1AL
455 #define OCR1AL3_REG OCR1AL
456 #define OCR1AL4_REG OCR1AL
457 #define OCR1AL5_REG OCR1AL
458 #define OCR1AL6_REG OCR1AL
459 #define OCR1AL7_REG OCR1AL
462 #define SPR0_REG SPCR
463 #define SPR1_REG SPCR
464 #define CPHA_REG SPCR
465 #define CPOL_REG SPCR
466 #define MSTR_REG SPCR
467 #define DORD_REG SPCR
469 #define SPIE_REG SPCR
472 #define AD0_PORT PORTA
475 #define AD1_PORT PORTA
478 #define AD2_PORT PORTA
481 #define AD3_PORT PORTA
484 #define AD4_PORT PORTA
487 #define AD5_PORT PORTA
490 #define AD6_PORT PORTA
493 #define AD7_PORT PORTA
496 #define T0_PORT PORTB
499 #define T1_PORT PORTB
502 #define AIN0_PORT PORTB
505 #define AIN1_PORT PORTB
508 #define SS_PORT PORTB
511 #define MOSI_PORT PORTB
514 #define MISO_PORT PORTB
517 #define SCK_PORT PORTB
520 #define A8_PORT PORTC
523 #define A9_PORT PORTC
526 #define A10_PORT PORTC
529 #define A11_PORT PORTC
532 #define A12_PORT PORTC
535 #define A13_PORT PORTC
538 #define A14_PORT PORTC
541 #define A15_PORT PORTC
544 #define RXD_PORT PORTD
547 #define TXD_PORT PORTD
550 #define INT0_PORT PORTD
553 #define INT1_PORT PORTD
557 #define OC1A_PORT PORTD
560 #define WR_PORT PORTD
563 #define RD_PORT PORTD