2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER1_AVAILABLE
70 /* overflow interrupt number */
71 #define SIG_OVERFLOW0_NUM 0
72 #define SIG_OVERFLOW1_NUM 1
73 #define SIG_OVERFLOW_TOTAL_NUM 2
75 /* output compare interrupt number */
76 #define SIG_OUTPUT_COMPARE1_NUM 0
77 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 1
81 #define PWM_TOTAL_NUM 1
83 /* input capture interrupt number */
84 #define SIG_INPUT_CAPTURE1_NUM 0
85 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
89 #define WDP0_REG WDTCR
90 #define WDP1_REG WDTCR
91 #define WDP2_REG WDTCR
93 #define WDTOE_REG WDTCR
96 #define INT0_REG GIMSK
97 #define INT1_REG GIMSK
100 #define MUX0_REG ADMUX
101 #define MUX1_REG ADMUX
102 #define MUX2_REG ADMUX
103 #define ADCBG_REG ADMUX
106 #define CS00_REG TCCR0
107 #define CS01_REG TCCR0
108 #define CS02_REG TCCR0
121 #define DDB0_REG DDRB
122 #define DDB1_REG DDRB
123 #define DDB2_REG DDRB
124 #define DDB3_REG DDRB
125 #define DDB4_REG DDRB
126 #define DDB5_REG DDRB
129 #define EEDR0_REG EEDR
130 #define EEDR1_REG EEDR
131 #define EEDR2_REG EEDR
132 #define EEDR3_REG EEDR
133 #define EEDR4_REG EEDR
134 #define EEDR5_REG EEDR
135 #define EEDR6_REG EEDR
136 #define EEDR7_REG EEDR
139 #define DDC0_REG DDRC
140 #define DDC1_REG DDRC
141 #define DDC2_REG DDRC
142 #define DDC3_REG DDRC
143 #define DDC4_REG DDRC
144 #define DDC5_REG DDRC
147 #define PIND0_REG PIND
148 #define PIND1_REG PIND
149 #define PIND2_REG PIND
150 #define PIND3_REG PIND
151 #define PIND4_REG PIND
152 #define PIND5_REG PIND
153 #define PIND6_REG PIND
154 #define PIND7_REG PIND
157 #define PWM10_REG TCCR1A
158 #define PWM11_REG TCCR1A
159 #define COM10_REG TCCR1A
160 #define COM11_REG TCCR1A
163 #define DDD0_REG DDRD
164 #define DDD1_REG DDRD
165 #define DDD2_REG DDRD
166 #define DDD3_REG DDRD
167 #define DDD4_REG DDRD
168 #define DDD5_REG DDRD
169 #define DDD6_REG DDRD
170 #define DDD7_REG DDRD
173 #define CS10_REG TCCR1B
174 #define CS11_REG TCCR1B
175 #define CS12_REG TCCR1B
176 #define CTC1_REG TCCR1B
177 #define ICES1_REG TCCR1B
178 #define ICNC1_REG TCCR1B
181 #define INTF0_REG GIFR
182 #define INTF1_REG GIFR
185 #define TOIE0_REG TIMSK
186 #define TICIE1_REG TIMSK
187 #define OCIE1_REG TIMSK
188 #define TOIE1_REG TIMSK
191 #define SPDR0_REG SPDR
192 #define SPDR1_REG SPDR
193 #define SPDR2_REG SPDR
194 #define SPDR3_REG SPDR
195 #define SPDR4_REG SPDR
196 #define SPDR5_REG SPDR
197 #define SPDR6_REG SPDR
198 #define SPDR7_REG SPDR
201 #define UBRRHI0_REG UBRRHI
202 #define UBRRHI1_REG UBRRHI
203 #define UBRRHI2_REG UBRRHI
204 #define UBRRHI3_REG UBRRHI
207 #define WCOL_REG SPSR
208 #define SPIF_REG SPSR
211 #define ACIS0_REG ACSR
212 #define ACIS1_REG ACSR
213 #define ACIC_REG ACSR
214 #define ACIE_REG ACSR
217 #define AINBG_REG ACSR
221 #define ICR1H0_REG ICR1H
222 #define ICR1H1_REG ICR1H
223 #define ICR1H2_REG ICR1H
224 #define ICR1H3_REG ICR1H
225 #define ICR1H4_REG ICR1H
226 #define ICR1H5_REG ICR1H
227 #define ICR1H6_REG ICR1H
228 #define ICR1H7_REG ICR1H
231 #define MPCM_REG UCSRA
234 #define UDRE_REG UCSRA
235 #define TXC_REG UCSRA
236 #define RXC_REG UCSRA
239 #define TXB8_REG UCSRB
240 #define RXB8_REG UCSRB
241 #define CHR9_REG UCSRB
242 #define TXEN_REG UCSRB
243 #define RXEN_REG UCSRB
244 #define UDRIE_REG UCSRB
245 #define TXCIE_REG UCSRB
246 #define RXCIE_REG UCSRB
249 #define ICR1L0_REG ICR1L
250 #define ICR1L1_REG ICR1L
251 #define ICR1L2_REG ICR1L
252 #define ICR1L3_REG ICR1L
253 #define ICR1L4_REG ICR1L
254 #define ICR1L5_REG ICR1L
255 #define ICR1L6_REG ICR1L
256 #define ICR1L7_REG ICR1L
259 #define UBRR0_REG UBRR
260 #define UBRR1_REG UBRR
261 #define UBRR2_REG UBRR
262 #define UBRR3_REG UBRR
263 #define UBRR4_REG UBRR
264 #define UBRR5_REG UBRR
265 #define UBRR6_REG UBRR
266 #define UBRR7_REG UBRR
269 #define ADC0_REG ADCL
270 #define ADC1_REG ADCL
271 #define ADC2_REG ADCL
272 #define ADC3_REG ADCL
273 #define ADC4_REG ADCL
274 #define ADC5_REG ADCL
275 #define ADC6_REG ADCL
276 #define ADC7_REG ADCL
279 #define PORF_REG MCUSR
280 #define EXTRF_REG MCUSR
281 #define BORF_REG MCUSR
282 #define WDRF_REG MCUSR
285 #define EERE_REG EECR
286 #define EEWE_REG EECR
287 #define EEMWE_REG EECR
288 #define EERIE_REG EECR
291 #define TCNT1L0_REG TCNT1L
292 #define TCNT1L1_REG TCNT1L
293 #define TCNT1L2_REG TCNT1L
294 #define TCNT1L3_REG TCNT1L
295 #define TCNT1L4_REG TCNT1L
296 #define TCNT1L5_REG TCNT1L
297 #define TCNT1L6_REG TCNT1L
298 #define TCNT1L7_REG TCNT1L
301 #define PORTB0_REG PORTB
302 #define PORTB1_REG PORTB
303 #define PORTB2_REG PORTB
304 #define PORTB3_REG PORTB
305 #define PORTB4_REG PORTB
306 #define PORTB5_REG PORTB
309 #define PORTD0_REG PORTD
310 #define PORTD1_REG PORTD
311 #define PORTD2_REG PORTD
312 #define PORTD3_REG PORTD
313 #define PORTD4_REG PORTD
314 #define PORTD5_REG PORTD
315 #define PORTD6_REG PORTD
316 #define PORTD7_REG PORTD
319 #define EEAR0_REG EEAR
320 #define EEAR1_REG EEAR
321 #define EEAR2_REG EEAR
322 #define EEAR3_REG EEAR
323 #define EEAR4_REG EEAR
324 #define EEAR5_REG EEAR
325 #define EEAR6_REG EEAR
326 #define EEAR7_REG EEAR
329 #define TCNT1H0_REG TCNT1H
330 #define TCNT1H1_REG TCNT1H
331 #define TCNT1H2_REG TCNT1H
332 #define TCNT1H3_REG TCNT1H
333 #define TCNT1H4_REG TCNT1H
334 #define TCNT1H5_REG TCNT1H
335 #define TCNT1H6_REG TCNT1H
336 #define TCNT1H7_REG TCNT1H
339 #define PORTC0_REG PORTC
340 #define PORTC1_REG PORTC
341 #define PORTC2_REG PORTC
342 #define PORTC3_REG PORTC
343 #define PORTC4_REG PORTC
344 #define PORTC5_REG PORTC
347 #define ADC8_REG ADCH
348 #define ADC9_REG ADCH
351 #define TCNT00_REG TCNT0
352 #define TCNT01_REG TCNT0
353 #define TCNT02_REG TCNT0
354 #define TCNT03_REG TCNT0
355 #define TCNT04_REG TCNT0
356 #define TCNT05_REG TCNT0
357 #define TCNT06_REG TCNT0
358 #define TCNT07_REG TCNT0
361 #define TOV0_REG TIFR
362 #define ICF1_REG TIFR
363 #define OCF1_REG TIFR
364 #define TOV1_REG TIFR
377 #define OCR1AL0_REG OCR1L
378 #define OCR1AL1_REG OCR1L
379 #define OCR1AL2_REG OCR1L
380 #define OCR1AL3_REG OCR1L
381 #define OCR1AL4_REG OCR1L
382 #define OCR1AL5_REG OCR1L
383 #define OCR1AL6_REG OCR1L
384 #define OCR1AL7_REG OCR1L
387 #define ADPS0_REG ADCSR
388 #define ADPS1_REG ADCSR
389 #define ADPS2_REG ADCSR
390 #define ADIE_REG ADCSR
391 #define ADIF_REG ADCSR
392 #define ADFR_REG ADCSR
393 #define ADSC_REG ADCSR
394 #define ADEN_REG ADCSR
397 #define OCR1AH0_REG OCR1H
398 #define OCR1AH1_REG OCR1H
399 #define OCR1AH2_REG OCR1H
400 #define OCR1AH3_REG OCR1H
401 #define OCR1AH4_REG OCR1H
402 #define OCR1AH5_REG OCR1H
403 #define OCR1AH6_REG OCR1H
404 #define OCR1AH7_REG OCR1H
407 #define PINC0_REG PINC
408 #define PINC1_REG PINC
409 #define PINC2_REG PINC
410 #define PINC3_REG PINC
411 #define PINC4_REG PINC
412 #define PINC5_REG PINC
415 #define PINB0_REG PINB
416 #define PINB1_REG PINB
417 #define PINB2_REG PINB
418 #define PINB3_REG PINB
419 #define PINB4_REG PINB
420 #define PINB5_REG PINB
433 #define ISC00_REG MCUCR
434 #define ISC01_REG MCUCR
435 #define ISC10_REG MCUCR
436 #define ISC11_REG MCUCR
441 #define SPR0_REG SPCR
442 #define SPR1_REG SPCR
443 #define CPHA_REG SPCR
444 #define CPOL_REG SPCR
445 #define MSTR_REG SPCR
446 #define DORD_REG SPCR
448 #define SPIE_REG SPCR
451 #define ADC0_PORT PORTC
454 #define ADC1_PORT PORTC
457 #define ADC2_PORT PORTC
460 #define ADC3_PORT PORTC
463 #define ADC4_PORT PORTC
466 #define ADC5_PORT PORTC
469 #define RXD_PORT PORTD
472 #define TXD_PORT PORTD
475 #define INT0_PORT PORTD