2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER0A_AVAILABLE
69 #define TIMER0B_AVAILABLE
70 #define TIMER1_AVAILABLE
71 #define TIMER1A_AVAILABLE
72 #define TIMER1B_AVAILABLE
73 #define TIMER1C_AVAILABLE
75 /* overflow interrupt number */
76 #define SIG_OVERFLOW0_NUM 0
77 #define SIG_OVERFLOW1_NUM 1
78 #define SIG_OVERFLOW_TOTAL_NUM 2
80 /* output compare interrupt number */
81 #define SIG_OUTPUT_COMPARE0A_NUM 0
82 #define SIG_OUTPUT_COMPARE0B_NUM 1
83 #define SIG_OUTPUT_COMPARE1A_NUM 2
84 #define SIG_OUTPUT_COMPARE1B_NUM 3
85 #define SIG_OUTPUT_COMPARE1C_NUM 4
86 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
94 #define PWM_TOTAL_NUM 5
96 /* input capture interrupt number */
97 #define SIG_INPUT_CAPTURE1_NUM 0
98 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
102 #define SUSPE_REG UDIEN
103 #define SOFE_REG UDIEN
104 #define EORSTE_REG UDIEN
105 #define WAKEUPE_REG UDIEN
106 #define EORSME_REG UDIEN
107 #define UPRSME_REG UDIEN
110 #define WDP0_REG WDTCSR
111 #define WDP1_REG WDTCSR
112 #define WDP2_REG WDTCSR
113 #define WDE_REG WDTCSR
114 #define WDCE_REG WDTCSR
115 #define WDP3_REG WDTCSR
116 #define WDIE_REG WDTCSR
117 #define WDIF_REG WDTCSR
120 #define EEDR0_REG EEDR
121 #define EEDR1_REG EEDR
122 #define EEDR2_REG EEDR
123 #define EEDR3_REG EEDR
124 #define EEDR4_REG EEDR
125 #define EEDR5_REG EEDR
126 #define EEDR6_REG EEDR
127 #define EEDR7_REG EEDR
130 #define ACIS0_REG ACSR
131 #define ACIS1_REG ACSR
132 #define ACIC_REG ACSR
133 #define ACIE_REG ACSR
136 #define ACBG_REG ACSR
140 #define PS2EN_REG PS2CON
143 #define EPRST0_REG UERST
144 #define EPRST1_REG UERST
145 #define EPRST2_REG UERST
146 #define EPRST3_REG UERST
147 #define EPRST4_REG UERST
150 #define ALLOC_REG UECFG1X
151 #define EPBK0_REG UECFG1X
152 #define EPBK1_REG UECFG1X
153 #define EPSIZE0_REG UECFG1X
154 #define EPSIZE1_REG UECFG1X
155 #define EPSIZE2_REG UECFG1X
158 #define UDR1_0_REG UDR1
159 #define UDR1_1_REG UDR1
160 #define UDR1_2_REG UDR1
161 #define UDR1_3_REG UDR1
162 #define UDR1_4_REG UDR1
163 #define UDR1_5_REG UDR1
164 #define UDR1_6_REG UDR1
165 #define UDR1_7_REG UDR1
168 #define SPDR0_REG SPDR
169 #define SPDR1_REG SPDR
170 #define SPDR2_REG SPDR
171 #define SPDR3_REG SPDR
172 #define SPDR4_REG SPDR
173 #define SPDR5_REG SPDR
174 #define SPDR6_REG SPDR
175 #define SPDR7_REG SPDR
178 #define SPI2X_REG SPSR
179 #define WCOL_REG SPSR
180 #define SPIF_REG SPSR
183 #define ICR1H0_REG ICR1H
184 #define ICR1H1_REG ICR1H
185 #define ICR1H2_REG ICR1H
186 #define ICR1H3_REG ICR1H
187 #define ICR1H4_REG ICR1H
188 #define ICR1H5_REG ICR1H
189 #define ICR1H6_REG ICR1H
190 #define ICR1H7_REG ICR1H
193 #define ICR1L0_REG ICR1L
194 #define ICR1L1_REG ICR1L
195 #define ICR1L2_REG ICR1L
196 #define ICR1L3_REG ICR1L
197 #define ICR1L4_REG ICR1L
198 #define ICR1L5_REG ICR1L
199 #define ICR1L6_REG ICR1L
200 #define ICR1L7_REG ICR1L
203 #define EPINT0_REG UEINT
204 #define EPINT1_REG UEINT
205 #define EPINT2_REG UEINT
206 #define EPINT3_REG UEINT
207 #define EPINT4_REG UEINT
210 #define TCNT1L0_REG TCNT1L
211 #define TCNT1L1_REG TCNT1L
212 #define TCNT1L2_REG TCNT1L
213 #define TCNT1L3_REG TCNT1L
214 #define TCNT1L4_REG TCNT1L
215 #define TCNT1L5_REG TCNT1L
216 #define TCNT1L6_REG TCNT1L
217 #define TCNT1L7_REG TCNT1L
220 #define PORTD0_REG PORTD
221 #define PORTD1_REG PORTD
222 #define PORTD2_REG PORTD
223 #define PORTD3_REG PORTD
224 #define PORTD4_REG PORTD
225 #define PORTD5_REG PORTD
226 #define PORTD6_REG PORTD
227 #define PORTD7_REG PORTD
230 #define TCNT1H0_REG TCNT1H
231 #define TCNT1H1_REG TCNT1H
232 #define TCNT1H2_REG TCNT1H
233 #define TCNT1H3_REG TCNT1H
234 #define TCNT1H4_REG TCNT1H
235 #define TCNT1H5_REG TCNT1H
236 #define TCNT1H6_REG TCNT1H
237 #define TCNT1H7_REG TCNT1H
240 #define PORTC0_REG PORTC
241 #define PORTC1_REG PORTC
242 #define PORTC2_REG PORTC
243 #define PORTC4_REG PORTC
244 #define PORTC5_REG PORTC
245 #define PORTC6_REG PORTC
246 #define PORTC7_REG PORTC
249 #define REGDIS_REG REGCR
252 #define ISC40_REG EICRB
253 #define ISC41_REG EICRB
254 #define ISC50_REG EICRB
255 #define ISC51_REG EICRB
256 #define ISC60_REG EICRB
257 #define ISC61_REG EICRB
258 #define ISC70_REG EICRB
259 #define ISC71_REG EICRB
262 #define DAT0_REG UEDATX
263 #define DAT1_REG UEDATX
264 #define DAT2_REG UEDATX
265 #define DAT3_REG UEDATX
266 #define DAT4_REG UEDATX
267 #define DAT5_REG UEDATX
268 #define DAT6_REG UEDATX
269 #define DAT7_REG UEDATX
272 #define ISC00_REG EICRA
273 #define ISC01_REG EICRA
274 #define ISC10_REG EICRA
275 #define ISC11_REG EICRA
276 #define ISC20_REG EICRA
277 #define ISC21_REG EICRA
278 #define ISC30_REG EICRA
279 #define ISC31_REG EICRA
282 #define EPDIR_REG UECFG0X
283 #define EPTYPE0_REG UECFG0X
284 #define EPTYPE1_REG UECFG0X
287 #define AIN0D_REG DIDR1
288 #define AIN1D_REG DIDR1
291 #define EXCKSEL0_REG CLKSEL1
292 #define EXCKSEL1_REG CLKSEL1
293 #define EXCKSEL2_REG CLKSEL1
294 #define EXCKSEL3_REG CLKSEL1
295 #define RCCKSEL0_REG CLKSEL1
296 #define RCCKSEL1_REG CLKSEL1
297 #define RCCKSEL2_REG CLKSEL1
298 #define RCCKSEL3_REG CLKSEL1
301 #define CLKS_REG CLKSEL0
302 #define EXTE_REG CLKSEL0
303 #define RCE_REG CLKSEL0
304 #define EXSUT0_REG CLKSEL0
305 #define EXSUT1_REG CLKSEL0
306 #define RCSUT0_REG CLKSEL0
307 #define RCSUT1_REG CLKSEL0
310 #define CLKPS0_REG CLKPR
311 #define CLKPS1_REG CLKPR
312 #define CLKPS2_REG CLKPR
313 #define CLKPS3_REG CLKPR
314 #define CLKPCE_REG CLKPR
319 #define DATAI_REG UPOE
320 #define SCKI_REG UPOE
321 #define UPDRV0_REG UPOE
322 #define UPDRV1_REG UPOE
323 #define UPWE0_REG UPOE
324 #define UPWE1_REG UPOE
337 #define EPNUM0_REG UENUM
338 #define EPNUM1_REG UENUM
339 #define EPNUM2_REG UENUM
342 #define UBRR1_0_REG UBRR1L
343 #define UBRR1_1_REG UBRR1L
344 #define UBRR1_2_REG UBRR1L
345 #define UBRR1_3_REG UBRR1L
346 #define UBRR1_4_REG UBRR1L
347 #define UBRR1_5_REG UBRR1L
348 #define UBRR1_6_REG UBRR1L
349 #define UBRR1_7_REG UBRR1L
352 #define DDC0_REG DDRC
353 #define DDC1_REG DDRC
354 #define DDC2_REG DDRC
355 #define DDC4_REG DDRC
356 #define DDC5_REG DDRC
357 #define DDC6_REG DDRC
358 #define DDC7_REG DDRC
361 #define WGM10_REG TCCR1A
362 #define WGM11_REG TCCR1A
363 #define COM1C0_REG TCCR1A
364 #define COM1C1_REG TCCR1A
365 #define COM1B0_REG TCCR1A
366 #define COM1B1_REG TCCR1A
367 #define COM1A0_REG TCCR1A
368 #define COM1A1_REG TCCR1A
371 #define FOC1C_REG TCCR1C
372 #define FOC1B_REG TCCR1C
373 #define FOC1A_REG TCCR1C
376 #define CS10_REG TCCR1B
377 #define CS11_REG TCCR1B
378 #define CS12_REG TCCR1B
379 #define WGM12_REG TCCR1B
380 #define WGM13_REG TCCR1B
381 #define ICES1_REG TCCR1B
382 #define ICNC1_REG TCCR1B
385 #define CAL0_REG OSCCAL
386 #define CAL1_REG OSCCAL
387 #define CAL2_REG OSCCAL
388 #define CAL3_REG OSCCAL
389 #define CAL4_REG OSCCAL
390 #define CAL5_REG OSCCAL
391 #define CAL6_REG OSCCAL
392 #define CAL7_REG OSCCAL
395 #define GPIOR10_REG GPIOR1
396 #define GPIOR11_REG GPIOR1
397 #define GPIOR12_REG GPIOR1
398 #define GPIOR13_REG GPIOR1
399 #define GPIOR14_REG GPIOR1
400 #define GPIOR15_REG GPIOR1
401 #define GPIOR16_REG GPIOR1
402 #define GPIOR17_REG GPIOR1
405 #define GPIOR00_REG GPIOR0
406 #define GPIOR01_REG GPIOR0
407 #define GPIOR02_REG GPIOR0
408 #define GPIOR03_REG GPIOR0
409 #define GPIOR04_REG GPIOR0
410 #define GPIOR05_REG GPIOR0
411 #define GPIOR06_REG GPIOR0
412 #define GPIOR07_REG GPIOR0
415 #define GPIOR20_REG GPIOR2
416 #define GPIOR21_REG GPIOR2
417 #define GPIOR22_REG GPIOR2
418 #define GPIOR23_REG GPIOR2
419 #define GPIOR24_REG GPIOR2
420 #define GPIOR25_REG GPIOR2
421 #define GPIOR26_REG GPIOR2
422 #define GPIOR27_REG GPIOR2
425 #define DETACH_REG UDCON
426 #define RMWKUP_REG UDCON
427 #define RSTCPU_REG UDCON
430 #define WCLKD0_REG WDTCKD
431 #define WCLKD1_REG WDTCKD
432 #define WDEWIE_REG WDTCKD
433 #define WDEWIF_REG WDTCKD
436 #define PCIE0_REG PCICR
437 #define PCIE1_REG PCICR
440 #define TCNT0_0_REG TCNT0
441 #define TCNT0_1_REG TCNT0
442 #define TCNT0_2_REG TCNT0
443 #define TCNT0_3_REG TCNT0
444 #define TCNT0_4_REG TCNT0
445 #define TCNT0_5_REG TCNT0
446 #define TCNT0_6_REG TCNT0
447 #define TCNT0_7_REG TCNT0
450 #define SUSPI_REG UDINT
451 #define SOFI_REG UDINT
452 #define EORSTI_REG UDINT
453 #define WAKEUPI_REG UDINT
454 #define EORSMI_REG UDINT
455 #define UPRSMI_REG UDINT
458 #define CS00_REG TCCR0B
459 #define CS01_REG TCCR0B
460 #define CS02_REG TCCR0B
461 #define WGM02_REG TCCR0B
462 #define FOC0B_REG TCCR0B
463 #define FOC0A_REG TCCR0B
466 #define FNCERR_REG UDMFN
469 #define WGM00_REG TCCR0A
470 #define WGM01_REG TCCR0A
471 #define COM0B0_REG TCCR0A
472 #define COM0B1_REG TCCR0A
473 #define COM0A0_REG TCCR0A
474 #define COM0A1_REG TCCR0A
477 #define DWDR0_REG DWDR
478 #define DWDR1_REG DWDR
479 #define DWDR2_REG DWDR
480 #define DWDR3_REG DWDR
481 #define DWDR4_REG DWDR
482 #define DWDR5_REG DWDR
483 #define DWDR6_REG DWDR
484 #define DWDR7_REG DWDR
487 #define SPR0_REG SPCR
488 #define SPR1_REG SPCR
489 #define CPHA_REG SPCR
490 #define CPOL_REG SPCR
491 #define MSTR_REG SPCR
492 #define DORD_REG SPCR
494 #define SPIE_REG SPCR
497 #define TOV1_REG TIFR1
498 #define OCF1A_REG TIFR1
499 #define OCF1B_REG TIFR1
500 #define OCF1C_REG TIFR1
501 #define ICF1_REG TIFR1
504 #define BYCT0_REG UEBCLX
505 #define BYCT1_REG UEBCLX
506 #define BYCT2_REG UEBCLX
507 #define BYCT3_REG UEBCLX
508 #define BYCT4_REG UEBCLX
509 #define BYCT5_REG UEBCLX
510 #define BYCT6_REG UEBCLX
511 #define BYCT7_REG UEBCLX
514 #define CURRBK0_REG UESTA1X
515 #define CURRBK1_REG UESTA1X
516 #define CTRLDIR_REG UESTA1X
519 #define PSRSYNC_REG GTCCR
520 #define TSM_REG GTCCR
533 #define TXINI_REG UEINTX
534 #define STALLEDI_REG UEINTX
535 #define RXOUTI_REG UEINTX
536 #define RXSTPI_REG UEINTX
537 #define NAKOUTI_REG UEINTX
538 #define RWAL_REG UEINTX
539 #define NAKINI_REG UEINTX
540 #define FIFOCON_REG UEINTX
543 #define OCR1BL0_REG OCR1BL
544 #define OCR1BL1_REG OCR1BL
545 #define OCR1BL2_REG OCR1BL
546 #define OCR1BL3_REG OCR1BL
547 #define OCR1BL4_REG OCR1BL
548 #define OCR1BL5_REG OCR1BL
549 #define OCR1BL6_REG OCR1BL
550 #define OCR1BL7_REG OCR1BL
553 #define OCR1BH0_REG OCR1BH
554 #define OCR1BH1_REG OCR1BH
555 #define OCR1BH2_REG OCR1BH
556 #define OCR1BH3_REG OCR1BH
557 #define OCR1BH4_REG OCR1BH
558 #define OCR1BH5_REG OCR1BH
559 #define OCR1BH6_REG OCR1BH
560 #define OCR1BH7_REG OCR1BH
573 #define FRZCLK_REG USBCON
574 #define USBE_REG USBCON
577 #define PORF_REG MCUSR
578 #define EXTRF_REG MCUSR
579 #define BORF_REG MCUSR
580 #define WDRF_REG MCUSR
581 #define USBRF_REG MCUSR
584 #define EERE_REG EECR
585 #define EEPE_REG EECR
586 #define EEMPE_REG EECR
587 #define EERIE_REG EECR
588 #define EEPM0_REG EECR
589 #define EEPM1_REG EECR
598 #define PCIF0_REG PCIFR
599 #define PCIF1_REG PCIFR
602 #define EPEN_REG UECONX
603 #define RSTDT_REG UECONX
604 #define STALLRQC_REG UECONX
605 #define STALLRQ_REG UECONX
608 #define EEAR8_REG EEARH
609 #define EEAR9_REG EEARH
610 #define EEAR10_REG EEARH
611 #define EEAR11_REG EEARH
614 #define EEAR0_REG EEARL
615 #define EEAR1_REG EEARL
616 #define EEAR2_REG EEARL
617 #define EEAR3_REG EEARL
618 #define EEAR4_REG EEARL
619 #define EEAR5_REG EEARL
620 #define EEAR6_REG EEARL
621 #define EEAR7_REG EEARL
624 #define IVCE_REG MCUCR
625 #define IVSEL_REG MCUCR
626 #define PUD_REG MCUCR
629 #define OCR1CL0_REG OCR1CL
630 #define OCR1CL1_REG OCR1CL
631 #define OCR1CL2_REG OCR1CL
632 #define OCR1CL3_REG OCR1CL
633 #define OCR1CL4_REG OCR1CL
634 #define OCR1CL5_REG OCR1CL
635 #define OCR1CL6_REG OCR1CL
636 #define OCR1CL7_REG OCR1CL
639 #define OCR1CH0_REG OCR1CH
640 #define OCR1CH1_REG OCR1CH
641 #define OCR1CH2_REG OCR1CH
642 #define OCR1CH3_REG OCR1CH
643 #define OCR1CH4_REG OCR1CH
644 #define OCR1CH5_REG OCR1CH
645 #define OCR1CH6_REG OCR1CH
646 #define OCR1CH7_REG OCR1CH
649 #define TXINE_REG UEIENX
650 #define STALLEDE_REG UEIENX
651 #define RXOUTE_REG UEIENX
652 #define RXSTPE_REG UEIENX
653 #define NAKOUTE_REG UEIENX
654 #define NAKINE_REG UEIENX
655 #define FLERRE_REG UEIENX
658 #define TXB81_REG UCSR1B
659 #define RXB81_REG UCSR1B
660 #define UCSZ12_REG UCSR1B
661 #define TXEN1_REG UCSR1B
662 #define RXEN1_REG UCSR1B
663 #define UDRIE1_REG UCSR1B
664 #define TXCIE1_REG UCSR1B
665 #define RXCIE1_REG UCSR1B
668 #define UCPOL1_REG UCSR1C
669 #define UCSZ10_REG UCSR1C
670 #define UCSZ11_REG UCSR1C
671 #define USBS1_REG UCSR1C
672 #define UPM10_REG UCSR1C
673 #define UPM11_REG UCSR1C
674 #define UMSEL10_REG UCSR1C
675 #define UMSEL11_REG UCSR1C
678 #define MPCM1_REG UCSR1A
679 #define U2X1_REG UCSR1A
680 #define UPE1_REG UCSR1A
681 #define DOR1_REG UCSR1A
682 #define FE1_REG UCSR1A
683 #define UDRE1_REG UCSR1A
684 #define TXC1_REG UCSR1A
685 #define RXC1_REG UCSR1A
688 #define RTSEN_REG UCSR1D
689 #define CTSEN_REG UCSR1D
692 #define DDB0_REG DDRB
693 #define DDB1_REG DDRB
694 #define DDB2_REG DDRB
695 #define DDB3_REG DDRB
696 #define DDB4_REG DDRB
697 #define DDB5_REG DDRB
698 #define DDB6_REG DDRB
699 #define DDB7_REG DDRB
702 #define EIND0_REG EIND
705 #define FNUM0_REG UDFNUML
706 #define FNUM1_REG UDFNUML
707 #define FNUM2_REG UDFNUML
708 #define FNUM3_REG UDFNUML
709 #define FNUM4_REG UDFNUML
710 #define FNUM5_REG UDFNUML
711 #define FNUM6_REG UDFNUML
712 #define FNUM7_REG UDFNUML
715 #define FNUM8_REG UDFNUMH
716 #define FNUM9_REG UDFNUMH
717 #define FNUM10_REG UDFNUMH
720 #define INT0_REG EIMSK
721 #define INT1_REG EIMSK
722 #define INT2_REG EIMSK
723 #define INT3_REG EIMSK
724 #define INT4_REG EIMSK
725 #define INT5_REG EIMSK
726 #define INT6_REG EIMSK
727 #define INT7_REG EIMSK
730 #define PRSPI_REG PRR0
731 #define PRTIM1_REG PRR0
732 #define PRTIM0_REG PRR0
735 #define UBRR1_8_REG UBRR1H
736 #define UBRR1_9_REG UBRR1H
737 #define UBRR1_10_REG UBRR1H
738 #define UBRR1_11_REG UBRR1H
741 #define OCROA_0_REG OCR0A
742 #define OCROA_1_REG OCR0A
743 #define OCROA_2_REG OCR0A
744 #define OCROA_3_REG OCR0A
745 #define OCROA_4_REG OCR0A
746 #define OCROA_5_REG OCR0A
747 #define OCROA_6_REG OCR0A
748 #define OCROA_7_REG OCR0A
751 #define OCR0B_0_REG OCR0B
752 #define OCR0B_1_REG OCR0B
753 #define OCR0B_2_REG OCR0B
754 #define OCR0B_3_REG OCR0B
755 #define OCR0B_4_REG OCR0B
756 #define OCR0B_5_REG OCR0B
757 #define OCR0B_6_REG OCR0B
758 #define OCR0B_7_REG OCR0B
761 #define DDD0_REG DDRD
762 #define DDD1_REG DDRD
763 #define DDD2_REG DDRD
764 #define DDD3_REG DDRD
765 #define DDD4_REG DDRD
766 #define DDD5_REG DDRD
767 #define DDD6_REG DDRD
768 #define DDD7_REG DDRD
771 #define UADD0_REG UDADDR
772 #define UADD1_REG UDADDR
773 #define UADD2_REG UDADDR
774 #define UADD3_REG UDADDR
775 #define UADD4_REG UDADDR
776 #define UADD5_REG UDADDR
777 #define UADD6_REG UDADDR
778 #define ADDEN_REG UDADDR
781 #define SPMEN_REG SPMCSR
782 #define PGERS_REG SPMCSR
783 #define PGWRT_REG SPMCSR
784 #define BLBSET_REG SPMCSR
785 #define RWWSRE_REG SPMCSR
786 #define SIGRD_REG SPMCSR
787 #define RWWSB_REG SPMCSR
788 #define SPMIE_REG SPMCSR
791 #define NBUSYBK0_REG UESTA0X
792 #define NBUSYBK1_REG UESTA0X
793 #define DTSEQ0_REG UESTA0X
794 #define DTSEQ1_REG UESTA0X
795 #define UNDERFI_REG UESTA0X
796 #define OVERFI_REG UESTA0X
797 #define CFGOK_REG UESTA0X
800 #define PORTB0_REG PORTB
801 #define PORTB1_REG PORTB
802 #define PORTB2_REG PORTB
803 #define PORTB3_REG PORTB
804 #define PORTB4_REG PORTB
805 #define PORTB5_REG PORTB
806 #define PORTB6_REG PORTB
807 #define PORTB7_REG PORTB
810 #define TOIE0_REG TIMSK0
811 #define OCIE0A_REG TIMSK0
812 #define OCIE0B_REG TIMSK0
815 #define TOIE1_REG TIMSK1
816 #define OCIE1A_REG TIMSK1
817 #define OCIE1B_REG TIMSK1
818 #define OCIE1C_REG TIMSK1
819 #define ICIE1_REG TIMSK1
822 #define EXTON_REG CLKSTA
823 #define RCON_REG CLKSTA
826 #define PLOCK_REG PLLCSR
827 #define PLLE_REG PLLCSR
828 #define PLLP0_REG PLLCSR
829 #define PLLP1_REG PLLCSR
830 #define PLLP2_REG PLLCSR
833 #define PCINT0_REG PCMSK0
834 #define PCINT1_REG PCMSK0
835 #define PCINT2_REG PCMSK0
836 #define PCINT3_REG PCMSK0
837 #define PCINT4_REG PCMSK0
838 #define PCINT5_REG PCMSK0
839 #define PCINT6_REG PCMSK0
840 #define PCINT7_REG PCMSK0
843 #define PCINT8_REG PCMSK1
844 #define PCINT9_REG PCMSK1
845 #define PCINT10_REG PCMSK1
846 #define PCINT11_REG PCMSK1
847 #define PCINT12_REG PCMSK1
850 #define PINC0_REG PINC
851 #define PINC1_REG PINC
852 #define PINC2_REG PINC
853 #define PINC4_REG PINC
854 #define PINC5_REG PINC
855 #define PINC6_REG PINC
856 #define PINC7_REG PINC
859 #define PINB0_REG PINB
860 #define PINB1_REG PINB
861 #define PINB2_REG PINB
862 #define PINB3_REG PINB
863 #define PINB4_REG PINB
864 #define PINB5_REG PINB
865 #define PINB6_REG PINB
866 #define PINB7_REG PINB
869 #define INTF0_REG EIFR
870 #define INTF1_REG EIFR
871 #define INTF2_REG EIFR
872 #define INTF3_REG EIFR
873 #define INTF4_REG EIFR
874 #define INTF5_REG EIFR
875 #define INTF6_REG EIFR
876 #define INTF7_REG EIFR
879 #define PIND0_REG PIND
880 #define PIND1_REG PIND
881 #define PIND2_REG PIND
882 #define PIND3_REG PIND
883 #define PIND4_REG PIND
884 #define PIND5_REG PIND
885 #define PIND6_REG PIND
886 #define PIND7_REG PIND
889 #define OCR1AH0_REG OCR1AH
890 #define OCR1AH1_REG OCR1AH
891 #define OCR1AH2_REG OCR1AH
892 #define OCR1AH3_REG OCR1AH
893 #define OCR1AH4_REG OCR1AH
894 #define OCR1AH5_REG OCR1AH
895 #define OCR1AH6_REG OCR1AH
896 #define OCR1AH7_REG OCR1AH
899 #define OCR1AL0_REG OCR1AL
900 #define OCR1AL1_REG OCR1AL
901 #define OCR1AL2_REG OCR1AL
902 #define OCR1AL3_REG OCR1AL
903 #define OCR1AL4_REG OCR1AL
904 #define OCR1AL5_REG OCR1AL
905 #define OCR1AL6_REG OCR1AL
906 #define OCR1AL7_REG OCR1AL
909 #define TOV0_REG TIFR0
910 #define OCF0A_REG TIFR0
911 #define OCF0B_REG TIFR0
914 #define PRUSART1_REG PRR1
915 #define PRUSB_REG PRR1