2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_32 3
32 #define TIMER0_PRESCALER_DIV_64 4
33 #define TIMER0_PRESCALER_DIV_128 5
34 #define TIMER0_PRESCALER_DIV_256 6
35 #define TIMER0_PRESCALER_DIV_1024 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 32
41 #define TIMER0_PRESCALER_REG_4 64
42 #define TIMER0_PRESCALER_REG_5 128
43 #define TIMER0_PRESCALER_REG_6 256
44 #define TIMER0_PRESCALER_REG_7 1024
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_64 3
70 #define TIMER2_PRESCALER_DIV_256 4
71 #define TIMER2_PRESCALER_DIV_1024 5
72 #define TIMER2_PRESCALER_DIV_FALL 6
73 #define TIMER2_PRESCALER_DIV_RISE 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 64
79 #define TIMER2_PRESCALER_REG_4 256
80 #define TIMER2_PRESCALER_REG_5 1024
81 #define TIMER2_PRESCALER_REG_6 -1
82 #define TIMER2_PRESCALER_REG_7 -2
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER1_AVAILABLE
88 #define TIMER1A_AVAILABLE
89 #define TIMER1B_AVAILABLE
90 #define TIMER2_AVAILABLE
92 /* overflow interrupt number */
93 #define SIG_OVERFLOW0_NUM 0
94 #define SIG_OVERFLOW1_NUM 1
95 #define SIG_OVERFLOW2_NUM 2
96 #define SIG_OVERFLOW_TOTAL_NUM 3
98 /* output compare interrupt number */
99 #define SIG_OUTPUT_COMPARE0_NUM 0
100 #define SIG_OUTPUT_COMPARE1A_NUM 1
101 #define SIG_OUTPUT_COMPARE1B_NUM 2
102 #define SIG_OUTPUT_COMPARE2_NUM 3
103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
110 #define PWM_TOTAL_NUM 4
112 /* input capture interrupt number */
113 #define SIG_INPUT_CAPTURE1_NUM 0
114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
118 #define WDP0_REG WDTCR
119 #define WDP1_REG WDTCR
120 #define WDP2_REG WDTCR
121 #define WDE_REG WDTCR
122 #define WDTOE_REG WDTCR
125 #define ICR1H0_REG ICR1H
126 #define ICR1H1_REG ICR1H
127 #define ICR1H2_REG ICR1H
128 #define ICR1H3_REG ICR1H
129 #define ICR1H4_REG ICR1H
130 #define ICR1H5_REG ICR1H
131 #define ICR1H6_REG ICR1H
132 #define ICR1H7_REG ICR1H
135 #define MUX0_REG ADMUX
136 #define MUX1_REG ADMUX
137 #define MUX2_REG ADMUX
140 #define CS00_REG TCCR0
141 #define CS01_REG TCCR0
142 #define CS02_REG TCCR0
143 #define CTC0_REG TCCR0
144 #define COM00_REG TCCR0
145 #define COM01_REG TCCR0
146 #define PWM0_REG TCCR0
159 #define DDB0_REG DDRB
160 #define DDB1_REG DDRB
161 #define DDB2_REG DDRB
162 #define DDB3_REG DDRB
163 #define DDB4_REG DDRB
164 #define DDB5_REG DDRB
165 #define DDB6_REG DDRB
166 #define DDB7_REG DDRB
169 #define XDIV0_REG XDIV
170 #define XDIV1_REG XDIV
171 #define XDIV2_REG XDIV
172 #define XDIV3_REG XDIV
173 #define XDIV4_REG XDIV
174 #define XDIV5_REG XDIV
175 #define XDIV6_REG XDIV
176 #define XDIVEN_REG XDIV
179 #define EEDR0_REG EEDR
180 #define EEDR1_REG EEDR
181 #define EEDR2_REG EEDR
182 #define EEDR3_REG EEDR
183 #define EEDR4_REG EEDR
184 #define EEDR5_REG EEDR
185 #define EEDR6_REG EEDR
186 #define EEDR7_REG EEDR
189 #define DDA0_REG DDRA
190 #define DDA1_REG DDRA
191 #define DDA2_REG DDRA
192 #define DDA3_REG DDRA
193 #define DDA4_REG DDRA
194 #define DDA5_REG DDRA
195 #define DDA6_REG DDRA
196 #define DDA7_REG DDRA
199 #define PWM10_REG TCCR1A
200 #define PWM11_REG TCCR1A
201 #define COM1B0_REG TCCR1A
202 #define COM1B1_REG TCCR1A
203 #define COM1A0_REG TCCR1A
204 #define COM1A1_REG TCCR1A
207 #define DDD0_REG DDRD
208 #define DDD1_REG DDRD
209 #define DDD2_REG DDRD
210 #define DDD3_REG DDRD
211 #define DDD4_REG DDRD
212 #define DDD5_REG DDRD
213 #define DDD6_REG DDRD
214 #define DDD7_REG DDRD
217 #define CS10_REG TCCR1B
218 #define CS11_REG TCCR1B
219 #define CS12_REG TCCR1B
220 #define CTC1_REG TCCR1B
221 #define ICES1_REG TCCR1B
222 #define ICNC1_REG TCCR1B
225 #define TOIE2_REG TIMSK
226 #define OCIE2_REG TIMSK
227 #define TOIE0_REG TIMSK
228 #define OCIE0_REG TIMSK
229 #define TOIE1_REG TIMSK
230 #define OCIE1B_REG TIMSK
231 #define OCIE1A_REG TIMSK
232 #define TICIE1_REG TIMSK
235 #define INT0_REG EIMSK
236 #define INT1_REG EIMSK
237 #define INT2_REG EIMSK
238 #define INT3_REG EIMSK
239 #define INT4_REG EIMSK
240 #define INT5_REG EIMSK
241 #define INT6_REG EIMSK
242 #define INT7_REG EIMSK
245 #define ISC40_REG EICR
246 #define ISC41_REG EICR
247 #define ISC50_REG EICR
248 #define ISC51_REG EICR
249 #define ISC60_REG EICR
250 #define ISC61_REG EICR
251 #define ISC70_REG EICR
252 #define ISC71_REG EICR
255 #define RAMPZ0_REG RAMPZ
258 #define SPDR0_REG SPDR
259 #define SPDR1_REG SPDR
260 #define SPDR2_REG SPDR
261 #define SPDR3_REG SPDR
262 #define SPDR4_REG SPDR
263 #define SPDR5_REG SPDR
264 #define SPDR6_REG SPDR
265 #define SPDR7_REG SPDR
268 #define WCOL_REG SPSR
269 #define SPIF_REG SPSR
272 #define ACIS0_REG ACSR
273 #define ACIS1_REG ACSR
274 #define ACIC_REG ACSR
275 #define ACIE_REG ACSR
291 #define OCR1BL0_REG OCR1BL
292 #define OCR1BL1_REG OCR1BL
293 #define OCR1BL2_REG OCR1BL
294 #define OCR1BL3_REG OCR1BL
295 #define OCR1BL4_REG OCR1BL
296 #define OCR1BL5_REG OCR1BL
297 #define OCR1BL6_REG OCR1BL
298 #define OCR1BL7_REG OCR1BL
311 #define OCR1BH0_REG OCR1BH
312 #define OCR1BH1_REG OCR1BH
313 #define OCR1BH2_REG OCR1BH
314 #define OCR1BH3_REG OCR1BH
315 #define OCR1BH4_REG OCR1BH
316 #define OCR1BH5_REG OCR1BH
317 #define OCR1BH6_REG OCR1BH
318 #define OCR1BH7_REG OCR1BH
321 #define PIND0_REG PIND
322 #define PIND1_REG PIND
323 #define PIND2_REG PIND
324 #define PIND3_REG PIND
325 #define PIND4_REG PIND
326 #define PIND5_REG PIND
327 #define PIND6_REG PIND
328 #define PIND7_REG PIND
331 #define ICR1L0_REG ICR1L
332 #define ICR1L1_REG ICR1L
333 #define ICR1L2_REG ICR1L
334 #define ICR1L3_REG ICR1L
335 #define ICR1L4_REG ICR1L
336 #define ICR1L5_REG ICR1L
337 #define ICR1L6_REG ICR1L
338 #define ICR1L7_REG ICR1L
341 #define DDE0_REG DDRE
342 #define DDE1_REG DDRE
343 #define DDE2_REG DDRE
344 #define DDE3_REG DDRE
345 #define DDE4_REG DDRE
346 #define DDE5_REG DDRE
347 #define DDE6_REG DDRE
348 #define DDE7_REG DDRE
351 #define ADC0_REG ADCL
352 #define ADC1_REG ADCL
353 #define ADC2_REG ADCL
354 #define ADC3_REG ADCL
355 #define ADC4_REG ADCL
356 #define ADC5_REG ADCL
357 #define ADC6_REG ADCL
358 #define ADC7_REG ADCL
361 #define PORF_REG MCUSR
362 #define EXTRF_REG MCUSR
365 #define EERE_REG EECR
366 #define EEWE_REG EECR
367 #define EEMWE_REG EECR
368 #define EERIE_REG EECR
371 #define TCNT1L0_REG TCNT1L
372 #define TCNT1L1_REG TCNT1L
373 #define TCNT1L2_REG TCNT1L
374 #define TCNT1L3_REG TCNT1L
375 #define TCNT1L4_REG TCNT1L
376 #define TCNT1L5_REG TCNT1L
377 #define TCNT1L6_REG TCNT1L
378 #define TCNT1L7_REG TCNT1L
381 #define PORTB0_REG PORTB
382 #define PORTB1_REG PORTB
383 #define PORTB2_REG PORTB
384 #define PORTB3_REG PORTB
385 #define PORTB4_REG PORTB
386 #define PORTB5_REG PORTB
387 #define PORTB6_REG PORTB
388 #define PORTB7_REG PORTB
391 #define PORTD0_REG PORTD
392 #define PORTD1_REG PORTD
393 #define PORTD2_REG PORTD
394 #define PORTD3_REG PORTD
395 #define PORTD4_REG PORTD
396 #define PORTD5_REG PORTD
397 #define PORTD6_REG PORTD
398 #define PORTD7_REG PORTD
401 #define PORTE0_REG PORTE
402 #define PORTE1_REG PORTE
403 #define PORTE2_REG PORTE
404 #define PORTE3_REG PORTE
405 #define PORTE4_REG PORTE
406 #define PORTE5_REG PORTE
407 #define PORTE6_REG PORTE
408 #define PORTE7_REG PORTE
411 #define TCNT1H0_REG TCNT1H
412 #define TCNT1H1_REG TCNT1H
413 #define TCNT1H2_REG TCNT1H
414 #define TCNT1H3_REG TCNT1H
415 #define TCNT1H4_REG TCNT1H
416 #define TCNT1H5_REG TCNT1H
417 #define TCNT1H6_REG TCNT1H
418 #define TCNT1H7_REG TCNT1H
421 #define PORTC0_REG PORTC
422 #define PORTC1_REG PORTC
423 #define PORTC2_REG PORTC
424 #define PORTC3_REG PORTC
425 #define PORTC4_REG PORTC
426 #define PORTC5_REG PORTC
427 #define PORTC6_REG PORTC
428 #define PORTC7_REG PORTC
431 #define ADC8_REG ADCH
432 #define ADC9_REG ADCH
435 #define PORTA0_REG PORTA
436 #define PORTA1_REG PORTA
437 #define PORTA2_REG PORTA
438 #define PORTA3_REG PORTA
439 #define PORTA4_REG PORTA
440 #define PORTA5_REG PORTA
441 #define PORTA6_REG PORTA
442 #define PORTA7_REG PORTA
445 #define TCNT2_0_REG TCNT2
446 #define TCNT2_1_REG TCNT2
447 #define TCNT2_2_REG TCNT2
448 #define TCNT2_3_REG TCNT2
449 #define TCNT2_4_REG TCNT2
450 #define TCNT2_5_REG TCNT2
451 #define TCNT2_6_REG TCNT2
452 #define TCNT2_7_REG TCNT2
455 #define TCNT0_0_REG TCNT0
456 #define TCNT0_1_REG TCNT0
457 #define TCNT0_2_REG TCNT0
458 #define TCNT0_3_REG TCNT0
459 #define TCNT0_4_REG TCNT0
460 #define TCNT0_5_REG TCNT0
461 #define TCNT0_6_REG TCNT0
462 #define TCNT0_7_REG TCNT0
475 #define UBRR0_REG UBRR
476 #define UBRR1_REG UBRR
477 #define UBRR2_REG UBRR
478 #define UBRR3_REG UBRR
479 #define UBRR4_REG UBRR
480 #define UBRR5_REG UBRR
481 #define UBRR6_REG UBRR
482 #define UBRR7_REG UBRR
485 #define ADPS0_REG ADCSR
486 #define ADPS1_REG ADCSR
487 #define ADPS2_REG ADCSR
488 #define ADIE_REG ADCSR
489 #define ADIF_REG ADCSR
490 #define ADSC_REG ADCSR
491 #define ADEN_REG ADCSR
494 #define CS20_REG TCCR2
495 #define CS21_REG TCCR2
496 #define CS22_REG TCCR2
497 #define CTC2_REG TCCR2
498 #define COM20_REG TCCR2
499 #define COM21_REG TCCR2
500 #define PWM2_REG TCCR2
503 #define TOV2_REG TIFR
504 #define OCF2_REG TIFR
505 #define TOV0_REG TIFR
506 #define OCF0_REG TIFR
507 #define TOV1_REG TIFR
508 #define OCF1B_REG TIFR
509 #define OCF1A_REG TIFR
510 #define ICF1_REG TIFR
518 #define UDRIE_REG UCR
519 #define TXCIE_REG UCR
520 #define RXCIE_REG UCR
523 #define EEAR8_REG EEARH
524 #define EEAR9_REG EEARH
525 #define EEAR10_REG EEARH
526 #define EEAR11_REG EEARH
529 #define EEARL0_REG EEARL
530 #define EEARL1_REG EEARL
531 #define EEARL2_REG EEARL
532 #define EEARL3_REG EEARL
533 #define EEARL4_REG EEARL
534 #define EEARL5_REG EEARL
535 #define EEARL6_REG EEARL
536 #define EEARL7_REG EEARL
539 #define PINB0_REG PINB
540 #define PINB1_REG PINB
541 #define PINB2_REG PINB
542 #define PINB3_REG PINB
543 #define PINB4_REG PINB
544 #define PINB5_REG PINB
545 #define PINB6_REG PINB
546 #define PINB7_REG PINB
549 #define INTF4_REG EIFR
550 #define INTF5_REG EIFR
551 #define INTF6_REG EIFR
552 #define INTF7_REG EIFR
555 #define PINF0_REG PINF
556 #define PINF1_REG PINF
557 #define PINF2_REG PINF
558 #define PINF3_REG PINF
559 #define PINF4_REG PINF
560 #define PINF5_REG PINF
561 #define PINF6_REG PINF
562 #define PINF7_REG PINF
565 #define PINE0_REG PINE
566 #define PINE1_REG PINE
567 #define PINE2_REG PINE
568 #define PINE3_REG PINE
569 #define PINE4_REG PINE
570 #define PINE5_REG PINE
571 #define PINE6_REG PINE
572 #define PINE7_REG PINE
575 #define SM0_REG MCUCR
576 #define SM1_REG MCUCR
578 #define SRW_REG MCUCR
579 #define SRE_REG MCUCR
582 #define OCR1AH0_REG OCR1AH
583 #define OCR1AH1_REG OCR1AH
584 #define OCR1AH2_REG OCR1AH
585 #define OCR1AH3_REG OCR1AH
586 #define OCR1AH4_REG OCR1AH
587 #define OCR1AH5_REG OCR1AH
588 #define OCR1AH6_REG OCR1AH
589 #define OCR1AH7_REG OCR1AH
592 #define OCR1AL0_REG OCR1AL
593 #define OCR1AL1_REG OCR1AL
594 #define OCR1AL2_REG OCR1AL
595 #define OCR1AL3_REG OCR1AL
596 #define OCR1AL4_REG OCR1AL
597 #define OCR1AL5_REG OCR1AL
598 #define OCR1AL6_REG OCR1AL
599 #define OCR1AL7_REG OCR1AL
602 #define SPR0_REG SPCR
603 #define SPR1_REG SPCR
604 #define CPHA_REG SPCR
605 #define CPOL_REG SPCR
606 #define MSTR_REG SPCR
607 #define DORD_REG SPCR
609 #define SPIE_REG SPCR
619 #define OCR0_0_REG OCR0
620 #define OCR0_1_REG OCR0
621 #define OCR0_2_REG OCR0
622 #define OCR0_3_REG OCR0
623 #define OCR0_4_REG OCR0
624 #define OCR0_5_REG OCR0
625 #define OCR0_6_REG OCR0
626 #define OCR0_7_REG OCR0
629 #define PINA0_REG PINA
630 #define PINA1_REG PINA
631 #define PINA2_REG PINA
632 #define PINA3_REG PINA
633 #define PINA4_REG PINA
634 #define PINA5_REG PINA
635 #define PINA6_REG PINA
636 #define PINA7_REG PINA
639 #define OCR2_0_REG OCR2
640 #define OCR2_1_REG OCR2
641 #define OCR2_2_REG OCR2
642 #define OCR2_3_REG OCR2
643 #define OCR2_4_REG OCR2
644 #define OCR2_5_REG OCR2
645 #define OCR2_6_REG OCR2
646 #define OCR2_7_REG OCR2
649 #define TCR0UB_REG ASSR
650 #define OCR0UB_REG ASSR
651 #define TCN0UB_REG ASSR
655 #define AD0_PORT PORTA
658 #define AD1_PORT PORTA
661 #define AD2_PORT PORTA
664 #define AD3_PORT PORTA
667 #define AD4_PORT PORTA
670 #define AD5_PORT PORTA
673 #define AD6_PORT PORTA
676 #define AD7_PORT PORTA
679 #define SS_PORT PORTB
682 #define SCK_PORT PORTB
685 #define MOSI_PORT PORTB
688 #define MISO_PORT PORTB
691 #define OC0_PORT PORTB
693 #define PWM0_PORT PORTB
696 #define OC1A_PORT PORTB
698 #define PWM1A_PORT PORTB
701 #define OC1B_PORT PORTB
703 #define PWM1B_PORT PORTB
706 #define OC2_PORT PORTB
708 #define PWM2_PORT PORTB
710 #define OC1C_PORT PORTB
713 #define A8_PORT PORTC
716 #define A9_PORT PORTC
719 #define A10_PORT PORTC
722 #define A11_PORT PORTC
725 #define A12_PORT PORTC
728 #define A13_PORT PORTC
731 #define A14_PORT PORTC
734 #define A15_PORT PORTC
737 #define INT0_PORT PORTD
740 #define INT1_PORT PORTD
743 #define INT2_PORT PORTD
746 #define INT3_PORT PORTD
749 #define IC1_PORT PORTD
753 #define T1_PORT PORTD
756 #define T2_PORT PORTD
759 #define RXD0_PORT PORTE
761 #define PDI_PORT PORTE
764 #define TXD0_PORT PORTE
766 #define PDO_PORT PORTE
769 #define AC+_PORT PORTE
772 #define AC-_PORT PORTE
775 #define INT4_PORT PORTE
778 #define INT5_PORT PORTE
781 #define INT6_PORT PORTE
784 #define INT7_PORT PORTE
787 #define ADC0_PORT PORTF
790 #define ADC1_PORT PORTF
793 #define ADC2_PORT PORTF
796 #define ADC3_PORT PORTF
799 #define ADC4_PORT PORTF
802 #define ADC5_PORT PORTF
805 #define ADC6_PORT PORTF
808 #define ADC7_PORT PORTF