2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
84 /* prescalers timer 3 */
85 #define TIMER3_PRESCALER_DIV_0 0
86 #define TIMER3_PRESCALER_DIV_1 1
87 #define TIMER3_PRESCALER_DIV_8 2
88 #define TIMER3_PRESCALER_DIV_64 3
89 #define TIMER3_PRESCALER_DIV_256 4
90 #define TIMER3_PRESCALER_DIV_1024 5
91 #define TIMER3_PRESCALER_DIV_FALL 6
92 #define TIMER3_PRESCALER_DIV_RISE 7
94 #define TIMER3_PRESCALER_REG_0 0
95 #define TIMER3_PRESCALER_REG_1 1
96 #define TIMER3_PRESCALER_REG_2 8
97 #define TIMER3_PRESCALER_REG_3 64
98 #define TIMER3_PRESCALER_REG_4 256
99 #define TIMER3_PRESCALER_REG_5 1024
100 #define TIMER3_PRESCALER_REG_6 -1
101 #define TIMER3_PRESCALER_REG_7 -2
104 /* available timers */
105 #define TIMER0_AVAILABLE
106 #define TIMER0A_AVAILABLE
107 #define TIMER0B_AVAILABLE
108 #define TIMER1_AVAILABLE
109 #define TIMER1A_AVAILABLE
110 #define TIMER1B_AVAILABLE
111 #define TIMER2_AVAILABLE
112 #define TIMER2A_AVAILABLE
113 #define TIMER2B_AVAILABLE
114 #define TIMER3_AVAILABLE
115 #define TIMER3A_AVAILABLE
116 #define TIMER3B_AVAILABLE
118 /* overflow interrupt number */
119 #define SIG_OVERFLOW0_NUM 0
120 #define SIG_OVERFLOW1_NUM 1
121 #define SIG_OVERFLOW2_NUM 2
122 #define SIG_OVERFLOW3_NUM 3
123 #define SIG_OVERFLOW_TOTAL_NUM 4
125 /* output compare interrupt number */
126 #define SIG_OUTPUT_COMPARE0A_NUM 0
127 #define SIG_OUTPUT_COMPARE0B_NUM 1
128 #define SIG_OUTPUT_COMPARE1A_NUM 2
129 #define SIG_OUTPUT_COMPARE1B_NUM 3
130 #define SIG_OUTPUT_COMPARE2A_NUM 4
131 #define SIG_OUTPUT_COMPARE2B_NUM 5
132 #define SIG_OUTPUT_COMPARE3A_NUM 6
133 #define SIG_OUTPUT_COMPARE3B_NUM 7
134 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
145 #define PWM_TOTAL_NUM 8
147 /* input capture interrupt number */
148 #define SIG_INPUT_CAPTURE1_NUM 0
149 #define SIG_INPUT_CAPTURE3_NUM 1
150 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
154 #define MUX0_REG ADMUX
155 #define MUX1_REG ADMUX
156 #define MUX2_REG ADMUX
157 #define MUX3_REG ADMUX
158 #define MUX4_REG ADMUX
159 #define ADLAR_REG ADMUX
160 #define REFS0_REG ADMUX
161 #define REFS1_REG ADMUX
164 #define WDP0_REG WDTCSR
165 #define WDP1_REG WDTCSR
166 #define WDP2_REG WDTCSR
167 #define WDE_REG WDTCSR
168 #define WDCE_REG WDTCSR
169 #define WDP3_REG WDTCSR
170 #define WDIE_REG WDTCSR
171 #define WDIF_REG WDTCSR
174 #define EEDR0_REG EEDR
175 #define EEDR1_REG EEDR
176 #define EEDR2_REG EEDR
177 #define EEDR3_REG EEDR
178 #define EEDR4_REG EEDR
179 #define EEDR5_REG EEDR
180 #define EEDR6_REG EEDR
181 #define EEDR7_REG EEDR
184 #define ACIS0_REG ACSR
185 #define ACIS1_REG ACSR
186 #define ACIC_REG ACSR
187 #define ACIE_REG ACSR
190 #define ACBG_REG ACSR
194 #define RAMPZ0_REG RAMPZ
197 #define OCR2B_0_REG OCR2B
198 #define OCR2B_1_REG OCR2B
199 #define OCR2B_2_REG OCR2B
200 #define OCR2B_3_REG OCR2B
201 #define OCR2B_4_REG OCR2B
202 #define OCR2B_5_REG OCR2B
203 #define OCR2B_6_REG OCR2B
204 #define OCR2B_7_REG OCR2B
207 #define OCR2A_0_REG OCR2A
208 #define OCR2A_1_REG OCR2A
209 #define OCR2A_2_REG OCR2A
210 #define OCR2A_3_REG OCR2A
211 #define OCR2A_4_REG OCR2A
212 #define OCR2A_5_REG OCR2A
213 #define OCR2A_6_REG OCR2A
214 #define OCR2A_7_REG OCR2A
217 #define SPDR0_REG SPDR
218 #define SPDR1_REG SPDR
219 #define SPDR2_REG SPDR
220 #define SPDR3_REG SPDR
221 #define SPDR4_REG SPDR
222 #define SPDR5_REG SPDR
223 #define SPDR6_REG SPDR
224 #define SPDR7_REG SPDR
227 #define SPI2X_REG SPSR
228 #define WCOL_REG SPSR
229 #define SPIF_REG SPSR
242 #define ICR1L0_REG ICR1L
243 #define ICR1L1_REG ICR1L
244 #define ICR1L2_REG ICR1L
245 #define ICR1L3_REG ICR1L
246 #define ICR1L4_REG ICR1L
247 #define ICR1L5_REG ICR1L
248 #define ICR1L6_REG ICR1L
249 #define ICR1L7_REG ICR1L
252 #define EEAR8_REG EEARH
253 #define EEAR9_REG EEARH
254 #define EEAR10_REG EEARH
255 #define EEAR11_REG EEARH
258 #define MPCM0_REG UCSR0A
259 #define U2X0_REG UCSR0A
260 #define UPE0_REG UCSR0A
261 #define DOR0_REG UCSR0A
262 #define FE0_REG UCSR0A
263 #define UDRE0_REG UCSR0A
264 #define TXC0_REG UCSR0A
265 #define RXC0_REG UCSR0A
268 #define UCPOL0_REG UCSR0C
269 #define UCSZ00_REG UCSR0C
270 #define UCSZ01_REG UCSR0C
271 #define USBS0_REG UCSR0C
272 #define UPM00_REG UCSR0C
273 #define UPM01_REG UCSR0C
274 #define UMSEL00_REG UCSR0C
275 #define UMSEL01_REG UCSR0C
278 #define TXB80_REG UCSR0B
279 #define RXB80_REG UCSR0B
280 #define UCSZ02_REG UCSR0B
281 #define TXEN0_REG UCSR0B
282 #define RXEN0_REG UCSR0B
283 #define UDRIE0_REG UCSR0B
284 #define TXCIE0_REG UCSR0B
285 #define RXCIE0_REG UCSR0B
288 #define TCNT1H0_REG TCNT1H
289 #define TCNT1H1_REG TCNT1H
290 #define TCNT1H2_REG TCNT1H
291 #define TCNT1H3_REG TCNT1H
292 #define TCNT1H4_REG TCNT1H
293 #define TCNT1H5_REG TCNT1H
294 #define TCNT1H6_REG TCNT1H
295 #define TCNT1H7_REG TCNT1H
298 #define PORTC0_REG PORTC
299 #define PORTC1_REG PORTC
300 #define PORTC2_REG PORTC
301 #define PORTC3_REG PORTC
302 #define PORTC4_REG PORTC
303 #define PORTC5_REG PORTC
304 #define PORTC6_REG PORTC
305 #define PORTC7_REG PORTC
308 #define PORTA0_REG PORTA
309 #define PORTA1_REG PORTA
310 #define PORTA2_REG PORTA
311 #define PORTA3_REG PORTA
312 #define PORTA4_REG PORTA
313 #define PORTA5_REG PORTA
314 #define PORTA6_REG PORTA
315 #define PORTA7_REG PORTA
318 #define INT0_REG EIMSK
319 #define INT1_REG EIMSK
320 #define INT2_REG EIMSK
323 #define UDR1_0_REG UDR1
324 #define UDR1_1_REG UDR1
325 #define UDR1_2_REG UDR1
326 #define UDR1_3_REG UDR1
327 #define UDR1_4_REG UDR1
328 #define UDR1_5_REG UDR1
329 #define UDR1_6_REG UDR1
330 #define UDR1_7_REG UDR1
333 #define UDR0_0_REG UDR0
334 #define UDR0_1_REG UDR0
335 #define UDR0_2_REG UDR0
336 #define UDR0_3_REG UDR0
337 #define UDR0_4_REG UDR0
338 #define UDR0_5_REG UDR0
339 #define UDR0_6_REG UDR0
340 #define UDR0_7_REG UDR0
343 #define ISC00_REG EICRA
344 #define ISC01_REG EICRA
345 #define ISC10_REG EICRA
346 #define ISC11_REG EICRA
347 #define ISC20_REG EICRA
348 #define ISC21_REG EICRA
351 #define ADC0D_REG DIDR0
352 #define ADC1D_REG DIDR0
353 #define ADC2D_REG DIDR0
354 #define ADC3D_REG DIDR0
355 #define ADC4D_REG DIDR0
356 #define ADC5D_REG DIDR0
357 #define ADC6D_REG DIDR0
358 #define ADC7D_REG DIDR0
361 #define AIN0D_REG DIDR1
362 #define AIN1D_REG DIDR1
365 #define TCR2BUB_REG ASSR
366 #define TCR2AUB_REG ASSR
367 #define OCR2BUB_REG ASSR
368 #define OCR2AUB_REG ASSR
369 #define TCN2UB_REG ASSR
371 #define EXCLK_REG ASSR
374 #define CLKPS0_REG CLKPR
375 #define CLKPS1_REG CLKPR
376 #define CLKPS2_REG CLKPR
377 #define CLKPS3_REG CLKPR
378 #define CLKPCE_REG CLKPR
391 #define UBRR_0_REG UBRR1L
392 #define UBRR_1_REG UBRR1L
393 #define UBRR_2_REG UBRR1L
394 #define UBRR_3_REG UBRR1L
395 #define UBRR_4_REG UBRR1L
396 #define UBRR_5_REG UBRR1L
397 #define UBRR_6_REG UBRR1L
398 #define UBRR_7_REG UBRR1L
401 #define DDC0_REG DDRC
402 #define DDC1_REG DDRC
403 #define DDC2_REG DDRC
404 #define DDC3_REG DDRC
405 #define DDC4_REG DDRC
406 #define DDC5_REG DDRC
407 #define DDC6_REG DDRC
408 #define DDC7_REG DDRC
411 /* #define OCR3AL0_REG OCR3AL */ /* dup in OCR3BL */
412 /* #define OCR3AL1_REG OCR3AL */ /* dup in OCR3BL */
413 /* #define OCR3AL2_REG OCR3AL */ /* dup in OCR3BL */
414 /* #define OCR3AL3_REG OCR3AL */ /* dup in OCR3BL */
415 /* #define OCR3AL4_REG OCR3AL */ /* dup in OCR3BL */
416 /* #define OCR3AL5_REG OCR3AL */ /* dup in OCR3BL */
417 /* #define OCR3AL6_REG OCR3AL */ /* dup in OCR3BL */
418 /* #define OCR3AL7_REG OCR3AL */ /* dup in OCR3BL */
421 #define DDA0_REG DDRA
422 #define DDA1_REG DDRA
423 #define DDA2_REG DDRA
424 #define DDA3_REG DDRA
425 #define DDA4_REG DDRA
426 #define DDA5_REG DDRA
427 #define DDA6_REG DDRA
428 #define DDA7_REG DDRA
431 #define UBRR_8_REG UBRR1H
432 #define UBRR_9_REG UBRR1H
433 #define UBRR_10_REG UBRR1H
434 #define UBRR_11_REG UBRR1H
437 /* #define OCR3AH0_REG OCR3AH */ /* dup in OCR3BH */
438 /* #define OCR3AH1_REG OCR3AH */ /* dup in OCR3BH */
439 /* #define OCR3AH2_REG OCR3AH */ /* dup in OCR3BH */
440 /* #define OCR3AH3_REG OCR3AH */ /* dup in OCR3BH */
441 /* #define OCR3AH4_REG OCR3AH */ /* dup in OCR3BH */
442 /* #define OCR3AH5_REG OCR3AH */ /* dup in OCR3BH */
443 /* #define OCR3AH6_REG OCR3AH */ /* dup in OCR3BH */
444 /* #define OCR3AH7_REG OCR3AH */ /* dup in OCR3BH */
447 #define CS10_REG TCCR1B
448 #define CS11_REG TCCR1B
449 #define CS12_REG TCCR1B
450 #define WGM12_REG TCCR1B
451 #define WGM13_REG TCCR1B
452 #define ICES1_REG TCCR1B
453 #define ICNC1_REG TCCR1B
456 #define CAL0_REG OSCCAL
457 #define CAL1_REG OSCCAL
458 #define CAL2_REG OSCCAL
459 #define CAL3_REG OSCCAL
460 #define CAL4_REG OSCCAL
461 #define CAL5_REG OSCCAL
462 #define CAL6_REG OSCCAL
463 #define CAL7_REG OSCCAL
466 #define DDD0_REG DDRD
467 #define DDD1_REG DDRD
468 #define DDD2_REG DDRD
469 #define DDD3_REG DDRD
470 #define DDD4_REG DDRD
471 #define DDD5_REG DDRD
472 #define DDD6_REG DDRD
473 #define DDD7_REG DDRD
476 #define GPIOR10_REG GPIOR1
477 #define GPIOR11_REG GPIOR1
478 #define GPIOR12_REG GPIOR1
479 #define GPIOR13_REG GPIOR1
480 #define GPIOR14_REG GPIOR1
481 #define GPIOR15_REG GPIOR1
482 #define GPIOR16_REG GPIOR1
483 #define GPIOR17_REG GPIOR1
486 #define GPIOR00_REG GPIOR0
487 #define GPIOR01_REG GPIOR0
488 #define GPIOR02_REG GPIOR0
489 #define GPIOR03_REG GPIOR0
490 #define GPIOR04_REG GPIOR0
491 #define GPIOR05_REG GPIOR0
492 #define GPIOR06_REG GPIOR0
493 #define GPIOR07_REG GPIOR0
496 #define GPIOR20_REG GPIOR2
497 #define GPIOR21_REG GPIOR2
498 #define GPIOR22_REG GPIOR2
499 #define GPIOR23_REG GPIOR2
500 #define GPIOR24_REG GPIOR2
501 #define GPIOR25_REG GPIOR2
502 #define GPIOR26_REG GPIOR2
503 #define GPIOR27_REG GPIOR2
506 #define PCIE0_REG PCICR
507 #define PCIE1_REG PCICR
508 #define PCIE2_REG PCICR
509 #define PCIE3_REG PCICR
512 #define TCNT2_0_REG TCNT2
513 #define TCNT2_1_REG TCNT2
514 #define TCNT2_2_REG TCNT2
515 #define TCNT2_3_REG TCNT2
516 #define TCNT2_4_REG TCNT2
517 #define TCNT2_5_REG TCNT2
518 #define TCNT2_6_REG TCNT2
519 #define TCNT2_7_REG TCNT2
522 #define TCNT0_0_REG TCNT0
523 #define TCNT0_1_REG TCNT0
524 #define TCNT0_2_REG TCNT0
525 #define TCNT0_3_REG TCNT0
526 #define TCNT0_4_REG TCNT0
527 #define TCNT0_5_REG TCNT0
528 #define TCNT0_6_REG TCNT0
529 #define TCNT0_7_REG TCNT0
532 #define TWGCE_REG TWAR
533 #define TWA0_REG TWAR
534 #define TWA1_REG TWAR
535 #define TWA2_REG TWAR
536 #define TWA3_REG TWAR
537 #define TWA4_REG TWAR
538 #define TWA5_REG TWAR
539 #define TWA6_REG TWAR
542 #define CS00_REG TCCR0B
543 #define CS01_REG TCCR0B
544 #define CS02_REG TCCR0B
545 #define WGM02_REG TCCR0B
546 #define FOC0B_REG TCCR0B
547 #define FOC0A_REG TCCR0B
550 #define WGM00_REG TCCR0A
551 #define WGM01_REG TCCR0A
552 #define COM0B0_REG TCCR0A
553 #define COM0B1_REG TCCR0A
554 #define COM0A0_REG TCCR0A
555 #define COM0A1_REG TCCR0A
558 #define TOV2_REG TIFR2
559 #define OCF2A_REG TIFR2
560 #define OCF2B_REG TIFR2
563 #define TOV3_REG TIFR3
564 #define OCF3A_REG TIFR3
565 #define OCF3B_REG TIFR3
566 #define ICF3_REG TIFR3
569 #define SPR0_REG SPCR
570 #define SPR1_REG SPCR
571 #define CPHA_REG SPCR
572 #define CPOL_REG SPCR
573 #define MSTR_REG SPCR
574 #define DORD_REG SPCR
576 #define SPIE_REG SPCR
579 #define TOV1_REG TIFR1
580 #define OCF1A_REG TIFR1
581 #define OCF1B_REG TIFR1
582 #define ICF1_REG TIFR1
585 #define PSRSYNC_REG GTCCR
586 #define TSM_REG GTCCR
587 #define PSRASY_REG GTCCR
590 #define TWBR0_REG TWBR
591 #define TWBR1_REG TWBR
592 #define TWBR2_REG TWBR
593 #define TWBR3_REG TWBR
594 #define TWBR4_REG TWBR
595 #define TWBR5_REG TWBR
596 #define TWBR6_REG TWBR
597 #define TWBR7_REG TWBR
600 #define ICR1H0_REG ICR1H
601 #define ICR1H1_REG ICR1H
602 #define ICR1H2_REG ICR1H
603 #define ICR1H3_REG ICR1H
604 #define ICR1H4_REG ICR1H
605 #define ICR1H5_REG ICR1H
606 #define ICR1H6_REG ICR1H
607 #define ICR1H7_REG ICR1H
610 #define FOC3B_REG TCCR3C
611 #define FOC3A_REG TCCR3C
614 #define CS30_REG TCCR3B
615 #define CS31_REG TCCR3B
616 #define CS32_REG TCCR3B
617 #define WGM32_REG TCCR3B
618 #define WGM33_REG TCCR3B
619 #define ICES3_REG TCCR3B
620 #define ICNC3_REG TCCR3B
623 #define WGM30_REG TCCR3A
624 #define WGM31_REG TCCR3A
625 #define COM3B0_REG TCCR3A
626 #define COM3B1_REG TCCR3A
627 #define COM3A0_REG TCCR3A
628 #define COM3A1_REG TCCR3A
631 /* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
632 /* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
633 /* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
634 /* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
635 /* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
636 /* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
637 /* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
638 /* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
641 #define TCNT3H0_REG TCNT3H
642 #define TCNT3H1_REG TCNT3H
643 #define TCNT3H2_REG TCNT3H
644 #define TCNT3H3_REG TCNT3H
645 #define TCNT3H4_REG TCNT3H
646 #define TCNT3H5_REG TCNT3H
647 #define TCNT3H6_REG TCNT3H
648 #define TCNT3H7_REG TCNT3H
651 /* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
652 /* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
653 /* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
654 /* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
655 /* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
656 /* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
657 /* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
658 /* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
661 #define TCNT3L0_REG TCNT3L
662 #define TCNT3L1_REG TCNT3L
663 #define TCNT3L2_REG TCNT3L
664 #define TCNT3L3_REG TCNT3L
665 #define TCNT3L4_REG TCNT3L
666 #define TCNT3L5_REG TCNT3L
667 #define TCNT3L6_REG TCNT3L
668 #define TCNT3L7_REG TCNT3L
681 #define JTRF_REG MCUSR
682 #define PORF_REG MCUSR
683 #define EXTRF_REG MCUSR
684 #define BORF_REG MCUSR
685 #define WDRF_REG MCUSR
688 #define EERE_REG EECR
689 #define EEPE_REG EECR
690 #define EEMPE_REG EECR
691 #define EERIE_REG EECR
692 #define EEPM0_REG EECR
693 #define EEPM1_REG EECR
702 #define TWIE_REG TWCR
703 #define TWEN_REG TWCR
704 #define TWWC_REG TWCR
705 #define TWSTO_REG TWCR
706 #define TWSTA_REG TWCR
707 #define TWEA_REG TWCR
708 #define TWINT_REG TWCR
711 #define PCIF0_REG PCIFR
712 #define PCIF1_REG PCIFR
713 #define PCIF2_REG PCIFR
714 #define PCIF3_REG PCIFR
717 #define WGM20_REG TCCR2A
718 #define WGM21_REG TCCR2A
719 #define COM2B0_REG TCCR2A
720 #define COM2B1_REG TCCR2A
721 #define COM2A0_REG TCCR2A
722 #define COM2A1_REG TCCR2A
725 #define CS20_REG TCCR2B
726 #define CS21_REG TCCR2B
727 #define CS22_REG TCCR2B
728 #define WGM22_REG TCCR2B
729 #define FOC2B_REG TCCR2B
730 #define FOC2A_REG TCCR2B
733 #define UBRR8_REG UBRR0H
734 #define UBRR9_REG UBRR0H
735 #define UBRR10_REG UBRR0H
736 #define UBRR11_REG UBRR0H
739 #define UBRR0_REG UBRR0L
740 #define UBRR1_REG UBRR0L
741 #define UBRR2_REG UBRR0L
742 #define UBRR3_REG UBRR0L
743 #define UBRR4_REG UBRR0L
744 #define UBRR5_REG UBRR0L
745 #define UBRR6_REG UBRR0L
746 #define UBRR7_REG UBRR0L
749 #define TWPS0_REG TWSR
750 #define TWPS1_REG TWSR
751 #define TWS3_REG TWSR
752 #define TWS4_REG TWSR
753 #define TWS5_REG TWSR
754 #define TWS6_REG TWSR
755 #define TWS7_REG TWSR
758 #define EEAR0_REG EEARL
759 #define EEAR1_REG EEARL
760 #define EEAR2_REG EEARL
761 #define EEAR3_REG EEARL
762 #define EEAR4_REG EEARL
763 #define EEAR5_REG EEARL
764 #define EEAR6_REG EEARL
765 #define EEAR7_REG EEARL
768 #define JTD_REG MCUCR
769 #define IVCE_REG MCUCR
770 #define IVSEL_REG MCUCR
771 #define PUD_REG MCUCR
772 #define BODSE_REG MCUCR
773 #define BODS_REG MCUCR
776 #define OCDR0_REG OCDR
777 #define OCDR1_REG OCDR
778 #define OCDR2_REG OCDR
779 #define OCDR3_REG OCDR
780 #define OCDR4_REG OCDR
781 #define OCDR5_REG OCDR
782 #define OCDR6_REG OCDR
783 #define OCDR7_REG OCDR
786 #define PINA0_REG PINA
787 #define PINA1_REG PINA
788 #define PINA2_REG PINA
789 #define PINA3_REG PINA
790 #define PINA4_REG PINA
791 #define PINA5_REG PINA
792 #define PINA6_REG PINA
793 #define PINA7_REG PINA
796 #define TXB81_REG UCSR1B
797 #define RXB81_REG UCSR1B
798 #define UCSZ12_REG UCSR1B
799 #define TXEN1_REG UCSR1B
800 #define RXEN1_REG UCSR1B
801 #define UDRIE1_REG UCSR1B
802 #define TXCIE1_REG UCSR1B
803 #define RXCIE1_REG UCSR1B
806 #define UCPOL1_REG UCSR1C
807 #define UCSZ10_REG UCSR1C
808 #define UCSZ11_REG UCSR1C
809 #define USBS1_REG UCSR1C
810 #define UPM10_REG UCSR1C
811 #define UPM11_REG UCSR1C
812 #define UMSEL10_REG UCSR1C
813 #define UMSEL11_REG UCSR1C
816 #define MPCM1_REG UCSR1A
817 #define U2X1_REG UCSR1A
818 #define UPE1_REG UCSR1A
819 #define DOR1_REG UCSR1A
820 #define FE1_REG UCSR1A
821 #define UDRE1_REG UCSR1A
822 #define TXC1_REG UCSR1A
823 #define RXC1_REG UCSR1A
826 #define DDB0_REG DDRB
827 #define DDB1_REG DDRB
828 #define DDB2_REG DDRB
829 #define DDB3_REG DDRB
830 #define DDB4_REG DDRB
831 #define DDB5_REG DDRB
832 #define DDB6_REG DDRB
833 #define DDB7_REG DDRB
836 #define TWD0_REG TWDR
837 #define TWD1_REG TWDR
838 #define TWD2_REG TWDR
839 #define TWD3_REG TWDR
840 #define TWD4_REG TWDR
841 #define TWD5_REG TWDR
842 #define TWD6_REG TWDR
843 #define TWD7_REG TWDR
846 #define TWAM0_REG TWAMR
847 #define TWAM1_REG TWAMR
848 #define TWAM2_REG TWAMR
849 #define TWAM3_REG TWAMR
850 #define TWAM4_REG TWAMR
851 #define TWAM5_REG TWAMR
852 #define TWAM6_REG TWAMR
855 #define ADPS0_REG ADCSRA
856 #define ADPS1_REG ADCSRA
857 #define ADPS2_REG ADCSRA
858 #define ADIE_REG ADCSRA
859 #define ADIF_REG ADCSRA
860 #define ADATE_REG ADCSRA
861 #define ADSC_REG ADCSRA
862 #define ADEN_REG ADCSRA
865 #define ACME_REG ADCSRB
866 #define ADTS0_REG ADCSRB
867 #define ADTS1_REG ADCSRB
868 #define ADTS2_REG ADCSRB
871 #define PRADC_REG PRR0
872 #define PRUSART0_REG PRR0
873 #define PRSPI_REG PRR0
874 #define PRTIM1_REG PRR0
875 #define PRUSART1_REG PRR0
876 #define PRTIM0_REG PRR0
877 #define PRTIM2_REG PRR0
878 #define PRTWI_REG PRR0
881 #define WGM10_REG TCCR1A
882 #define WGM11_REG TCCR1A
883 #define COM1B0_REG TCCR1A
884 #define COM1B1_REG TCCR1A
885 #define COM1A0_REG TCCR1A
886 #define COM1A1_REG TCCR1A
889 #define OCROA_0_REG OCR0A
890 #define OCROA_1_REG OCR0A
891 #define OCROA_2_REG OCR0A
892 #define OCROA_3_REG OCR0A
893 #define OCROA_4_REG OCR0A
894 #define OCROA_5_REG OCR0A
895 #define OCROA_6_REG OCR0A
896 #define OCROA_7_REG OCR0A
899 #define OCR0B_0_REG OCR0B
900 #define OCR0B_1_REG OCR0B
901 #define OCR0B_2_REG OCR0B
902 #define OCR0B_3_REG OCR0B
903 #define OCR0B_4_REG OCR0B
904 #define OCR0B_5_REG OCR0B
905 #define OCR0B_6_REG OCR0B
906 #define OCR0B_7_REG OCR0B
909 #define TCNT1L0_REG TCNT1L
910 #define TCNT1L1_REG TCNT1L
911 #define TCNT1L2_REG TCNT1L
912 #define TCNT1L3_REG TCNT1L
913 #define TCNT1L4_REG TCNT1L
914 #define TCNT1L5_REG TCNT1L
915 #define TCNT1L6_REG TCNT1L
916 #define TCNT1L7_REG TCNT1L
919 #define FOC1B_REG TCCR1C
920 #define FOC1A_REG TCCR1C
923 #define ICR3H0_REG ICR3H
924 #define ICR3H1_REG ICR3H
925 #define ICR3H2_REG ICR3H
926 #define ICR3H3_REG ICR3H
927 #define ICR3H4_REG ICR3H
928 #define ICR3H5_REG ICR3H
929 #define ICR3H6_REG ICR3H
930 #define ICR3H7_REG ICR3H
933 #define PORTD0_REG PORTD
934 #define PORTD1_REG PORTD
935 #define PORTD2_REG PORTD
936 #define PORTD3_REG PORTD
937 #define PORTD4_REG PORTD
938 #define PORTD5_REG PORTD
939 #define PORTD6_REG PORTD
940 #define PORTD7_REG PORTD
943 #define ICR3L0_REG ICR3L
944 #define ICR3L1_REG ICR3L
945 #define ICR3L2_REG ICR3L
946 #define ICR3L3_REG ICR3L
947 #define ICR3L4_REG ICR3L
948 #define ICR3L5_REG ICR3L
949 #define ICR3L6_REG ICR3L
950 #define ICR3L7_REG ICR3L
953 #define SPMEN_REG SPMCSR
954 #define PGERS_REG SPMCSR
955 #define PGWRT_REG SPMCSR
956 #define BLBSET_REG SPMCSR
957 #define RWWSRE_REG SPMCSR
958 #define SIGRD_REG SPMCSR
959 #define RWWSB_REG SPMCSR
960 #define SPMIE_REG SPMCSR
963 #define PORTB0_REG PORTB
964 #define PORTB1_REG PORTB
965 #define PORTB2_REG PORTB
966 #define PORTB3_REG PORTB
967 #define PORTB4_REG PORTB
968 #define PORTB5_REG PORTB
969 #define PORTB6_REG PORTB
970 #define PORTB7_REG PORTB
973 #define ADCL0_REG ADCL
974 #define ADCL1_REG ADCL
975 #define ADCL2_REG ADCL
976 #define ADCL3_REG ADCL
977 #define ADCL4_REG ADCL
978 #define ADCL5_REG ADCL
979 #define ADCL6_REG ADCL
980 #define ADCL7_REG ADCL
983 #define ADCH0_REG ADCH
984 #define ADCH1_REG ADCH
985 #define ADCH2_REG ADCH
986 #define ADCH3_REG ADCH
987 #define ADCH4_REG ADCH
988 #define ADCH5_REG ADCH
989 #define ADCH6_REG ADCH
990 #define ADCH7_REG ADCH
993 /* #define OCR3AL0_REG OCR3BL */ /* dup in OCR3AL */
994 /* #define OCR3AL1_REG OCR3BL */ /* dup in OCR3AL */
995 /* #define OCR3AL2_REG OCR3BL */ /* dup in OCR3AL */
996 /* #define OCR3AL3_REG OCR3BL */ /* dup in OCR3AL */
997 /* #define OCR3AL4_REG OCR3BL */ /* dup in OCR3AL */
998 /* #define OCR3AL5_REG OCR3BL */ /* dup in OCR3AL */
999 /* #define OCR3AL6_REG OCR3BL */ /* dup in OCR3AL */
1000 /* #define OCR3AL7_REG OCR3BL */ /* dup in OCR3AL */
1003 /* #define OCR3AH0_REG OCR3BH */ /* dup in OCR3AH */
1004 /* #define OCR3AH1_REG OCR3BH */ /* dup in OCR3AH */
1005 /* #define OCR3AH2_REG OCR3BH */ /* dup in OCR3AH */
1006 /* #define OCR3AH3_REG OCR3BH */ /* dup in OCR3AH */
1007 /* #define OCR3AH4_REG OCR3BH */ /* dup in OCR3AH */
1008 /* #define OCR3AH5_REG OCR3BH */ /* dup in OCR3AH */
1009 /* #define OCR3AH6_REG OCR3BH */ /* dup in OCR3AH */
1010 /* #define OCR3AH7_REG OCR3BH */ /* dup in OCR3AH */
1013 #define TOIE2_REG TIMSK2
1014 #define OCIE2A_REG TIMSK2
1015 #define OCIE2B_REG TIMSK2
1018 #define TOIE3_REG TIMSK3
1019 #define OCIE3A_REG TIMSK3
1020 #define OCIE3B_REG TIMSK3
1021 #define ICIE3_REG TIMSK3
1024 #define TOIE0_REG TIMSK0
1025 #define OCIE0A_REG TIMSK0
1026 #define OCIE0B_REG TIMSK0
1029 #define TOIE1_REG TIMSK1
1030 #define OCIE1A_REG TIMSK1
1031 #define OCIE1B_REG TIMSK1
1032 #define ICIE1_REG TIMSK1
1035 #define PCINT0_REG PCMSK0
1036 #define PCINT1_REG PCMSK0
1037 #define PCINT2_REG PCMSK0
1038 #define PCINT3_REG PCMSK0
1039 #define PCINT4_REG PCMSK0
1040 #define PCINT5_REG PCMSK0
1041 #define PCINT6_REG PCMSK0
1042 #define PCINT7_REG PCMSK0
1045 #define PCINT8_REG PCMSK1
1046 #define PCINT9_REG PCMSK1
1047 #define PCINT10_REG PCMSK1
1048 #define PCINT11_REG PCMSK1
1049 #define PCINT12_REG PCMSK1
1050 #define PCINT13_REG PCMSK1
1051 #define PCINT14_REG PCMSK1
1052 #define PCINT15_REG PCMSK1
1055 #define PCINT16_REG PCMSK2
1056 #define PCINT17_REG PCMSK2
1057 #define PCINT18_REG PCMSK2
1058 #define PCINT19_REG PCMSK2
1059 #define PCINT20_REG PCMSK2
1060 #define PCINT21_REG PCMSK2
1061 #define PCINT22_REG PCMSK2
1062 #define PCINT23_REG PCMSK2
1065 #define PCINT24_REG PCMSK3
1066 #define PCINT25_REG PCMSK3
1067 #define PCINT26_REG PCMSK3
1068 #define PCINT27_REG PCMSK3
1069 #define PCINT28_REG PCMSK3
1070 #define PCINT29_REG PCMSK3
1071 #define PCINT30_REG PCMSK3
1072 #define PCINT31_REG PCMSK3
1075 #define PINC0_REG PINC
1076 #define PINC1_REG PINC
1077 #define PINC2_REG PINC
1078 #define PINC3_REG PINC
1079 #define PINC4_REG PINC
1080 #define PINC5_REG PINC
1081 #define PINC6_REG PINC
1082 #define PINC7_REG PINC
1085 #define PINB0_REG PINB
1086 #define PINB1_REG PINB
1087 #define PINB2_REG PINB
1088 #define PINB3_REG PINB
1089 #define PINB4_REG PINB
1090 #define PINB5_REG PINB
1091 #define PINB6_REG PINB
1092 #define PINB7_REG PINB
1095 #define INTF0_REG EIFR
1096 #define INTF1_REG EIFR
1097 #define INTF2_REG EIFR
1100 #define PIND0_REG PIND
1101 #define PIND1_REG PIND
1102 #define PIND2_REG PIND
1103 #define PIND3_REG PIND
1104 #define PIND4_REG PIND
1105 #define PIND5_REG PIND
1106 #define PIND6_REG PIND
1107 #define PIND7_REG PIND
1110 /* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
1111 /* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
1112 /* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
1113 /* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
1114 /* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
1115 /* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
1116 /* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
1117 /* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
1120 /* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
1121 /* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
1122 /* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
1123 /* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
1124 /* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
1125 /* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
1126 /* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
1127 /* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
1130 #define TOV0_REG TIFR0
1131 #define OCF0A_REG TIFR0
1132 #define OCF0B_REG TIFR0
1135 #define PRTIM3_REG PRR1
1138 #define ADC0_PORT PORTA
1140 #define PCINT0_PORT PORTA
1141 #define PCINT0_BIT 0
1143 #define ADC1_PORT PORTA
1145 #define PCINT1_PORT PORTA
1146 #define PCINT1_BIT 1
1148 #define ADC2_PORT PORTA
1150 #define PCINT2_PORT PORTA
1151 #define PCINT2_BIT 2
1153 #define ADC3_PORT PORTA
1155 #define PCINT3_PORT PORTA
1156 #define PCINT3_BIT 3
1158 #define ADC4_PORT PORTA
1160 #define PCINT4_PORT PORTA
1161 #define PCINT4_BIT 4
1163 #define ADC5_PORT PORTA
1165 #define PCINT5_PORT PORTA
1166 #define PCINT5_BIT 5
1168 #define ADC6_PORT PORTA
1170 #define PCINT6_PORT PORTA
1171 #define PCINT6_BIT 6
1173 #define ADC7_PORT PORTA
1175 #define PCINT7_PORT PORTA
1176 #define PCINT7_BIT 7
1178 #define XCK_PORT PORTB
1180 #define T0_PORT PORTB
1182 #define PCINT9_PORT PORTB
1183 #define PCINT9_BIT 0
1185 #define T1_PORT PORTB
1187 #define CLKO_PORT PORTB
1189 #define PCINT9_PORT PORTB
1190 #define PCINT9_BIT 1
1192 #define AIN0_PORT PORTB
1194 #define INT2_PORT PORTB
1196 #define PCINT10_PORT PORTB
1197 #define PCINT10_BIT 2
1199 #define AIN1_PORT PORTB
1201 #define OC0A_PORT PORTB
1203 #define PCINT11_PORT PORTB
1204 #define PCINT11_BIT 3
1206 #define SS_PORT PORTB
1208 #define OC0B_PORT PORTB
1210 #define PCINT12_PORT PORTB
1211 #define PCINT12_BIT 4
1213 #define MOSI_PORT PORTB
1215 #define PCINT13_PORT PORTB
1216 #define PCINT13_BIT 5
1218 #define MISO_PORT PORTB
1220 #define PCINT14_PORT PORTB
1221 #define PCINT14_BIT 6
1223 #define SCK_PORT PORTB
1225 #define PCINT15_PORT PORTB
1226 #define PCINT15_BIT 7
1228 #define SCL_PORT PORTC
1230 #define PCINT16_PORT PORTC
1231 #define PCINT16_BIT 0
1233 #define SDA_PORT PORTC
1235 #define PCINT17_PORT PORTC
1236 #define PCINT17_BIT 1
1238 #define TCK_PORT PORTC
1240 #define PCINT18_PORT PORTC
1241 #define PCINT18_BIT 2
1243 #define TMS_PORT PORTC
1245 #define PCINT19_PORT PORTC
1246 #define PCINT19_BIT 3
1248 #define TDO_PORT PORTC
1250 #define PCINT20_PORT PORTC
1251 #define PCINT20_BIT 4
1253 #define TDI_PORT PORTC
1255 #define PCINT21_PORT PORTC
1256 #define PCINT21_BIT 5
1258 #define TOSC1_PORT PORTC
1260 #define PCINT22_PORT PORTC
1261 #define PCINT22_BIT 6
1263 #define TOSC2_PORT PORTC
1265 #define PCINT23_PORT PORTC
1266 #define PCINT23_BIT 7
1268 #define RXD_PORT PORTD
1270 #define PCINT24_PORT PORTD
1271 #define PCINT24_BIT 0
1273 #define TXD_PORT PORTD
1275 #define PCINT25_PORT PORTD
1276 #define PCINT25_BIT 1
1278 #define INT0_PORT PORTD
1280 #define RDX1_PORT PORTD
1282 #define PCINT26_PORT PORTD
1283 #define PCINT26_BIT 2
1285 #define INT1_PORT PORTD
1287 #define TXD1_PORT PORTD
1289 #define PCINT27_PORT PORTD
1290 #define PCINT27_BIT 3
1292 #define OC1B_PORT PORTD
1294 #define XCK1_PORT PORTD
1296 #define PCINT28_PORT PORTD
1297 #define PCINT28_BIT 4
1299 #define OC1A_PORT PORTD
1301 #define PCINT29_PORT PORTD
1302 #define PCINT29_BIT 5
1304 #define ICP_PORT PORTD
1306 #define OC2B_PORT PORTD
1308 #define PCINT30_PORT PORTD
1309 #define PCINT30_BIT 6
1311 #define OC2A_PORT PORTD
1313 #define PCINT31_PORT PORTD
1314 #define PCINT31_BIT 7