2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
84 /* prescalers timer 3 */
85 #define TIMER3_PRESCALER_DIV_0 0
86 #define TIMER3_PRESCALER_DIV_1 1
87 #define TIMER3_PRESCALER_DIV_8 2
88 #define TIMER3_PRESCALER_DIV_64 3
89 #define TIMER3_PRESCALER_DIV_256 4
90 #define TIMER3_PRESCALER_DIV_1024 5
91 #define TIMER3_PRESCALER_DIV_FALL 6
92 #define TIMER3_PRESCALER_DIV_RISE 7
94 #define TIMER3_PRESCALER_REG_0 0
95 #define TIMER3_PRESCALER_REG_1 1
96 #define TIMER3_PRESCALER_REG_2 8
97 #define TIMER3_PRESCALER_REG_3 64
98 #define TIMER3_PRESCALER_REG_4 256
99 #define TIMER3_PRESCALER_REG_5 1024
100 #define TIMER3_PRESCALER_REG_6 -1
101 #define TIMER3_PRESCALER_REG_7 -2
103 /* prescalers timer 4 */
104 #define TIMER4_PRESCALER_DIV_0 0
105 #define TIMER4_PRESCALER_DIV_1 1
106 #define TIMER4_PRESCALER_DIV_8 2
107 #define TIMER4_PRESCALER_DIV_64 3
108 #define TIMER4_PRESCALER_DIV_256 4
109 #define TIMER4_PRESCALER_DIV_1024 5
110 #define TIMER4_PRESCALER_DIV_FALL 6
111 #define TIMER4_PRESCALER_DIV_RISE 7
113 #define TIMER4_PRESCALER_REG_0 0
114 #define TIMER4_PRESCALER_REG_1 1
115 #define TIMER4_PRESCALER_REG_2 8
116 #define TIMER4_PRESCALER_REG_3 64
117 #define TIMER4_PRESCALER_REG_4 256
118 #define TIMER4_PRESCALER_REG_5 1024
119 #define TIMER4_PRESCALER_REG_6 -1
120 #define TIMER4_PRESCALER_REG_7 -2
122 /* prescalers timer 5 */
123 #define TIMER5_PRESCALER_DIV_0 0
124 #define TIMER5_PRESCALER_DIV_1 1
125 #define TIMER5_PRESCALER_DIV_8 2
126 #define TIMER5_PRESCALER_DIV_64 3
127 #define TIMER5_PRESCALER_DIV_256 4
128 #define TIMER5_PRESCALER_DIV_1024 5
129 #define TIMER5_PRESCALER_DIV_FALL 6
130 #define TIMER5_PRESCALER_DIV_RISE 7
132 #define TIMER5_PRESCALER_REG_0 0
133 #define TIMER5_PRESCALER_REG_1 1
134 #define TIMER5_PRESCALER_REG_2 8
135 #define TIMER5_PRESCALER_REG_3 64
136 #define TIMER5_PRESCALER_REG_4 256
137 #define TIMER5_PRESCALER_REG_5 1024
138 #define TIMER5_PRESCALER_REG_6 -1
139 #define TIMER5_PRESCALER_REG_7 -2
142 /* available timers */
143 #define TIMER0_AVAILABLE
144 #define TIMER0A_AVAILABLE
145 #define TIMER0B_AVAILABLE
146 #define TIMER1_AVAILABLE
147 #define TIMER1A_AVAILABLE
148 #define TIMER1B_AVAILABLE
149 #define TIMER1C_AVAILABLE
150 #define TIMER2_AVAILABLE
151 #define TIMER2A_AVAILABLE
152 #define TIMER2B_AVAILABLE
153 #define TIMER3_AVAILABLE
154 #define TIMER3A_AVAILABLE
155 #define TIMER3B_AVAILABLE
156 #define TIMER3C_AVAILABLE
157 #define TIMER4_AVAILABLE
158 #define TIMER4A_AVAILABLE
159 #define TIMER4B_AVAILABLE
160 #define TIMER4C_AVAILABLE
161 #define TIMER5_AVAILABLE
162 #define TIMER5A_AVAILABLE
163 #define TIMER5B_AVAILABLE
164 #define TIMER5C_AVAILABLE
166 /* overflow interrupt number */
167 #define SIG_OVERFLOW0_NUM 0
168 #define SIG_OVERFLOW1_NUM 1
169 #define SIG_OVERFLOW2_NUM 2
170 #define SIG_OVERFLOW3_NUM 3
171 #define SIG_OVERFLOW4_NUM 4
172 #define SIG_OVERFLOW5_NUM 5
173 #define SIG_OVERFLOW_TOTAL_NUM 6
175 /* output compare interrupt number */
176 #define SIG_OUTPUT_COMPARE0A_NUM 0
177 #define SIG_OUTPUT_COMPARE0B_NUM 1
178 #define SIG_OUTPUT_COMPARE1A_NUM 2
179 #define SIG_OUTPUT_COMPARE1B_NUM 3
180 #define SIG_OUTPUT_COMPARE1C_NUM 4
181 #define SIG_OUTPUT_COMPARE2A_NUM 5
182 #define SIG_OUTPUT_COMPARE2B_NUM 6
183 #define SIG_OUTPUT_COMPARE3A_NUM 7
184 #define SIG_OUTPUT_COMPARE3B_NUM 8
185 #define SIG_OUTPUT_COMPARE3C_NUM 9
186 #define SIG_OUTPUT_COMPARE4A_NUM 10
187 #define SIG_OUTPUT_COMPARE4B_NUM 11
188 #define SIG_OUTPUT_COMPARE4C_NUM 12
189 #define SIG_OUTPUT_COMPARE5A_NUM 13
190 #define SIG_OUTPUT_COMPARE5B_NUM 14
191 #define SIG_OUTPUT_COMPARE5C_NUM 15
192 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
211 #define PWM_TOTAL_NUM 16
213 /* input capture interrupt number */
214 #define SIG_INPUT_CAPTURE1_NUM 0
215 #define SIG_INPUT_CAPTURE3_NUM 1
216 #define SIG_INPUT_CAPTURE4_NUM 2
217 #define SIG_INPUT_CAPTURE5_NUM 3
218 #define SIG_INPUT_CAPTURE_TOTAL_NUM 4
222 /* #define UBRR8_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
223 /* #define UBRR9_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
224 /* #define UBRR10_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
225 /* #define UBRR11_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
228 /* #define UBRR0_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
229 /* #define UBRR1_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
230 /* #define UBRR2_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
231 /* #define UBRR3_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
232 /* #define UBRR4_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
233 /* #define UBRR5_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
234 /* #define UBRR6_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
235 /* #define UBRR7_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
238 #define OCROA_0_REG OCR0A
239 #define OCROA_1_REG OCR0A
240 #define OCROA_2_REG OCR0A
241 #define OCROA_3_REG OCR0A
242 #define OCROA_4_REG OCR0A
243 #define OCROA_5_REG OCR0A
244 #define OCROA_6_REG OCR0A
245 #define OCROA_7_REG OCR0A
248 #define MUX0_REG ADMUX
249 #define MUX1_REG ADMUX
250 #define MUX2_REG ADMUX
251 #define MUX3_REG ADMUX
252 #define MUX4_REG ADMUX
253 #define ADLAR_REG ADMUX
254 #define REFS0_REG ADMUX
255 #define REFS1_REG ADMUX
258 #define MPCM3_REG UCSR3A
259 #define U2X3_REG UCSR3A
260 #define UPE3_REG UCSR3A
261 #define DOR3_REG UCSR3A
262 #define FE3_REG UCSR3A
263 #define UDRE3_REG UCSR3A
264 #define TXC3_REG UCSR3A
265 #define RXC3_REG UCSR3A
268 #define TXB83_REG UCSR3B
269 #define RXB83_REG UCSR3B
270 #define UCSZ32_REG UCSR3B
271 #define TXEN3_REG UCSR3B
272 #define RXEN3_REG UCSR3B
273 #define UDRIE3_REG UCSR3B
274 #define TXCIE3_REG UCSR3B
275 #define RXCIE3_REG UCSR3B
278 #define UCPOL3_REG UCSR3C
279 #define UCSZ30_REG UCSR3C
280 #define UCSZ31_REG UCSR3C
281 #define USBS3_REG UCSR3C
282 #define UPM30_REG UCSR3C
283 #define UPM31_REG UCSR3C
284 #define UMSEL30_REG UCSR3C
285 #define UMSEL31_REG UCSR3C
288 #define EEDR0_REG EEDR
289 #define EEDR1_REG EEDR
290 #define EEDR2_REG EEDR
291 #define EEDR3_REG EEDR
292 #define EEDR4_REG EEDR
293 #define EEDR5_REG EEDR
294 #define EEDR6_REG EEDR
295 #define EEDR7_REG EEDR
298 #define ACIS0_REG ACSR
299 #define ACIS1_REG ACSR
300 #define ACIC_REG ACSR
301 #define ACIE_REG ACSR
304 #define ACBG_REG ACSR
308 #define RAMPZ0_REG RAMPZ
309 #define RAMPZ1_REG RAMPZ
312 #define OCR2B_0_REG OCR2B
313 #define OCR2B_1_REG OCR2B
314 #define OCR2B_2_REG OCR2B
315 #define OCR2B_3_REG OCR2B
316 #define OCR2B_4_REG OCR2B
317 #define OCR2B_5_REG OCR2B
318 #define OCR2B_6_REG OCR2B
319 #define OCR2B_7_REG OCR2B
322 #define OCR2A_0_REG OCR2A
323 #define OCR2A_1_REG OCR2A
324 #define OCR2A_2_REG OCR2A
325 #define OCR2A_3_REG OCR2A
326 #define OCR2A_4_REG OCR2A
327 #define OCR2A_5_REG OCR2A
328 #define OCR2A_6_REG OCR2A
329 #define OCR2A_7_REG OCR2A
332 #define SPDR0_REG SPDR
333 #define SPDR1_REG SPDR
334 #define SPDR2_REG SPDR
335 #define SPDR3_REG SPDR
336 #define SPDR4_REG SPDR
337 #define SPDR5_REG SPDR
338 #define SPDR6_REG SPDR
339 #define SPDR7_REG SPDR
342 #define SPI2X_REG SPSR
343 #define WCOL_REG SPSR
344 #define SPIF_REG SPSR
347 #define ICR1H0_REG ICR1H
348 #define ICR1H1_REG ICR1H
349 #define ICR1H2_REG ICR1H
350 #define ICR1H3_REG ICR1H
351 #define ICR1H4_REG ICR1H
352 #define ICR1H5_REG ICR1H
353 #define ICR1H6_REG ICR1H
354 #define ICR1H7_REG ICR1H
357 #define ICR1L0_REG ICR1L
358 #define ICR1L1_REG ICR1L
359 #define ICR1L2_REG ICR1L
360 #define ICR1L3_REG ICR1L
361 #define ICR1L4_REG ICR1L
362 #define ICR1L5_REG ICR1L
363 #define ICR1L6_REG ICR1L
364 #define ICR1L7_REG ICR1L
367 #define EEAR8_REG EEARH
368 #define EEAR9_REG EEARH
369 #define EEAR10_REG EEARH
370 #define EEAR11_REG EEARH
373 #define PORTL0_REG PORTL
374 #define PORTL1_REG PORTL
375 #define PORTL2_REG PORTL
376 #define PORTL3_REG PORTL
377 #define PORTL4_REG PORTL
378 #define PORTL5_REG PORTL
379 #define PORTL6_REG PORTL
380 #define PORTL7_REG PORTL
383 #define PORTJ0_REG PORTJ
384 #define PORTJ1_REG PORTJ
385 #define PORTJ2_REG PORTJ
386 #define PORTJ3_REG PORTJ
387 #define PORTJ4_REG PORTJ
388 #define PORTJ5_REG PORTJ
389 #define PORTJ6_REG PORTJ
390 #define PORTJ7_REG PORTJ
393 #define PORTK0_REG PORTK
394 #define PORTK1_REG PORTK
395 #define PORTK2_REG PORTK
396 #define PORTK3_REG PORTK
397 #define PORTK4_REG PORTK
398 #define PORTK5_REG PORTK
399 #define PORTK6_REG PORTK
400 #define PORTK7_REG PORTK
403 #define PORTH0_REG PORTH
404 #define PORTH1_REG PORTH
405 #define PORTH2_REG PORTH
406 #define PORTH3_REG PORTH
407 #define PORTH4_REG PORTH
408 #define PORTH5_REG PORTH
409 #define PORTH6_REG PORTH
410 #define PORTH7_REG PORTH
413 #define MPCM0_REG UCSR0A
414 #define U2X0_REG UCSR0A
415 #define UPE0_REG UCSR0A
416 #define DOR0_REG UCSR0A
417 #define FE0_REG UCSR0A
418 #define UDRE0_REG UCSR0A
419 #define TXC0_REG UCSR0A
420 #define RXC0_REG UCSR0A
423 #define PORTG0_REG PORTG
424 #define PORTG1_REG PORTG
425 #define PORTG2_REG PORTG
426 #define PORTG3_REG PORTG
427 #define PORTG4_REG PORTG
428 #define PORTG5_REG PORTG
431 #define UCPOL0_REG UCSR0C
432 #define UCSZ00_REG UCSR0C
433 #define UCSZ01_REG UCSR0C
434 #define USBS0_REG UCSR0C
435 #define UPM00_REG UCSR0C
436 #define UPM01_REG UCSR0C
437 #define UMSEL00_REG UCSR0C
438 #define UMSEL01_REG UCSR0C
441 #define TXB80_REG UCSR0B
442 #define RXB80_REG UCSR0B
443 #define UCSZ02_REG UCSR0B
444 #define TXEN0_REG UCSR0B
445 #define RXEN0_REG UCSR0B
446 #define UDRIE0_REG UCSR0B
447 #define TXCIE0_REG UCSR0B
448 #define RXCIE0_REG UCSR0B
451 #define TCNT1H0_REG TCNT1H
452 #define TCNT1H1_REG TCNT1H
453 #define TCNT1H2_REG TCNT1H
454 #define TCNT1H3_REG TCNT1H
455 #define TCNT1H4_REG TCNT1H
456 #define TCNT1H5_REG TCNT1H
457 #define TCNT1H6_REG TCNT1H
458 #define TCNT1H7_REG TCNT1H
461 #define PORTC0_REG PORTC
462 #define PORTC1_REG PORTC
463 #define PORTC2_REG PORTC
464 #define PORTC3_REG PORTC
465 #define PORTC4_REG PORTC
466 #define PORTC5_REG PORTC
467 #define PORTC6_REG PORTC
468 #define PORTC7_REG PORTC
471 #define PORTA0_REG PORTA
472 #define PORTA1_REG PORTA
473 #define PORTA2_REG PORTA
474 #define PORTA3_REG PORTA
475 #define PORTA4_REG PORTA
476 #define PORTA5_REG PORTA
477 #define PORTA6_REG PORTA
478 #define PORTA7_REG PORTA
481 #define GPIOR10_REG GPIOR1
482 #define GPIOR11_REG GPIOR1
483 #define GPIOR12_REG GPIOR1
484 #define GPIOR13_REG GPIOR1
485 #define GPIOR14_REG GPIOR1
486 #define GPIOR15_REG GPIOR1
487 #define GPIOR16_REG GPIOR1
488 #define GPIOR17_REG GPIOR1
491 #define INT0_REG EIMSK
492 #define INT1_REG EIMSK
493 #define INT2_REG EIMSK
494 #define INT3_REG EIMSK
495 #define INT4_REG EIMSK
496 #define INT5_REG EIMSK
497 #define INT6_REG EIMSK
498 #define INT7_REG EIMSK
501 #define UDR1_0_REG UDR1
502 #define UDR1_1_REG UDR1
503 #define UDR1_2_REG UDR1
504 #define UDR1_3_REG UDR1
505 #define UDR1_4_REG UDR1
506 #define UDR1_5_REG UDR1
507 #define UDR1_6_REG UDR1
508 #define UDR1_7_REG UDR1
511 #define UDR0_0_REG UDR0
512 #define UDR0_1_REG UDR0
513 #define UDR0_2_REG UDR0
514 #define UDR0_3_REG UDR0
515 #define UDR0_4_REG UDR0
516 #define UDR0_5_REG UDR0
517 #define UDR0_6_REG UDR0
518 #define UDR0_7_REG UDR0
521 #define UDR3_0_REG UDR3
522 #define UDR3_1_REG UDR3
523 #define UDR3_2_REG UDR3
524 #define UDR3_3_REG UDR3
525 #define UDR3_4_REG UDR3
526 #define UDR3_5_REG UDR3
527 #define UDR3_6_REG UDR3
528 #define UDR3_7_REG UDR3
531 #define UDR2_0_REG UDR2
532 #define UDR2_1_REG UDR2
533 #define UDR2_2_REG UDR2
534 #define UDR2_3_REG UDR2
535 #define UDR2_4_REG UDR2
536 #define UDR2_5_REG UDR2
537 #define UDR2_6_REG UDR2
538 #define UDR2_7_REG UDR2
541 #define ISC40_REG EICRB
542 #define ISC41_REG EICRB
543 #define ISC50_REG EICRB
544 #define ISC51_REG EICRB
545 #define ISC60_REG EICRB
546 #define ISC61_REG EICRB
547 #define ISC70_REG EICRB
548 #define ISC71_REG EICRB
551 #define ISC00_REG EICRA
552 #define ISC01_REG EICRA
553 #define ISC10_REG EICRA
554 #define ISC11_REG EICRA
555 #define ISC20_REG EICRA
556 #define ISC21_REG EICRA
557 #define ISC30_REG EICRA
558 #define ISC31_REG EICRA
561 #define ADC0D_REG DIDR0
562 #define ADC1D_REG DIDR0
563 #define ADC2D_REG DIDR0
564 #define ADC3D_REG DIDR0
565 #define ADC4D_REG DIDR0
566 #define ADC5D_REG DIDR0
567 #define ADC6D_REG DIDR0
568 #define ADC7D_REG DIDR0
571 #define AIN0D_REG DIDR1
572 #define AIN1D_REG DIDR1
575 #define ADC8D_REG DIDR2
576 #define ADC9D_REG DIDR2
577 #define ADC10D_REG DIDR2
578 #define ADC11D_REG DIDR2
579 #define ADC12D_REG DIDR2
580 #define ADC13D_REG DIDR2
581 #define ADC14D_REG DIDR2
582 #define ADC15D_REG DIDR2
585 #define DDF0_REG DDRF
586 #define DDF1_REG DDRF
587 #define DDF2_REG DDRF
588 #define DDF3_REG DDRF
589 #define DDF4_REG DDRF
590 #define DDF5_REG DDRF
591 #define DDF6_REG DDRF
592 #define DDF7_REG DDRF
595 #define TCR2BUB_REG ASSR
596 #define TCR2AUB_REG ASSR
597 #define OCR2BUB_REG ASSR
598 #define OCR2AUB_REG ASSR
599 #define TCN2UB_REG ASSR
601 #define EXCLK_REG ASSR
604 #define CLKPS0_REG CLKPR
605 #define CLKPS1_REG CLKPR
606 #define CLKPS2_REG CLKPR
607 #define CLKPS3_REG CLKPR
608 #define CLKPCE_REG CLKPR
611 #define OCR0B_0_REG OCR0B
612 #define OCR0B_1_REG OCR0B
613 #define OCR0B_2_REG OCR0B
614 #define OCR0B_3_REG OCR0B
615 #define OCR0B_4_REG OCR0B
616 #define OCR0B_5_REG OCR0B
617 #define OCR0B_6_REG OCR0B
618 #define OCR0B_7_REG OCR0B
621 #define WDP0_REG WDTCSR
622 #define WDP1_REG WDTCSR
623 #define WDP2_REG WDTCSR
624 #define WDE_REG WDTCSR
625 #define WDCE_REG WDTCSR
626 #define WDP3_REG WDTCSR
627 #define WDIE_REG WDTCSR
628 #define WDIF_REG WDTCSR
641 #define DDJ0_REG DDRJ
642 #define DDJ1_REG DDRJ
643 #define DDJ2_REG DDRJ
644 #define DDJ3_REG DDRJ
645 #define DDJ4_REG DDRJ
646 #define DDJ5_REG DDRJ
647 #define DDJ6_REG DDRJ
648 #define DDJ7_REG DDRJ
651 #define DDK0_REG DDRK
652 #define DDK1_REG DDRK
653 #define DDK2_REG DDRK
654 #define DDK3_REG DDRK
655 #define DDK4_REG DDRK
656 #define DDK5_REG DDRK
657 #define DDK6_REG DDRK
658 #define DDK7_REG DDRK
661 #define DDH0_REG DDRH
662 #define DDH1_REG DDRH
663 #define DDH2_REG DDRH
664 #define DDH3_REG DDRH
665 #define DDH4_REG DDRH
666 #define DDH5_REG DDRH
667 #define DDH6_REG DDRH
668 #define DDH7_REG DDRH
671 #define DDL0_REG DDRL
672 #define DDL1_REG DDRL
673 #define DDL2_REG DDRL
674 #define DDL3_REG DDRL
675 #define DDL4_REG DDRL
676 #define DDL5_REG DDRL
677 #define DDL6_REG DDRL
678 #define DDL7_REG DDRL
681 #define UBRR_0_REG UBRR1L
682 #define UBRR_1_REG UBRR1L
683 #define UBRR_2_REG UBRR1L
684 #define UBRR_3_REG UBRR1L
685 #define UBRR_4_REG UBRR1L
686 #define UBRR_5_REG UBRR1L
687 #define UBRR_6_REG UBRR1L
688 #define UBRR_7_REG UBRR1L
691 #define DDC0_REG DDRC
692 #define DDC1_REG DDRC
693 #define DDC2_REG DDRC
694 #define DDC3_REG DDRC
695 #define DDC4_REG DDRC
696 #define DDC5_REG DDRC
697 #define DDC6_REG DDRC
698 #define DDC7_REG DDRC
701 #define OCR3AL0_REG OCR3AL
702 #define OCR3AL1_REG OCR3AL
703 #define OCR3AL2_REG OCR3AL
704 #define OCR3AL3_REG OCR3AL
705 #define OCR3AL4_REG OCR3AL
706 #define OCR3AL5_REG OCR3AL
707 #define OCR3AL6_REG OCR3AL
708 #define OCR3AL7_REG OCR3AL
711 #define DDA0_REG DDRA
712 #define DDA1_REG DDRA
713 #define DDA2_REG DDRA
714 #define DDA3_REG DDRA
715 #define DDA4_REG DDRA
716 #define DDA5_REG DDRA
717 #define DDA6_REG DDRA
718 #define DDA7_REG DDRA
721 #define UBRR_8_REG UBRR1H
722 #define UBRR_9_REG UBRR1H
723 #define UBRR_10_REG UBRR1H
724 #define UBRR_11_REG UBRR1H
727 #define DDG0_REG DDRG
728 #define DDG1_REG DDRG
729 #define DDG2_REG DDRG
730 #define DDG3_REG DDRG
731 #define DDG4_REG DDRG
732 #define DDG5_REG DDRG
735 #define OCR3AH0_REG OCR3AH
736 #define OCR3AH1_REG OCR3AH
737 #define OCR3AH2_REG OCR3AH
738 #define OCR3AH3_REG OCR3AH
739 #define OCR3AH4_REG OCR3AH
740 #define OCR3AH5_REG OCR3AH
741 #define OCR3AH6_REG OCR3AH
742 #define OCR3AH7_REG OCR3AH
745 #define CS10_REG TCCR1B
746 #define CS11_REG TCCR1B
747 #define CS12_REG TCCR1B
748 #define WGM12_REG TCCR1B
749 #define WGM13_REG TCCR1B
750 #define ICES1_REG TCCR1B
751 #define ICNC1_REG TCCR1B
754 #define CAL0_REG OSCCAL
755 #define CAL1_REG OSCCAL
756 #define CAL2_REG OSCCAL
757 #define CAL3_REG OSCCAL
758 #define CAL4_REG OSCCAL
759 #define CAL5_REG OSCCAL
760 #define CAL6_REG OSCCAL
761 #define CAL7_REG OSCCAL
764 #define DDD0_REG DDRD
765 #define DDD1_REG DDRD
766 #define DDD2_REG DDRD
767 #define DDD3_REG DDRD
768 #define DDD4_REG DDRD
769 #define DDD5_REG DDRD
770 #define DDD6_REG DDRD
771 #define DDD7_REG DDRD
774 #define TCNT5H0_REG TCNT5H
775 #define TCNT5H1_REG TCNT5H
776 #define TCNT5H2_REG TCNT5H
777 #define TCNT5H3_REG TCNT5H
778 #define TCNT5H4_REG TCNT5H
779 #define TCNT5H5_REG TCNT5H
780 #define TCNT5H6_REG TCNT5H
781 #define TCNT5H7_REG TCNT5H
784 #define GPIOR00_REG GPIOR0
785 #define GPIOR01_REG GPIOR0
786 #define GPIOR02_REG GPIOR0
787 #define GPIOR03_REG GPIOR0
788 #define GPIOR04_REG GPIOR0
789 #define GPIOR05_REG GPIOR0
790 #define GPIOR06_REG GPIOR0
791 #define GPIOR07_REG GPIOR0
794 #define GPIOR20_REG GPIOR2
795 #define GPIOR21_REG GPIOR2
796 #define GPIOR22_REG GPIOR2
797 #define GPIOR23_REG GPIOR2
798 #define GPIOR24_REG GPIOR2
799 #define GPIOR25_REG GPIOR2
800 #define GPIOR26_REG GPIOR2
801 #define GPIOR27_REG GPIOR2
804 #define TCNT5L0_REG TCNT5L
805 #define TCNT5L1_REG TCNT5L
806 #define TCNT5L2_REG TCNT5L
807 #define TCNT5L3_REG TCNT5L
808 #define TCNT5L4_REG TCNT5L
809 #define TCNT5L5_REG TCNT5L
810 #define TCNT5L6_REG TCNT5L
811 #define TCNT5L7_REG TCNT5L
814 /* #define UBRR8_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
815 /* #define UBRR9_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
816 /* #define UBRR10_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
817 /* #define UBRR11_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
820 /* #define UBRR0_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
821 /* #define UBRR1_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
822 /* #define UBRR2_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
823 /* #define UBRR3_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
824 /* #define UBRR4_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
825 /* #define UBRR5_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
826 /* #define UBRR6_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
827 /* #define UBRR7_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
830 #define PCIE0_REG PCICR
831 #define PCIE1_REG PCICR
832 #define PCIE2_REG PCICR
835 #define TCNT2_0_REG TCNT2
836 #define TCNT2_1_REG TCNT2
837 #define TCNT2_2_REG TCNT2
838 #define TCNT2_3_REG TCNT2
839 #define TCNT2_4_REG TCNT2
840 #define TCNT2_5_REG TCNT2
841 #define TCNT2_6_REG TCNT2
842 #define TCNT2_7_REG TCNT2
845 #define TXB82_REG UCSR2B
846 #define RXB82_REG UCSR2B
847 #define UCSZ22_REG UCSR2B
848 #define TXEN2_REG UCSR2B
849 #define RXEN2_REG UCSR2B
850 #define UDRIE2_REG UCSR2B
851 #define TXCIE2_REG UCSR2B
852 #define RXCIE2_REG UCSR2B
855 #define MPCM2_REG UCSR2A
856 #define U2X2_REG UCSR2A
857 #define UPE2_REG UCSR2A
858 #define DOR2_REG UCSR2A
859 #define FE2_REG UCSR2A
860 #define UDRE2_REG UCSR2A
861 #define TXC2_REG UCSR2A
862 #define RXC2_REG UCSR2A
865 #define TWGCE_REG TWAR
866 #define TWA0_REG TWAR
867 #define TWA1_REG TWAR
868 #define TWA2_REG TWAR
869 #define TWA3_REG TWAR
870 #define TWA4_REG TWAR
871 #define TWA5_REG TWAR
872 #define TWA6_REG TWAR
875 #define CS00_REG TCCR0B
876 #define CS01_REG TCCR0B
877 #define CS02_REG TCCR0B
878 #define WGM02_REG TCCR0B
879 #define FOC0B_REG TCCR0B
880 #define FOC0A_REG TCCR0B
883 #define WGM00_REG TCCR0A
884 #define WGM01_REG TCCR0A
885 #define COM0B0_REG TCCR0A
886 #define COM0B1_REG TCCR0A
887 #define COM0A0_REG TCCR0A
888 #define COM0A1_REG TCCR0A
891 #define UCPOL2_REG UCSR2C
892 #define UCSZ20_REG UCSR2C
893 #define UCSZ21_REG UCSR2C
894 #define USBS2_REG UCSR2C
895 #define UPM20_REG UCSR2C
896 #define UPM21_REG UCSR2C
897 #define UMSEL20_REG UCSR2C
898 #define UMSEL21_REG UCSR2C
901 #define TCNT0_0_REG TCNT0
902 #define TCNT0_1_REG TCNT0
903 #define TCNT0_2_REG TCNT0
904 #define TCNT0_3_REG TCNT0
905 #define TCNT0_4_REG TCNT0
906 #define TCNT0_5_REG TCNT0
907 #define TCNT0_6_REG TCNT0
908 #define TCNT0_7_REG TCNT0
911 #define TOV4_REG TIFR4
912 #define OCF4A_REG TIFR4
913 #define OCF4B_REG TIFR4
914 #define OCF4C_REG TIFR4
915 #define ICF4_REG TIFR4
918 #define TOV5_REG TIFR5
919 #define OCF5A_REG TIFR5
920 #define OCF5B_REG TIFR5
921 #define OCF5C_REG TIFR5
922 #define ICF5_REG TIFR5
925 #define TOV2_REG TIFR2
926 #define OCF2A_REG TIFR2
927 #define OCF2B_REG TIFR2
930 #define TOV3_REG TIFR3
931 #define OCF3A_REG TIFR3
932 #define OCF3B_REG TIFR3
933 #define OCF3C_REG TIFR3
934 #define ICF3_REG TIFR3
937 #define SPR0_REG SPCR
938 #define SPR1_REG SPCR
939 #define CPHA_REG SPCR
940 #define CPOL_REG SPCR
941 #define MSTR_REG SPCR
942 #define DORD_REG SPCR
944 #define SPIE_REG SPCR
947 #define TOV1_REG TIFR1
948 #define OCF1A_REG TIFR1
949 #define OCF1B_REG TIFR1
950 #define OCF1C_REG TIFR1
951 #define ICF1_REG TIFR1
954 #define OCR4AH0_REG OCR4AH
955 #define OCR4AH1_REG OCR4AH
956 #define OCR4AH2_REG OCR4AH
957 #define OCR4AH3_REG OCR4AH
958 #define OCR4AH4_REG OCR4AH
959 #define OCR4AH5_REG OCR4AH
960 #define OCR4AH6_REG OCR4AH
961 #define OCR4AH7_REG OCR4AH
964 #define OCR5CH0_REG OCR5CH
965 #define OCR5CH1_REG OCR5CH
966 #define OCR5CH2_REG OCR5CH
967 #define OCR5CH3_REG OCR5CH
968 #define OCR5CH4_REG OCR5CH
969 #define OCR5CH5_REG OCR5CH
970 #define OCR5CH6_REG OCR5CH
971 #define OCR5CH7_REG OCR5CH
974 #define OCR4AL0_REG OCR4AL
975 #define OCR4AL1_REG OCR4AL
976 #define OCR4AL2_REG OCR4AL
977 #define OCR4AL3_REG OCR4AL
978 #define OCR4AL4_REG OCR4AL
979 #define OCR4AL5_REG OCR4AL
980 #define OCR4AL6_REG OCR4AL
981 #define OCR4AL7_REG OCR4AL
984 #define OCR5CL0_REG OCR5CL
985 #define OCR5CL1_REG OCR5CL
986 #define OCR5CL2_REG OCR5CL
987 #define OCR5CL3_REG OCR5CL
988 #define OCR5CL4_REG OCR5CL
989 #define OCR5CL5_REG OCR5CL
990 #define OCR5CL6_REG OCR5CL
991 #define OCR5CL7_REG OCR5CL
994 #define OCR3CH0_REG OCR3CH
995 #define OCR3CH1_REG OCR3CH
996 #define OCR3CH2_REG OCR3CH
997 #define OCR3CH3_REG OCR3CH
998 #define OCR3CH4_REG OCR3CH
999 #define OCR3CH5_REG OCR3CH
1000 #define OCR3CH6_REG OCR3CH
1001 #define OCR3CH7_REG OCR3CH
1004 #define OCR3CL0_REG OCR3CL
1005 #define OCR3CL1_REG OCR3CL
1006 #define OCR3CL2_REG OCR3CL
1007 #define OCR3CL3_REG OCR3CL
1008 #define OCR3CL4_REG OCR3CL
1009 #define OCR3CL5_REG OCR3CL
1010 #define OCR3CL6_REG OCR3CL
1011 #define OCR3CL7_REG OCR3CL
1014 #define PSRSYNC_REG GTCCR
1015 #define TSM_REG GTCCR
1016 #define PSRASY_REG GTCCR
1019 #define TWBR0_REG TWBR
1020 #define TWBR1_REG TWBR
1021 #define TWBR2_REG TWBR
1022 #define TWBR3_REG TWBR
1023 #define TWBR4_REG TWBR
1024 #define TWBR5_REG TWBR
1025 #define TWBR6_REG TWBR
1026 #define TWBR7_REG TWBR
1031 #define SP10_REG SPH
1032 #define SP11_REG SPH
1033 #define SP12_REG SPH
1034 #define SP13_REG SPH
1035 #define SP14_REG SPH
1036 #define SP15_REG SPH
1039 #define FOC3C_REG TCCR3C
1040 #define FOC3B_REG TCCR3C
1041 #define FOC3A_REG TCCR3C
1044 #define CS30_REG TCCR3B
1045 #define CS31_REG TCCR3B
1046 #define CS32_REG TCCR3B
1047 #define WGM32_REG TCCR3B
1048 #define WGM33_REG TCCR3B
1049 #define ICES3_REG TCCR3B
1050 #define ICNC3_REG TCCR3B
1053 #define WGM30_REG TCCR3A
1054 #define WGM31_REG TCCR3A
1055 #define COM3C0_REG TCCR3A
1056 #define COM3C1_REG TCCR3A
1057 #define COM3B0_REG TCCR3A
1058 #define COM3B1_REG TCCR3A
1059 #define COM3A0_REG TCCR3A
1060 #define COM3A1_REG TCCR3A
1063 #define PORTF0_REG PORTF
1064 #define PORTF1_REG PORTF
1065 #define PORTF2_REG PORTF
1066 #define PORTF3_REG PORTF
1067 #define PORTF4_REG PORTF
1068 #define PORTF5_REG PORTF
1069 #define PORTF6_REG PORTF
1070 #define PORTF7_REG PORTF
1073 #define PCINT8_REG PCMSK1
1074 #define PCINT9_REG PCMSK1
1075 #define PCINT10_REG PCMSK1
1076 #define PCINT11_REG PCMSK1
1077 #define PCINT12_REG PCMSK1
1078 #define PCINT13_REG PCMSK1
1079 #define PCINT14_REG PCMSK1
1080 #define PCINT15_REG PCMSK1
1083 #define OCR1BL0_REG OCR1BL
1084 #define OCR1BL1_REG OCR1BL
1085 #define OCR1BL2_REG OCR1BL
1086 #define OCR1BL3_REG OCR1BL
1087 #define OCR1BL4_REG OCR1BL
1088 #define OCR1BL5_REG OCR1BL
1089 #define OCR1BL6_REG OCR1BL
1090 #define OCR1BL7_REG OCR1BL
1093 #define TCNT3H0_REG TCNT3H
1094 #define TCNT3H1_REG TCNT3H
1095 #define TCNT3H2_REG TCNT3H
1096 #define TCNT3H3_REG TCNT3H
1097 #define TCNT3H4_REG TCNT3H
1098 #define TCNT3H5_REG TCNT3H
1099 #define TCNT3H6_REG TCNT3H
1100 #define TCNT3H7_REG TCNT3H
1103 #define OCR1BH0_REG OCR1BH
1104 #define OCR1BH1_REG OCR1BH
1105 #define OCR1BH2_REG OCR1BH
1106 #define OCR1BH3_REG OCR1BH
1107 #define OCR1BH4_REG OCR1BH
1108 #define OCR1BH5_REG OCR1BH
1109 #define OCR1BH6_REG OCR1BH
1110 #define OCR1BH7_REG OCR1BH
1113 #define TCNT3L0_REG TCNT3L
1114 #define TCNT3L1_REG TCNT3L
1115 #define TCNT3L2_REG TCNT3L
1116 #define TCNT3L3_REG TCNT3L
1117 #define TCNT3L4_REG TCNT3L
1118 #define TCNT3L5_REG TCNT3L
1119 #define TCNT3L6_REG TCNT3L
1120 #define TCNT3L7_REG TCNT3L
1123 #define ICR5L0_REG ICR5L
1124 #define ICR5L1_REG ICR5L
1125 #define ICR5L2_REG ICR5L
1126 #define ICR5L3_REG ICR5L
1127 #define ICR5L4_REG ICR5L
1128 #define ICR5L5_REG ICR5L
1129 #define ICR5L6_REG ICR5L
1130 #define ICR5L7_REG ICR5L
1143 #define ICR5H0_REG ICR5H
1144 #define ICR5H1_REG ICR5H
1145 #define ICR5H2_REG ICR5H
1146 #define ICR5H3_REG ICR5H
1147 #define ICR5H4_REG ICR5H
1148 #define ICR5H5_REG ICR5H
1149 #define ICR5H6_REG ICR5H
1150 #define ICR5H7_REG ICR5H
1153 #define JTRF_REG MCUSR
1154 #define PORF_REG MCUSR
1155 #define EXTRF_REG MCUSR
1156 #define BORF_REG MCUSR
1157 #define WDRF_REG MCUSR
1160 #define PINK0_REG PINK
1161 #define PINK1_REG PINK
1162 #define PINK2_REG PINK
1163 #define PINK3_REG PINK
1164 #define PINK4_REG PINK
1165 #define PINK5_REG PINK
1166 #define PINK6_REG PINK
1167 #define PINK7_REG PINK
1170 #define PINJ0_REG PINJ
1171 #define PINJ1_REG PINJ
1172 #define PINJ2_REG PINJ
1173 #define PINJ3_REG PINJ
1174 #define PINJ4_REG PINJ
1175 #define PINJ5_REG PINJ
1176 #define PINJ6_REG PINJ
1177 #define PINJ7_REG PINJ
1181 #define SM0_REG SMCR
1182 #define SM1_REG SMCR
1183 #define SM2_REG SMCR
1186 #define TWIE_REG TWCR
1187 #define TWEN_REG TWCR
1188 #define TWWC_REG TWCR
1189 #define TWSTO_REG TWCR
1190 #define TWSTA_REG TWCR
1191 #define TWEA_REG TWCR
1192 #define TWINT_REG TWCR
1195 #define PINH0_REG PINH
1196 #define PINH1_REG PINH
1197 #define PINH2_REG PINH
1198 #define PINH3_REG PINH
1199 #define PINH4_REG PINH
1200 #define PINH5_REG PINH
1201 #define PINH6_REG PINH
1202 #define PINH7_REG PINH
1205 #define PCIF0_REG PCIFR
1206 #define PCIF1_REG PCIFR
1207 #define PCIF2_REG PCIFR
1210 #define WGM20_REG TCCR2A
1211 #define WGM21_REG TCCR2A
1212 #define COM2B0_REG TCCR2A
1213 #define COM2B1_REG TCCR2A
1214 #define COM2A0_REG TCCR2A
1215 #define COM2A1_REG TCCR2A
1218 #define CS20_REG TCCR2B
1219 #define CS21_REG TCCR2B
1220 #define CS22_REG TCCR2B
1221 #define WGM22_REG TCCR2B
1222 #define FOC2B_REG TCCR2B
1223 #define FOC2A_REG TCCR2B
1226 /* #define UBRR8_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
1227 /* #define UBRR9_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
1228 /* #define UBRR10_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
1229 /* #define UBRR11_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
1232 #define PING0_REG PING
1233 #define PING1_REG PING
1234 #define PING2_REG PING
1235 #define PING3_REG PING
1236 #define PING4_REG PING
1237 #define PING5_REG PING
1240 /* #define UBRR0_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1241 /* #define UBRR1_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1242 /* #define UBRR2_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1243 /* #define UBRR3_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1244 /* #define UBRR4_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1245 /* #define UBRR5_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1246 /* #define UBRR6_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1247 /* #define UBRR7_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
1250 #define TWPS0_REG TWSR
1251 #define TWPS1_REG TWSR
1252 #define TWS3_REG TWSR
1253 #define TWS4_REG TWSR
1254 #define TWS5_REG TWSR
1255 #define TWS6_REG TWSR
1256 #define TWS7_REG TWSR
1259 #define ICR4H0_REG ICR4H
1260 #define ICR4H1_REG ICR4H
1261 #define ICR4H2_REG ICR4H
1262 #define ICR4H3_REG ICR4H
1263 #define ICR4H4_REG ICR4H
1264 #define ICR4H5_REG ICR4H
1265 #define ICR4H6_REG ICR4H
1266 #define ICR4H7_REG ICR4H
1269 #define EEAR0_REG EEARL
1270 #define EEAR1_REG EEARL
1271 #define EEAR2_REG EEARL
1272 #define EEAR3_REG EEARL
1273 #define EEAR4_REG EEARL
1274 #define EEAR5_REG EEARL
1275 #define EEAR6_REG EEARL
1276 #define EEAR7_REG EEARL
1279 #define PCINT16_REG PCMSK2
1280 #define PCINT17_REG PCMSK2
1281 #define PCINT18_REG PCMSK2
1282 #define PCINT19_REG PCMSK2
1283 #define PCINT20_REG PCMSK2
1284 #define PCINT21_REG PCMSK2
1285 #define PCINT22_REG PCMSK2
1286 #define PCINT23_REG PCMSK2
1289 #define ICR4L0_REG ICR4L
1290 #define ICR4L1_REG ICR4L
1291 #define ICR4L2_REG ICR4L
1292 #define ICR4L3_REG ICR4L
1293 #define ICR4L4_REG ICR4L
1294 #define ICR4L5_REG ICR4L
1295 #define ICR4L6_REG ICR4L
1296 #define ICR4L7_REG ICR4L
1299 #define JTD_REG MCUCR
1300 #define IVCE_REG MCUCR
1301 #define IVSEL_REG MCUCR
1302 #define PUD_REG MCUCR
1305 #define PINC0_REG PINC
1306 #define PINC1_REG PINC
1307 #define PINC2_REG PINC
1308 #define PINC3_REG PINC
1309 #define PINC4_REG PINC
1310 #define PINC5_REG PINC
1311 #define PINC6_REG PINC
1312 #define PINC7_REG PINC
1315 #define OCR1CL0_REG OCR1CL
1316 #define OCR1CL1_REG OCR1CL
1317 #define OCR1CL2_REG OCR1CL
1318 #define OCR1CL3_REG OCR1CL
1319 #define OCR1CL4_REG OCR1CL
1320 #define OCR1CL5_REG OCR1CL
1321 #define OCR1CL6_REG OCR1CL
1322 #define OCR1CL7_REG OCR1CL
1325 #define TCNT4L0_REG TCNT4L
1326 #define TCNT4L1_REG TCNT4L
1327 #define TCNT4L2_REG TCNT4L
1328 #define TCNT4L3_REG TCNT4L
1329 #define TCNT4L4_REG TCNT4L
1330 #define TCNT4L5_REG TCNT4L
1331 #define TCNT4L6_REG TCNT4L
1332 #define TCNT4L7_REG TCNT4L
1335 #define OCR1CH0_REG OCR1CH
1336 #define OCR1CH1_REG OCR1CH
1337 #define OCR1CH2_REG OCR1CH
1338 #define OCR1CH3_REG OCR1CH
1339 #define OCR1CH4_REG OCR1CH
1340 #define OCR1CH5_REG OCR1CH
1341 #define OCR1CH6_REG OCR1CH
1342 #define OCR1CH7_REG OCR1CH
1345 #define TCNT4H0_REG TCNT4H
1346 #define TCNT4H1_REG TCNT4H
1347 #define TCNT4H2_REG TCNT4H
1348 #define TCNT4H3_REG TCNT4H
1349 #define TCNT4H4_REG TCNT4H
1350 #define TCNT4H5_REG TCNT4H
1351 #define TCNT4H6_REG TCNT4H
1352 #define TCNT4H7_REG TCNT4H
1355 #define OCDR0_REG OCDR
1356 #define OCDR1_REG OCDR
1357 #define OCDR2_REG OCDR
1358 #define OCDR3_REG OCDR
1359 #define OCDR4_REG OCDR
1360 #define OCDR5_REG OCDR
1361 #define OCDR6_REG OCDR
1362 #define OCDR7_REG OCDR
1365 #define PINA0_REG PINA
1366 #define PINA1_REG PINA
1367 #define PINA2_REG PINA
1368 #define PINA3_REG PINA
1369 #define PINA4_REG PINA
1370 #define PINA5_REG PINA
1371 #define PINA6_REG PINA
1372 #define PINA7_REG PINA
1375 #define EERE_REG EECR
1376 #define EEPE_REG EECR
1377 #define EEMPE_REG EECR
1378 #define EERIE_REG EECR
1379 #define EEPM0_REG EECR
1380 #define EEPM1_REG EECR
1383 #define TXB81_REG UCSR1B
1384 #define RXB81_REG UCSR1B
1385 #define UCSZ12_REG UCSR1B
1386 #define TXEN1_REG UCSR1B
1387 #define RXEN1_REG UCSR1B
1388 #define UDRIE1_REG UCSR1B
1389 #define TXCIE1_REG UCSR1B
1390 #define RXCIE1_REG UCSR1B
1393 #define UCPOL1_REG UCSR1C
1394 #define UCSZ10_REG UCSR1C
1395 #define UCSZ11_REG UCSR1C
1396 #define USBS1_REG UCSR1C
1397 #define UPM10_REG UCSR1C
1398 #define UPM11_REG UCSR1C
1399 #define UMSEL10_REG UCSR1C
1400 #define UMSEL11_REG UCSR1C
1403 #define MPCM1_REG UCSR1A
1404 #define U2X1_REG UCSR1A
1405 #define UPE1_REG UCSR1A
1406 #define DOR1_REG UCSR1A
1407 #define FE1_REG UCSR1A
1408 #define UDRE1_REG UCSR1A
1409 #define TXC1_REG UCSR1A
1410 #define RXC1_REG UCSR1A
1413 #define DDB0_REG DDRB
1414 #define DDB1_REG DDRB
1415 #define DDB2_REG DDRB
1416 #define DDB3_REG DDRB
1417 #define DDB4_REG DDRB
1418 #define DDB5_REG DDRB
1419 #define DDB6_REG DDRB
1420 #define DDB7_REG DDRB
1423 #define EIND0_REG EIND
1426 #define TWD0_REG TWDR
1427 #define TWD1_REG TWDR
1428 #define TWD2_REG TWDR
1429 #define TWD3_REG TWDR
1430 #define TWD4_REG TWDR
1431 #define TWD5_REG TWDR
1432 #define TWD6_REG TWDR
1433 #define TWD7_REG TWDR
1436 #define WGM50_REG TCCR5A
1437 #define WGM51_REG TCCR5A
1438 #define COM5C0_REG TCCR5A
1439 #define COM5C1_REG TCCR5A
1440 #define COM5B0_REG TCCR5A
1441 #define COM5B1_REG TCCR5A
1442 #define COM5A0_REG TCCR5A
1443 #define COM5A1_REG TCCR5A
1446 #define OCR1AH0_REG OCR1AH
1447 #define OCR1AH1_REG OCR1AH
1448 #define OCR1AH2_REG OCR1AH
1449 #define OCR1AH3_REG OCR1AH
1450 #define OCR1AH4_REG OCR1AH
1451 #define OCR1AH5_REG OCR1AH
1452 #define OCR1AH6_REG OCR1AH
1453 #define OCR1AH7_REG OCR1AH
1456 #define FOC5C_REG TCCR5C
1457 #define FOC5B_REG TCCR5C
1458 #define FOC5A_REG TCCR5C
1461 #define CS50_REG TCCR5B
1462 #define CS51_REG TCCR5B
1463 #define CS52_REG TCCR5B
1464 #define WGM52_REG TCCR5B
1465 #define WGM53_REG TCCR5B
1466 #define ICES5_REG TCCR5B
1467 #define ICNC5_REG TCCR5B
1470 #define ADPS0_REG ADCSRA
1471 #define ADPS1_REG ADCSRA
1472 #define ADPS2_REG ADCSRA
1473 #define ADIE_REG ADCSRA
1474 #define ADIF_REG ADCSRA
1475 #define ADATE_REG ADCSRA
1476 #define ADSC_REG ADCSRA
1477 #define ADEN_REG ADCSRA
1480 #define ACME_REG ADCSRB
1481 #define ADTS0_REG ADCSRB
1482 #define ADTS1_REG ADCSRB
1483 #define ADTS2_REG ADCSRB
1484 #define MUX5_REG ADCSRB
1487 #define OCR5AL0_REG OCR5AL
1488 #define OCR5AL1_REG OCR5AL
1489 #define OCR5AL2_REG OCR5AL
1490 #define OCR5AL3_REG OCR5AL
1491 #define OCR5AL4_REG OCR5AL
1492 #define OCR5AL5_REG OCR5AL
1493 #define OCR5AL6_REG OCR5AL
1494 #define OCR5AL7_REG OCR5AL
1497 #define WGM10_REG TCCR1A
1498 #define WGM11_REG TCCR1A
1499 #define COM1C0_REG TCCR1A
1500 #define COM1C1_REG TCCR1A
1501 #define COM1B0_REG TCCR1A
1502 #define COM1B1_REG TCCR1A
1503 #define COM1A0_REG TCCR1A
1504 #define COM1A1_REG TCCR1A
1507 #define OCR4CH0_REG OCR4CH
1508 #define OCR4CH1_REG OCR4CH
1509 #define OCR4CH2_REG OCR4CH
1510 #define OCR4CH3_REG OCR4CH
1511 #define OCR4CH4_REG OCR4CH
1512 #define OCR4CH5_REG OCR4CH
1513 #define OCR4CH6_REG OCR4CH
1514 #define OCR4CH7_REG OCR4CH
1517 #define OCR5AH0_REG OCR5AH
1518 #define OCR5AH1_REG OCR5AH
1519 #define OCR5AH2_REG OCR5AH
1520 #define OCR5AH3_REG OCR5AH
1521 #define OCR5AH4_REG OCR5AH
1522 #define OCR5AH5_REG OCR5AH
1523 #define OCR5AH6_REG OCR5AH
1524 #define OCR5AH7_REG OCR5AH
1527 #define OCR4CL0_REG OCR4CL
1528 #define OCR4CL1_REG OCR4CL
1529 #define OCR4CL2_REG OCR4CL
1530 #define OCR4CL3_REG OCR4CL
1531 #define OCR4CL4_REG OCR4CL
1532 #define OCR4CL5_REG OCR4CL
1533 #define OCR4CL6_REG OCR4CL
1534 #define OCR4CL7_REG OCR4CL
1537 #define TCNT1L0_REG TCNT1L
1538 #define TCNT1L1_REG TCNT1L
1539 #define TCNT1L2_REG TCNT1L
1540 #define TCNT1L3_REG TCNT1L
1541 #define TCNT1L4_REG TCNT1L
1542 #define TCNT1L5_REG TCNT1L
1543 #define TCNT1L6_REG TCNT1L
1544 #define TCNT1L7_REG TCNT1L
1547 #define FOC1C_REG TCCR1C
1548 #define FOC1B_REG TCCR1C
1549 #define FOC1A_REG TCCR1C
1552 #define ICR3H0_REG ICR3H
1553 #define ICR3H1_REG ICR3H
1554 #define ICR3H2_REG ICR3H
1555 #define ICR3H3_REG ICR3H
1556 #define ICR3H4_REG ICR3H
1557 #define ICR3H5_REG ICR3H
1558 #define ICR3H6_REG ICR3H
1559 #define ICR3H7_REG ICR3H
1562 #define DDE0_REG DDRE
1563 #define DDE1_REG DDRE
1564 #define DDE2_REG DDRE
1565 #define DDE3_REG DDRE
1566 #define DDE4_REG DDRE
1567 #define DDE5_REG DDRE
1568 #define DDE6_REG DDRE
1569 #define DDE7_REG DDRE
1572 #define PORTD0_REG PORTD
1573 #define PORTD1_REG PORTD
1574 #define PORTD2_REG PORTD
1575 #define PORTD3_REG PORTD
1576 #define PORTD4_REG PORTD
1577 #define PORTD5_REG PORTD
1578 #define PORTD6_REG PORTD
1579 #define PORTD7_REG PORTD
1582 #define ICR3L0_REG ICR3L
1583 #define ICR3L1_REG ICR3L
1584 #define ICR3L2_REG ICR3L
1585 #define ICR3L3_REG ICR3L
1586 #define ICR3L4_REG ICR3L
1587 #define ICR3L5_REG ICR3L
1588 #define ICR3L6_REG ICR3L
1589 #define ICR3L7_REG ICR3L
1592 #define PORTE0_REG PORTE
1593 #define PORTE1_REG PORTE
1594 #define PORTE2_REG PORTE
1595 #define PORTE3_REG PORTE
1596 #define PORTE4_REG PORTE
1597 #define PORTE5_REG PORTE
1598 #define PORTE6_REG PORTE
1599 #define PORTE7_REG PORTE
1602 #define SPMEN_REG SPMCSR
1603 #define PGERS_REG SPMCSR
1604 #define PGWRT_REG SPMCSR
1605 #define BLBSET_REG SPMCSR
1606 #define RWWSRE_REG SPMCSR
1607 #define SIGRD_REG SPMCSR
1608 #define RWWSB_REG SPMCSR
1609 #define SPMIE_REG SPMCSR
1612 #define PORTB0_REG PORTB
1613 #define PORTB1_REG PORTB
1614 #define PORTB2_REG PORTB
1615 #define PORTB3_REG PORTB
1616 #define PORTB4_REG PORTB
1617 #define PORTB5_REG PORTB
1618 #define PORTB6_REG PORTB
1619 #define PORTB7_REG PORTB
1622 #define ADCL0_REG ADCL
1623 #define ADCL1_REG ADCL
1624 #define ADCL2_REG ADCL
1625 #define ADCL3_REG ADCL
1626 #define ADCL4_REG ADCL
1627 #define ADCL5_REG ADCL
1628 #define ADCL6_REG ADCL
1629 #define ADCL7_REG ADCL
1632 #define ADCH0_REG ADCH
1633 #define ADCH1_REG ADCH
1634 #define ADCH2_REG ADCH
1635 #define ADCH3_REG ADCH
1636 #define ADCH4_REG ADCH
1637 #define ADCH5_REG ADCH
1638 #define ADCH6_REG ADCH
1639 #define ADCH7_REG ADCH
1642 #define OCR5BH0_REG OCR5BH
1643 #define OCR5BH1_REG OCR5BH
1644 #define OCR5BH2_REG OCR5BH
1645 #define OCR5BH3_REG OCR5BH
1646 #define OCR5BH4_REG OCR5BH
1647 #define OCR5BH5_REG OCR5BH
1648 #define OCR5BH6_REG OCR5BH
1649 #define OCR5BH7_REG OCR5BH
1652 #define OCR3BL0_REG OCR3BL
1653 #define OCR3BL1_REG OCR3BL
1654 #define OCR3BL2_REG OCR3BL
1655 #define OCR3BL3_REG OCR3BL
1656 #define OCR3BL4_REG OCR3BL
1657 #define OCR3BL5_REG OCR3BL
1658 #define OCR3BL6_REG OCR3BL
1659 #define OCR3BL7_REG OCR3BL
1662 #define OCR5BL0_REG OCR5BL
1663 #define OCR5BL1_REG OCR5BL
1664 #define OCR5BL2_REG OCR5BL
1665 #define OCR5BL3_REG OCR5BL
1666 #define OCR5BL4_REG OCR5BL
1667 #define OCR5BL5_REG OCR5BL
1668 #define OCR5BL6_REG OCR5BL
1669 #define OCR5BL7_REG OCR5BL
1672 #define OCR3BH0_REG OCR3BH
1673 #define OCR3BH1_REG OCR3BH
1674 #define OCR3BH2_REG OCR3BH
1675 #define OCR3BH3_REG OCR3BH
1676 #define OCR3BH4_REG OCR3BH
1677 #define OCR3BH5_REG OCR3BH
1678 #define OCR3BH6_REG OCR3BH
1679 #define OCR3BH7_REG OCR3BH
1682 #define TOIE2_REG TIMSK2
1683 #define OCIE2A_REG TIMSK2
1684 #define OCIE2B_REG TIMSK2
1687 #define TOIE3_REG TIMSK3
1688 #define OCIE3A_REG TIMSK3
1689 #define OCIE3B_REG TIMSK3
1690 #define OCIE3C_REG TIMSK3
1691 #define ICIE3_REG TIMSK3
1694 #define TOIE0_REG TIMSK0
1695 #define OCIE0A_REG TIMSK0
1696 #define OCIE0B_REG TIMSK0
1699 #define TOIE1_REG TIMSK1
1700 #define OCIE1A_REG TIMSK1
1701 #define OCIE1B_REG TIMSK1
1702 #define OCIE1C_REG TIMSK1
1703 #define ICIE1_REG TIMSK1
1706 #define TOIE4_REG TIMSK4
1707 #define OCIE4A_REG TIMSK4
1708 #define OCIE4B_REG TIMSK4
1709 #define OCIE4C_REG TIMSK4
1710 #define ICIE4_REG TIMSK4
1713 #define TOIE5_REG TIMSK5
1714 #define OCIE5A_REG TIMSK5
1715 #define OCIE5B_REG TIMSK5
1716 #define OCIE5C_REG TIMSK5
1717 #define ICIE5_REG TIMSK5
1720 #define CS40_REG TCCR4B
1721 #define CS41_REG TCCR4B
1722 #define CS42_REG TCCR4B
1723 #define WGM42_REG TCCR4B
1724 #define WGM43_REG TCCR4B
1725 #define ICES4_REG TCCR4B
1726 #define ICNC4_REG TCCR4B
1729 #define FOC4C_REG TCCR4C
1730 #define FOC4B_REG TCCR4C
1731 #define FOC4A_REG TCCR4C
1734 #define WGM40_REG TCCR4A
1735 #define WGM41_REG TCCR4A
1736 #define COM4C0_REG TCCR4A
1737 #define COM4C1_REG TCCR4A
1738 #define COM4B0_REG TCCR4A
1739 #define COM4B1_REG TCCR4A
1740 #define COM4A0_REG TCCR4A
1741 #define COM4A1_REG TCCR4A
1744 #define PCINT0_REG PCMSK0
1745 #define PCINT1_REG PCMSK0
1746 #define PCINT2_REG PCMSK0
1747 #define PCINT3_REG PCMSK0
1748 #define PCINT4_REG PCMSK0
1749 #define PCINT5_REG PCMSK0
1750 #define PCINT6_REG PCMSK0
1751 #define PCINT7_REG PCMSK0
1754 #define XMM0_REG XMCRB
1755 #define XMM1_REG XMCRB
1756 #define XMM2_REG XMCRB
1757 #define XMBK_REG XMCRB
1760 #define SRW00_REG XMCRA
1761 #define SRW01_REG XMCRA
1762 #define SRW10_REG XMCRA
1763 #define SRW11_REG XMCRA
1764 #define SRL0_REG XMCRA
1765 #define SRL1_REG XMCRA
1766 #define SRL2_REG XMCRA
1767 #define SRE_REG XMCRA
1770 #define PINL0_REG PINL
1771 #define PINL1_REG PINL
1772 #define PINL2_REG PINL
1773 #define PINL3_REG PINL
1774 #define PINL4_REG PINL
1775 #define PINL5_REG PINL
1776 #define PINL6_REG PINL
1777 #define PINL7_REG PINL
1780 #define OCR4BL0_REG OCR4BL
1781 #define OCR4BL1_REG OCR4BL
1782 #define OCR4BL2_REG OCR4BL
1783 #define OCR4BL3_REG OCR4BL
1784 #define OCR4BL4_REG OCR4BL
1785 #define OCR4BL5_REG OCR4BL
1786 #define OCR4BL6_REG OCR4BL
1787 #define OCR4BL7_REG OCR4BL
1790 #define PINB0_REG PINB
1791 #define PINB1_REG PINB
1792 #define PINB2_REG PINB
1793 #define PINB3_REG PINB
1794 #define PINB4_REG PINB
1795 #define PINB5_REG PINB
1796 #define PINB6_REG PINB
1797 #define PINB7_REG PINB
1800 #define INTF0_REG EIFR
1801 #define INTF1_REG EIFR
1802 #define INTF2_REG EIFR
1803 #define INTF3_REG EIFR
1804 #define INTF4_REG EIFR
1805 #define INTF5_REG EIFR
1806 #define INTF6_REG EIFR
1807 #define INTF7_REG EIFR
1810 #define OCR4BH0_REG OCR4BH
1811 #define OCR4BH1_REG OCR4BH
1812 #define OCR4BH2_REG OCR4BH
1813 #define OCR4BH3_REG OCR4BH
1814 #define OCR4BH4_REG OCR4BH
1815 #define OCR4BH5_REG OCR4BH
1816 #define OCR4BH6_REG OCR4BH
1817 #define OCR4BH7_REG OCR4BH
1820 #define PINF0_REG PINF
1821 #define PINF1_REG PINF
1822 #define PINF2_REG PINF
1823 #define PINF3_REG PINF
1824 #define PINF4_REG PINF
1825 #define PINF5_REG PINF
1826 #define PINF6_REG PINF
1827 #define PINF7_REG PINF
1830 #define PINE0_REG PINE
1831 #define PINE1_REG PINE
1832 #define PINE2_REG PINE
1833 #define PINE3_REG PINE
1834 #define PINE4_REG PINE
1835 #define PINE5_REG PINE
1836 #define PINE6_REG PINE
1837 #define PINE7_REG PINE
1840 #define PIND0_REG PIND
1841 #define PIND1_REG PIND
1842 #define PIND2_REG PIND
1843 #define PIND3_REG PIND
1844 #define PIND4_REG PIND
1845 #define PIND5_REG PIND
1846 #define PIND6_REG PIND
1847 #define PIND7_REG PIND
1850 #define TWAM0_REG TWAMR
1851 #define TWAM1_REG TWAMR
1852 #define TWAM2_REG TWAMR
1853 #define TWAM3_REG TWAMR
1854 #define TWAM4_REG TWAMR
1855 #define TWAM5_REG TWAMR
1856 #define TWAM6_REG TWAMR
1859 #define PRADC_REG PRR0
1860 #define PRUSART0_REG PRR0
1861 #define PRSPI_REG PRR0
1862 #define PRTIM1_REG PRR0
1863 #define PRTIM0_REG PRR0
1864 #define PRTIM2_REG PRR0
1865 #define PRTWI_REG PRR0
1868 #define OCR1AL0_REG OCR1AL
1869 #define OCR1AL1_REG OCR1AL
1870 #define OCR1AL2_REG OCR1AL
1871 #define OCR1AL3_REG OCR1AL
1872 #define OCR1AL4_REG OCR1AL
1873 #define OCR1AL5_REG OCR1AL
1874 #define OCR1AL6_REG OCR1AL
1875 #define OCR1AL7_REG OCR1AL
1878 #define TOV0_REG TIFR0
1879 #define OCF0A_REG TIFR0
1880 #define OCF0B_REG TIFR0
1883 #define PRUSART1_REG PRR1
1884 #define PRUSART2_REG PRR1
1885 #define PRUSART3_REG PRR1
1886 #define PRTIM3_REG PRR1
1887 #define PRTIM4_REG PRR1
1888 #define PRTIM5_REG PRR1
1891 #define AD0_PORT PORTA
1894 #define AD1_PORT PORTA
1897 #define AD2_PORT PORTA
1900 #define AD3_PORT PORTA
1903 #define AD4_PORT PORTA
1906 #define AD5_PORT PORTA
1909 #define AD6_PORT PORTA
1912 #define AD7_PORT PORTA
1915 #define SS_PORT PORTB
1917 #define PCINT0_PORT PORTB
1918 #define PCINT0_BIT 0
1920 #define SCK_PORT PORTB
1922 #define PCINT1_PORT PORTB
1923 #define PCINT1_BIT 1
1925 #define MOSI_PORT PORTB
1927 #define PCINT2_PORT PORTB
1928 #define PCINT2_BIT 2
1930 #define MISO_PORT PORTB
1932 #define PCINT3_PORT PORTB
1933 #define PCINT3_BIT 3
1935 #define OC2A_PORT PORTB
1937 #define PCINT4_PORT PORTB
1938 #define PCINT4_BIT 4
1940 #define OC1A_PORT PORTB
1942 #define PCINT5_PORT PORTB
1943 #define PCINT5_BIT 5
1945 #define OC1B_PORT PORTB
1947 #define PCINT6_PORT PORTB
1948 #define PCINT6_BIT 6
1950 #define OC0A_PORT PORTB
1952 #define OC1C_PORT PORTB
1954 #define PCINT7_PORT PORTB
1955 #define PCINT7_BIT 7
1957 #define A8_PORT PORTC
1960 #define A9_PORT PORTC
1963 #define A10_PORT PORTC
1966 #define A11_PORT PORTC
1969 #define A12_PORT PORTC
1972 #define A13_PORT PORTC
1975 #define A14_PORT PORTC
1978 #define A15_PORT PORTC
1981 #define SCL_PORT PORTD
1983 #define INT0_PORT PORTD
1986 #define SDA_PORT PORTD
1988 #define INT1_PORT PORTD
1991 #define RXD1_PORT PORTD
1993 #define INT2_PORT PORTD
1996 #define TXD1_PORT PORTD
1998 #define INT3_PORT PORTD
2001 #define ICP1_PORT PORTD
2004 #define XCK1_PORT PORTD
2007 #define T1_PORT PORTD
2010 #define T0_PORT PORTD
2013 #define RXD_PORT PORTE
2015 #define PCINT8_PORT PORTE
2016 #define PCINT8_BIT 0
2018 #define TXD0_PORT PORTE
2021 #define XCK_PORT PORTE
2023 #define AIN0_PORT PORTE
2026 #define OC3A_PORT PORTE
2028 #define AIN1_PORT PORTE
2031 #define OC3B_PORT PORTE
2033 #define INT4_PORT PORTE
2036 #define OC3C_PORT PORTE
2038 #define INT5_PORT PORTE
2041 #define T3_PORT PORTE
2043 #define INT6_PORT PORTE
2046 #define CLKO_PORT PORTE
2048 #define ICP3_PORT PORTE
2050 #define INT7_PORT PORTE
2053 #define ADC0_PORT PORTF
2056 #define ADC1_PORT PORTF
2059 #define ADC2_PORT PORTF
2062 #define ADC3_PORT PORTF
2065 #define ADC4_PORT PORTF
2067 #define TCK_PORT PORTF
2070 #define ADC5_PORT PORTF
2072 #define TMS_PORT PORTF
2075 #define ADC6_PORT PORTF
2077 #define TDO_PORT PORTF
2080 #define ADC7_PORT PORTF
2082 #define TDI_PORT PORTF
2085 #define WR_PORT PORTG
2088 #define RD_PORT PORTG
2091 #define ALE_PORT PORTG
2094 #define TOSC2_PORT PORTG
2097 #define TOSC1_PORT PORTG
2100 #define OC0B_PORT PORTG
2103 #define RXD2_PORT PORTH
2106 #define TXD2_PORT PORTH
2109 #define XCK2_PORT PORTH
2112 #define OC4A_PORT PORTH
2115 #define OC4B_PORT PORTH
2118 #define OC2B_PORT PORTH
2121 #define T4_PORT PORTH
2124 #define RXD3_PORT PORTJ
2126 #define PCINT9_PORT PORTJ
2127 #define PCINT9_BIT 0
2129 #define TXD3_PORT PORTJ
2131 #define PCINT10_PORT PORTJ
2132 #define PCINT10_BIT 1
2134 #define XCK3_PORT PORTJ
2136 #define PCINT11_PORT PORTJ
2137 #define PCINT11_BIT 2
2139 #define PCINT12_PORT PORTJ
2140 #define PCINT12_BIT 3
2142 #define PCINT13_PORT PORTJ
2143 #define PCINT13_BIT 4
2145 #define PCINT14_PORT PORTJ
2146 #define PCINT14_BIT 5
2148 #define PCINT15_PORT PORTJ
2149 #define PCINT15_BIT 6
2151 #define ADC8_PORT PORTK
2153 #define PCINT16_PORT PORTK
2154 #define PCINT16_BIT 0
2156 #define ADC9_PORT PORTK
2158 #define PCINT17_PORT PORTK
2159 #define PCINT17_BIT 1
2161 #define ADC10_PORT PORTK
2163 #define PCINT18_PORT PORTK
2164 #define PCINT18_BIT 2
2166 #define ADC11_PORT PORTK
2168 #define PCINT19_PORT PORTK
2169 #define PCINT19_BIT 3
2171 #define ADC12_PORT PORTK
2173 #define PCINT20_PORT PORTK
2174 #define PCINT20_BIT 4
2176 #define ADC13_PORT PORTK
2178 #define PCINT21_PORT PORTK
2179 #define PCINT21_BIT 5
2181 #define ADC14_PORT PORTK
2183 #define PCINT22_PORT PORTK
2184 #define PCINT22_BIT 6
2186 #define ADC15_PORT PORTK
2188 #define PCINT23_PORT PORTK
2189 #define PCINT23_BIT 7
2191 #define ICP4_PORT PORTL
2194 #define ICP5_PORT PORTL
2197 #define T5_PORT PORTL
2200 #define OC5A_PORT PORTL
2203 #define OC5B_PORT PORTL
2206 #define OC5C_PORT PORTL