2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER0A_AVAILABLE
88 #define TIMER0B_AVAILABLE
89 #define TIMER1_AVAILABLE
90 #define TIMER1A_AVAILABLE
91 #define TIMER1B_AVAILABLE
92 #define TIMER2_AVAILABLE
93 #define TIMER2A_AVAILABLE
94 #define TIMER2B_AVAILABLE
96 /* overflow interrupt number */
97 #define SIG_OVERFLOW0_NUM 0
98 #define SIG_OVERFLOW1_NUM 1
99 #define SIG_OVERFLOW2_NUM 2
100 #define SIG_OVERFLOW_TOTAL_NUM 3
102 /* output compare interrupt number */
103 #define SIG_OUTPUT_COMPARE0A_NUM 0
104 #define SIG_OUTPUT_COMPARE0B_NUM 1
105 #define SIG_OUTPUT_COMPARE1A_NUM 2
106 #define SIG_OUTPUT_COMPARE1B_NUM 3
107 #define SIG_OUTPUT_COMPARE2A_NUM 4
108 #define SIG_OUTPUT_COMPARE2B_NUM 5
109 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
118 #define PWM_TOTAL_NUM 6
120 /* input capture interrupt number */
121 #define SIG_INPUT_CAPTURE1_NUM 0
122 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
126 #define MUX0_REG ADMUX
127 #define MUX1_REG ADMUX
128 #define MUX2_REG ADMUX
129 #define MUX3_REG ADMUX
130 #define MUX4_REG ADMUX
131 #define ADLAR_REG ADMUX
132 #define REFS0_REG ADMUX
133 #define REFS1_REG ADMUX
136 #define WDP0_REG WDTCSR
137 #define WDP1_REG WDTCSR
138 #define WDP2_REG WDTCSR
139 #define WDE_REG WDTCSR
140 #define WDCE_REG WDTCSR
141 #define WDP3_REG WDTCSR
142 #define WDIE_REG WDTCSR
143 #define WDIF_REG WDTCSR
146 #define EEDR0_REG EEDR
147 #define EEDR1_REG EEDR
148 #define EEDR2_REG EEDR
149 #define EEDR3_REG EEDR
150 #define EEDR4_REG EEDR
151 #define EEDR5_REG EEDR
152 #define EEDR6_REG EEDR
153 #define EEDR7_REG EEDR
156 #define ACIS0_REG ACSR
157 #define ACIS1_REG ACSR
158 #define ACIC_REG ACSR
159 #define ACIE_REG ACSR
162 #define ACBG_REG ACSR
166 #define SPR00_REG SPCR0
167 #define SPR10_REG SPCR0
168 #define CPHA0_REG SPCR0
169 #define CPOL0_REG SPCR0
170 #define MSTR0_REG SPCR0
171 #define DORD0_REG SPCR0
172 #define SPE0_REG SPCR0
173 #define SPIE0_REG SPCR0
176 #define RAMPZ0_REG RAMPZ
179 #define OCR2B_0_REG OCR2B
180 #define OCR2B_1_REG OCR2B
181 #define OCR2B_2_REG OCR2B
182 #define OCR2B_3_REG OCR2B
183 #define OCR2B_4_REG OCR2B
184 #define OCR2B_5_REG OCR2B
185 #define OCR2B_6_REG OCR2B
186 #define OCR2B_7_REG OCR2B
189 #define OCR2A_0_REG OCR2A
190 #define OCR2A_1_REG OCR2A
191 #define OCR2A_2_REG OCR2A
192 #define OCR2A_3_REG OCR2A
193 #define OCR2A_4_REG OCR2A
194 #define OCR2A_5_REG OCR2A
195 #define OCR2A_6_REG OCR2A
196 #define OCR2A_7_REG OCR2A
206 #define ICR1L0_REG ICR1L
207 #define ICR1L1_REG ICR1L
208 #define ICR1L2_REG ICR1L
209 #define ICR1L3_REG ICR1L
210 #define ICR1L4_REG ICR1L
211 #define ICR1L5_REG ICR1L
212 #define ICR1L6_REG ICR1L
213 #define ICR1L7_REG ICR1L
216 #define TWPS0_REG TWSR
217 #define TWPS1_REG TWSR
218 #define TWS3_REG TWSR
219 #define TWS4_REG TWSR
220 #define TWS5_REG TWSR
221 #define TWS6_REG TWSR
222 #define TWS7_REG TWSR
225 #define MPCM0_REG UCSR0A
226 #define U2X0_REG UCSR0A
227 #define UPE0_REG UCSR0A
228 #define DOR0_REG UCSR0A
229 #define FE0_REG UCSR0A
230 #define UDRE0_REG UCSR0A
231 #define TXC0_REG UCSR0A
232 #define RXC0_REG UCSR0A
235 #define UCPOL0_REG UCSR0C
236 #define UCSZ00_REG UCSR0C
237 #define UCSZ01_REG UCSR0C
238 #define USBS0_REG UCSR0C
239 #define UPM00_REG UCSR0C
240 #define UPM01_REG UCSR0C
241 #define UMSEL00_REG UCSR0C
242 #define UMSEL01_REG UCSR0C
245 #define TXB80_REG UCSR0B
246 #define RXB80_REG UCSR0B
247 #define UCSZ02_REG UCSR0B
248 #define TXEN0_REG UCSR0B
249 #define RXEN0_REG UCSR0B
250 #define UDRIE0_REG UCSR0B
251 #define TXCIE0_REG UCSR0B
252 #define RXCIE0_REG UCSR0B
255 #define TCNT1H0_REG TCNT1H
256 #define TCNT1H1_REG TCNT1H
257 #define TCNT1H2_REG TCNT1H
258 #define TCNT1H3_REG TCNT1H
259 #define TCNT1H4_REG TCNT1H
260 #define TCNT1H5_REG TCNT1H
261 #define TCNT1H6_REG TCNT1H
262 #define TCNT1H7_REG TCNT1H
265 #define PORTC0_REG PORTC
266 #define PORTC1_REG PORTC
267 #define PORTC2_REG PORTC
268 #define PORTC3_REG PORTC
269 #define PORTC4_REG PORTC
270 #define PORTC5_REG PORTC
271 #define PORTC6_REG PORTC
272 #define PORTC7_REG PORTC
275 #define PORTA0_REG PORTA
276 #define PORTA1_REG PORTA
277 #define PORTA2_REG PORTA
278 #define PORTA3_REG PORTA
279 #define PORTA4_REG PORTA
280 #define PORTA5_REG PORTA
281 #define PORTA6_REG PORTA
282 #define PORTA7_REG PORTA
285 #define UDR1_0_REG UDR1
286 #define UDR1_1_REG UDR1
287 #define UDR1_2_REG UDR1
288 #define UDR1_3_REG UDR1
289 #define UDR1_4_REG UDR1
290 #define UDR1_5_REG UDR1
291 #define UDR1_6_REG UDR1
292 #define UDR1_7_REG UDR1
295 #define UDR0_0_REG UDR0
296 #define UDR0_1_REG UDR0
297 #define UDR0_2_REG UDR0
298 #define UDR0_3_REG UDR0
299 #define UDR0_4_REG UDR0
300 #define UDR0_5_REG UDR0
301 #define UDR0_6_REG UDR0
302 #define UDR0_7_REG UDR0
305 #define ISC00_REG EICRA
306 #define ISC01_REG EICRA
307 #define ISC10_REG EICRA
308 #define ISC11_REG EICRA
309 #define ISC20_REG EICRA
310 #define ISC21_REG EICRA
313 #define ADC0D_REG DIDR0
314 #define ADC1D_REG DIDR0
315 #define ADC2D_REG DIDR0
316 #define ADC3D_REG DIDR0
317 #define ADC4D_REG DIDR0
318 #define ADC5D_REG DIDR0
319 #define ADC6D_REG DIDR0
320 #define ADC7D_REG DIDR0
323 #define AIN0D_REG DIDR1
324 #define AIN1D_REG DIDR1
327 #define SPDRB0_REG SPDR0
328 #define SPDRB1_REG SPDR0
329 #define SPDRB2_REG SPDR0
330 #define SPDRB3_REG SPDR0
331 #define SPDRB4_REG SPDR0
332 #define SPDRB5_REG SPDR0
333 #define SPDRB6_REG SPDR0
334 #define SPDRB7_REG SPDR0
337 #define TCR2BUB_REG ASSR
338 #define TCR2AUB_REG ASSR
339 #define OCR2BUB_REG ASSR
340 #define OCR2AUB_REG ASSR
341 #define TCN2UB_REG ASSR
343 #define EXCLK_REG ASSR
346 #define CLKPS0_REG CLKPR
347 #define CLKPS1_REG CLKPR
348 #define CLKPS2_REG CLKPR
349 #define CLKPS3_REG CLKPR
350 #define CLKPCE_REG CLKPR
363 #define UBRR_0_REG UBRR1L
364 #define UBRR_1_REG UBRR1L
365 #define UBRR_2_REG UBRR1L
366 #define UBRR_3_REG UBRR1L
367 #define UBRR_4_REG UBRR1L
368 #define UBRR_5_REG UBRR1L
369 #define UBRR_6_REG UBRR1L
370 #define UBRR_7_REG UBRR1L
373 #define DDC0_REG DDRC
374 #define DDC1_REG DDRC
375 #define DDC2_REG DDRC
376 #define DDC3_REG DDRC
377 #define DDC4_REG DDRC
378 #define DDC5_REG DDRC
379 #define DDC6_REG DDRC
380 #define DDC7_REG DDRC
383 #define DDA0_REG DDRA
384 #define DDA1_REG DDRA
385 #define DDA2_REG DDRA
386 #define DDA3_REG DDRA
387 #define DDA4_REG DDRA
388 #define DDA5_REG DDRA
389 #define DDA6_REG DDRA
390 #define DDA7_REG DDRA
393 #define UBRR_8_REG UBRR1H
394 #define UBRR_9_REG UBRR1H
395 #define UBRR_10_REG UBRR1H
396 #define UBRR_11_REG UBRR1H
399 #define FOC1B_REG TCCR1C
400 #define FOC1A_REG TCCR1C
403 #define CS10_REG TCCR1B
404 #define CS11_REG TCCR1B
405 #define CS12_REG TCCR1B
406 #define WGM12_REG TCCR1B
407 #define WGM13_REG TCCR1B
408 #define ICES1_REG TCCR1B
409 #define ICNC1_REG TCCR1B
412 #define CAL0_REG OSCCAL
413 #define CAL1_REG OSCCAL
414 #define CAL2_REG OSCCAL
415 #define CAL3_REG OSCCAL
416 #define CAL4_REG OSCCAL
417 #define CAL5_REG OSCCAL
418 #define CAL6_REG OSCCAL
419 #define CAL7_REG OSCCAL
422 #define GPIOR10_REG GPIOR1
423 #define GPIOR11_REG GPIOR1
424 #define GPIOR12_REG GPIOR1
425 #define GPIOR13_REG GPIOR1
426 #define GPIOR14_REG GPIOR1
427 #define GPIOR15_REG GPIOR1
428 #define GPIOR16_REG GPIOR1
429 #define GPIOR17_REG GPIOR1
432 #define GPIOR00_REG GPIOR0
433 #define GPIOR01_REG GPIOR0
434 #define GPIOR02_REG GPIOR0
435 #define GPIOR03_REG GPIOR0
436 #define GPIOR04_REG GPIOR0
437 #define GPIOR05_REG GPIOR0
438 #define GPIOR06_REG GPIOR0
439 #define GPIOR07_REG GPIOR0
442 #define GPIOR20_REG GPIOR2
443 #define GPIOR21_REG GPIOR2
444 #define GPIOR22_REG GPIOR2
445 #define GPIOR23_REG GPIOR2
446 #define GPIOR24_REG GPIOR2
447 #define GPIOR25_REG GPIOR2
448 #define GPIOR26_REG GPIOR2
449 #define GPIOR27_REG GPIOR2
452 #define SPI2X0_REG SPSR0
453 #define WCOL0_REG SPSR0
454 #define SPIF0_REG SPSR0
457 #define PCIE0_REG PCICR
458 #define PCIE1_REG PCICR
459 #define PCIE2_REG PCICR
460 #define PCIE3_REG PCICR
463 #define TCNT2_0_REG TCNT2
464 #define TCNT2_1_REG TCNT2
465 #define TCNT2_2_REG TCNT2
466 #define TCNT2_3_REG TCNT2
467 #define TCNT2_4_REG TCNT2
468 #define TCNT2_5_REG TCNT2
469 #define TCNT2_6_REG TCNT2
470 #define TCNT2_7_REG TCNT2
473 #define TCNT0_0_REG TCNT0
474 #define TCNT0_1_REG TCNT0
475 #define TCNT0_2_REG TCNT0
476 #define TCNT0_3_REG TCNT0
477 #define TCNT0_4_REG TCNT0
478 #define TCNT0_5_REG TCNT0
479 #define TCNT0_6_REG TCNT0
480 #define TCNT0_7_REG TCNT0
483 #define TWGCE_REG TWAR
484 #define TWA0_REG TWAR
485 #define TWA1_REG TWAR
486 #define TWA2_REG TWAR
487 #define TWA3_REG TWAR
488 #define TWA4_REG TWAR
489 #define TWA5_REG TWAR
490 #define TWA6_REG TWAR
493 #define CS00_REG TCCR0B
494 #define CS01_REG TCCR0B
495 #define CS02_REG TCCR0B
496 #define WGM02_REG TCCR0B
497 #define FOC0B_REG TCCR0B
498 #define FOC0A_REG TCCR0B
501 #define WGM00_REG TCCR0A
502 #define WGM01_REG TCCR0A
503 #define COM0B0_REG TCCR0A
504 #define COM0B1_REG TCCR0A
505 #define COM0A0_REG TCCR0A
506 #define COM0A1_REG TCCR0A
509 #define TOV2_REG TIFR2
510 #define OCF2A_REG TIFR2
511 #define OCF2B_REG TIFR2
514 #define TOV0_REG TIFR0
515 #define OCF0A_REG TIFR0
516 #define OCF0B_REG TIFR0
519 #define TOV1_REG TIFR1
520 #define OCF1A_REG TIFR1
521 #define OCF1B_REG TIFR1
522 #define ICF1_REG TIFR1
525 #define PSRSYNC_REG GTCCR
526 #define TSM_REG GTCCR
527 #define PSRASY_REG GTCCR
530 #define TWBR0_REG TWBR
531 #define TWBR1_REG TWBR
532 #define TWBR2_REG TWBR
533 #define TWBR3_REG TWBR
534 #define TWBR4_REG TWBR
535 #define TWBR5_REG TWBR
536 #define TWBR6_REG TWBR
537 #define TWBR7_REG TWBR
540 #define ICR1H0_REG ICR1H
541 #define ICR1H1_REG ICR1H
542 #define ICR1H2_REG ICR1H
543 #define ICR1H3_REG ICR1H
544 #define ICR1H4_REG ICR1H
545 #define ICR1H5_REG ICR1H
546 #define ICR1H6_REG ICR1H
547 #define ICR1H7_REG ICR1H
550 /* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
551 /* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
552 /* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
553 /* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
554 /* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
555 /* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
556 /* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
557 /* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
560 #define PCIF0_REG PCIFR
561 #define PCIF1_REG PCIFR
562 #define PCIF2_REG PCIFR
563 #define PCIF3_REG PCIFR
576 /* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
577 /* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
578 /* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
579 /* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
580 /* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
581 /* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
582 /* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
583 /* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
586 #define EERE_REG EECR
587 #define EEPE_REG EECR
588 #define EEMPE_REG EECR
589 #define EERIE_REG EECR
590 #define EEPM0_REG EECR
591 #define EEPM1_REG EECR
600 #define TWIE_REG TWCR
601 #define TWEN_REG TWCR
602 #define TWWC_REG TWCR
603 #define TWSTO_REG TWCR
604 #define TWSTA_REG TWCR
605 #define TWEA_REG TWCR
606 #define TWINT_REG TWCR
609 #define WGM20_REG TCCR2A
610 #define WGM21_REG TCCR2A
611 #define COM2B0_REG TCCR2A
612 #define COM2B1_REG TCCR2A
613 #define COM2A0_REG TCCR2A
614 #define COM2A1_REG TCCR2A
617 #define CS20_REG TCCR2B
618 #define CS21_REG TCCR2B
619 #define CS22_REG TCCR2B
620 #define WGM22_REG TCCR2B
621 #define FOC2B_REG TCCR2B
622 #define FOC2A_REG TCCR2B
625 #define UBRR8_REG UBRR0H
626 #define UBRR9_REG UBRR0H
627 #define UBRR10_REG UBRR0H
628 #define UBRR11_REG UBRR0H
631 #define UBRR0_REG UBRR0L
632 #define UBRR1_REG UBRR0L
633 #define UBRR2_REG UBRR0L
634 #define UBRR3_REG UBRR0L
635 #define UBRR4_REG UBRR0L
636 #define UBRR5_REG UBRR0L
637 #define UBRR6_REG UBRR0L
638 #define UBRR7_REG UBRR0L
641 #define EEAR8_REG EEARH
642 #define EEAR9_REG EEARH
643 #define EEAR10_REG EEARH
644 #define EEAR11_REG EEARH
647 #define EEAR0_REG EEARL
648 #define EEAR1_REG EEARL
649 #define EEAR2_REG EEARL
650 #define EEAR3_REG EEARL
651 #define EEAR4_REG EEARL
652 #define EEAR5_REG EEARL
653 #define EEAR6_REG EEARL
654 #define EEAR7_REG EEARL
657 #define JTD_REG MCUCR
658 #define IVCE_REG MCUCR
659 #define IVSEL_REG MCUCR
660 #define PUD_REG MCUCR
661 #define BODSE_REG MCUCR
662 #define BODS_REG MCUCR
665 #define JTRF_REG MCUSR
666 #define PORF_REG MCUSR
667 #define EXTRF_REG MCUSR
668 #define BORF_REG MCUSR
669 #define WDRF_REG MCUSR
672 #define OCDR0_REG OCDR
673 #define OCDR1_REG OCDR
674 #define OCDR2_REG OCDR
675 #define OCDR3_REG OCDR
676 #define OCDR4_REG OCDR
677 #define OCDR5_REG OCDR
678 #define OCDR6_REG OCDR
679 #define OCDR7_REG OCDR
682 #define PINA0_REG PINA
683 #define PINA1_REG PINA
684 #define PINA2_REG PINA
685 #define PINA3_REG PINA
686 #define PINA4_REG PINA
687 #define PINA5_REG PINA
688 #define PINA6_REG PINA
689 #define PINA7_REG PINA
692 #define TXB81_REG UCSR1B
693 #define RXB81_REG UCSR1B
694 #define UCSZ12_REG UCSR1B
695 #define TXEN1_REG UCSR1B
696 #define RXEN1_REG UCSR1B
697 #define UDRIE1_REG UCSR1B
698 #define TXCIE1_REG UCSR1B
699 #define RXCIE1_REG UCSR1B
702 #define UCPOL1_REG UCSR1C
703 #define UCSZ10_REG UCSR1C
704 #define UCSZ11_REG UCSR1C
705 #define USBS1_REG UCSR1C
706 #define UPM10_REG UCSR1C
707 #define UPM11_REG UCSR1C
708 #define UMSEL10_REG UCSR1C
709 #define UMSEL11_REG UCSR1C
712 #define MPCM1_REG UCSR1A
713 #define U2X1_REG UCSR1A
714 #define UPE1_REG UCSR1A
715 #define DOR1_REG UCSR1A
716 #define FE1_REG UCSR1A
717 #define UDRE1_REG UCSR1A
718 #define TXC1_REG UCSR1A
719 #define RXC1_REG UCSR1A
722 #define DDB0_REG DDRB
723 #define DDB1_REG DDRB
724 #define DDB2_REG DDRB
725 #define DDB3_REG DDRB
726 #define DDB4_REG DDRB
727 #define DDB5_REG DDRB
728 #define DDB6_REG DDRB
729 #define DDB7_REG DDRB
732 #define TWD0_REG TWDR
733 #define TWD1_REG TWDR
734 #define TWD2_REG TWDR
735 #define TWD3_REG TWDR
736 #define TWD4_REG TWDR
737 #define TWD5_REG TWDR
738 #define TWD6_REG TWDR
739 #define TWD7_REG TWDR
742 #define TWAM0_REG TWAMR
743 #define TWAM1_REG TWAMR
744 #define TWAM2_REG TWAMR
745 #define TWAM3_REG TWAMR
746 #define TWAM4_REG TWAMR
747 #define TWAM5_REG TWAMR
748 #define TWAM6_REG TWAMR
751 #define ADPS0_REG ADCSRA
752 #define ADPS1_REG ADCSRA
753 #define ADPS2_REG ADCSRA
754 #define ADIE_REG ADCSRA
755 #define ADIF_REG ADCSRA
756 #define ADATE_REG ADCSRA
757 #define ADSC_REG ADCSRA
758 #define ADEN_REG ADCSRA
761 #define ACME_REG ADCSRB
762 #define ADTS0_REG ADCSRB
763 #define ADTS1_REG ADCSRB
764 #define ADTS2_REG ADCSRB
767 #define PRADC_REG PRR0
768 #define PRUSART0_REG PRR0
769 #define PRSPI_REG PRR0
770 #define PRTIM1_REG PRR0
771 #define PRUSART1_REG PRR0
772 #define PRTIM0_REG PRR0
773 #define PRTIM2_REG PRR0
774 #define PRTWI_REG PRR0
777 #define WGM10_REG TCCR1A
778 #define WGM11_REG TCCR1A
779 #define COM1B0_REG TCCR1A
780 #define COM1B1_REG TCCR1A
781 #define COM1A0_REG TCCR1A
782 #define COM1A1_REG TCCR1A
785 #define OCROA_0_REG OCR0A
786 #define OCROA_1_REG OCR0A
787 #define OCROA_2_REG OCR0A
788 #define OCROA_3_REG OCR0A
789 #define OCROA_4_REG OCR0A
790 #define OCROA_5_REG OCR0A
791 #define OCROA_6_REG OCR0A
792 #define OCROA_7_REG OCR0A
795 #define OCR0B_0_REG OCR0B
796 #define OCR0B_1_REG OCR0B
797 #define OCR0B_2_REG OCR0B
798 #define OCR0B_3_REG OCR0B
799 #define OCR0B_4_REG OCR0B
800 #define OCR0B_5_REG OCR0B
801 #define OCR0B_6_REG OCR0B
802 #define OCR0B_7_REG OCR0B
805 #define TCNT1L0_REG TCNT1L
806 #define TCNT1L1_REG TCNT1L
807 #define TCNT1L2_REG TCNT1L
808 #define TCNT1L3_REG TCNT1L
809 #define TCNT1L4_REG TCNT1L
810 #define TCNT1L5_REG TCNT1L
811 #define TCNT1L6_REG TCNT1L
812 #define TCNT1L7_REG TCNT1L
815 #define DDD0_REG DDRD
816 #define DDD1_REG DDRD
817 #define DDD2_REG DDRD
818 #define DDD3_REG DDRD
819 #define DDD4_REG DDRD
820 #define DDD5_REG DDRD
821 #define DDD6_REG DDRD
822 #define DDD7_REG DDRD
825 #define PORTD0_REG PORTD
826 #define PORTD1_REG PORTD
827 #define PORTD2_REG PORTD
828 #define PORTD3_REG PORTD
829 #define PORTD4_REG PORTD
830 #define PORTD5_REG PORTD
831 #define PORTD6_REG PORTD
832 #define PORTD7_REG PORTD
835 #define SPMEN_REG SPMCSR
836 #define PGERS_REG SPMCSR
837 #define PGWRT_REG SPMCSR
838 #define BLBSET_REG SPMCSR
839 #define RWWSRE_REG SPMCSR
840 #define SIGRD_REG SPMCSR
841 #define RWWSB_REG SPMCSR
842 #define SPMIE_REG SPMCSR
845 #define PORTB0_REG PORTB
846 #define PORTB1_REG PORTB
847 #define PORTB2_REG PORTB
848 #define PORTB3_REG PORTB
849 #define PORTB4_REG PORTB
850 #define PORTB5_REG PORTB
851 #define PORTB6_REG PORTB
852 #define PORTB7_REG PORTB
855 #define ADCL0_REG ADCL
856 #define ADCL1_REG ADCL
857 #define ADCL2_REG ADCL
858 #define ADCL3_REG ADCL
859 #define ADCL4_REG ADCL
860 #define ADCL5_REG ADCL
861 #define ADCL6_REG ADCL
862 #define ADCL7_REG ADCL
865 #define ADCH0_REG ADCH
866 #define ADCH1_REG ADCH
867 #define ADCH2_REG ADCH
868 #define ADCH3_REG ADCH
869 #define ADCH4_REG ADCH
870 #define ADCH5_REG ADCH
871 #define ADCH6_REG ADCH
872 #define ADCH7_REG ADCH
875 #define TOIE2_REG TIMSK2
876 #define OCIE2A_REG TIMSK2
877 #define OCIE2B_REG TIMSK2
880 #define INT0_REG EIMSK
881 #define INT1_REG EIMSK
882 #define INT2_REG EIMSK
885 #define TOIE0_REG TIMSK0
886 #define OCIE0A_REG TIMSK0
887 #define OCIE0B_REG TIMSK0
890 #define TOIE1_REG TIMSK1
891 #define OCIE1A_REG TIMSK1
892 #define OCIE1B_REG TIMSK1
893 #define ICIE1_REG TIMSK1
896 #define PCINT0_REG PCMSK0
897 #define PCINT1_REG PCMSK0
898 #define PCINT2_REG PCMSK0
899 #define PCINT3_REG PCMSK0
900 #define PCINT4_REG PCMSK0
901 #define PCINT5_REG PCMSK0
902 #define PCINT6_REG PCMSK0
903 #define PCINT7_REG PCMSK0
906 #define PCINT8_REG PCMSK1
907 #define PCINT9_REG PCMSK1
908 #define PCINT10_REG PCMSK1
909 #define PCINT11_REG PCMSK1
910 #define PCINT12_REG PCMSK1
911 #define PCINT13_REG PCMSK1
912 #define PCINT14_REG PCMSK1
913 #define PCINT15_REG PCMSK1
916 #define PCINT16_REG PCMSK2
917 #define PCINT17_REG PCMSK2
918 #define PCINT18_REG PCMSK2
919 #define PCINT19_REG PCMSK2
920 #define PCINT20_REG PCMSK2
921 #define PCINT21_REG PCMSK2
922 #define PCINT22_REG PCMSK2
923 #define PCINT23_REG PCMSK2
926 #define PCINT24_REG PCMSK3
927 #define PCINT25_REG PCMSK3
928 #define PCINT26_REG PCMSK3
929 #define PCINT27_REG PCMSK3
930 #define PCINT28_REG PCMSK3
931 #define PCINT29_REG PCMSK3
932 #define PCINT30_REG PCMSK3
933 #define PCINT31_REG PCMSK3
936 #define PINC0_REG PINC
937 #define PINC1_REG PINC
938 #define PINC2_REG PINC
939 #define PINC3_REG PINC
940 #define PINC4_REG PINC
941 #define PINC5_REG PINC
942 #define PINC6_REG PINC
943 #define PINC7_REG PINC
946 #define PINB0_REG PINB
947 #define PINB1_REG PINB
948 #define PINB2_REG PINB
949 #define PINB3_REG PINB
950 #define PINB4_REG PINB
951 #define PINB5_REG PINB
952 #define PINB6_REG PINB
953 #define PINB7_REG PINB
956 #define INTF0_REG EIFR
957 #define INTF1_REG EIFR
958 #define INTF2_REG EIFR
961 #define PIND0_REG PIND
962 #define PIND1_REG PIND
963 #define PIND2_REG PIND
964 #define PIND3_REG PIND
965 #define PIND4_REG PIND
966 #define PIND5_REG PIND
967 #define PIND6_REG PIND
968 #define PIND7_REG PIND
971 /* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
972 /* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
973 /* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
974 /* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
975 /* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
976 /* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
977 /* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
978 /* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
981 /* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
982 /* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
983 /* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
984 /* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
985 /* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
986 /* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
987 /* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
988 /* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
991 #define ADC0_PORT PORTA
993 #define PCINT0_PORT PORTA
996 #define ADC1_PORT PORTA
998 #define PCINT1_PORT PORTA
1001 #define ADC2_PORT PORTA
1003 #define PCINT2_PORT PORTA
1004 #define PCINT2_BIT 2
1006 #define ADC3_PORT PORTA
1008 #define PCINT3_PORT PORTA
1009 #define PCINT3_BIT 3
1011 #define ADC4_PORT PORTA
1013 #define PCINT4_PORT PORTA
1014 #define PCINT4_BIT 4
1016 #define ADC5_PORT PORTA
1018 #define PCINT5_PORT PORTA
1019 #define PCINT5_BIT 5
1021 #define ADC6_PORT PORTA
1023 #define PCINT6_PORT PORTA
1024 #define PCINT6_BIT 6
1026 #define ADC7_PORT PORTA
1028 #define PCINT7_PORT PORTA
1029 #define PCINT7_BIT 7
1031 #define XCK_PORT PORTB
1033 #define T0_PORT PORTB
1035 #define PCINT9_PORT PORTB
1036 #define PCINT9_BIT 0
1038 #define T1_PORT PORTB
1040 #define CLKO_PORT PORTB
1042 #define PCINT9_PORT PORTB
1043 #define PCINT9_BIT 1
1045 #define AIN0_PORT PORTB
1047 #define INT2_PORT PORTB
1049 #define PCINT10_PORT PORTB
1050 #define PCINT10_BIT 2
1052 #define AIN1_PORT PORTB
1054 #define OC0A_PORT PORTB
1056 #define PCINT11_PORT PORTB
1057 #define PCINT11_BIT 3
1059 #define SS_PORT PORTB
1061 #define OC0B_PORT PORTB
1063 #define PCINT12_PORT PORTB
1064 #define PCINT12_BIT 4
1066 #define MOSI_PORT PORTB
1068 #define PCINT13_PORT PORTB
1069 #define PCINT13_BIT 5
1071 #define MISO_PORT PORTB
1073 #define PCINT14_PORT PORTB
1074 #define PCINT14_BIT 6
1076 #define SCK_PORT PORTB
1078 #define PCINT15_PORT PORTB
1079 #define PCINT15_BIT 7
1081 #define SCL_PORT PORTC
1083 #define PCINT16_PORT PORTC
1084 #define PCINT16_BIT 0
1086 #define SDA_PORT PORTC
1088 #define PCINT17_PORT PORTC
1089 #define PCINT17_BIT 1
1091 #define TCK_PORT PORTC
1093 #define PCINT18_PORT PORTC
1094 #define PCINT18_BIT 2
1096 #define TMS_PORT PORTC
1098 #define PCINT19_PORT PORTC
1099 #define PCINT19_BIT 3
1101 #define TDO_PORT PORTC
1103 #define PCINT20_PORT PORTC
1104 #define PCINT20_BIT 4
1106 #define TDI_PORT PORTC
1108 #define PCINT21_PORT PORTC
1109 #define PCINT21_BIT 5
1111 #define TOSC1_PORT PORTC
1113 #define PCINT22_PORT PORTC
1114 #define PCINT22_BIT 6
1116 #define TOSC2_PORT PORTC
1118 #define PCINT23_PORT PORTC
1119 #define PCINT23_BIT 7
1121 #define RXD_PORT PORTD
1123 #define PCINT24_PORT PORTD
1124 #define PCINT24_BIT 0
1126 #define TXD_PORT PORTD
1128 #define PCINT25_PORT PORTD
1129 #define PCINT25_BIT 1
1131 #define INT0_PORT PORTD
1133 #define PCINT26_PORT PORTD
1134 #define PCINT26_BIT 2
1136 #define INT1_PORT PORTD
1138 #define PCINT27_PORT PORTD
1139 #define PCINT27_BIT 3
1141 #define OC1B_PORT PORTD
1143 #define PCINT28_PORT PORTD
1144 #define PCINT28_BIT 4
1146 #define OC1A_PORT PORTD
1148 #define PCINT29_PORT PORTD
1149 #define PCINT29_BIT 5
1151 #define ICP_PORT PORTD
1153 #define OC2B_PORT PORTD
1155 #define PCINT30_PORT PORTD
1156 #define PCINT30_BIT 6
1158 #define OC2A_PORT PORTD
1160 #define PCINT31_PORT PORTD
1161 #define PCINT31_BIT 7