2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER1_AVAILABLE
88 #define TIMER1A_AVAILABLE
89 #define TIMER1B_AVAILABLE
90 #define TIMER2_AVAILABLE
92 /* overflow interrupt number */
93 #define SIG_OVERFLOW0_NUM 0
94 #define SIG_OVERFLOW1_NUM 1
95 #define SIG_OVERFLOW2_NUM 2
96 #define SIG_OVERFLOW_TOTAL_NUM 3
98 /* output compare interrupt number */
99 #define SIG_OUTPUT_COMPARE0_NUM 0
100 #define SIG_OUTPUT_COMPARE1A_NUM 1
101 #define SIG_OUTPUT_COMPARE1B_NUM 2
102 #define SIG_OUTPUT_COMPARE2_NUM 3
103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
110 #define PWM_TOTAL_NUM 4
112 /* input capture interrupt number */
113 #define SIG_INPUT_CAPTURE1_NUM 0
114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
118 #define WDP0_REG WDTCR
119 #define WDP1_REG WDTCR
120 #define WDP2_REG WDTCR
121 #define WDE_REG WDTCR
122 #define WDCE_REG WDTCR
125 #define MUX0_REG ADMUX
126 #define MUX1_REG ADMUX
127 #define MUX2_REG ADMUX
128 #define MUX3_REG ADMUX
129 #define MUX4_REG ADMUX
130 #define ADLAR_REG ADMUX
131 #define REFS0_REG ADMUX
132 #define REFS1_REG ADMUX
135 #define EEDR0_REG EEDR
136 #define EEDR1_REG EEDR
137 #define EEDR2_REG EEDR
138 #define EEDR3_REG EEDR
139 #define EEDR4_REG EEDR
140 #define EEDR5_REG EEDR
141 #define EEDR6_REG EEDR
142 #define EEDR7_REG EEDR
145 #define OCR2A0_REG OCR2A
146 #define OCR2A1_REG OCR2A
147 #define OCR2A2_REG OCR2A
148 #define OCR2A3_REG OCR2A
149 #define OCR2A4_REG OCR2A
150 #define OCR2A5_REG OCR2A
151 #define OCR2A6_REG OCR2A
152 #define OCR2A7_REG OCR2A
155 #define SPDR0_REG SPDR
156 #define SPDR1_REG SPDR
157 #define SPDR2_REG SPDR
158 #define SPDR3_REG SPDR
159 #define SPDR4_REG SPDR
160 #define SPDR5_REG SPDR
161 #define SPDR6_REG SPDR
162 #define SPDR7_REG SPDR
165 #define SPI2X_REG SPSR
166 #define WCOL_REG SPSR
167 #define SPIF_REG SPSR
180 #define ICR1L0_REG ICR1L
181 #define ICR1L1_REG ICR1L
182 #define ICR1L2_REG ICR1L
183 #define ICR1L3_REG ICR1L
184 #define ICR1L4_REG ICR1L
185 #define ICR1L5_REG ICR1L
186 #define ICR1L6_REG ICR1L
187 #define ICR1L7_REG ICR1L
190 #define PRADC_REG PRR
191 #define PRUSART0_REG PRR
192 #define PRSPI_REG PRR
193 #define PRTIM1_REG PRR
194 #define PRLCD_REG PRR
197 #define PORTJ0_REG PORTJ
198 #define PORTJ1_REG PORTJ
199 #define PORTJ2_REG PORTJ
200 #define PORTJ3_REG PORTJ
201 #define PORTJ4_REG PORTJ
202 #define PORTJ5_REG PORTJ
203 #define PORTJ6_REG PORTJ
206 #define PORTH0_REG PORTH
207 #define PORTH1_REG PORTH
208 #define PORTH2_REG PORTH
209 #define PORTH3_REG PORTH
210 #define PORTH4_REG PORTH
211 #define PORTH5_REG PORTH
212 #define PORTH6_REG PORTH
213 #define PORTH7_REG PORTH
216 #define PORTF0_REG PORTF
217 #define PORTF1_REG PORTF
218 #define PORTF2_REG PORTF
219 #define PORTF3_REG PORTF
220 #define PORTF4_REG PORTF
221 #define PORTF5_REG PORTF
222 #define PORTF6_REG PORTF
223 #define PORTF7_REG PORTF
226 #define PORTG0_REG PORTG
227 #define PORTG1_REG PORTG
228 #define PORTG2_REG PORTG
229 #define PORTG3_REG PORTG
230 #define PORTG4_REG PORTG
233 #define UCPOL0_REG UCSR0C
234 #define UCSZ00_REG UCSR0C
235 #define UCSZ01_REG UCSR0C
236 #define USBS0_REG UCSR0C
237 #define UPM00_REG UCSR0C
238 #define UPM01_REG UCSR0C
239 #define UMSEL0_REG UCSR0C
242 #define PORTE0_REG PORTE
243 #define PORTE1_REG PORTE
244 #define PORTE2_REG PORTE
245 #define PORTE3_REG PORTE
246 #define PORTE4_REG PORTE
247 #define PORTE5_REG PORTE
248 #define PORTE6_REG PORTE
249 #define PORTE7_REG PORTE
252 #define TCNT1H0_REG TCNT1H
253 #define TCNT1H1_REG TCNT1H
254 #define TCNT1H2_REG TCNT1H
255 #define TCNT1H3_REG TCNT1H
256 #define TCNT1H4_REG TCNT1H
257 #define TCNT1H5_REG TCNT1H
258 #define TCNT1H6_REG TCNT1H
259 #define TCNT1H7_REG TCNT1H
262 #define PORTC0_REG PORTC
263 #define PORTC1_REG PORTC
264 #define PORTC2_REG PORTC
265 #define PORTC3_REG PORTC
266 #define PORTC4_REG PORTC
267 #define PORTC5_REG PORTC
268 #define PORTC6_REG PORTC
269 #define PORTC7_REG PORTC
272 #define PORTA0_REG PORTA
273 #define PORTA1_REG PORTA
274 #define PORTA2_REG PORTA
275 #define PORTA3_REG PORTA
276 #define PORTA4_REG PORTA
277 #define PORTA5_REG PORTA
278 #define PORTA6_REG PORTA
279 #define PORTA7_REG PORTA
282 #define UDR00_REG UDR0
283 #define UDR01_REG UDR0
284 #define UDR02_REG UDR0
285 #define UDR03_REG UDR0
286 #define UDR04_REG UDR0
287 #define UDR05_REG UDR0
288 #define UDR06_REG UDR0
289 #define UDR07_REG UDR0
292 #define ISC00_REG EICRA
293 #define ISC01_REG EICRA
296 #define ADC0D_REG DIDR0
297 #define ADC1D_REG DIDR0
298 #define ADC2D_REG DIDR0
299 #define ADC3D_REG DIDR0
300 #define ADC4D_REG DIDR0
301 #define ADC5D_REG DIDR0
302 #define ADC6D_REG DIDR0
303 #define ADC7D_REG DIDR0
306 #define AIN0D_REG DIDR1
307 #define AIN1D_REG DIDR1
310 #define TCR2UB_REG ASSR
311 #define OCR2UB_REG ASSR
312 #define TCN2UB_REG ASSR
314 #define EXCLK_REG ASSR
317 #define CLKPS0_REG CLKPR
318 #define CLKPS1_REG CLKPR
319 #define CLKPS2_REG CLKPR
320 #define CLKPS3_REG CLKPR
321 #define CLKPCE_REG CLKPR
334 #define DDJ0_REG DDRJ
335 #define DDJ1_REG DDRJ
336 #define DDJ2_REG DDRJ
337 #define DDJ3_REG DDRJ
338 #define DDJ4_REG DDRJ
339 #define DDJ5_REG DDRJ
340 #define DDJ6_REG DDRJ
343 #define DDH0_REG DDRH
344 #define DDH1_REG DDRH
345 #define DDH2_REG DDRH
346 #define DDH3_REG DDRH
347 #define DDH4_REG DDRH
348 #define DDH5_REG DDRH
349 #define DDH6_REG DDRH
350 #define DDH7_REG DDRH
353 #define DDB0_REG DDRB
354 #define DDB1_REG DDRB
355 #define DDB2_REG DDRB
356 #define DDB3_REG DDRB
357 #define DDB4_REG DDRB
358 #define DDB5_REG DDRB
359 #define DDB6_REG DDRB
360 #define DDB7_REG DDRB
363 #define DDC0_REG DDRC
364 #define DDC1_REG DDRC
365 #define DDC2_REG DDRC
366 #define DDC3_REG DDRC
367 #define DDC4_REG DDRC
368 #define DDC5_REG DDRC
369 #define DDC6_REG DDRC
370 #define DDC7_REG DDRC
373 #define DDA0_REG DDRA
374 #define DDA1_REG DDRA
375 #define DDA2_REG DDRA
376 #define DDA3_REG DDRA
377 #define DDA4_REG DDRA
378 #define DDA5_REG DDRA
379 #define DDA6_REG DDRA
380 #define DDA7_REG DDRA
383 #define WGM10_REG TCCR1A
384 #define WGM11_REG TCCR1A
385 #define COM1B0_REG TCCR1A
386 #define COM1B1_REG TCCR1A
387 #define COM1A0_REG TCCR1A
388 #define COM1A1_REG TCCR1A
391 #define DDG0_REG DDRG
392 #define DDG1_REG DDRG
393 #define DDG2_REG DDRG
394 #define DDG3_REG DDRG
395 #define DDG4_REG DDRG
398 #define FOC1B_REG TCCR1C
399 #define FOC1A_REG TCCR1C
402 #define CS10_REG TCCR1B
403 #define CS11_REG TCCR1B
404 #define CS12_REG TCCR1B
405 #define WGM12_REG TCCR1B
406 #define WGM13_REG TCCR1B
407 #define ICES1_REG TCCR1B
408 #define ICNC1_REG TCCR1B
411 #define CAL0_REG OSCCAL
412 #define CAL1_REG OSCCAL
413 #define CAL2_REG OSCCAL
414 #define CAL3_REG OSCCAL
415 #define CAL4_REG OSCCAL
416 #define CAL5_REG OSCCAL
417 #define CAL6_REG OSCCAL
418 #define CAL7_REG OSCCAL
421 #define GPIOR10_REG GPIOR1
422 #define GPIOR11_REG GPIOR1
423 #define GPIOR12_REG GPIOR1
424 #define GPIOR13_REG GPIOR1
425 #define GPIOR14_REG GPIOR1
426 #define GPIOR15_REG GPIOR1
427 #define GPIOR16_REG GPIOR1
428 #define GPIOR17_REG GPIOR1
431 #define GPIOR00_REG GPIOR0
432 #define GPIOR01_REG GPIOR0
433 #define GPIOR02_REG GPIOR0
434 #define GPIOR03_REG GPIOR0
435 #define GPIOR04_REG GPIOR0
436 #define GPIOR05_REG GPIOR0
437 #define GPIOR06_REG GPIOR0
438 #define GPIOR07_REG GPIOR0
441 #define GPIOR20_REG GPIOR2
442 #define GPIOR21_REG GPIOR2
443 #define GPIOR22_REG GPIOR2
444 #define GPIOR23_REG GPIOR2
445 #define GPIOR24_REG GPIOR2
446 #define GPIOR25_REG GPIOR2
447 #define GPIOR26_REG GPIOR2
448 #define GPIOR27_REG GPIOR2
451 #define DDE0_REG DDRE
452 #define DDE1_REG DDRE
453 #define DDE2_REG DDRE
454 #define DDE3_REG DDRE
455 #define DDE4_REG DDRE
456 #define DDE5_REG DDRE
457 #define DDE6_REG DDRE
458 #define DDE7_REG DDRE
461 #define TCNT2_0_REG TCNT2
462 #define TCNT2_1_REG TCNT2
463 #define TCNT2_2_REG TCNT2
464 #define TCNT2_3_REG TCNT2
465 #define TCNT2_4_REG TCNT2
466 #define TCNT2_5_REG TCNT2
467 #define TCNT2_6_REG TCNT2
468 #define TCNT2_7_REG TCNT2
471 #define TCNT0_0_REG TCNT0
472 #define TCNT0_1_REG TCNT0
473 #define TCNT0_2_REG TCNT0
474 #define TCNT0_3_REG TCNT0
475 #define TCNT0_4_REG TCNT0
476 #define TCNT0_5_REG TCNT0
477 #define TCNT0_6_REG TCNT0
478 #define TCNT0_7_REG TCNT0
481 #define CS00_REG TCCR0A
482 #define CS01_REG TCCR0A
483 #define CS02_REG TCCR0A
484 #define WGM01_REG TCCR0A
485 #define COM0A0_REG TCCR0A
486 #define COM0A1_REG TCCR0A
487 #define WGM00_REG TCCR0A
488 #define FOC0A_REG TCCR0A
491 #define TOV2_REG TIFR2
492 #define OCF2A_REG TIFR2
495 #define TOV0_REG TIFR0
496 #define OCF0A_REG TIFR0
499 #define TOV1_REG TIFR1
500 #define OCF1A_REG TIFR1
501 #define OCF1B_REG TIFR1
502 #define ICF1_REG TIFR1
505 #define PSR310_REG GTCCR
506 #define TSM_REG GTCCR
507 #define PSR2_REG GTCCR
510 #define ICR1H0_REG ICR1H
511 #define ICR1H1_REG ICR1H
512 #define ICR1H2_REG ICR1H
513 #define ICR1H3_REG ICR1H
514 #define ICR1H4_REG ICR1H
515 #define ICR1H5_REG ICR1H
516 #define ICR1H6_REG ICR1H
517 #define ICR1H7_REG ICR1H
520 #define OCR1BL0_REG OCR1BL
521 #define OCR1BL1_REG OCR1BL
522 #define OCR1BL2_REG OCR1BL
523 #define OCR1BL3_REG OCR1BL
524 #define OCR1BL4_REG OCR1BL
525 #define OCR1BL5_REG OCR1BL
526 #define OCR1BL6_REG OCR1BL
527 #define OCR1BL7_REG OCR1BL
530 #define OCR1BH0_REG OCR1BH
531 #define OCR1BH1_REG OCR1BH
532 #define OCR1BH2_REG OCR1BH
533 #define OCR1BH3_REG OCR1BH
534 #define OCR1BH4_REG OCR1BH
535 #define OCR1BH5_REG OCR1BH
536 #define OCR1BH6_REG OCR1BH
537 #define OCR1BH7_REG OCR1BH
550 #define JTRF_REG MCUSR
551 #define PORF_REG MCUSR
552 #define EXTRF_REG MCUSR
553 #define BORF_REG MCUSR
554 #define WDRF_REG MCUSR
557 #define EERE_REG EECR
558 #define EEWE_REG EECR
559 #define EEMWE_REG EECR
560 #define EERIE_REG EECR
569 #define CS20_REG TCCR2A
570 #define CS21_REG TCCR2A
571 #define CS22_REG TCCR2A
572 #define WGM21_REG TCCR2A
573 #define COM2A0_REG TCCR2A
574 #define COM2A1_REG TCCR2A
575 #define WGM20_REG TCCR2A
576 #define FOC2A_REG TCCR2A
579 #define UBRR8_REG UBRR0H
580 #define UBRR9_REG UBRR0H
581 #define UBRR10_REG UBRR0H
582 #define UBRR11_REG UBRR0H
585 #define UBRR0_REG UBRR0L
586 #define UBRR1_REG UBRR0L
587 #define UBRR2_REG UBRR0L
588 #define UBRR3_REG UBRR0L
589 #define UBRR4_REG UBRR0L
590 #define UBRR5_REG UBRR0L
591 #define UBRR6_REG UBRR0L
592 #define UBRR7_REG UBRR0L
595 #define EEAR8_REG EEARH
596 #define EEAR9_REG EEARH
599 #define EEAR00_REG EEARL
600 #define EEAR1_REG EEARL
601 #define EEAR2_REG EEARL
602 #define EEAR3_REG EEARL
603 #define EEAR4_REG EEARL
604 #define EEAR5_REG EEARL
605 #define EEAR6_REG EEARL
606 #define EEAR7_REG EEARL
609 #define JTD_REG MCUCR
610 #define IVCE_REG MCUCR
611 #define IVSEL_REG MCUCR
612 #define PUD_REG MCUCR
613 #define BODSE_REG MCUCR
614 #define BODS_REG MCUCR
617 #define PINC0_REG PINC
618 #define PINC1_REG PINC
619 #define PINC2_REG PINC
620 #define PINC3_REG PINC
621 #define PINC4_REG PINC
622 #define PINC5_REG PINC
623 #define PINC6_REG PINC
624 #define PINC7_REG PINC
627 #define OCDR0_REG OCDR
628 #define OCDR1_REG OCDR
629 #define OCDR2_REG OCDR
630 #define OCDR3_REG OCDR
631 #define OCDR4_REG OCDR
632 #define OCDR5_REG OCDR
633 #define OCDR6_REG OCDR
634 #define OCDR7_REG OCDR
637 #define PINA0_REG PINA
638 #define PINA1_REG PINA
639 #define PINA2_REG PINA
640 #define PINA3_REG PINA
641 #define PINA4_REG PINA
642 #define PINA5_REG PINA
643 #define PINA6_REG PINA
644 #define PINA7_REG PINA
647 #define ADPS0_REG ADCSRA
648 #define ADPS1_REG ADCSRA
649 #define ADPS2_REG ADCSRA
650 #define ADIE_REG ADCSRA
651 #define ADIF_REG ADCSRA
652 #define ADATE_REG ADCSRA
653 #define ADSC_REG ADCSRA
654 #define ADEN_REG ADCSRA
657 #define ACME_REG ADCSRB
658 #define ADTS0_REG ADCSRB
659 #define ADTS1_REG ADCSRB
660 #define ADTS2_REG ADCSRB
663 #define DDF0_REG DDRF
664 #define DDF1_REG DDRF
665 #define DDF2_REG DDRF
666 #define DDF3_REG DDRF
667 #define DDF4_REG DDRF
668 #define DDF5_REG DDRF
669 #define DDF6_REG DDRF
670 #define DDF7_REG DDRF
673 #define OCR0A0_REG OCR0A
674 #define OCR0A1_REG OCR0A
675 #define OCR0A2_REG OCR0A
676 #define OCR0A3_REG OCR0A
677 #define OCR0A4_REG OCR0A
678 #define OCR0A5_REG OCR0A
679 #define OCR0A6_REG OCR0A
680 #define OCR0A7_REG OCR0A
683 #define ACIS0_REG ACSR
684 #define ACIS1_REG ACSR
685 #define ACIC_REG ACSR
686 #define ACIE_REG ACSR
689 #define ACBG_REG ACSR
693 #define MPCM0_REG UCSR0A
694 #define U2X0_REG UCSR0A
695 #define UPE0_REG UCSR0A
696 #define DOR0_REG UCSR0A
697 #define FE0_REG UCSR0A
698 #define UDRE0_REG UCSR0A
699 #define TXC0_REG UCSR0A
700 #define RXC0_REG UCSR0A
703 #define TXB80_REG UCSR0B
704 #define RXB80_REG UCSR0B
705 #define UCSZ02_REG UCSR0B
706 #define TXEN0_REG UCSR0B
707 #define RXEN0_REG UCSR0B
708 #define UDRIE0_REG UCSR0B
709 #define TXCIE0_REG UCSR0B
710 #define RXCIE0_REG UCSR0B
713 #define DDD0_REG DDRD
714 #define DDD1_REG DDRD
715 #define DDD2_REG DDRD
716 #define DDD3_REG DDRD
717 #define DDD4_REG DDRD
718 #define DDD5_REG DDRD
719 #define DDD6_REG DDRD
720 #define DDD7_REG DDRD
723 #define USITC_REG USICR
724 #define USICLK_REG USICR
725 #define USICS0_REG USICR
726 #define USICS1_REG USICR
727 #define USIWM0_REG USICR
728 #define USIWM1_REG USICR
729 #define USIOIE_REG USICR
730 #define USISIE_REG USICR
733 #define PORTD0_REG PORTD
734 #define PORTD1_REG PORTD
735 #define PORTD2_REG PORTD
736 #define PORTD3_REG PORTD
737 #define PORTD4_REG PORTD
738 #define PORTD5_REG PORTD
739 #define PORTD6_REG PORTD
740 #define PORTD7_REG PORTD
743 #define USICNT0_REG USISR
744 #define USICNT1_REG USISR
745 #define USICNT2_REG USISR
746 #define USICNT3_REG USISR
747 #define USIDC_REG USISR
748 #define USIPF_REG USISR
749 #define USIOIF_REG USISR
750 #define USISIF_REG USISR
753 #define SPMEN_REG SPMCSR
754 #define PGERS_REG SPMCSR
755 #define PGWRT_REG SPMCSR
756 #define BLBSET_REG SPMCSR
757 #define RWWSRE_REG SPMCSR
758 #define RWWSB_REG SPMCSR
759 #define SPMIE_REG SPMCSR
762 #define PORTB0_REG PORTB
763 #define PORTB1_REG PORTB
764 #define PORTB2_REG PORTB
765 #define PORTB3_REG PORTB
766 #define PORTB4_REG PORTB
767 #define PORTB5_REG PORTB
768 #define PORTB6_REG PORTB
769 #define PORTB7_REG PORTB
772 #define ADCL0_REG ADCL
773 #define ADCL1_REG ADCL
774 #define ADCL2_REG ADCL
775 #define ADCL3_REG ADCL
776 #define ADCL4_REG ADCL
777 #define ADCL5_REG ADCL
778 #define ADCL6_REG ADCL
779 #define ADCL7_REG ADCL
782 #define ADCH0_REG ADCH
783 #define ADCH1_REG ADCH
784 #define ADCH2_REG ADCH
785 #define ADCH3_REG ADCH
786 #define ADCH4_REG ADCH
787 #define ADCH5_REG ADCH
788 #define ADCH6_REG ADCH
789 #define ADCH7_REG ADCH
792 #define TOIE2_REG TIMSK2
793 #define OCIE2A_REG TIMSK2
796 #define INT0_REG EIMSK
797 #define PCIE0_REG EIMSK
798 #define PCIE1_REG EIMSK
799 #define PCIE2_REG EIMSK
800 #define PCIE3_REG EIMSK
803 #define TOIE0_REG TIMSK0
804 #define OCIE0A_REG TIMSK0
807 #define TOIE1_REG TIMSK1
808 #define OCIE1A_REG TIMSK1
809 #define OCIE1B_REG TIMSK1
810 #define ICIE1_REG TIMSK1
813 #define PINJ0_REG PINJ
814 #define PINJ1_REG PINJ
815 #define PINJ2_REG PINJ
816 #define PINJ3_REG PINJ
817 #define PINJ4_REG PINJ
818 #define PINJ5_REG PINJ
819 #define PINJ6_REG PINJ
822 #define PINH0_REG PINH
823 #define PINH1_REG PINH
824 #define PINH2_REG PINH
825 #define PINH3_REG PINH
826 #define PINH4_REG PINH
827 #define PINH5_REG PINH
828 #define PINH6_REG PINH
829 #define PINH7_REG PINH
832 #define PCINT0_REG PCMSK0
833 #define PCINT1_REG PCMSK0
834 #define PCINT2_REG PCMSK0
835 #define PCINT3_REG PCMSK0
836 #define PCINT4_REG PCMSK0
837 #define PCINT5_REG PCMSK0
838 #define PCINT6_REG PCMSK0
839 #define PCINT7_REG PCMSK0
842 #define PCINT8_REG PCMSK1
843 #define PCINT9_REG PCMSK1
844 #define PCINT10_REG PCMSK1
845 #define PCINT11_REG PCMSK1
846 #define PCINT12_REG PCMSK1
847 #define PCINT13_REG PCMSK1
848 #define PCINT14_REG PCMSK1
849 #define PCINT15_REG PCMSK1
852 #define PCINT16_REG PCMSK2
853 #define PCINT17_REG PCMSK2
854 #define PCINT18_REG PCMSK2
855 #define PCINT19_REG PCMSK2
856 #define PCINT20_REG PCMSK2
857 #define PCINT21_REG PCMSK2
858 #define PCINT22_REG PCMSK2
859 #define PCINT23_REG PCMSK2
862 #define PCINT24_REG PCMSK3
863 #define PCINT25_REG PCMSK3
864 #define PCINT26_REG PCMSK3
865 #define PCINT27_REG PCMSK3
866 #define PCINT28_REG PCMSK3
867 #define PCINT29_REG PCMSK3
868 #define PCINT30_REG PCMSK3
871 #define TCNT1L0_REG TCNT1L
872 #define TCNT1L1_REG TCNT1L
873 #define TCNT1L2_REG TCNT1L
874 #define TCNT1L3_REG TCNT1L
875 #define TCNT1L4_REG TCNT1L
876 #define TCNT1L5_REG TCNT1L
877 #define TCNT1L6_REG TCNT1L
878 #define TCNT1L7_REG TCNT1L
881 #define PINB0_REG PINB
882 #define PINB1_REG PINB
883 #define PINB2_REG PINB
884 #define PINB3_REG PINB
885 #define PINB4_REG PINB
886 #define PINB5_REG PINB
887 #define PINB6_REG PINB
888 #define PINB7_REG PINB
891 #define INTF0_REG EIFR
892 #define PCIF0_REG EIFR
893 #define PCIF1_REG EIFR
894 #define PCIF2_REG EIFR
895 #define PCIF3_REG EIFR
898 #define PING0_REG PING
899 #define PING1_REG PING
900 #define PING2_REG PING
901 #define PING3_REG PING
902 #define PING4_REG PING
903 #define PING5_REG PING
906 #define PINF0_REG PINF
907 #define PINF1_REG PINF
908 #define PINF2_REG PINF
909 #define PINF3_REG PINF
910 #define PINF4_REG PINF
911 #define PINF5_REG PINF
912 #define PINF6_REG PINF
913 #define PINF7_REG PINF
916 #define PINE0_REG PINE
917 #define PINE1_REG PINE
918 #define PINE2_REG PINE
919 #define PINE3_REG PINE
920 #define PINE4_REG PINE
921 #define PINE5_REG PINE
922 #define PINE6_REG PINE
923 #define PINE7_REG PINE
926 #define PIND0_REG PIND
927 #define PIND1_REG PIND
928 #define PIND2_REG PIND
929 #define PIND3_REG PIND
930 #define PIND4_REG PIND
931 #define PIND5_REG PIND
932 #define PIND6_REG PIND
933 #define PIND7_REG PIND
936 #define OCR1AH0_REG OCR1AH
937 #define OCR1AH1_REG OCR1AH
938 #define OCR1AH2_REG OCR1AH
939 #define OCR1AH3_REG OCR1AH
940 #define OCR1AH4_REG OCR1AH
941 #define OCR1AH5_REG OCR1AH
942 #define OCR1AH6_REG OCR1AH
943 #define OCR1AH7_REG OCR1AH
946 #define OCR1AL0_REG OCR1AL
947 #define OCR1AL1_REG OCR1AL
948 #define OCR1AL2_REG OCR1AL
949 #define OCR1AL3_REG OCR1AL
950 #define OCR1AL4_REG OCR1AL
951 #define OCR1AL5_REG OCR1AL
952 #define OCR1AL6_REG OCR1AL
953 #define OCR1AL7_REG OCR1AL
956 #define SPR0_REG SPCR
957 #define SPR1_REG SPCR
958 #define CPHA_REG SPCR
959 #define CPOL_REG SPCR
960 #define MSTR_REG SPCR
961 #define DORD_REG SPCR
963 #define SPIE_REG SPCR
966 #define USIDR0_REG USIDR
967 #define USIDR1_REG USIDR
968 #define USIDR2_REG USIDR
969 #define USIDR3_REG USIDR
970 #define USIDR4_REG USIDR
971 #define USIDR5_REG USIDR
972 #define USIDR6_REG USIDR
973 #define USIDR7_REG USIDR