2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER0A_AVAILABLE
88 #define TIMER0B_AVAILABLE
89 #define TIMER1_AVAILABLE
90 #define TIMER1A_AVAILABLE
91 #define TIMER1B_AVAILABLE
92 #define TIMER2_AVAILABLE
93 #define TIMER2A_AVAILABLE
94 #define TIMER2B_AVAILABLE
96 /* overflow interrupt number */
97 #define SIG_OVERFLOW0_NUM 0
98 #define SIG_OVERFLOW1_NUM 1
99 #define SIG_OVERFLOW2_NUM 2
100 #define SIG_OVERFLOW_TOTAL_NUM 3
102 /* output compare interrupt number */
103 #define SIG_OUTPUT_COMPARE0A_NUM 0
104 #define SIG_OUTPUT_COMPARE0B_NUM 1
105 #define SIG_OUTPUT_COMPARE1A_NUM 2
106 #define SIG_OUTPUT_COMPARE1B_NUM 3
107 #define SIG_OUTPUT_COMPARE2A_NUM 4
108 #define SIG_OUTPUT_COMPARE2B_NUM 5
109 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
118 #define PWM_TOTAL_NUM 6
120 /* input capture interrupt number */
121 #define SIG_INPUT_CAPTURE1_NUM 0
122 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
126 #define MUX0_REG ADMUX
127 #define MUX1_REG ADMUX
128 #define MUX2_REG ADMUX
129 #define MUX3_REG ADMUX
130 #define ADLAR_REG ADMUX
131 #define REFS0_REG ADMUX
132 #define REFS1_REG ADMUX
135 #define WDP0_REG WDTCSR
136 #define WDP1_REG WDTCSR
137 #define WDP2_REG WDTCSR
138 #define WDE_REG WDTCSR
139 #define WDCE_REG WDTCSR
140 #define WDP3_REG WDTCSR
141 #define WDIE_REG WDTCSR
142 #define WDIF_REG WDTCSR
145 #define EEDR0_REG EEDR
146 #define EEDR1_REG EEDR
147 #define EEDR2_REG EEDR
148 #define EEDR3_REG EEDR
149 #define EEDR4_REG EEDR
150 #define EEDR5_REG EEDR
151 #define EEDR6_REG EEDR
152 #define EEDR7_REG EEDR
155 #define ACIS0_REG ACSR
156 #define ACIS1_REG ACSR
157 #define ACIC_REG ACSR
158 #define ACIE_REG ACSR
161 #define ACBG_REG ACSR
165 #define OCR2B_0_REG OCR2B
166 #define OCR2B_1_REG OCR2B
167 #define OCR2B_2_REG OCR2B
168 #define OCR2B_3_REG OCR2B
169 #define OCR2B_4_REG OCR2B
170 #define OCR2B_5_REG OCR2B
171 #define OCR2B_6_REG OCR2B
172 #define OCR2B_7_REG OCR2B
175 #define OCR2A_0_REG OCR2A
176 #define OCR2A_1_REG OCR2A
177 #define OCR2A_2_REG OCR2A
178 #define OCR2A_3_REG OCR2A
179 #define OCR2A_4_REG OCR2A
180 #define OCR2A_5_REG OCR2A
181 #define OCR2A_6_REG OCR2A
182 #define OCR2A_7_REG OCR2A
185 #define SPDR0_REG SPDR
186 #define SPDR1_REG SPDR
187 #define SPDR2_REG SPDR
188 #define SPDR3_REG SPDR
189 #define SPDR4_REG SPDR
190 #define SPDR5_REG SPDR
191 #define SPDR6_REG SPDR
192 #define SPDR7_REG SPDR
195 #define SPI2X_REG SPSR
196 #define WCOL_REG SPSR
197 #define SPIF_REG SPSR
206 #define ICR1L0_REG ICR1L
207 #define ICR1L1_REG ICR1L
208 #define ICR1L2_REG ICR1L
209 #define ICR1L3_REG ICR1L
210 #define ICR1L4_REG ICR1L
211 #define ICR1L5_REG ICR1L
212 #define ICR1L6_REG ICR1L
213 #define ICR1L7_REG ICR1L
216 #define PRADC_REG PRR
217 #define PRUSART0_REG PRR
218 #define PRSPI_REG PRR
219 #define PRTIM1_REG PRR
220 #define PRTIM0_REG PRR
221 #define PRTIM2_REG PRR
222 #define PRTWI_REG PRR
225 #define TWPS0_REG TWSR
226 #define TWPS1_REG TWSR
227 #define TWS3_REG TWSR
228 #define TWS4_REG TWSR
229 #define TWS5_REG TWSR
230 #define TWS6_REG TWSR
231 #define TWS7_REG TWSR
234 #define MPCM0_REG UCSR0A
235 #define U2X0_REG UCSR0A
236 #define UPE0_REG UCSR0A
237 #define DOR0_REG UCSR0A
238 #define FE0_REG UCSR0A
239 #define UDRE0_REG UCSR0A
240 #define TXC0_REG UCSR0A
241 #define RXC0_REG UCSR0A
244 #define PORTD0_REG PORTD
245 #define PORTD1_REG PORTD
246 #define PORTD2_REG PORTD
247 #define PORTD3_REG PORTD
248 #define PORTD4_REG PORTD
249 #define PORTD5_REG PORTD
250 #define PORTD6_REG PORTD
251 #define PORTD7_REG PORTD
254 #define TXB80_REG UCSR0B
255 #define RXB80_REG UCSR0B
256 #define UCSZ02_REG UCSR0B
257 #define TXEN0_REG UCSR0B
258 #define RXEN0_REG UCSR0B
259 #define UDRIE0_REG UCSR0B
260 #define TXCIE0_REG UCSR0B
261 #define RXCIE0_REG UCSR0B
264 #define PORTB0_REG PORTB
265 #define PORTB1_REG PORTB
266 #define PORTB2_REG PORTB
267 #define PORTB3_REG PORTB
268 #define PORTB4_REG PORTB
269 #define PORTB5_REG PORTB
270 #define PORTB6_REG PORTB
271 #define PORTB7_REG PORTB
274 #define PORTC0_REG PORTC
275 #define PORTC1_REG PORTC
276 #define PORTC2_REG PORTC
277 #define PORTC3_REG PORTC
278 #define PORTC4_REG PORTC
279 #define PORTC5_REG PORTC
280 #define PORTC6_REG PORTC
283 #define UDR0_0_REG UDR0
284 #define UDR0_1_REG UDR0
285 #define UDR0_2_REG UDR0
286 #define UDR0_3_REG UDR0
287 #define UDR0_4_REG UDR0
288 #define UDR0_5_REG UDR0
289 #define UDR0_6_REG UDR0
290 #define UDR0_7_REG UDR0
293 #define ISC00_REG EICRA
294 #define ISC01_REG EICRA
295 #define ISC10_REG EICRA
296 #define ISC11_REG EICRA
299 #define ADC0D_REG DIDR0
300 #define ADC1D_REG DIDR0
301 #define ADC2D_REG DIDR0
302 #define ADC3D_REG DIDR0
303 #define ADC4D_REG DIDR0
304 #define ADC5D_REG DIDR0
307 #define AIN0D_REG DIDR1
308 #define AIN1D_REG DIDR1
311 #define TCR2BUB_REG ASSR
312 #define TCR2AUB_REG ASSR
313 #define OCR2BUB_REG ASSR
314 #define OCR2AUB_REG ASSR
315 #define TCN2UB_REG ASSR
317 #define EXCLK_REG ASSR
320 #define CLKPS0_REG CLKPR
321 #define CLKPS1_REG CLKPR
322 #define CLKPS2_REG CLKPR
323 #define CLKPS3_REG CLKPR
324 #define CLKPCE_REG CLKPR
337 #define DDB0_REG DDRB
338 #define DDB1_REG DDRB
339 #define DDB2_REG DDRB
340 #define DDB3_REG DDRB
341 #define DDB4_REG DDRB
342 #define DDB5_REG DDRB
343 #define DDB6_REG DDRB
344 #define DDB7_REG DDRB
347 #define DDC0_REG DDRC
348 #define DDC1_REG DDRC
349 #define DDC2_REG DDRC
350 #define DDC3_REG DDRC
351 #define DDC4_REG DDRC
352 #define DDC5_REG DDRC
353 #define DDC6_REG DDRC
356 #define WGM10_REG TCCR1A
357 #define WGM11_REG TCCR1A
358 #define COM1B0_REG TCCR1A
359 #define COM1B1_REG TCCR1A
360 #define COM1A0_REG TCCR1A
361 #define COM1A1_REG TCCR1A
364 #define FOC1B_REG TCCR1C
365 #define FOC1A_REG TCCR1C
368 #define CS10_REG TCCR1B
369 #define CS11_REG TCCR1B
370 #define CS12_REG TCCR1B
371 #define WGM12_REG TCCR1B
372 #define WGM13_REG TCCR1B
373 #define ICES1_REG TCCR1B
374 #define ICNC1_REG TCCR1B
377 #define CAL0_REG OSCCAL
378 #define CAL1_REG OSCCAL
379 #define CAL2_REG OSCCAL
380 #define CAL3_REG OSCCAL
381 #define CAL4_REG OSCCAL
382 #define CAL5_REG OSCCAL
383 #define CAL6_REG OSCCAL
384 #define CAL7_REG OSCCAL
387 #define GPIOR10_REG GPIOR1
388 #define GPIOR11_REG GPIOR1
389 #define GPIOR12_REG GPIOR1
390 #define GPIOR13_REG GPIOR1
391 #define GPIOR14_REG GPIOR1
392 #define GPIOR15_REG GPIOR1
393 #define GPIOR16_REG GPIOR1
394 #define GPIOR17_REG GPIOR1
397 #define GPIOR00_REG GPIOR0
398 #define GPIOR01_REG GPIOR0
399 #define GPIOR02_REG GPIOR0
400 #define GPIOR03_REG GPIOR0
401 #define GPIOR04_REG GPIOR0
402 #define GPIOR05_REG GPIOR0
403 #define GPIOR06_REG GPIOR0
404 #define GPIOR07_REG GPIOR0
407 #define GPIOR20_REG GPIOR2
408 #define GPIOR21_REG GPIOR2
409 #define GPIOR22_REG GPIOR2
410 #define GPIOR23_REG GPIOR2
411 #define GPIOR24_REG GPIOR2
412 #define GPIOR25_REG GPIOR2
413 #define GPIOR26_REG GPIOR2
414 #define GPIOR27_REG GPIOR2
417 #define PCIE0_REG PCICR
418 #define PCIE1_REG PCICR
419 #define PCIE2_REG PCICR
422 #define TCNT2_0_REG TCNT2
423 #define TCNT2_1_REG TCNT2
424 #define TCNT2_2_REG TCNT2
425 #define TCNT2_3_REG TCNT2
426 #define TCNT2_4_REG TCNT2
427 #define TCNT2_5_REG TCNT2
428 #define TCNT2_6_REG TCNT2
429 #define TCNT2_7_REG TCNT2
432 #define TCNT0_0_REG TCNT0
433 #define TCNT0_1_REG TCNT0
434 #define TCNT0_2_REG TCNT0
435 #define TCNT0_3_REG TCNT0
436 #define TCNT0_4_REG TCNT0
437 #define TCNT0_5_REG TCNT0
438 #define TCNT0_6_REG TCNT0
439 #define TCNT0_7_REG TCNT0
442 #define TWGCE_REG TWAR
443 #define TWA0_REG TWAR
444 #define TWA1_REG TWAR
445 #define TWA2_REG TWAR
446 #define TWA3_REG TWAR
447 #define TWA4_REG TWAR
448 #define TWA5_REG TWAR
449 #define TWA6_REG TWAR
452 #define CS00_REG TCCR0B
453 #define CS01_REG TCCR0B
454 #define CS02_REG TCCR0B
455 #define WGM02_REG TCCR0B
456 #define FOC0B_REG TCCR0B
457 #define FOC0A_REG TCCR0B
460 #define WGM00_REG TCCR0A
461 #define WGM01_REG TCCR0A
462 #define COM0B0_REG TCCR0A
463 #define COM0B1_REG TCCR0A
464 #define COM0A0_REG TCCR0A
465 #define COM0A1_REG TCCR0A
468 #define TOV2_REG TIFR2
469 #define OCF2A_REG TIFR2
470 #define OCF2B_REG TIFR2
473 #define TOV0_REG TIFR0
474 #define OCF0A_REG TIFR0
475 #define OCF0B_REG TIFR0
478 #define TOV1_REG TIFR1
479 #define OCF1A_REG TIFR1
480 #define OCF1B_REG TIFR1
481 #define ICF1_REG TIFR1
484 #define PSRSYNC_REG GTCCR
485 #define TSM_REG GTCCR
486 #define PSRASY_REG GTCCR
489 #define TWBR0_REG TWBR
490 #define TWBR1_REG TWBR
491 #define TWBR2_REG TWBR
492 #define TWBR3_REG TWBR
493 #define TWBR4_REG TWBR
494 #define TWBR5_REG TWBR
495 #define TWBR6_REG TWBR
496 #define TWBR7_REG TWBR
499 #define ICR1H0_REG ICR1H
500 #define ICR1H1_REG ICR1H
501 #define ICR1H2_REG ICR1H
502 #define ICR1H3_REG ICR1H
503 #define ICR1H4_REG ICR1H
504 #define ICR1H5_REG ICR1H
505 #define ICR1H6_REG ICR1H
506 #define ICR1H7_REG ICR1H
509 #define OCR1BL0_REG OCR1BL
510 #define OCR1BL1_REG OCR1BL
511 #define OCR1BL2_REG OCR1BL
512 #define OCR1BL3_REG OCR1BL
513 #define OCR1BL4_REG OCR1BL
514 #define OCR1BL5_REG OCR1BL
515 #define OCR1BL6_REG OCR1BL
516 #define OCR1BL7_REG OCR1BL
519 #define PCIF0_REG PCIFR
520 #define PCIF1_REG PCIFR
521 #define PCIF2_REG PCIFR
534 #define OCR1BH0_REG OCR1BH
535 #define OCR1BH1_REG OCR1BH
536 #define OCR1BH2_REG OCR1BH
537 #define OCR1BH3_REG OCR1BH
538 #define OCR1BH4_REG OCR1BH
539 #define OCR1BH5_REG OCR1BH
540 #define OCR1BH6_REG OCR1BH
541 #define OCR1BH7_REG OCR1BH
544 #define EERE_REG EECR
545 #define EEPE_REG EECR
546 #define EEMPE_REG EECR
547 #define EERIE_REG EECR
548 #define EEPM0_REG EECR
549 #define EEPM1_REG EECR
558 #define TWIE_REG TWCR
559 #define TWEN_REG TWCR
560 #define TWWC_REG TWCR
561 #define TWSTO_REG TWCR
562 #define TWSTA_REG TWCR
563 #define TWEA_REG TWCR
564 #define TWINT_REG TWCR
567 #define WGM20_REG TCCR2A
568 #define WGM21_REG TCCR2A
569 #define COM2B0_REG TCCR2A
570 #define COM2B1_REG TCCR2A
571 #define COM2A0_REG TCCR2A
572 #define COM2A1_REG TCCR2A
575 #define CS20_REG TCCR2B
576 #define CS21_REG TCCR2B
577 #define CS22_REG TCCR2B
578 #define WGM22_REG TCCR2B
579 #define FOC2B_REG TCCR2B
580 #define FOC2A_REG TCCR2B
583 #define UBRR8_REG UBRR0H
584 #define UBRR9_REG UBRR0H
585 #define UBRR10_REG UBRR0H
586 #define UBRR11_REG UBRR0H
589 #define UBRR0_REG UBRR0L
590 #define UBRR1_REG UBRR0L
591 #define UBRR2_REG UBRR0L
592 #define UBRR3_REG UBRR0L
593 #define UBRR4_REG UBRR0L
594 #define UBRR5_REG UBRR0L
595 #define UBRR6_REG UBRR0L
596 #define UBRR7_REG UBRR0L
599 #define EEAR8_REG EEARH
600 #define EEAR9_REG EEARH
603 #define EEAR0_REG EEARL
604 #define EEAR1_REG EEARL
605 #define EEAR2_REG EEARL
606 #define EEAR3_REG EEARL
607 #define EEAR4_REG EEARL
608 #define EEAR5_REG EEARL
609 #define EEAR6_REG EEARL
610 #define EEAR7_REG EEARL
613 #define IVCE_REG MCUCR
614 #define IVSEL_REG MCUCR
615 #define PUD_REG MCUCR
616 #define BODSE_REG MCUCR
617 #define BODS_REG MCUCR
620 #define PORF_REG MCUSR
621 #define EXTRF_REG MCUSR
622 #define BORF_REG MCUSR
623 #define WDRF_REG MCUSR
626 #define TWD0_REG TWDR
627 #define TWD1_REG TWDR
628 #define TWD2_REG TWDR
629 #define TWD3_REG TWDR
630 #define TWD4_REG TWDR
631 #define TWD5_REG TWDR
632 #define TWD6_REG TWDR
633 #define TWD7_REG TWDR
636 #define OCR1AH0_REG OCR1AH
637 #define OCR1AH1_REG OCR1AH
638 #define OCR1AH2_REG OCR1AH
639 #define OCR1AH3_REG OCR1AH
640 #define OCR1AH4_REG OCR1AH
641 #define OCR1AH5_REG OCR1AH
642 #define OCR1AH6_REG OCR1AH
643 #define OCR1AH7_REG OCR1AH
646 #define ADPS0_REG ADCSRA
647 #define ADPS1_REG ADCSRA
648 #define ADPS2_REG ADCSRA
649 #define ADIE_REG ADCSRA
650 #define ADIF_REG ADCSRA
651 #define ADATE_REG ADCSRA
652 #define ADSC_REG ADCSRA
653 #define ADEN_REG ADCSRA
656 #define ADTS0_REG ADCSRB
657 #define ADTS1_REG ADCSRB
658 #define ADTS2_REG ADCSRB
659 #define ACME_REG ADCSRB
662 #define OCROA_0_REG OCR0A
663 #define OCROA_1_REG OCR0A
664 #define OCROA_2_REG OCR0A
665 #define OCROA_3_REG OCR0A
666 #define OCROA_4_REG OCR0A
667 #define OCROA_5_REG OCR0A
668 #define OCROA_6_REG OCR0A
669 #define OCROA_7_REG OCR0A
672 #define OCR0B_0_REG OCR0B
673 #define OCR0B_1_REG OCR0B
674 #define OCR0B_2_REG OCR0B
675 #define OCR0B_3_REG OCR0B
676 #define OCR0B_4_REG OCR0B
677 #define OCR0B_5_REG OCR0B
678 #define OCR0B_6_REG OCR0B
679 #define OCR0B_7_REG OCR0B
682 #define TCNT1L0_REG TCNT1L
683 #define TCNT1L1_REG TCNT1L
684 #define TCNT1L2_REG TCNT1L
685 #define TCNT1L3_REG TCNT1L
686 #define TCNT1L4_REG TCNT1L
687 #define TCNT1L5_REG TCNT1L
688 #define TCNT1L6_REG TCNT1L
689 #define TCNT1L7_REG TCNT1L
692 #define DDD0_REG DDRD
693 #define DDD1_REG DDRD
694 #define DDD2_REG DDRD
695 #define DDD3_REG DDRD
696 #define DDD4_REG DDRD
697 #define DDD5_REG DDRD
698 #define DDD6_REG DDRD
699 #define DDD7_REG DDRD
702 #define UCPOL0_REG UCSR0C
703 #define UCSZ00_REG UCSR0C
704 #define UCSZ01_REG UCSR0C
705 #define USBS0_REG UCSR0C
706 #define UPM00_REG UCSR0C
707 #define UPM01_REG UCSR0C
708 #define UMSEL00_REG UCSR0C
709 #define UMSEL01_REG UCSR0C
712 #define SELFPRGEN_REG SPMCSR
713 #define PGERS_REG SPMCSR
714 #define PGWRT_REG SPMCSR
715 #define BLBSET_REG SPMCSR
716 #define RWWSRE_REG SPMCSR
717 #define RWWSB_REG SPMCSR
718 #define SPMIE_REG SPMCSR
721 #define TCNT1H0_REG TCNT1H
722 #define TCNT1H1_REG TCNT1H
723 #define TCNT1H2_REG TCNT1H
724 #define TCNT1H3_REG TCNT1H
725 #define TCNT1H4_REG TCNT1H
726 #define TCNT1H5_REG TCNT1H
727 #define TCNT1H6_REG TCNT1H
728 #define TCNT1H7_REG TCNT1H
731 #define ADCL0_REG ADCL
732 #define ADCL1_REG ADCL
733 #define ADCL2_REG ADCL
734 #define ADCL3_REG ADCL
735 #define ADCL4_REG ADCL
736 #define ADCL5_REG ADCL
737 #define ADCL6_REG ADCL
738 #define ADCL7_REG ADCL
741 #define ADCH0_REG ADCH
742 #define ADCH1_REG ADCH
743 #define ADCH2_REG ADCH
744 #define ADCH3_REG ADCH
745 #define ADCH4_REG ADCH
746 #define ADCH5_REG ADCH
747 #define ADCH6_REG ADCH
748 #define ADCH7_REG ADCH
751 #define TOIE2_REG TIMSK2
752 #define OCIE2A_REG TIMSK2
753 #define OCIE2B_REG TIMSK2
756 #define INT0_REG EIMSK
757 #define INT1_REG EIMSK
760 #define TOIE0_REG TIMSK0
761 #define OCIE0A_REG TIMSK0
762 #define OCIE0B_REG TIMSK0
765 #define TOIE1_REG TIMSK1
766 #define OCIE1A_REG TIMSK1
767 #define OCIE1B_REG TIMSK1
768 #define ICIE1_REG TIMSK1
771 #define PCINT0_REG PCMSK0
772 #define PCINT1_REG PCMSK0
773 #define PCINT2_REG PCMSK0
774 #define PCINT3_REG PCMSK0
775 #define PCINT4_REG PCMSK0
776 #define PCINT5_REG PCMSK0
777 #define PCINT6_REG PCMSK0
778 #define PCINT7_REG PCMSK0
781 #define PCINT8_REG PCMSK1
782 #define PCINT9_REG PCMSK1
783 #define PCINT10_REG PCMSK1
784 #define PCINT11_REG PCMSK1
785 #define PCINT12_REG PCMSK1
786 #define PCINT13_REG PCMSK1
787 #define PCINT14_REG PCMSK1
790 #define PCINT16_REG PCMSK2
791 #define PCINT17_REG PCMSK2
792 #define PCINT18_REG PCMSK2
793 #define PCINT19_REG PCMSK2
794 #define PCINT20_REG PCMSK2
795 #define PCINT21_REG PCMSK2
796 #define PCINT22_REG PCMSK2
797 #define PCINT23_REG PCMSK2
800 #define PINC0_REG PINC
801 #define PINC1_REG PINC
802 #define PINC2_REG PINC
803 #define PINC3_REG PINC
804 #define PINC4_REG PINC
805 #define PINC5_REG PINC
806 #define PINC6_REG PINC
809 #define PINB0_REG PINB
810 #define PINB1_REG PINB
811 #define PINB2_REG PINB
812 #define PINB3_REG PINB
813 #define PINB4_REG PINB
814 #define PINB5_REG PINB
815 #define PINB6_REG PINB
816 #define PINB7_REG PINB
819 #define INTF0_REG EIFR
820 #define INTF1_REG EIFR
823 #define PIND0_REG PIND
824 #define PIND1_REG PIND
825 #define PIND2_REG PIND
826 #define PIND3_REG PIND
827 #define PIND4_REG PIND
828 #define PIND5_REG PIND
829 #define PIND6_REG PIND
830 #define PIND7_REG PIND
833 #define TWAM0_REG TWAMR
834 #define TWAM1_REG TWAMR
835 #define TWAM2_REG TWAMR
836 #define TWAM3_REG TWAMR
837 #define TWAM4_REG TWAMR
838 #define TWAM5_REG TWAMR
839 #define TWAM6_REG TWAMR
842 #define OCR1AL0_REG OCR1AL
843 #define OCR1AL1_REG OCR1AL
844 #define OCR1AL2_REG OCR1AL
845 #define OCR1AL3_REG OCR1AL
846 #define OCR1AL4_REG OCR1AL
847 #define OCR1AL5_REG OCR1AL
848 #define OCR1AL6_REG OCR1AL
849 #define OCR1AL7_REG OCR1AL
852 #define SPR0_REG SPCR
853 #define SPR1_REG SPCR
854 #define CPHA_REG SPCR
855 #define CPOL_REG SPCR
856 #define MSTR_REG SPCR
857 #define DORD_REG SPCR
859 #define SPIE_REG SPCR
862 #define ICP1_PORT PORTB
864 #define CLKO_PORT PORTB
866 #define PCINT0_PORT PORTB
869 #define OC1A_PORT PORTB
871 #define PCINT1_PORT PORTB
874 #define SS_PORT PORTB
876 #define OC1B_PORT PORTB
878 #define PCINT2_PORT PORTB
881 #define MOSI_PORT PORTB
883 #define OC2A_PORT PORTB
885 #define PCINT3_PORT PORTB
888 #define MISO_PORT PORTB
890 #define PCINT4_PORT PORTB
893 #define SCK_PORT PORTB
895 #define PCINT5_PORT PORTB
898 #define XTAL1_PORT PORTB
900 #define TOSC1_PORT PORTB
902 #define PCINT6_PORT PORTB
905 #define XTAL2_PORT PORTB
907 #define TOSC2_PORT PORTB
909 #define PCINT7_PORT PORTB
912 #define ADC0_PORT PORTC
914 #define PCINT8_PORT PORTC
917 #define ADC1_PORT PORTC
919 #define PCINT9_PORT PORTC
922 #define ADC2_PORT PORTC
924 #define PCINT10_PORT PORTC
925 #define PCINT10_BIT 2
927 #define ADC3_PORT PORTC
929 #define PCINT11_PORT PORTC
930 #define PCINT11_BIT 3
932 #define ADC4_PORT PORTC
934 #define SDA_PORT PORTC
936 #define PCINT12_PORT PORTC
937 #define PCINT12_BIT 4
939 #define ADC5_PORT PORTC
941 #define SCL_PORT PORTC
943 #define PCINT13_PORT PORTC
944 #define PCINT13_BIT 5
946 #define RESET_PORT PORTC
948 #define PCINT14_PORT PORTC
949 #define PCINT14_BIT 6
951 #define RXD_PORT PORTD
953 #define PCINT16_PORT PORTD
954 #define PCINT16_BIT 0
956 #define TXD_PORT PORTD
958 #define PCINT17_PORT PORTD
959 #define PCINT17_BIT 1
961 #define INT0_PORT PORTD
963 #define PCINT18_PORT PORTD
964 #define PCINT18_BIT 2
966 #define PCINT19_PORT PORTD
967 #define PCINT19_BIT 3
968 #define OC2B_PORT PORTD
970 #define INT1_PORT PORTD
973 #define XCK_PORT PORTD
975 #define T0_PORT PORTD
977 #define PCINT20_PORT PORTD
978 #define PCINT20_BIT 4
980 #define T1_PORT PORTD
982 #define OC0B_PORT PORTD
984 #define PCINT21_PORT PORTD
985 #define PCINT21_BIT 5
987 #define AIN0_PORT PORTD
989 #define OC0A_PORT PORTD
991 #define PCINT22_PORT PORTD
992 #define PCINT22_BIT 6
994 #define AIN1_PORT PORTD
996 #define PCINT23_PORT PORTD
997 #define PCINT23_BIT 7