2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER1_AVAILABLE
88 #define TIMER1A_AVAILABLE
89 #define TIMER1B_AVAILABLE
90 #define TIMER2_AVAILABLE
92 /* overflow interrupt number */
93 #define SIG_OVERFLOW0_NUM 0
94 #define SIG_OVERFLOW1_NUM 1
95 #define SIG_OVERFLOW2_NUM 2
96 #define SIG_OVERFLOW_TOTAL_NUM 3
98 /* output compare interrupt number */
99 #define SIG_OUTPUT_COMPARE0_NUM 0
100 #define SIG_OUTPUT_COMPARE1A_NUM 1
101 #define SIG_OUTPUT_COMPARE1B_NUM 2
102 #define SIG_OUTPUT_COMPARE2_NUM 3
103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
110 #define PWM_TOTAL_NUM 4
112 /* input capture interrupt number */
113 #define SIG_INPUT_CAPTURE1_NUM 0
114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
118 #define WDP0_REG WDTCR
119 #define WDP1_REG WDTCR
120 #define WDP2_REG WDTCR
121 #define WDE_REG WDTCR
122 #define WDCE_REG WDTCR
125 #define MUX0_REG ADMUX
126 #define MUX1_REG ADMUX
127 #define MUX2_REG ADMUX
128 #define MUX3_REG ADMUX
129 #define MUX4_REG ADMUX
130 #define ADLAR_REG ADMUX
131 #define REFS0_REG ADMUX
132 #define REFS1_REG ADMUX
135 #define EEDR0_REG EEDR
136 #define EEDR1_REG EEDR
137 #define EEDR2_REG EEDR
138 #define EEDR3_REG EEDR
139 #define EEDR4_REG EEDR
140 #define EEDR5_REG EEDR
141 #define EEDR6_REG EEDR
142 #define EEDR7_REG EEDR
145 #define OCR2A0_REG OCR2A
146 #define OCR2A1_REG OCR2A
147 #define OCR2A2_REG OCR2A
148 #define OCR2A3_REG OCR2A
149 #define OCR2A4_REG OCR2A
150 #define OCR2A5_REG OCR2A
151 #define OCR2A6_REG OCR2A
152 #define OCR2A7_REG OCR2A
155 #define SPDR0_REG SPDR
156 #define SPDR1_REG SPDR
157 #define SPDR2_REG SPDR
158 #define SPDR3_REG SPDR
159 #define SPDR4_REG SPDR
160 #define SPDR5_REG SPDR
161 #define SPDR6_REG SPDR
162 #define SPDR7_REG SPDR
165 #define SPI2X_REG SPSR
166 #define WCOL_REG SPSR
167 #define SPIF_REG SPSR
180 #define ICR1L0_REG ICR1L
181 #define ICR1L1_REG ICR1L
182 #define ICR1L2_REG ICR1L
183 #define ICR1L3_REG ICR1L
184 #define ICR1L4_REG ICR1L
185 #define ICR1L5_REG ICR1L
186 #define ICR1L6_REG ICR1L
187 #define ICR1L7_REG ICR1L
190 #define PRADC_REG PRR
191 #define PRUSART0_REG PRR
192 #define PRSPI_REG PRR
193 #define PRTIM1_REG PRR
194 #define PRLCD_REG PRR
197 #define PORTJ0_REG PORTJ
198 #define PORTJ1_REG PORTJ
199 #define PORTJ2_REG PORTJ
200 #define PORTJ3_REG PORTJ
201 #define PORTJ4_REG PORTJ
202 #define PORTJ5_REG PORTJ
203 #define PORTJ6_REG PORTJ
206 #define PORTH0_REG PORTH
207 #define PORTH1_REG PORTH
208 #define PORTH2_REG PORTH
209 #define PORTH3_REG PORTH
210 #define PORTH4_REG PORTH
211 #define PORTH5_REG PORTH
212 #define PORTH6_REG PORTH
213 #define PORTH7_REG PORTH
216 #define MPCM0_REG UCSR0A
217 #define U2X0_REG UCSR0A
218 #define UPE0_REG UCSR0A
219 #define DOR0_REG UCSR0A
220 #define FE0_REG UCSR0A
221 #define UDRE0_REG UCSR0A
222 #define TXC0_REG UCSR0A
223 #define RXC0_REG UCSR0A
226 #define PORTG0_REG PORTG
227 #define PORTG1_REG PORTG
228 #define PORTG2_REG PORTG
229 #define PORTG3_REG PORTG
230 #define PORTG4_REG PORTG
233 #define UCPOL0_REG UCSR0C
234 #define UCSZ00_REG UCSR0C
235 #define UCSZ01_REG UCSR0C
236 #define USBS0_REG UCSR0C
237 #define UPM00_REG UCSR0C
238 #define UPM01_REG UCSR0C
239 #define UMSEL0_REG UCSR0C
242 #define USICNT0_REG USISR
243 #define USICNT1_REG USISR
244 #define USICNT2_REG USISR
245 #define USICNT3_REG USISR
246 #define USIDC_REG USISR
247 #define USIPF_REG USISR
248 #define USIOIF_REG USISR
249 #define USISIF_REG USISR
252 #define TCNT1H0_REG TCNT1H
253 #define TCNT1H1_REG TCNT1H
254 #define TCNT1H2_REG TCNT1H
255 #define TCNT1H3_REG TCNT1H
256 #define TCNT1H4_REG TCNT1H
257 #define TCNT1H5_REG TCNT1H
258 #define TCNT1H6_REG TCNT1H
259 #define TCNT1H7_REG TCNT1H
262 #define PORTC0_REG PORTC
263 #define PORTC1_REG PORTC
264 #define PORTC2_REG PORTC
265 #define PORTC3_REG PORTC
266 #define PORTC4_REG PORTC
267 #define PORTC5_REG PORTC
268 #define PORTC6_REG PORTC
269 #define PORTC7_REG PORTC
272 #define PORTA0_REG PORTA
273 #define PORTA1_REG PORTA
274 #define PORTA2_REG PORTA
275 #define PORTA3_REG PORTA
276 #define PORTA4_REG PORTA
277 #define PORTA5_REG PORTA
278 #define PORTA6_REG PORTA
279 #define PORTA7_REG PORTA
282 #define UDR00_REG UDR0
283 #define UDR01_REG UDR0
284 #define UDR02_REG UDR0
285 #define UDR03_REG UDR0
286 #define UDR04_REG UDR0
287 #define UDR05_REG UDR0
288 #define UDR06_REG UDR0
289 #define UDR07_REG UDR0
292 #define GPIOR20_REG GPIOR2
293 #define GPIOR21_REG GPIOR2
294 #define GPIOR22_REG GPIOR2
295 #define GPIOR23_REG GPIOR2
296 #define GPIOR24_REG GPIOR2
297 #define GPIOR25_REG GPIOR2
298 #define GPIOR26_REG GPIOR2
299 #define GPIOR27_REG GPIOR2
302 #define ISC00_REG EICRA
303 #define ISC01_REG EICRA
306 #define ADC0D_REG DIDR0
307 #define ADC1D_REG DIDR0
308 #define ADC2D_REG DIDR0
309 #define ADC3D_REG DIDR0
310 #define ADC4D_REG DIDR0
311 #define ADC5D_REG DIDR0
312 #define ADC6D_REG DIDR0
313 #define ADC7D_REG DIDR0
316 #define AIN0D_REG DIDR1
317 #define AIN1D_REG DIDR1
320 #define TCR2UB_REG ASSR
321 #define OCR2UB_REG ASSR
322 #define TCN2UB_REG ASSR
324 #define EXCLK_REG ASSR
327 #define CLKPS0_REG CLKPR
328 #define CLKPS1_REG CLKPR
329 #define CLKPS2_REG CLKPR
330 #define CLKPS3_REG CLKPR
331 #define CLKPCE_REG CLKPR
344 #define DDJ0_REG DDRJ
345 #define DDJ1_REG DDRJ
346 #define DDJ2_REG DDRJ
347 #define DDJ3_REG DDRJ
348 #define DDJ4_REG DDRJ
349 #define DDJ5_REG DDRJ
350 #define DDJ6_REG DDRJ
353 #define DDH0_REG DDRH
354 #define DDH1_REG DDRH
355 #define DDH2_REG DDRH
356 #define DDH3_REG DDRH
357 #define DDH4_REG DDRH
358 #define DDH5_REG DDRH
359 #define DDH6_REG DDRH
360 #define DDH7_REG DDRH
363 #define DDB0_REG DDRB
364 #define DDB1_REG DDRB
365 #define DDB2_REG DDRB
366 #define DDB3_REG DDRB
367 #define DDB4_REG DDRB
368 #define DDB5_REG DDRB
369 #define DDB6_REG DDRB
370 #define DDB7_REG DDRB
373 #define DDC0_REG DDRC
374 #define DDC1_REG DDRC
375 #define DDC2_REG DDRC
376 #define DDC3_REG DDRC
377 #define DDC4_REG DDRC
378 #define DDC5_REG DDRC
379 #define DDC6_REG DDRC
380 #define DDC7_REG DDRC
383 #define DDA0_REG DDRA
384 #define DDA1_REG DDRA
385 #define DDA2_REG DDRA
386 #define DDA3_REG DDRA
387 #define DDA4_REG DDRA
388 #define DDA5_REG DDRA
389 #define DDA6_REG DDRA
390 #define DDA7_REG DDRA
393 #define WGM10_REG TCCR1A
394 #define WGM11_REG TCCR1A
395 #define COM1B0_REG TCCR1A
396 #define COM1B1_REG TCCR1A
397 #define COM1A0_REG TCCR1A
398 #define COM1A1_REG TCCR1A
401 #define DDG0_REG DDRG
402 #define DDG1_REG DDRG
403 #define DDG2_REG DDRG
404 #define DDG3_REG DDRG
405 #define DDG4_REG DDRG
408 #define FOC1B_REG TCCR1C
409 #define FOC1A_REG TCCR1C
412 #define CS10_REG TCCR1B
413 #define CS11_REG TCCR1B
414 #define CS12_REG TCCR1B
415 #define WGM12_REG TCCR1B
416 #define WGM13_REG TCCR1B
417 #define ICES1_REG TCCR1B
418 #define ICNC1_REG TCCR1B
421 #define CAL0_REG OSCCAL
422 #define CAL1_REG OSCCAL
423 #define CAL2_REG OSCCAL
424 #define CAL3_REG OSCCAL
425 #define CAL4_REG OSCCAL
426 #define CAL5_REG OSCCAL
427 #define CAL6_REG OSCCAL
428 #define CAL7_REG OSCCAL
431 #define SEG024_REG LCDDR3
432 #define SEG025_REG LCDDR3
433 #define SEG026_REG LCDDR3
434 #define SEG027_REG LCDDR3
435 #define SEG028_REG LCDDR3
436 #define SEG029_REG LCDDR3
437 #define SEG030_REG LCDDR3
438 #define SEG031_REG LCDDR3
441 #define SEG016_REG LCDDR2
442 #define SEG017_REG LCDDR2
443 #define SEG018_REG LCDDR2
444 #define SEG019_REG LCDDR2
445 #define SEG020_REG LCDDR2
446 #define SEG021_REG LCDDR2
447 #define SEG022_REG LCDDR2
448 #define SEG023_REG LCDDR2
451 #define SEG008_REG LCDDR1
452 #define SEG009_REG LCDDR1
453 #define SEG010_REG LCDDR1
454 #define SEG011_REG LCDDR1
455 #define SEG012_REG LCDDR1
456 #define SEG013_REG LCDDR1
457 #define SEG014_REG LCDDR1
458 #define SEG015_REG LCDDR1
461 #define SEG000_REG LCDDR0
462 #define SEG001_REG LCDDR0
463 #define SEG002_REG LCDDR0
464 #define SEG003_REG LCDDR0
465 #define SEG004_REG LCDDR0
466 #define SEG005_REG LCDDR0
467 #define SEG006_REG LCDDR0
468 #define SEG007_REG LCDDR0
471 #define SEG116_REG LCDDR7
472 #define SEG117_REG LCDDR7
473 #define SEG118_REG LCDDR7
474 #define SEG119_REG LCDDR7
475 #define SEG120_REG LCDDR7
476 #define SEG121_REG LCDDR7
477 #define SEG122_REG LCDDR7
478 #define SEG123_REG LCDDR7
481 #define SEG108_REG LCDDR6
482 #define SEG109_REG LCDDR6
483 #define SEG110_REG LCDDR6
484 #define SEG111_REG LCDDR6
485 #define SEG112_REG LCDDR6
486 #define SEG113_REG LCDDR6
487 #define SEG114_REG LCDDR6
488 #define SEG115_REG LCDDR6
491 #define SEG100_REG LCDDR5
492 #define SEG101_REG LCDDR5
493 #define SEG102_REG LCDDR5
494 #define SEG103_REG LCDDR5
495 #define SEG104_REG LCDDR5
496 #define SEG105_REG LCDDR5
497 #define SEG106_REG LCDDR5
498 #define SEG107_REG LCDDR5
501 #define SEG032_REG LCDDR4
502 #define SEG033_REG LCDDR4
503 #define SEG034_REG LCDDR4
504 #define SEG035_REG LCDDR4
505 #define SEG036_REG LCDDR4
506 #define SEG037_REG LCDDR4
507 #define SEG038_REG LCDDR4
508 #define SEG039_REG LCDDR4
511 #define GPIOR10_REG GPIOR1
512 #define GPIOR11_REG GPIOR1
513 #define GPIOR12_REG GPIOR1
514 #define GPIOR13_REG GPIOR1
515 #define GPIOR14_REG GPIOR1
516 #define GPIOR15_REG GPIOR1
517 #define GPIOR16_REG GPIOR1
518 #define GPIOR17_REG GPIOR1
521 #define GPIOR00_REG GPIOR0
522 #define GPIOR01_REG GPIOR0
523 #define GPIOR02_REG GPIOR0
524 #define GPIOR03_REG GPIOR0
525 #define GPIOR04_REG GPIOR0
526 #define GPIOR05_REG GPIOR0
527 #define GPIOR06_REG GPIOR0
528 #define GPIOR07_REG GPIOR0
531 #define SEG132_REG LCDDR9
532 #define SEG133_REG LCDDR9
533 #define SEG134_REG LCDDR9
534 #define SEG135_REG LCDDR9
535 #define SEG136_REG LCDDR9
536 #define SEG137_REG LCDDR9
537 #define SEG138_REG LCDDR9
538 #define SEG139_REG LCDDR9
541 #define SEG124_REG LCDDR8
542 #define SEG125_REG LCDDR8
543 #define SEG126_REG LCDDR8
544 #define SEG127_REG LCDDR8
545 #define SEG128_REG LCDDR8
546 #define SEG129_REG LCDDR8
547 #define SEG130_REG LCDDR8
548 #define SEG131_REG LCDDR8
551 #define LCDBL_REG LCDCRA
552 #define LCDIE_REG LCDCRA
553 #define LCDIF_REG LCDCRA
554 #define LCDAB_REG LCDCRA
555 #define LCDEN_REG LCDCRA
558 #define DDE0_REG DDRE
559 #define DDE1_REG DDRE
560 #define DDE2_REG DDRE
561 #define DDE3_REG DDRE
562 #define DDE4_REG DDRE
563 #define DDE5_REG DDRE
564 #define DDE6_REG DDRE
565 #define DDE7_REG DDRE
568 #define LCDPM0_REG LCDCRB
569 #define LCDPM1_REG LCDCRB
570 #define LCDPM2_REG LCDCRB
571 #define LCDPM3_REG LCDCRB
572 #define LCDMUX0_REG LCDCRB
573 #define LCDMUX1_REG LCDCRB
574 #define LCD2B_REG LCDCRB
575 #define LCDCS_REG LCDCRB
578 #define TCNT2_0_REG TCNT2
579 #define TCNT2_1_REG TCNT2
580 #define TCNT2_2_REG TCNT2
581 #define TCNT2_3_REG TCNT2
582 #define TCNT2_4_REG TCNT2
583 #define TCNT2_5_REG TCNT2
584 #define TCNT2_6_REG TCNT2
585 #define TCNT2_7_REG TCNT2
588 #define TCNT0_0_REG TCNT0
589 #define TCNT0_1_REG TCNT0
590 #define TCNT0_2_REG TCNT0
591 #define TCNT0_3_REG TCNT0
592 #define TCNT0_4_REG TCNT0
593 #define TCNT0_5_REG TCNT0
594 #define TCNT0_6_REG TCNT0
595 #define TCNT0_7_REG TCNT0
598 #define CS00_REG TCCR0A
599 #define CS01_REG TCCR0A
600 #define CS02_REG TCCR0A
601 #define WGM01_REG TCCR0A
602 #define COM0A0_REG TCCR0A
603 #define COM0A1_REG TCCR0A
604 #define WGM00_REG TCCR0A
605 #define FOC0A_REG TCCR0A
608 #define TOV2_REG TIFR2
609 #define OCF2A_REG TIFR2
612 #define SPR0_REG SPCR
613 #define SPR1_REG SPCR
614 #define CPHA_REG SPCR
615 #define CPOL_REG SPCR
616 #define MSTR_REG SPCR
617 #define DORD_REG SPCR
619 #define SPIE_REG SPCR
622 #define TOV1_REG TIFR1
623 #define OCF1A_REG TIFR1
624 #define OCF1B_REG TIFR1
625 #define ICF1_REG TIFR1
628 #define PSR310_REG GTCCR
629 #define TSM_REG GTCCR
630 #define PSR2_REG GTCCR
633 #define ICR1H0_REG ICR1H
634 #define ICR1H1_REG ICR1H
635 #define ICR1H2_REG ICR1H
636 #define ICR1H3_REG ICR1H
637 #define ICR1H4_REG ICR1H
638 #define ICR1H5_REG ICR1H
639 #define ICR1H6_REG ICR1H
640 #define ICR1H7_REG ICR1H
643 #define SEG332_REG LCDDR19
644 #define SEG333_REG LCDDR19
645 #define SEG334_REG LCDDR19
646 #define SEG335_REG LCDDR19
647 #define SEG336_REG LCDDR19
648 #define SEG337_REG LCDDR19
649 #define SEG338_REG LCDDR19
650 #define SEG339_REG LCDDR19
653 #define SEG324_REG LCDDR18
654 #define SEG325_REG LCDDR18
655 #define SEG326_REG LCDDR18
656 #define SEG327_REG LCDDR18
657 #define SEG328_REG LCDDR18
658 #define SEG329_REG LCDDR18
659 #define SEG330_REG LCDDR18
660 #define SEG331_REG LCDDR18
663 #define SEG224_REG LCDDR13
664 #define SEG225_REG LCDDR13
665 #define SEG226_REG LCDDR13
666 #define SEG227_REG LCDDR13
667 #define SEG228_REG LCDDR13
668 #define SEG229_REG LCDDR13
669 #define SEG230_REG LCDDR13
670 #define SEG231_REG LCDDR13
673 #define SEG216_REG LCDDR12
674 #define SEG217_REG LCDDR12
675 #define SEG218_REG LCDDR12
676 #define SEG219_REG LCDDR12
677 #define SEG220_REG LCDDR12
678 #define SEG221_REG LCDDR12
679 #define SEG222_REG LCDDR12
680 #define SEG223_REG LCDDR12
683 #define SEG208_REG LCDDR11
684 #define SEG209_REG LCDDR11
685 #define SEG210_REG LCDDR11
686 #define SEG211_REG LCDDR11
687 #define SEG212_REG LCDDR11
688 #define SEG213_REG LCDDR11
689 #define SEG214_REG LCDDR11
690 #define SEG215_REG LCDDR11
693 #define SEG200_REG LCDDR10
694 #define SEG201_REG LCDDR10
695 #define SEG202_REG LCDDR10
696 #define SEG203_REG LCDDR10
697 #define SEG204_REG LCDDR10
698 #define SEG205_REG LCDDR10
699 #define SEG206_REG LCDDR10
700 #define SEG207_REG LCDDR10
703 #define SEG316_REG LCDDR17
704 #define SEG317_REG LCDDR17
705 #define SEG318_REG LCDDR17
706 #define SEG319_REG LCDDR17
707 #define SEG320_REG LCDDR17
708 #define SEG321_REG LCDDR17
709 #define SEG322_REG LCDDR17
710 #define SEG323_REG LCDDR17
713 #define SEG308_REG LCDDR16
714 #define SEG309_REG LCDDR16
715 #define SEG310_REG LCDDR16
716 #define SEG311_REG LCDDR16
717 #define SEG312_REG LCDDR16
718 #define SEG313_REG LCDDR16
719 #define SEG314_REG LCDDR16
720 #define SEG315_REG LCDDR16
723 #define SEG300_REG LCDDR15
724 #define SEG301_REG LCDDR15
725 #define SEG302_REG LCDDR15
726 #define SEG303_REG LCDDR15
727 #define SEG304_REG LCDDR15
728 #define SEG305_REG LCDDR15
729 #define SEG306_REG LCDDR15
730 #define SEG307_REG LCDDR15
733 #define SEG232_REG LCDDR14
734 #define SEG233_REG LCDDR14
735 #define SEG234_REG LCDDR14
736 #define SEG235_REG LCDDR14
737 #define SEG236_REG LCDDR14
738 #define SEG237_REG LCDDR14
739 #define SEG238_REG LCDDR14
740 #define SEG239_REG LCDDR14
743 #define OCR1BL0_REG OCR1BL
744 #define OCR1BL1_REG OCR1BL
745 #define OCR1BL2_REG OCR1BL
746 #define OCR1BL3_REG OCR1BL
747 #define OCR1BL4_REG OCR1BL
748 #define OCR1BL5_REG OCR1BL
749 #define OCR1BL6_REG OCR1BL
750 #define OCR1BL7_REG OCR1BL
753 #define OCR1BH0_REG OCR1BH
754 #define OCR1BH1_REG OCR1BH
755 #define OCR1BH2_REG OCR1BH
756 #define OCR1BH3_REG OCR1BH
757 #define OCR1BH4_REG OCR1BH
758 #define OCR1BH5_REG OCR1BH
759 #define OCR1BH6_REG OCR1BH
760 #define OCR1BH7_REG OCR1BH
773 #define JTRF_REG MCUSR
774 #define PORF_REG MCUSR
775 #define EXTRF_REG MCUSR
776 #define BORF_REG MCUSR
777 #define WDRF_REG MCUSR
780 #define EERE_REG EECR
781 #define EEWE_REG EECR
782 #define EEMWE_REG EECR
783 #define EERIE_REG EECR
792 #define CS20_REG TCCR2A
793 #define CS21_REG TCCR2A
794 #define CS22_REG TCCR2A
795 #define WGM21_REG TCCR2A
796 #define COM2A0_REG TCCR2A
797 #define COM2A1_REG TCCR2A
798 #define WGM20_REG TCCR2A
799 #define FOC2A_REG TCCR2A
802 #define UBRR8_REG UBRR0H
803 #define UBRR9_REG UBRR0H
804 #define UBRR10_REG UBRR0H
805 #define UBRR11_REG UBRR0H
808 #define UBRR0_REG UBRR0L
809 #define UBRR1_REG UBRR0L
810 #define UBRR2_REG UBRR0L
811 #define UBRR3_REG UBRR0L
812 #define UBRR4_REG UBRR0L
813 #define UBRR5_REG UBRR0L
814 #define UBRR6_REG UBRR0L
815 #define UBRR7_REG UBRR0L
818 #define EEAR8_REG EEARH
819 #define EEAR9_REG EEARH
822 #define EEAR00_REG EEARL
823 #define EEAR1_REG EEARL
824 #define EEAR2_REG EEARL
825 #define EEAR3_REG EEARL
826 #define EEAR4_REG EEARL
827 #define EEAR5_REG EEARL
828 #define EEAR6_REG EEARL
829 #define EEAR7_REG EEARL
832 #define JTD_REG MCUCR
833 #define IVCE_REG MCUCR
834 #define IVSEL_REG MCUCR
835 #define PUD_REG MCUCR
838 #define OCDR0_REG OCDR
839 #define OCDR1_REG OCDR
840 #define OCDR2_REG OCDR
841 #define OCDR3_REG OCDR
842 #define OCDR4_REG OCDR
843 #define OCDR5_REG OCDR
844 #define OCDR6_REG OCDR
845 #define OCDR7_REG OCDR
848 #define PINA0_REG PINA
849 #define PINA1_REG PINA
850 #define PINA2_REG PINA
851 #define PINA3_REG PINA
852 #define PINA4_REG PINA
853 #define PINA5_REG PINA
854 #define PINA6_REG PINA
855 #define PINA7_REG PINA
858 #define PORTE0_REG PORTE
859 #define PORTE1_REG PORTE
860 #define PORTE2_REG PORTE
861 #define PORTE3_REG PORTE
862 #define PORTE4_REG PORTE
863 #define PORTE5_REG PORTE
864 #define PORTE6_REG PORTE
865 #define PORTE7_REG PORTE
868 #define LCDCC0_REG LCDCCR
869 #define LCDCC1_REG LCDCCR
870 #define LCDCC2_REG LCDCCR
871 #define LCDCC3_REG LCDCCR
872 #define LCDDC0_REG LCDCCR
873 #define LCDDC1_REG LCDCCR
874 #define LCDDC2_REG LCDCCR
877 #define PINE0_REG PINE
878 #define PINE1_REG PINE
879 #define PINE2_REG PINE
880 #define PINE3_REG PINE
881 #define PINE4_REG PINE
882 #define PINE5_REG PINE
883 #define PINE6_REG PINE
884 #define PINE7_REG PINE
887 #define ADPS0_REG ADCSRA
888 #define ADPS1_REG ADCSRA
889 #define ADPS2_REG ADCSRA
890 #define ADIE_REG ADCSRA
891 #define ADIF_REG ADCSRA
892 #define ADATE_REG ADCSRA
893 #define ADSC_REG ADCSRA
894 #define ADEN_REG ADCSRA
897 #define ACME_REG ADCSRB
898 #define ADTS0_REG ADCSRB
899 #define ADTS1_REG ADCSRB
900 #define ADTS2_REG ADCSRB
903 #define DDF0_REG DDRF
904 #define DDF1_REG DDRF
905 #define DDF2_REG DDRF
906 #define DDF3_REG DDRF
907 #define DDF4_REG DDRF
908 #define DDF5_REG DDRF
909 #define DDF6_REG DDRF
910 #define DDF7_REG DDRF
913 #define OCR0A0_REG OCR0A
914 #define OCR0A1_REG OCR0A
915 #define OCR0A2_REG OCR0A
916 #define OCR0A3_REG OCR0A
917 #define OCR0A4_REG OCR0A
918 #define OCR0A5_REG OCR0A
919 #define OCR0A6_REG OCR0A
920 #define OCR0A7_REG OCR0A
923 #define ACIS0_REG ACSR
924 #define ACIS1_REG ACSR
925 #define ACIC_REG ACSR
926 #define ACIE_REG ACSR
929 #define ACBG_REG ACSR
933 #define TCNT1L0_REG TCNT1L
934 #define TCNT1L1_REG TCNT1L
935 #define TCNT1L2_REG TCNT1L
936 #define TCNT1L3_REG TCNT1L
937 #define TCNT1L4_REG TCNT1L
938 #define TCNT1L5_REG TCNT1L
939 #define TCNT1L6_REG TCNT1L
940 #define TCNT1L7_REG TCNT1L
943 #define DDD0_REG DDRD
944 #define DDD1_REG DDRD
945 #define DDD2_REG DDRD
946 #define DDD3_REG DDRD
947 #define DDD4_REG DDRD
948 #define DDD5_REG DDRD
949 #define DDD6_REG DDRD
950 #define DDD7_REG DDRD
953 #define USITC_REG USICR
954 #define USICLK_REG USICR
955 #define USICS0_REG USICR
956 #define USICS1_REG USICR
957 #define USIWM0_REG USICR
958 #define USIWM1_REG USICR
959 #define USIOIE_REG USICR
960 #define USISIE_REG USICR
963 #define PORTD0_REG PORTD
964 #define PORTD1_REG PORTD
965 #define PORTD2_REG PORTD
966 #define PORTD3_REG PORTD
967 #define PORTD4_REG PORTD
968 #define PORTD5_REG PORTD
969 #define PORTD6_REG PORTD
970 #define PORTD7_REG PORTD
973 #define TXB80_REG UCSR0B
974 #define RXB80_REG UCSR0B
975 #define UCSZ02_REG UCSR0B
976 #define TXEN0_REG UCSR0B
977 #define RXEN0_REG UCSR0B
978 #define UDRIE0_REG UCSR0B
979 #define TXCIE0_REG UCSR0B
980 #define RXCIE0_REG UCSR0B
983 #define SPMEN_REG SPMCSR
984 #define PGERS_REG SPMCSR
985 #define PGWRT_REG SPMCSR
986 #define BLBSET_REG SPMCSR
987 #define RWWSRE_REG SPMCSR
988 #define RWWSB_REG SPMCSR
989 #define SPMIE_REG SPMCSR
992 #define PORTB0_REG PORTB
993 #define PORTB1_REG PORTB
994 #define PORTB2_REG PORTB
995 #define PORTB3_REG PORTB
996 #define PORTB4_REG PORTB
997 #define PORTB5_REG PORTB
998 #define PORTB6_REG PORTB
999 #define PORTB7_REG PORTB
1002 #define ADCL0_REG ADCL
1003 #define ADCL1_REG ADCL
1004 #define ADCL2_REG ADCL
1005 #define ADCL3_REG ADCL
1006 #define ADCL4_REG ADCL
1007 #define ADCL5_REG ADCL
1008 #define ADCL6_REG ADCL
1009 #define ADCL7_REG ADCL
1012 #define ADCH0_REG ADCH
1013 #define ADCH1_REG ADCH
1014 #define ADCH2_REG ADCH
1015 #define ADCH3_REG ADCH
1016 #define ADCH4_REG ADCH
1017 #define ADCH5_REG ADCH
1018 #define ADCH6_REG ADCH
1019 #define ADCH7_REG ADCH
1022 #define LCDCD0_REG LCDFRR
1023 #define LCDCD1_REG LCDFRR
1024 #define LCDCD2_REG LCDFRR
1025 #define LCDPS0_REG LCDFRR
1026 #define LCDPS1_REG LCDFRR
1027 #define LCDPS2_REG LCDFRR
1030 #define TOIE2_REG TIMSK2
1031 #define OCIE2A_REG TIMSK2
1034 #define INT0_REG EIMSK
1035 #define PCIE0_REG EIMSK
1036 #define PCIE1_REG EIMSK
1037 #define PCIE2_REG EIMSK
1038 #define PCIE3_REG EIMSK
1041 #define TOIE0_REG TIMSK0
1042 #define OCIE0A_REG TIMSK0
1045 #define TOIE1_REG TIMSK1
1046 #define OCIE1A_REG TIMSK1
1047 #define OCIE1B_REG TIMSK1
1048 #define ICIE1_REG TIMSK1
1051 #define PINJ0_REG PINJ
1052 #define PINJ1_REG PINJ
1053 #define PINJ2_REG PINJ
1054 #define PINJ3_REG PINJ
1055 #define PINJ4_REG PINJ
1056 #define PINJ5_REG PINJ
1057 #define PINJ6_REG PINJ
1060 #define PINH0_REG PINH
1061 #define PINH1_REG PINH
1062 #define PINH2_REG PINH
1063 #define PINH3_REG PINH
1064 #define PINH4_REG PINH
1065 #define PINH5_REG PINH
1066 #define PINH6_REG PINH
1067 #define PINH7_REG PINH
1070 #define PCINT0_REG PCMSK0
1071 #define PCINT1_REG PCMSK0
1072 #define PCINT2_REG PCMSK0
1073 #define PCINT3_REG PCMSK0
1074 #define PCINT4_REG PCMSK0
1075 #define PCINT5_REG PCMSK0
1076 #define PCINT6_REG PCMSK0
1077 #define PCINT7_REG PCMSK0
1080 #define PCINT8_REG PCMSK1
1081 #define PCINT9_REG PCMSK1
1082 #define PCINT10_REG PCMSK1
1083 #define PCINT11_REG PCMSK1
1084 #define PCINT12_REG PCMSK1
1085 #define PCINT13_REG PCMSK1
1086 #define PCINT14_REG PCMSK1
1087 #define PCINT15_REG PCMSK1
1090 #define PCINT16_REG PCMSK2
1091 #define PCINT17_REG PCMSK2
1092 #define PCINT18_REG PCMSK2
1093 #define PCINT19_REG PCMSK2
1094 #define PCINT20_REG PCMSK2
1095 #define PCINT21_REG PCMSK2
1096 #define PCINT22_REG PCMSK2
1097 #define PCINT23_REG PCMSK2
1100 #define PCINT24_REG PCMSK3
1101 #define PCINT25_REG PCMSK3
1102 #define PCINT26_REG PCMSK3
1103 #define PCINT27_REG PCMSK3
1104 #define PCINT28_REG PCMSK3
1105 #define PCINT29_REG PCMSK3
1106 #define PCINT30_REG PCMSK3
1109 #define PINC0_REG PINC
1110 #define PINC1_REG PINC
1111 #define PINC2_REG PINC
1112 #define PINC3_REG PINC
1113 #define PINC4_REG PINC
1114 #define PINC5_REG PINC
1115 #define PINC6_REG PINC
1116 #define PINC7_REG PINC
1119 #define PINB0_REG PINB
1120 #define PINB1_REG PINB
1121 #define PINB2_REG PINB
1122 #define PINB3_REG PINB
1123 #define PINB4_REG PINB
1124 #define PINB5_REG PINB
1125 #define PINB6_REG PINB
1126 #define PINB7_REG PINB
1129 #define INTF0_REG EIFR
1130 #define PCIF0_REG EIFR
1131 #define PCIF1_REG EIFR
1132 #define PCIF2_REG EIFR
1133 #define PCIF3_REG EIFR
1136 #define PING0_REG PING
1137 #define PING1_REG PING
1138 #define PING2_REG PING
1139 #define PING3_REG PING
1140 #define PING4_REG PING
1141 #define PING5_REG PING
1144 #define PINF0_REG PINF
1145 #define PINF1_REG PINF
1146 #define PINF2_REG PINF
1147 #define PINF3_REG PINF
1148 #define PINF4_REG PINF
1149 #define PINF5_REG PINF
1150 #define PINF6_REG PINF
1151 #define PINF7_REG PINF
1154 #define PORTF0_REG PORTF
1155 #define PORTF1_REG PORTF
1156 #define PORTF2_REG PORTF
1157 #define PORTF3_REG PORTF
1158 #define PORTF4_REG PORTF
1159 #define PORTF5_REG PORTF
1160 #define PORTF6_REG PORTF
1161 #define PORTF7_REG PORTF
1164 #define PIND0_REG PIND
1165 #define PIND1_REG PIND
1166 #define PIND2_REG PIND
1167 #define PIND3_REG PIND
1168 #define PIND4_REG PIND
1169 #define PIND5_REG PIND
1170 #define PIND6_REG PIND
1171 #define PIND7_REG PIND
1174 #define OCR1AH0_REG OCR1AH
1175 #define OCR1AH1_REG OCR1AH
1176 #define OCR1AH2_REG OCR1AH
1177 #define OCR1AH3_REG OCR1AH
1178 #define OCR1AH4_REG OCR1AH
1179 #define OCR1AH5_REG OCR1AH
1180 #define OCR1AH6_REG OCR1AH
1181 #define OCR1AH7_REG OCR1AH
1184 #define OCR1AL0_REG OCR1AL
1185 #define OCR1AL1_REG OCR1AL
1186 #define OCR1AL2_REG OCR1AL
1187 #define OCR1AL3_REG OCR1AL
1188 #define OCR1AL4_REG OCR1AL
1189 #define OCR1AL5_REG OCR1AL
1190 #define OCR1AL6_REG OCR1AL
1191 #define OCR1AL7_REG OCR1AL
1194 #define TOV0_REG TIFR0
1195 #define OCF0A_REG TIFR0
1198 #define USIDR0_REG USIDR
1199 #define USIDR1_REG USIDR
1200 #define USIDR2_REG USIDR
1201 #define USIDR3_REG USIDR
1202 #define USIDR4_REG USIDR
1203 #define USIDR5_REG USIDR
1204 #define USIDR6_REG USIDR
1205 #define USIDR7_REG USIDR