2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER0A_AVAILABLE
69 #define TIMER0B_AVAILABLE
70 #define TIMER1_AVAILABLE
71 #define TIMER1A_AVAILABLE
72 #define TIMER1B_AVAILABLE
74 /* overflow interrupt number */
75 #define SIG_OVERFLOW0_NUM 0
76 #define SIG_OVERFLOW1_NUM 1
77 #define SIG_OVERFLOW_TOTAL_NUM 2
79 /* output compare interrupt number */
80 #define SIG_OUTPUT_COMPARE0A_NUM 0
81 #define SIG_OUTPUT_COMPARE0B_NUM 1
82 #define SIG_OUTPUT_COMPARE1A_NUM 2
83 #define SIG_OUTPUT_COMPARE1B_NUM 3
84 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
91 #define PWM_TOTAL_NUM 4
93 /* input capture interrupt number */
94 #define SIG_INPUT_CAPTURE1_NUM 0
95 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
99 #define PORTB0_REG PORTB
100 #define PORTB1_REG PORTB
101 #define PORTB2_REG PORTB
102 #define PORTB3_REG PORTB
103 #define PORTB4_REG PORTB
104 #define PORTB5_REG PORTB
105 #define PORTB6_REG PORTB
106 #define PORTB7_REG PORTB
109 #define LBT0_REG LINBTR
110 #define LBT1_REG LINBTR
111 #define LBT2_REG LINBTR
112 #define LBT3_REG LINBTR
113 #define LBT4_REG LINBTR
114 #define LBT5_REG LINBTR
115 #define LDISR_REG LINBTR
118 #define MUX0_REG ADMUX
119 #define MUX1_REG ADMUX
120 #define MUX2_REG ADMUX
121 #define MUX3_REG ADMUX
122 #define MUX4_REG ADMUX
123 #define ADLAR_REG ADMUX
124 #define REFS0_REG ADMUX
125 #define REFS1_REG ADMUX
128 #define LID0_REG LINIDR
129 #define LID1_REG LINIDR
130 #define LID2_REG LINIDR
131 #define LID3_REG LINIDR
132 #define LID4_REG LINIDR
133 #define LID5_REG LINIDR
134 #define LP0_REG LINIDR
135 #define LP1_REG LINIDR
138 #define WDP0_REG WDTCSR
139 #define WDP1_REG WDTCSR
140 #define WDP2_REG WDTCSR
141 #define WDE_REG WDTCSR
142 #define WDCE_REG WDTCSR
143 #define WDP3_REG WDTCSR
144 #define WDIE_REG WDTCSR
145 #define WDIF_REG WDTCSR
148 #define EEDR0_REG EEDR
149 #define EEDR1_REG EEDR
150 #define EEDR2_REG EEDR
151 #define EEDR3_REG EEDR
152 #define EEDR4_REG EEDR
153 #define EEDR5_REG EEDR
154 #define EEDR6_REG EEDR
155 #define EEDR7_REG EEDR
158 #define AC0O_REG ACSR
159 #define AC1O_REG ACSR
160 #define AC2O_REG ACSR
161 #define AC3O_REG ACSR
162 #define AC0IF_REG ACSR
163 #define AC1IF_REG ACSR
164 #define AC2IF_REG ACSR
165 #define AC3IF_REG ACSR
168 #define LINDX0_REG LINSEL
169 #define LINDX1_REG LINSEL
170 #define LINDX2_REG LINSEL
171 #define LAINC_REG LINSEL
174 #define LCMD0_REG LINCR
175 #define LCMD1_REG LINCR
176 #define LCMD2_REG LINCR
177 #define LENA_REG LINCR
178 #define LCONF0_REG LINCR
179 #define LCONF1_REG LINCR
180 #define LIN13_REG LINCR
181 #define LSWRES_REG LINCR
184 #define SPDR0_REG SPDR
185 #define SPDR1_REG SPDR
186 #define SPDR2_REG SPDR
187 #define SPDR3_REG SPDR
188 #define SPDR4_REG SPDR
189 #define SPDR5_REG SPDR
190 #define SPDR6_REG SPDR
191 #define SPDR7_REG SPDR
194 #define SPI2X_REG SPSR
195 #define WCOL_REG SPSR
196 #define SPIF_REG SPSR
199 #define ICR1H0_REG ICR1H
200 #define ICR1H1_REG ICR1H
201 #define ICR1H2_REG ICR1H
202 #define ICR1H3_REG ICR1H
203 #define ICR1H4_REG ICR1H
204 #define ICR1H5_REG ICR1H
205 #define ICR1H6_REG ICR1H
206 #define ICR1H7_REG ICR1H
209 #define ICR1L0_REG ICR1L
210 #define ICR1L1_REG ICR1L
211 #define ICR1L2_REG ICR1L
212 #define ICR1L3_REG ICR1L
213 #define ICR1L4_REG ICR1L
214 #define ICR1L5_REG ICR1L
215 #define ICR1L6_REG ICR1L
216 #define ICR1L7_REG ICR1L
219 #define AC1M0_REG AC1CON
220 #define AC1M1_REG AC1CON
221 #define AC1M2_REG AC1CON
222 #define AC1ICE_REG AC1CON
223 #define AC1IS0_REG AC1CON
224 #define AC1IS1_REG AC1CON
225 #define AC1IE_REG AC1CON
226 #define AC1EN_REG AC1CON
229 #define PRADC_REG PRR
230 #define PRLIN_REG PRR
231 #define PRSPI_REG PRR
232 #define PRTIM0_REG PRR
233 #define PRTIM1_REG PRR
234 #define PRPSC_REG PRR
235 #define PRCAN_REG PRR
238 #define LDIV0_REG LINBRRL
239 #define LDIV1_REG LINBRRL
240 #define LDIV2_REG LINBRRL
241 #define LDIV3_REG LINBRRL
242 #define LDIV4_REG LINBRRL
243 #define LDIV5_REG LINBRRL
244 #define LDIV6_REG LINBRRL
245 #define LDIV7_REG LINBRRL
248 #define LDIV8_REG LINBRRH
249 #define LDIV9_REG LINBRRH
250 #define LDIV10_REG LINBRRH
251 #define LDIV11_REG LINBRRH
254 #define ERRP_REG CANGSTA
255 #define BOFF_REG CANGSTA
256 #define ENFG_REG CANGSTA
257 #define RXBSY_REG CANGSTA
258 #define TXBSY_REG CANGSTA
259 #define OVFG_REG CANGSTA
262 #define SWRES_REG CANGCON
263 #define ENASTB_REG CANGCON
264 #define TEST_REG CANGCON
265 #define LISTEN_REG CANGCON
266 #define SYNTTC_REG CANGCON
267 #define TTC_REG CANGCON
268 #define OVRQ_REG CANGCON
269 #define ABRQ_REG CANGCON
272 #define PORTD0_REG PORTD
273 #define PORTD1_REG PORTD
274 #define PORTD2_REG PORTD
275 #define PORTD3_REG PORTD
276 #define PORTD4_REG PORTD
277 #define PORTD5_REG PORTD
278 #define PORTD6_REG PORTD
279 #define PORTD7_REG PORTD
282 #define PORTE0_REG PORTE
283 #define PORTE1_REG PORTE
284 #define PORTE2_REG PORTE
287 #define TCNT1H0_REG TCNT1H
288 #define TCNT1H1_REG TCNT1H
289 #define TCNT1H2_REG TCNT1H
290 #define TCNT1H3_REG TCNT1H
291 #define TCNT1H4_REG TCNT1H
292 #define TCNT1H5_REG TCNT1H
293 #define TCNT1H6_REG TCNT1H
294 #define TCNT1H7_REG TCNT1H
297 #define PORTC0_REG PORTC
298 #define PORTC1_REG PORTC
299 #define PORTC2_REG PORTC
300 #define PORTC3_REG PORTC
301 #define PORTC4_REG PORTC
302 #define PORTC5_REG PORTC
303 #define PORTC6_REG PORTC
304 #define PORTC7_REG PORTC
307 #define AMP1TS0_REG AMP1CSR
308 #define AMP1TS1_REG AMP1CSR
309 #define AMP1TS2_REG AMP1CSR
310 #define AMPCMP1_REG AMP1CSR
311 #define AMP1G0_REG AMP1CSR
312 #define AMP1G1_REG AMP1CSR
313 #define AMP1IS_REG AMP1CSR
314 #define AMP1EN_REG AMP1CSR
317 #define AC2M0_REG AC2CON
318 #define AC2M1_REG AC2CON
319 #define AC2M2_REG AC2CON
320 #define AC2IS0_REG AC2CON
321 #define AC2IS1_REG AC2CON
322 #define AC2IE_REG AC2CON
323 #define AC2EN_REG AC2CON
326 #define EEAR0_REG EEARL
327 #define EEAR1_REG EEARL
328 #define EEAR2_REG EEARL
329 #define EEAR3_REG EEARL
330 #define EEAR4_REG EEARL
331 #define EEAR5_REG EEARL
332 #define EEAR6_REG EEARL
333 #define EEAR7_REG EEARL
336 #define INT0_REG EIMSK
337 #define INT1_REG EIMSK
338 #define INT2_REG EIMSK
339 #define INT3_REG EIMSK
342 #define ISC00_REG EICRA
343 #define ISC01_REG EICRA
344 #define ISC10_REG EICRA
345 #define ISC11_REG EICRA
346 #define ISC20_REG EICRA
347 #define ISC21_REG EICRA
348 #define ISC30_REG EICRA
349 #define ISC31_REG EICRA
352 #define LRXOK_REG LINSIR
353 #define LTXOK_REG LINSIR
354 #define LIDOK_REG LINSIR
355 #define LERR_REG LINSIR
356 #define LBUSY_REG LINSIR
357 #define LIDST0_REG LINSIR
358 #define LIDST1_REG LINSIR
359 #define LIDST2_REG LINSIR
362 #define ADC0D_REG DIDR0
363 #define ADC1D_REG DIDR0
364 #define ADC2D_REG DIDR0
365 #define ADC3D_REG DIDR0
366 #define ADC4D_REG DIDR0
367 #define ADC5D_REG DIDR0
368 #define ADC6D_REG DIDR0
369 #define ADC7D_REG DIDR0
372 #define ADC8D_REG DIDR1
373 #define ADC9D_REG DIDR1
374 #define ADC10D_REG DIDR1
375 #define AMP0ND_REG DIDR1
376 #define AMP0PD_REG DIDR1
377 #define ACMP0D_REG DIDR1
378 #define AMP2PD_REG DIDR1
381 #define CLKPS0_REG CLKPR
382 #define CLKPS1_REG CLKPR
383 #define CLKPS2_REG CLKPR
384 #define CLKPS3_REG CLKPR
385 #define CLKPCE_REG CLKPR
398 #define IDMSK21_REG CANIDM1
399 #define IDMSK22_REG CANIDM1
400 #define IDMSK23_REG CANIDM1
401 #define IDMSK24_REG CANIDM1
402 #define IDMSK25_REG CANIDM1
403 #define IDMSK26_REG CANIDM1
404 #define IDMSK27_REG CANIDM1
405 #define IDMSK28_REG CANIDM1
408 #define IDMSK5_REG CANIDM3
409 #define IDMSK6_REG CANIDM3
410 #define IDMSK7_REG CANIDM3
411 #define IDMSK8_REG CANIDM3
412 #define IDMSK9_REG CANIDM3
413 #define IDMSK10_REG CANIDM3
414 #define IDMSK11_REG CANIDM3
415 #define IDMSK12_REG CANIDM3
418 #define IDMSK13_REG CANIDM2
419 #define IDMSK14_REG CANIDM2
420 #define IDMSK15_REG CANIDM2
421 #define IDMSK16_REG CANIDM2
422 #define IDMSK17_REG CANIDM2
423 #define IDMSK18_REG CANIDM2
424 #define IDMSK19_REG CANIDM2
425 #define IDMSK20_REG CANIDM2
428 #define IDEMSK_REG CANIDM4
429 #define RTRMSK_REG CANIDM4
430 #define IDMSK0_REG CANIDM4
431 #define IDMSK1_REG CANIDM4
432 #define IDMSK2_REG CANIDM4
433 #define IDMSK3_REG CANIDM4
434 #define IDMSK4_REG CANIDM4
437 #define DDB0_REG DDRB
438 #define DDB1_REG DDRB
439 #define DDB2_REG DDRB
440 #define DDB3_REG DDRB
441 #define DDB4_REG DDRB
442 #define DDB5_REG DDRB
443 #define DDB6_REG DDRB
444 #define DDB7_REG DDRB
447 #define DDC0_REG DDRC
448 #define DDC1_REG DDRC
449 #define DDC2_REG DDRC
450 #define DDC3_REG DDRC
451 #define DDC4_REG DDRC
452 #define DDC5_REG DDRC
453 #define DDC6_REG DDRC
454 #define DDC7_REG DDRC
457 #define WGM10_REG TCCR1A
458 #define WGM11_REG TCCR1A
459 #define COM1B0_REG TCCR1A
460 #define COM1B1_REG TCCR1A
461 #define COM1A0_REG TCCR1A
462 #define COM1A1_REG TCCR1A
465 #define FOC1B_REG TCCR1C
466 #define FOC1A_REG TCCR1C
469 #define CS10_REG TCCR1B
470 #define CS11_REG TCCR1B
471 #define CS12_REG TCCR1B
472 #define WGM12_REG TCCR1B
473 #define WGM13_REG TCCR1B
474 #define ICES1_REG TCCR1B
475 #define ICNC1_REG TCCR1B
478 #define CAL0_REG OSCCAL
479 #define CAL1_REG OSCCAL
480 #define CAL2_REG OSCCAL
481 #define CAL3_REG OSCCAL
482 #define CAL4_REG OSCCAL
483 #define CAL5_REG OSCCAL
484 #define CAL6_REG OSCCAL
487 #define GPIOR10_REG GPIOR1
488 #define GPIOR11_REG GPIOR1
489 #define GPIOR12_REG GPIOR1
490 #define GPIOR13_REG GPIOR1
491 #define GPIOR14_REG GPIOR1
492 #define GPIOR15_REG GPIOR1
493 #define GPIOR16_REG GPIOR1
494 #define GPIOR17_REG GPIOR1
497 #define GPIOR00_REG GPIOR0
498 #define GPIOR01_REG GPIOR0
499 #define GPIOR02_REG GPIOR0
500 #define GPIOR03_REG GPIOR0
501 #define GPIOR04_REG GPIOR0
502 #define GPIOR05_REG GPIOR0
503 #define GPIOR06_REG GPIOR0
504 #define GPIOR07_REG GPIOR0
507 #define GPIOR20_REG GPIOR2
508 #define GPIOR21_REG GPIOR2
509 #define GPIOR22_REG GPIOR2
510 #define GPIOR23_REG GPIOR2
511 #define GPIOR24_REG GPIOR2
512 #define GPIOR25_REG GPIOR2
513 #define GPIOR26_REG GPIOR2
514 #define GPIOR27_REG GPIOR2
517 #define AERG_REG CANGIT
518 #define FERG_REG CANGIT
519 #define CERG_REG CANGIT
520 #define SERG_REG CANGIT
521 #define BXOK_REG CANGIT
522 #define OVRTIM_REG CANGIT
523 #define BOFFIT_REG CANGIT
524 #define CANIT_REG CANGIT
527 #define AC3M0_REG AC3CON
528 #define AC3M1_REG AC3CON
529 #define AC3M2_REG AC3CON
530 #define AC3IS0_REG AC3CON
531 #define AC3IS1_REG AC3CON
532 #define AC3IE_REG AC3CON
533 #define AC3EN_REG AC3CON
536 #define LBERR_REG LINERR
537 #define LCERR_REG LINERR
538 #define LPERR_REG LINERR
539 #define LSERR_REG LINERR
540 #define LFERR_REG LINERR
541 #define LOVERR_REG LINERR
542 #define LTOERR_REG LINERR
543 #define LABORT_REG LINERR
546 #define PCIE0_REG PCICR
547 #define PCIE1_REG PCICR
548 #define PCIE2_REG PCICR
549 #define PCIE3_REG PCICR
552 #define ENOVRT_REG CANGIE
553 #define ENERG_REG CANGIE
554 #define ENBX_REG CANGIE
555 #define ENERR_REG CANGIE
556 #define ENTX_REG CANGIE
557 #define ENRX_REG CANGIE
558 #define ENBOFF_REG CANGIE
559 #define ENIT_REG CANGIE
562 #define TCNT0_0_REG TCNT0
563 #define TCNT0_1_REG TCNT0
564 #define TCNT0_2_REG TCNT0
565 #define TCNT0_3_REG TCNT0
566 #define TCNT0_4_REG TCNT0
567 #define TCNT0_5_REG TCNT0
568 #define TCNT0_6_REG TCNT0
569 #define TCNT0_7_REG TCNT0
572 #define IEMOB0_REG CANIE2
573 #define IEMOB1_REG CANIE2
574 #define IEMOB2_REG CANIE2
575 #define IEMOB3_REG CANIE2
576 #define IEMOB4_REG CANIE2
577 #define IEMOB5_REG CANIE2
580 #define SIT0_REG CANSIT2
581 #define SIT1_REG CANSIT2
582 #define SIT2_REG CANSIT2
583 #define SIT3_REG CANSIT2
584 #define SIT4_REG CANSIT2
585 #define SIT5_REG CANSIT2
588 #define CS00_REG TCCR0B
589 #define CS01_REG TCCR0B
590 #define CS02_REG TCCR0B
591 #define WGM02_REG TCCR0B
592 #define FOC0B_REG TCCR0B
593 #define FOC0A_REG TCCR0B
596 #define WGM00_REG TCCR0A
597 #define WGM01_REG TCCR0A
598 #define COM0B0_REG TCCR0A
599 #define COM0B1_REG TCCR0A
600 #define COM0A0_REG TCCR0A
601 #define COM0A1_REG TCCR0A
604 #define SPR0_REG SPCR
605 #define SPR1_REG SPCR
606 #define CPHA_REG SPCR
607 #define CPOL_REG SPCR
608 #define MSTR_REG SPCR
609 #define DORD_REG SPCR
611 #define SPIE_REG SPCR
614 #define TOV1_REG TIFR1
615 #define OCF1A_REG TIFR1
616 #define OCF1B_REG TIFR1
617 #define ICF1_REG TIFR1
620 #define RB0TAG_REG CANIDT4
621 #define RB1TAG_REG CANIDT4
622 #define RTRTAG_REG CANIDT4
623 #define IDT0_REG CANIDT4
624 #define IDT1_REG CANIDT4
625 #define IDT2_REG CANIDT4
626 #define IDT3_REG CANIDT4
627 #define IDT4_REG CANIDT4
630 #define IDT13_REG CANIDT2
631 #define IDT14_REG CANIDT2
632 #define IDT15_REG CANIDT2
633 #define IDT16_REG CANIDT2
634 #define IDT17_REG CANIDT2
635 #define IDT18_REG CANIDT2
636 #define IDT19_REG CANIDT2
637 #define IDT20_REG CANIDT2
640 #define IDT5_REG CANIDT3
641 #define IDT6_REG CANIDT3
642 #define IDT7_REG CANIDT3
643 #define IDT8_REG CANIDT3
644 #define IDT9_REG CANIDT3
645 #define IDT10_REG CANIDT3
646 #define IDT11_REG CANIDT3
647 #define IDT12_REG CANIDT3
650 #define IDT21_REG CANIDT1
651 #define IDT22_REG CANIDT1
652 #define IDT23_REG CANIDT1
653 #define IDT24_REG CANIDT1
654 #define IDT25_REG CANIDT1
655 #define IDT26_REG CANIDT1
656 #define IDT27_REG CANIDT1
657 #define IDT28_REG CANIDT1
660 #define PSR10_REG GTCCR
661 #define ICPSEL1_REG GTCCR
662 #define TSM_REG GTCCR
663 #define PSRSYNC_REG GTCCR
666 #define DLC0_REG CANCDMOB
667 #define DLC1_REG CANCDMOB
668 #define DLC2_REG CANCDMOB
669 #define DLC3_REG CANCDMOB
670 #define IDE_REG CANCDMOB
671 #define RPLV_REG CANCDMOB
672 #define CONMOB0_REG CANCDMOB
673 #define CONMOB1_REG CANCDMOB
686 #define CGP0_REG CANHPMOB
687 #define CGP1_REG CANHPMOB
688 #define CGP2_REG CANHPMOB
689 #define CGP3_REG CANHPMOB
690 #define HPMOB0_REG CANHPMOB
691 #define HPMOB1_REG CANHPMOB
692 #define HPMOB2_REG CANHPMOB
693 #define HPMOB3_REG CANHPMOB
696 #define OCR1BL0_REG OCR1BL
697 #define OCR1BL1_REG OCR1BL
698 #define OCR1BL2_REG OCR1BL
699 #define OCR1BL3_REG OCR1BL
700 #define OCR1BL4_REG OCR1BL
701 #define OCR1BL5_REG OCR1BL
702 #define OCR1BL6_REG OCR1BL
703 #define OCR1BL7_REG OCR1BL
706 #define OCR1BH0_REG OCR1BH
707 #define OCR1BH1_REG OCR1BH
708 #define OCR1BH2_REG OCR1BH
709 #define OCR1BH3_REG OCR1BH
710 #define OCR1BH4_REG OCR1BH
711 #define OCR1BH5_REG OCR1BH
712 #define OCR1BH6_REG OCR1BH
713 #define OCR1BH7_REG OCR1BH
726 #define PORF_REG MCUSR
727 #define EXTRF_REG MCUSR
728 #define BORF_REG MCUSR
729 #define WDRF_REG MCUSR
732 #define EERE_REG EECR
733 #define EEWE_REG EECR
734 #define EEMWE_REG EECR
735 #define EERIE_REG EECR
736 #define EEPM0_REG EECR
737 #define EEPM1_REG EECR
740 #define LENRXOK_REG LINENIR
741 #define LENTXOK_REG LINENIR
742 #define LENIDOK_REG LINENIR
743 #define LENERR_REG LINENIR
752 #define DAEN_REG DACON
753 #define DALA_REG DACON
754 #define DATS0_REG DACON
755 #define DATS1_REG DACON
756 #define DATS2_REG DACON
757 #define DAATE_REG DACON
760 #define PCIF0_REG PCIFR
761 #define PCIF1_REG PCIFR
762 #define PCIF2_REG PCIFR
763 #define PCIF3_REG PCIFR
766 #define AMP2TS0_REG AMP2CSR
767 #define AMP2TS1_REG AMP2CSR
768 #define AMP2TS2_REG AMP2CSR
769 #define AMPCMP2_REG AMP2CSR
770 #define AMP2G0_REG AMP2CSR
771 #define AMP2G1_REG AMP2CSR
772 #define AMP2IS_REG AMP2CSR
773 #define AMP2EN_REG AMP2CSR
776 #define LDATA0_REG LINDAT
777 #define LDATA1_REG LINDAT
778 #define LDATA2_REG LINDAT
779 #define LDATA3_REG LINDAT
780 #define LDATA4_REG LINDAT
781 #define LDATA5_REG LINDAT
782 #define LDATA6_REG LINDAT
783 #define LDATA7_REG LINDAT
786 #define EEAR8_REG EEARH
787 #define EEAR9_REG EEARH
790 #define INDX0_REG CANPAGE
791 #define INDX1_REG CANPAGE
792 #define INDX2_REG CANPAGE
793 #define AINC_REG CANPAGE
794 #define MOBNB0_REG CANPAGE
795 #define MOBNB1_REG CANPAGE
796 #define MOBNB2_REG CANPAGE
797 #define MOBNB3_REG CANPAGE
800 #define LRXDL0_REG LINDLR
801 #define LRXDL1_REG LINDLR
802 #define LRXDL2_REG LINDLR
803 #define LRXDL3_REG LINDLR
804 #define LTXDL0_REG LINDLR
805 #define LTXDL1_REG LINDLR
806 #define LTXDL2_REG LINDLR
807 #define LTXDL3_REG LINDLR
810 #define IVCE_REG MCUCR
811 #define IVSEL_REG MCUCR
812 #define PUD_REG MCUCR
813 #define SPIPS_REG MCUCR
816 #define INTF0_REG EIFR
817 #define INTF1_REG EIFR
818 #define INTF2_REG EIFR
819 #define INTF3_REG EIFR
822 #define AERR_REG CANSTMOB
823 #define FERR_REG CANSTMOB
824 #define CERR_REG CANSTMOB
825 #define SERR_REG CANSTMOB
826 #define BERR_REG CANSTMOB
827 #define RXOK_REG CANSTMOB
828 #define TXOK_REG CANSTMOB
829 #define DLCW_REG CANSTMOB
832 #define DACH0_REG DACH
833 #define DACH1_REG DACH
834 #define DACH2_REG DACH
835 #define DACH3_REG DACH
836 #define DACH4_REG DACH
837 #define DACH5_REG DACH
838 #define DACH6_REG DACH
839 #define DACH7_REG DACH
842 #define ADPS0_REG ADCSRA
843 #define ADPS1_REG ADCSRA
844 #define ADPS2_REG ADCSRA
845 #define ADIE_REG ADCSRA
846 #define ADIF_REG ADCSRA
847 #define ADATE_REG ADCSRA
848 #define ADSC_REG ADCSRA
849 #define ADEN_REG ADCSRA
852 #define ENMOB0_REG CANEN2
853 #define ENMOB1_REG CANEN2
854 #define ENMOB2_REG CANEN2
855 #define ENMOB3_REG CANEN2
856 #define ENMOB4_REG CANEN2
857 #define ENMOB5_REG CANEN2
860 #define ADTS0_REG ADCSRB
861 #define ADTS1_REG ADCSRB
862 #define ADTS2_REG ADCSRB
863 #define ADTS3_REG ADCSRB
864 #define AREFEN_REG ADCSRB
865 #define ISRCEN_REG ADCSRB
866 #define ADHSM_REG ADCSRB
869 /* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
870 /* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
871 /* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
872 /* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
873 /* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
874 /* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
875 /* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
876 /* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
879 /* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
880 /* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
881 /* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
882 /* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
883 /* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
884 /* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
885 /* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
886 /* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
889 #define TCNT1L0_REG TCNT1L
890 #define TCNT1L1_REG TCNT1L
891 #define TCNT1L2_REG TCNT1L
892 #define TCNT1L3_REG TCNT1L
893 #define TCNT1L4_REG TCNT1L
894 #define TCNT1L5_REG TCNT1L
895 #define TCNT1L6_REG TCNT1L
896 #define TCNT1L7_REG TCNT1L
899 #define DDD0_REG DDRD
900 #define DDD1_REG DDRD
901 #define DDD2_REG DDRD
902 #define DDD3_REG DDRD
903 #define DDD4_REG DDRD
904 #define DDD5_REG DDRD
905 #define DDD6_REG DDRD
906 #define DDD7_REG DDRD
909 #define DDE0_REG DDRE
910 #define DDE1_REG DDRE
911 #define DDE2_REG DDRE
914 #define SPMEN_REG SPMCSR
915 #define PGERS_REG SPMCSR
916 #define PGWRT_REG SPMCSR
917 #define BLBSET_REG SPMCSR
918 #define RWWSRE_REG SPMCSR
919 #define SIGRD_REG SPMCSR
920 #define RWWSB_REG SPMCSR
921 #define SPMIE_REG SPMCSR
924 #define PRS0_REG CANBT2
925 #define PRS1_REG CANBT2
926 #define PRS2_REG CANBT2
927 #define SJW0_REG CANBT2
928 #define SJW1_REG CANBT2
931 #define SMP_REG CANBT3
932 #define PHS10_REG CANBT3
933 #define PHS11_REG CANBT3
934 #define PHS12_REG CANBT3
935 #define PHS20_REG CANBT3
936 #define PHS21_REG CANBT3
937 #define PHS22_REG CANBT3
940 #define ADCL0_REG ADCL
941 #define ADCL1_REG ADCL
942 #define ADCL2_REG ADCL
943 #define ADCL3_REG ADCL
944 #define ADCL4_REG ADCL
945 #define ADCL5_REG ADCL
946 #define ADCL6_REG ADCL
947 #define ADCL7_REG ADCL
950 #define BRP0_REG CANBT1
951 #define BRP1_REG CANBT1
952 #define BRP2_REG CANBT1
953 #define BRP3_REG CANBT1
954 #define BRP4_REG CANBT1
955 #define BRP5_REG CANBT1
958 #define ADCH0_REG ADCH
959 #define ADCH1_REG ADCH
960 #define ADCH2_REG ADCH
961 #define ADCH3_REG ADCH
962 #define ADCH4_REG ADCH
963 #define ADCH5_REG ADCH
964 #define ADCH6_REG ADCH
965 #define ADCH7_REG ADCH
968 #define DACL0_REG DACL
969 #define DACL1_REG DACL
970 #define DACL2_REG DACL
971 #define DACL3_REG DACL
972 #define DACL4_REG DACL
973 #define DACL5_REG DACL
974 #define DACL6_REG DACL
975 #define DACL7_REG DACL
978 #define TOIE0_REG TIMSK0
979 #define OCIE0A_REG TIMSK0
980 #define OCIE0B_REG TIMSK0
983 #define TOIE1_REG TIMSK1
984 #define OCIE1A_REG TIMSK1
985 #define OCIE1B_REG TIMSK1
986 #define ICIE1_REG TIMSK1
989 #define AMP0TS0_REG AMP0CSR
990 #define AMP0TS1_REG AMP0CSR
991 #define AMP0TS2_REG AMP0CSR
992 #define AMPCMP0_REG AMP0CSR
993 #define AMP0G0_REG AMP0CSR
994 #define AMP0G1_REG AMP0CSR
995 #define AMP0IS_REG AMP0CSR
996 #define AMP0EN_REG AMP0CSR
999 #define PLOCK_REG PLLCSR
1000 #define PLLE_REG PLLCSR
1001 #define PLLF_REG PLLCSR
1004 #define PCINT0_REG PCMSK0
1005 #define PCINT1_REG PCMSK0
1006 #define PCINT2_REG PCMSK0
1007 #define PCINT3_REG PCMSK0
1008 #define PCINT4_REG PCMSK0
1009 #define PCINT5_REG PCMSK0
1010 #define PCINT6_REG PCMSK0
1011 #define PCINT7_REG PCMSK0
1014 #define PCINT8_REG PCMSK1
1015 #define PCINT9_REG PCMSK1
1016 #define PCINT10_REG PCMSK1
1017 #define PCINT11_REG PCMSK1
1018 #define PCINT12_REG PCMSK1
1019 #define PCINT13_REG PCMSK1
1020 #define PCINT14_REG PCMSK1
1021 #define PCINT15_REG PCMSK1
1024 #define PCINT16_REG PCMSK2
1025 #define PCINT17_REG PCMSK2
1026 #define PCINT18_REG PCMSK2
1027 #define PCINT19_REG PCMSK2
1028 #define PCINT20_REG PCMSK2
1029 #define PCINT21_REG PCMSK2
1030 #define PCINT22_REG PCMSK2
1031 #define PCINT23_REG PCMSK2
1034 #define PCINT24_REG PCMSK3
1035 #define PCINT25_REG PCMSK3
1036 #define PCINT26_REG PCMSK3
1039 #define PINC0_REG PINC
1040 #define PINC1_REG PINC
1041 #define PINC2_REG PINC
1042 #define PINC3_REG PINC
1043 #define PINC4_REG PINC
1044 #define PINC5_REG PINC
1045 #define PINC6_REG PINC
1046 #define PINC7_REG PINC
1049 #define PINB0_REG PINB
1050 #define PINB1_REG PINB
1051 #define PINB2_REG PINB
1052 #define PINB3_REG PINB
1053 #define PINB4_REG PINB
1054 #define PINB5_REG PINB
1055 #define PINB6_REG PINB
1056 #define PINB7_REG PINB
1059 #define AC0M0_REG AC0CON
1060 #define AC0M1_REG AC0CON
1061 #define AC0M2_REG AC0CON
1062 #define ACCKSEL_REG AC0CON
1063 #define AC0IS0_REG AC0CON
1064 #define AC0IS1_REG AC0CON
1065 #define AC0IE_REG AC0CON
1066 #define AC0EN_REG AC0CON
1069 #define PINE0_REG PINE
1070 #define PINE1_REG PINE
1071 #define PINE2_REG PINE
1074 #define PIND0_REG PIND
1075 #define PIND1_REG PIND
1076 #define PIND2_REG PIND
1077 #define PIND3_REG PIND
1078 #define PIND4_REG PIND
1079 #define PIND5_REG PIND
1080 #define PIND6_REG PIND
1081 #define PIND7_REG PIND
1084 #define OCR1AH0_REG OCR1AH
1085 #define OCR1AH1_REG OCR1AH
1086 #define OCR1AH2_REG OCR1AH
1087 #define OCR1AH3_REG OCR1AH
1088 #define OCR1AH4_REG OCR1AH
1089 #define OCR1AH5_REG OCR1AH
1090 #define OCR1AH6_REG OCR1AH
1091 #define OCR1AH7_REG OCR1AH
1094 #define OCR1AL0_REG OCR1AL
1095 #define OCR1AL1_REG OCR1AL
1096 #define OCR1AL2_REG OCR1AL
1097 #define OCR1AL3_REG OCR1AL
1098 #define OCR1AL4_REG OCR1AL
1099 #define OCR1AL5_REG OCR1AL
1100 #define OCR1AL6_REG OCR1AL
1101 #define OCR1AL7_REG OCR1AL
1104 #define TOV0_REG TIFR0
1105 #define OCF0A_REG TIFR0
1106 #define OCF0B_REG TIFR0
1109 #define MISO_PORT PORTB
1111 #define PCINT0_PORT PORTB
1112 #define PCINT0_BIT 0
1114 #define MOSI_PORT PORTB
1116 #define PCINT1_PORT PORTB
1117 #define PCINT1_BIT 1
1119 #define ADC5_PORT PORTB
1121 #define INT1_PORT PORTB
1123 #define ACMPN0_PORT PORTB
1124 #define ACMPN0_BIT 2
1125 #define PCINT2_PORT PORTB
1126 #define PCINT2_BIT 2
1128 #define AMP0-_PORT PORTB
1130 #define PCINT3_PORT PORTB
1131 #define PCINT3_BIT 3
1133 #define AMP0+_PORT PORTB
1135 #define PCINT4_PORT PORTB
1136 #define PCINT4_BIT 4
1138 #define ADC6_PORT PORTB
1140 #define INT2_PORT PORTB
1142 #define ACMPN1_PORT PORTB
1143 #define ACMPN1_BIT 5
1144 #define AMP2-_PORT PORTB
1146 #define PCINT5_PORT PORTB
1147 #define PCINT5_BIT 5
1149 #define ADC7_PORT PORTB
1151 #define PCINT6_PORT PORTB
1152 #define PCINT6_BIT 6
1154 #define ADC4_PORT PORTB
1156 #define SCK_PORT PORTB
1158 #define PCINT7_PORT PORTB
1159 #define PCINT7_BIT 7
1161 #define INT3_PORT PORTC
1163 #define PCINT8_PORT PORTC
1164 #define PCINT8_BIT 0
1166 #define OC1B_PORT PORTC
1168 #define SS_A_PORT PORTC
1170 #define PCINT9_PORT PORTC
1171 #define PCINT9_BIT 1
1173 #define T0_PORT PORTC
1175 #define TXCAN_PORT PORTC
1177 #define PCINT10_PORT PORTC
1178 #define PCINT10_BIT 2
1180 #define T1_PORT PORTC
1182 #define RXCAN_PORT PORTC
1184 #define ICP1B_PORT PORTC
1186 #define PCINT11_PORT PORTC
1187 #define PCINT11_BIT 3
1189 #define ADC8_PORT PORTC
1191 #define AMP1-_PORT PORTC
1193 #define ACMPN3_PORT PORTC
1194 #define ACMPN3_BIT 4
1195 #define PCINT12_PORT PORTC
1196 #define PCINT12_BIT 4
1198 #define ADC9_PORT PORTC
1200 #define AMP1+_PORT PORTC
1202 #define ACMP3_PORT PORTC
1204 #define PCINT13_PORT PORTC
1205 #define PCINT13_BIT 5
1207 #define ADC10_PORT PORTC
1209 #define ACMP1_PORT PORTC
1211 #define PCINT14_PORT PORTC
1212 #define PCINT14_BIT 6
1214 #define D2A_PORT PORTC
1216 #define AMP2+_PORT PORTC
1218 #define PCINT15_PORT PORTC
1219 #define PCINT15_BIT 7
1221 #define PCINT16_PORT PORTD
1222 #define PCINT16_BIT 0
1224 #define CLK0_PORT PORTD
1226 #define PCINT17_PORT PORTD
1227 #define PCINT17_BIT 1
1229 #define OC1A_PORT PORTD
1231 #define MISO_A_PORT PORTD
1232 #define MISO_A_BIT 2
1233 #define PCINT18_PORT PORTD
1234 #define PCINT18_BIT 2
1236 #define TXD_PORT PORTD
1238 #define TXLIN_PORT PORTD
1240 #define OC0A_PORT PORTD
1242 #define SS_PORT PORTD
1244 #define MOSI_A_PORT PORTD
1245 #define MOSI_A_BIT 3
1246 #define PCINT19_PORT PORTD
1247 #define PCINT19_BIT 3
1249 #define ADC1_PORT PORTD
1251 #define RXD_PORT PORTD
1253 #define RXLIN_PORT PORTD
1255 #define ICP1A_PORT PORTD
1257 #define SCK_A_PORT PORTD
1259 #define PCINT20_PORT PORTD
1260 #define PCINT20_BIT 4
1262 #define ADC2_PORT PORTD
1264 #define ACMP2_PORT PORTD
1266 #define PCINT21_PORT PORTD
1267 #define PCINT21_BIT 5
1269 #define ADC3_PORT PORTD
1271 #define ACMPN2_PORT PORTD
1272 #define ACMPN2_BIT 6
1273 #define INT0_PORT PORTD
1275 #define PCINT22_PORT PORTD
1276 #define PCINT22_BIT 6
1278 #define ACMP0_PORT PORTD
1280 #define PCINT23_PORT PORTD
1281 #define PCINT23_BIT 7
1283 #define RESET_PORT PORTE
1285 #define OCD_PORT PORTE
1287 #define PCINT24_PORT PORTE
1288 #define PCINT24_BIT 0
1290 #define OC0B_PORT PORTE
1292 #define XTAL1_PORT PORTE
1294 #define PCINT25_PORT PORTE
1295 #define PCINT25_BIT 1
1297 #define ADC0_PORT PORTE
1299 #define XTAL2_PORT PORTE
1301 #define PCINT26_PORT PORTE
1302 #define PCINT26_BIT 2