2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER0A_AVAILABLE
69 #define TIMER0B_AVAILABLE
70 #define TIMER1_AVAILABLE
71 #define TIMER1A_AVAILABLE
72 #define TIMER1B_AVAILABLE
74 /* overflow interrupt number */
75 #define SIG_OVERFLOW0_NUM 0
76 #define SIG_OVERFLOW1_NUM 1
77 #define SIG_OVERFLOW_TOTAL_NUM 2
79 /* output compare interrupt number */
80 #define SIG_OUTPUT_COMPARE0A_NUM 0
81 #define SIG_OUTPUT_COMPARE0B_NUM 1
82 #define SIG_OUTPUT_COMPARE1A_NUM 2
83 #define SIG_OUTPUT_COMPARE1B_NUM 3
84 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
91 #define PWM_TOTAL_NUM 4
93 /* input capture interrupt number */
94 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
98 #define CADAC16_REG CADAC2
99 #define CADAC17_REG CADAC2
100 #define CADAC18_REG CADAC2
101 #define CADAC19_REG CADAC2
102 #define CADAC20_REG CADAC2
103 #define CADAC21_REG CADAC2
104 #define CADAC22_REG CADAC2
105 #define CADAC23_REG CADAC2
108 #define CADAC24_REG CADAC3
109 #define CADAC25_REG CADAC3
110 #define CADAC26_REG CADAC3
111 #define CADAC27_REG CADAC3
112 #define CADAC28_REG CADAC3
113 #define CADAC29_REG CADAC3
114 #define CADAC30_REG CADAC3
115 #define CADAC31_REG CADAC3
118 #define CADAC00_REG CADAC0
119 #define CADAC01_REG CADAC0
120 #define CADAC02_REG CADAC0
121 #define CADAC03_REG CADAC0
122 #define CADAC04_REG CADAC0
123 #define CADAC05_REG CADAC0
124 #define CADAC06_REG CADAC0
125 #define CADAC07_REG CADAC0
128 #define CADAC08_REG CADAC1
129 #define CADAC09_REG CADAC1
130 #define CADAC10_REG CADAC1
131 #define CADAC11_REG CADAC1
132 #define CADAC12_REG CADAC1
133 #define CADAC13_REG CADAC1
134 #define CADAC14_REG CADAC1
135 #define CADAC15_REG CADAC1
138 #define CHCIE_REG BPIMSK
139 #define DHCIE_REG BPIMSK
140 #define COCIE_REG BPIMSK
141 #define DOCIE_REG BPIMSK
142 #define SCIE_REG BPIMSK
145 #define TCNT0H0_REG TCNT0H
146 #define TCNT0H1_REG TCNT0H
147 #define TCNT0H2_REG TCNT0H
148 #define TCNT0H3_REG TCNT0H
149 #define TCNT0H4_REG TCNT0H
150 #define TCNT0H5_REG TCNT0H
151 #define TCNT0H6_REG TCNT0H
152 #define TCNT0H7_REG TCNT0H
155 #define TCNT0L0_REG TCNT0L
156 #define TCNT0L1_REG TCNT0L
157 #define TCNT0L2_REG TCNT0L
158 #define TCNT0L3_REG TCNT0L
159 #define TCNT0L4_REG TCNT0L
160 #define TCNT0L5_REG TCNT0L
161 #define TCNT0L6_REG TCNT0L
162 #define TCNT0L7_REG TCNT0L
165 #define WDP0_REG WDTCSR
166 #define WDP1_REG WDTCSR
167 #define WDP2_REG WDTCSR
168 #define WDE_REG WDTCSR
169 #define WDCE_REG WDTCSR
170 #define WDP3_REG WDTCSR
171 #define WDIE_REG WDTCSR
172 #define WDIF_REG WDTCSR
175 #define EEDR0_REG EEDR
176 #define EEDR1_REG EEDR
177 #define EEDR2_REG EEDR
178 #define EEDR3_REG EEDR
179 #define EEDR4_REG EEDR
180 #define EEDR5_REG EEDR
181 #define EEDR6_REG EEDR
182 #define EEDR7_REG EEDR
185 #define SPDR0_REG SPDR
186 #define SPDR1_REG SPDR
187 #define SPDR2_REG SPDR
188 #define SPDR3_REG SPDR
189 #define SPDR4_REG SPDR
190 #define SPDR5_REG SPDR
191 #define SPDR6_REG SPDR
192 #define SPDR7_REG SPDR
195 #define SPI2X_REG SPSR
196 #define WCOL_REG SPSR
197 #define SPIF_REG SPSR
220 #define COCDL0_REG BPCOCD
221 #define COCDL1_REG BPCOCD
222 #define COCDL2_REG BPCOCD
223 #define COCDL3_REG BPCOCD
224 #define COCDL4_REG BPCOCD
225 #define COCDL5_REG BPCOCD
226 #define COCDL6_REG BPCOCD
227 #define COCDL7_REG BPCOCD
230 #define TWPS0_REG TWSR
231 #define TWPS1_REG TWSR
232 #define TWS3_REG TWSR
233 #define TWS4_REG TWSR
234 #define TWS5_REG TWSR
235 #define TWS6_REG TWSR
236 #define TWS7_REG TWSR
239 #define TCNT1L0_REG TCNT1L
240 #define TCNT1L1_REG TCNT1L
241 #define TCNT1L2_REG TCNT1L
242 #define TCNT1L3_REG TCNT1L
243 #define TCNT1L4_REG TCNT1L
244 #define TCNT1L5_REG TCNT1L
245 #define TCNT1L6_REG TCNT1L
246 #define TCNT1L7_REG TCNT1L
249 #define TCNT1H0_REG TCNT1H
250 #define TCNT1H1_REG TCNT1H
251 #define TCNT1H2_REG TCNT1H
252 #define TCNT1H3_REG TCNT1H
253 #define TCNT1H4_REG TCNT1H
254 #define TCNT1H5_REG TCNT1H
255 #define TCNT1H6_REG TCNT1H
256 #define TCNT1H7_REG TCNT1H
259 #define PORTC0_REG PORTC
260 #define PORTC1_REG PORTC
261 #define PORTC2_REG PORTC
262 #define PORTC3_REG PORTC
263 #define PORTC4_REG PORTC
264 #define PORTC5_REG PORTC
267 #define PORTA0_REG PORTA
268 #define PORTA1_REG PORTA
269 #define PORTA2_REG PORTA
270 #define PORTA3_REG PORTA
273 #define SCDL0_REG BPSCD
274 #define SCDL1_REG BPSCD
275 #define SCDL2_REG BPSCD
276 #define SCDL3_REG BPSCD
277 #define SCDL4_REG BPSCD
278 #define SCDL5_REG BPSCD
279 #define SCDL6_REG BPSCD
280 #define SCDL7_REG BPSCD
283 #define GPIOR00_REG GPIOR0
284 #define GPIOR01_REG GPIOR0
285 #define GPIOR02_REG GPIOR0
286 #define GPIOR03_REG GPIOR0
287 #define GPIOR04_REG GPIOR0
288 #define GPIOR05_REG GPIOR0
289 #define GPIOR06_REG GPIOR0
290 #define GPIOR07_REG GPIOR0
293 #define VADC8_REG VADCH
294 #define VADC9_REG VADCH
295 #define VADC10_REG VADCH
296 #define VADC11_REG VADCH
299 #define VADC0_REG VADCL
300 #define VADC1_REG VADCL
301 #define VADC2_REG VADCL
302 #define VADC3_REG VADCL
303 #define VADC4_REG VADCL
304 #define VADC5_REG VADCL
305 #define VADC6_REG VADCL
306 #define VADC7_REG VADCL
309 #define ISC00_REG EICRA
310 #define ISC01_REG EICRA
311 #define ISC10_REG EICRA
312 #define ISC11_REG EICRA
313 #define ISC20_REG EICRA
314 #define ISC21_REG EICRA
315 #define ISC30_REG EICRA
316 #define ISC31_REG EICRA
319 #define FCAL0_REG FOSCCAL
320 #define FCAL1_REG FOSCCAL
321 #define FCAL2_REG FOSCCAL
322 #define FCAL3_REG FOSCCAL
323 #define FCAL4_REG FOSCCAL
324 #define FCAL5_REG FOSCCAL
325 #define FCAL6_REG FOSCCAL
326 #define FCAL7_REG FOSCCAL
329 #define PA0DID_REG DIDR0
330 #define PA1DID_REG DIDR0
333 #define OCR1A0_REG OCR1A
334 #define OCR1A1_REG OCR1A
335 #define OCR1A2_REG OCR1A
336 #define OCR1A3_REG OCR1A
337 #define OCR1A4_REG OCR1A
338 #define OCR1A5_REG OCR1A
339 #define OCR1A6_REG OCR1A
340 #define OCR1A7_REG OCR1A
343 #define CLKPS0_REG CLKPR
344 #define CLKPS1_REG CLKPR
345 #define CLKPCE_REG CLKPR
348 #define OCR1B0_REG OCR1B
349 #define OCR1B1_REG OCR1B
350 #define OCR1B2_REG OCR1B
351 #define OCR1B3_REG OCR1B
352 #define OCR1B4_REG OCR1B
353 #define OCR1B5_REG OCR1B
354 #define OCR1B6_REG OCR1B
355 #define OCR1B7_REG OCR1B
368 #define CHCD_REG BPCR
369 #define DHCD_REG BPCR
370 #define COCD_REG BPCR
371 #define DOCD_REG BPCR
373 #define EPID_REG BPCR
376 #define DDB0_REG DDRB
377 #define DDB1_REG DDRB
378 #define DDB2_REG DDRB
379 #define DDB3_REG DDRB
380 #define DDB4_REG DDRB
381 #define DDB5_REG DDRB
382 #define DDB6_REG DDRB
383 #define DDB7_REG DDRB
386 #define DDA0_REG DDRA
387 #define DDA1_REG DDRA
388 #define DDA2_REG DDRA
389 #define DDA3_REG DDRA
392 #define WGM10_REG TCCR1A
393 #define ICS1_REG TCCR1A
394 #define ICES1_REG TCCR1A
395 #define ICNC1_REG TCCR1A
396 #define ICEN1_REG TCCR1A
397 #define TCW1_REG TCCR1A
400 #define CS10_REG TCCR1B
401 #define CS11_REG TCCR1B
402 #define CS12_REG TCCR1B
405 #define CHCDL0_REG BPCHCD
406 #define CHCDL1_REG BPCHCD
407 #define CHCDL2_REG BPCHCD
408 #define CHCDL3_REG BPCHCD
409 #define CHCDL4_REG BPCHCD
410 #define CHCDL5_REG BPCHCD
411 #define CHCDL6_REG BPCHCD
412 #define CHCDL7_REG BPCHCD
415 #define CADVSE_REG CADCSRC
418 #define CADICIF_REG CADCSRB
419 #define CADRCIF_REG CADCSRB
420 #define CADACIF_REG CADCSRB
421 #define CADICIE_REG CADCSRB
422 #define CADRCIE_REG CADCSRB
423 #define CADACIE_REG CADCSRB
426 #define CADSE_REG CADCSRA
427 #define CADSI0_REG CADCSRA
428 #define CADSI1_REG CADCSRA
429 #define CADAS0_REG CADCSRA
430 #define CADAS1_REG CADCSRA
431 #define CADUB_REG CADCSRA
432 #define CADPOL_REG CADCSRA
433 #define CADEN_REG CADCSRA
436 #define GPIOR10_REG GPIOR1
437 #define GPIOR11_REG GPIOR1
438 #define GPIOR12_REG GPIOR1
439 #define GPIOR13_REG GPIOR1
440 #define GPIOR14_REG GPIOR1
441 #define GPIOR15_REG GPIOR1
442 #define GPIOR16_REG GPIOR1
443 #define GPIOR17_REG GPIOR1
446 #define BPPL_REG BPPLR
447 #define BPPLE_REG BPPLR
450 #define GPIOR20_REG GPIOR2
451 #define GPIOR21_REG GPIOR2
452 #define GPIOR22_REG GPIOR2
453 #define GPIOR23_REG GPIOR2
454 #define GPIOR24_REG GPIOR2
455 #define GPIOR25_REG GPIOR2
456 #define GPIOR26_REG GPIOR2
457 #define GPIOR27_REG GPIOR2
460 #define CADRDC0_REG CADRDC
461 #define CADRDC1_REG CADRDC
462 #define CADRDC2_REG CADRDC
463 #define CADRDC3_REG CADRDC
464 #define CADRDC4_REG CADRDC
465 #define CADRDC5_REG CADRDC
466 #define CADRDC6_REG CADRDC
467 #define CADRDC7_REG CADRDC
470 #define PCIE0_REG PCICR
471 #define PCIE1_REG PCICR
474 #define TWGCE_REG TWAR
475 #define TWA0_REG TWAR
476 #define TWA1_REG TWAR
477 #define TWA2_REG TWAR
478 #define TWA3_REG TWAR
479 #define TWA4_REG TWAR
480 #define TWA5_REG TWAR
481 #define TWA6_REG TWAR
484 #define CS00_REG TCCR0B
485 #define CS01_REG TCCR0B
486 #define CS02_REG TCCR0B
489 #define WGM00_REG TCCR0A
490 #define ICS0_REG TCCR0A
491 #define ICES0_REG TCCR0A
492 #define ICNC0_REG TCCR0A
493 #define ICEN0_REG TCCR0A
494 #define TCW0_REG TCCR0A
497 #define DHCDL0_REG BPDHCD
498 #define DHCDL1_REG BPDHCD
499 #define DHCDL2_REG BPDHCD
500 #define DHCDL3_REG BPDHCD
501 #define DHCDL4_REG BPDHCD
502 #define DHCDL5_REG BPDHCD
503 #define DHCDL6_REG BPDHCD
504 #define DHCDL7_REG BPDHCD
507 #define TWBCIP_REG TWBCSR
508 #define TWBDT0_REG TWBCSR
509 #define TWBDT1_REG TWBCSR
510 #define TWBCIE_REG TWBCSR
511 #define TWBCIF_REG TWBCSR
514 #define SPR0_REG SPCR
515 #define SPR1_REG SPCR
516 #define CPHA_REG SPCR
517 #define CPOL_REG SPCR
518 #define MSTR_REG SPCR
519 #define DORD_REG SPCR
521 #define SPIE_REG SPCR
524 #define TOV1_REG TIFR1
525 #define OCF1A_REG TIFR1
526 #define OCF1B_REG TIFR1
527 #define ICF1_REG TIFR1
530 #define PSRSYNC_REG GTCCR
531 #define TSM_REG GTCCR
534 #define TWBR0_REG TWBR
535 #define TWBR1_REG TWBR
536 #define TWBR2_REG TWBR
537 #define TWBR3_REG TWBR
538 #define TWBR4_REG TWBR
539 #define TWBR5_REG TWBR
540 #define TWBR6_REG TWBR
541 #define TWBR7_REG TWBR
544 #define BGCR0_REG BGCRR
545 #define BGCR1_REG BGCRR
546 #define BGCR2_REG BGCRR
547 #define BGCR3_REG BGCRR
548 #define BGCR4_REG BGCRR
549 #define BGCR5_REG BGCRR
550 #define BGCR6_REG BGCRR
551 #define BGCR7_REG BGCRR
554 #define PCIF0_REG PCIFR
555 #define PCIF1_REG PCIFR
561 #define DUVRD_REG FCSR
564 #define VADMUX0_REG VADMUX
565 #define VADMUX1_REG VADMUX
566 #define VADMUX2_REG VADMUX
567 #define VADMUX3_REG VADMUX
570 #define PORF_REG MCUSR
571 #define EXTRF_REG MCUSR
572 #define BODRF_REG MCUSR
573 #define WDRF_REG MCUSR
574 #define OCDRF_REG MCUSR
577 #define EERE_REG EECR
578 #define EEPE_REG EECR
579 #define EEMPE_REG EECR
580 #define EERIE_REG EECR
581 #define EEPM0_REG EECR
582 #define EEPM1_REG EECR
591 #define TWIE_REG TWCR
592 #define TWEN_REG TWCR
593 #define TWWC_REG TWCR
594 #define TWSTO_REG TWCR
595 #define TWSTA_REG TWCR
596 #define TWEA_REG TWCR
597 #define TWINT_REG TWCR
600 #define EEAR8_REG EEARH
601 #define EEAR9_REG EEARH
604 #define CHCIF_REG BPIFR
605 #define DHCIF_REG BPIFR
606 #define COCIF_REG BPIFR
607 #define DOCIF_REG BPIFR
608 #define SCIF_REG BPIFR
611 #define EEAR0_REG EEARL
612 #define EEAR1_REG EEARL
613 #define EEAR2_REG EEARL
614 #define EEAR3_REG EEARL
615 #define EEAR4_REG EEARL
616 #define EEAR5_REG EEARL
617 #define EEAR6_REG EEARL
618 #define EEAR7_REG EEARL
621 #define VADCCIE_REG VADCSR
622 #define VADCCIF_REG VADCSR
623 #define VADSC_REG VADCSR
624 #define VADEN_REG VADCSR
627 #define IVCE_REG MCUCR
628 #define IVSEL_REG MCUCR
629 #define PUD_REG MCUCR
630 #define CKOE_REG MCUCR
633 #define CBE1_REG CBCR
634 #define CBE2_REG CBCR
635 #define CBE3_REG CBCR
636 #define CBE4_REG CBCR
639 #define CADRCC0_REG CADRCC
640 #define CADRCC1_REG CADRCC
641 #define CADRCC2_REG CADRCC
642 #define CADRCC3_REG CADRCC
643 #define CADRCC4_REG CADRCC
644 #define CADRCC5_REG CADRCC
645 #define CADRCC6_REG CADRCC
646 #define CADRCC7_REG CADRCC
649 #define OCPT0_REG BPOCTR
650 #define OCPT1_REG BPOCTR
651 #define OCPT2_REG BPOCTR
652 #define OCPT3_REG BPOCTR
653 #define OCPT4_REG BPOCTR
654 #define OCPT5_REG BPOCTR
657 #define PINA0_REG PINA
658 #define PINA1_REG PINA
659 #define PINA2_REG PINA
660 #define PINA3_REG PINA
663 #define DOCDL0_REG BPDOCD
664 #define DOCDL1_REG BPDOCD
665 #define DOCDL2_REG BPDOCD
666 #define DOCDL3_REG BPDOCD
667 #define DOCDL4_REG BPDOCD
668 #define DOCDL5_REG BPDOCD
669 #define DOCDL6_REG BPDOCD
670 #define DOCDL7_REG BPDOCD
673 #define SCPT0_REG BPSCTR
674 #define SCPT1_REG BPSCTR
675 #define SCPT2_REG BPSCTR
676 #define SCPT3_REG BPSCTR
677 #define SCPT4_REG BPSCTR
678 #define SCPT5_REG BPSCTR
679 #define SCPT6_REG BPSCTR
682 #define TWD0_REG TWDR
683 #define TWD1_REG TWDR
684 #define TWD2_REG TWDR
685 #define TWD3_REG TWDR
686 #define TWD4_REG TWDR
687 #define TWD5_REG TWDR
688 #define TWD6_REG TWDR
689 #define TWD7_REG TWDR
692 #define HCPT0_REG BPHCTR
693 #define HCPT1_REG BPHCTR
694 #define HCPT2_REG BPHCTR
695 #define HCPT3_REG BPHCTR
696 #define HCPT4_REG BPHCTR
697 #define HCPT5_REG BPHCTR
700 #define INT0_REG EIMSK
701 #define INT1_REG EIMSK
702 #define INT2_REG EIMSK
703 #define INT3_REG EIMSK
706 #define PRVADC_REG PRR0
707 #define PRTIM0_REG PRR0
708 #define PRTIM1_REG PRR0
709 #define PRSPI_REG PRR0
710 #define PRVRM_REG PRR0
711 #define PRTWI_REG PRR0
714 #define OCR0A0_REG OCR0A
715 #define OCR0A1_REG OCR0A
716 #define OCR0A2_REG OCR0A
717 #define OCR0A3_REG OCR0A
718 #define OCR0A4_REG OCR0A
719 #define OCR0A5_REG OCR0A
720 #define OCR0A6_REG OCR0A
721 #define OCR0A7_REG OCR0A
724 #define ROCWIE_REG ROCR
725 #define ROCWIF_REG ROCR
726 #define ROCD_REG ROCR
727 #define ROCS_REG ROCR
730 #define OCR0B0_REG OCR0B
731 #define OCR0B1_REG OCR0B
732 #define OCR0B2_REG OCR0B
733 #define OCR0B3_REG OCR0B
734 #define OCR0B4_REG OCR0B
735 #define OCR0B5_REG OCR0B
736 #define OCR0B6_REG OCR0B
737 #define OCR0B7_REG OCR0B
740 #define CADICH0_REG CADICH
741 #define CADICH1_REG CADICH
742 #define CADICH2_REG CADICH
743 #define CADICH3_REG CADICH
744 #define CADICH4_REG CADICH
745 #define CADICH5_REG CADICH
746 #define CADICH6_REG CADICH
747 #define CADICH7_REG CADICH
750 #define CADICL0_REG CADICL
751 #define CADICL1_REG CADICL
752 #define CADICL2_REG CADICL
753 #define CADICL3_REG CADICL
754 #define CADICL4_REG CADICL
755 #define CADICL5_REG CADICL
756 #define CADICL6_REG CADICL
757 #define CADICL7_REG CADICL
760 #define OSIEN_REG OSICSR
761 #define OSIST_REG OSICSR
762 #define OSISEL0_REG OSICSR
765 #define SPMEN_REG SPMCSR
766 #define PGERS_REG SPMCSR
767 #define PGWRT_REG SPMCSR
768 #define LBSET_REG SPMCSR
769 #define RWWSRE_REG SPMCSR
770 #define SIGRD_REG SPMCSR
771 #define RWWSB_REG SPMCSR
772 #define SPMIE_REG SPMCSR
775 #define PORTB0_REG PORTB
776 #define PORTB1_REG PORTB
777 #define PORTB2_REG PORTB
778 #define PORTB3_REG PORTB
779 #define PORTB4_REG PORTB
780 #define PORTB5_REG PORTB
781 #define PORTB6_REG PORTB
782 #define PORTB7_REG PORTB
785 #define CHGDIE_REG CHGDCSR
786 #define CHGDIF_REG CHGDCSR
787 #define CHGDISC0_REG CHGDCSR
788 #define CHGDISC1_REG CHGDCSR
789 #define BATTPVL_REG CHGDCSR
792 #define TOIE0_REG TIMSK0
793 #define OCIE0A_REG TIMSK0
794 #define OCIE0B_REG TIMSK0
795 #define ICIE0_REG TIMSK0
798 #define TOIE1_REG TIMSK1
799 #define OCIE1A_REG TIMSK1
800 #define OCIE1B_REG TIMSK1
801 #define ICIE1_REG TIMSK1
804 #define BGCC0_REG BGCCR
805 #define BGCC1_REG BGCCR
806 #define BGCC2_REG BGCCR
807 #define BGCC3_REG BGCCR
808 #define BGCC4_REG BGCCR
809 #define BGCC5_REG BGCCR
812 #define PCINT0_REG PCMSK0
813 #define PCINT1_REG PCMSK0
814 #define PCINT2_REG PCMSK0
815 #define PCINT3_REG PCMSK0
818 #define PCINT4_REG PCMSK1
819 #define PCINT5_REG PCMSK1
820 #define PCINT6_REG PCMSK1
821 #define PCINT7_REG PCMSK1
822 #define PCINT8_REG PCMSK1
823 #define PCINT9_REG PCMSK1
824 #define PCINT10_REG PCMSK1
825 #define PCINT11_REG PCMSK1
828 #define PINC0_REG PINC
829 #define PINC1_REG PINC
830 #define PINC2_REG PINC
831 #define PINC3_REG PINC
832 #define PINC4_REG PINC
835 #define PINB0_REG PINB
836 #define PINB1_REG PINB
837 #define PINB2_REG PINB
838 #define PINB3_REG PINB
839 #define PINB4_REG PINB
840 #define PINB5_REG PINB
841 #define PINB6_REG PINB
842 #define PINB7_REG PINB
845 #define INTF0_REG EIFR
846 #define INTF1_REG EIFR
847 #define INTF2_REG EIFR
848 #define INTF3_REG EIFR
851 #define BGSCDIE_REG BGCSR
852 #define BGSCDIF_REG BGCSR
853 #define BGSCDE_REG BGCSR
854 #define BGD_REG BGCSR
857 #define TWAM0_REG TWAMR
858 #define TWAM1_REG TWAMR
859 #define TWAM2_REG TWAMR
860 #define TWAM3_REG TWAMR
861 #define TWAM4_REG TWAMR
862 #define TWAM5_REG TWAMR
863 #define TWAM6_REG TWAMR
866 #define TOV0_REG TIFR0
867 #define OCF0A_REG TIFR0
868 #define OCF0B_REG TIFR0
869 #define ICF0_REG TIFR0