2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
84 /* prescalers timer 3 */
85 #define TIMER3_PRESCALER_DIV_0 0
86 #define TIMER3_PRESCALER_DIV_1 1
87 #define TIMER3_PRESCALER_DIV_8 2
88 #define TIMER3_PRESCALER_DIV_64 3
89 #define TIMER3_PRESCALER_DIV_256 4
90 #define TIMER3_PRESCALER_DIV_1024 5
91 #define TIMER3_PRESCALER_DIV_FALL 6
92 #define TIMER3_PRESCALER_DIV_RISE 7
94 #define TIMER3_PRESCALER_REG_0 0
95 #define TIMER3_PRESCALER_REG_1 1
96 #define TIMER3_PRESCALER_REG_2 8
97 #define TIMER3_PRESCALER_REG_3 64
98 #define TIMER3_PRESCALER_REG_4 256
99 #define TIMER3_PRESCALER_REG_5 1024
100 #define TIMER3_PRESCALER_REG_6 -1
101 #define TIMER3_PRESCALER_REG_7 -2
104 /* available timers */
105 #define TIMER0_AVAILABLE
106 #define TIMER0A_AVAILABLE
107 #define TIMER0B_AVAILABLE
108 #define TIMER1_AVAILABLE
109 #define TIMER1A_AVAILABLE
110 #define TIMER1B_AVAILABLE
111 #define TIMER1C_AVAILABLE
112 #define TIMER2_AVAILABLE
113 #define TIMER2A_AVAILABLE
114 #define TIMER2B_AVAILABLE
115 #define TIMER3_AVAILABLE
116 #define TIMER3A_AVAILABLE
117 #define TIMER3B_AVAILABLE
118 #define TIMER3C_AVAILABLE
120 /* overflow interrupt number */
121 #define SIG_OVERFLOW0_NUM 0
122 #define SIG_OVERFLOW1_NUM 1
123 #define SIG_OVERFLOW2_NUM 2
124 #define SIG_OVERFLOW3_NUM 3
125 #define SIG_OVERFLOW_TOTAL_NUM 4
127 /* output compare interrupt number */
128 #define SIG_OUTPUT_COMPARE0A_NUM 0
129 #define SIG_OUTPUT_COMPARE0B_NUM 1
130 #define SIG_OUTPUT_COMPARE1A_NUM 2
131 #define SIG_OUTPUT_COMPARE1B_NUM 3
132 #define SIG_OUTPUT_COMPARE1C_NUM 4
133 #define SIG_OUTPUT_COMPARE2A_NUM 5
134 #define SIG_OUTPUT_COMPARE2B_NUM 6
135 #define SIG_OUTPUT_COMPARE3A_NUM 7
136 #define SIG_OUTPUT_COMPARE3B_NUM 8
137 #define SIG_OUTPUT_COMPARE3C_NUM 9
138 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
151 #define PWM_TOTAL_NUM 10
153 /* input capture interrupt number */
154 #define SIG_INPUT_CAPTURE1_NUM 0
155 #define SIG_INPUT_CAPTURE3_NUM 1
156 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
160 #define UEBCHX_0_REG UEBCHX
161 #define UEBCHX_1_REG UEBCHX
162 #define UEBCHX_2_REG UEBCHX
165 #define MUX0_REG ADMUX
166 #define MUX1_REG ADMUX
167 #define MUX2_REG ADMUX
168 #define MUX3_REG ADMUX
169 #define MUX4_REG ADMUX
170 #define ADLAR_REG ADMUX
171 #define REFS0_REG ADMUX
172 #define REFS1_REG ADMUX
175 #define SUSPE_REG UDIEN
176 #define SOFE_REG UDIEN
177 #define EORSTE_REG UDIEN
178 #define WAKEUPE_REG UDIEN
179 #define EORSME_REG UDIEN
180 #define UPRSME_REG UDIEN
183 #define WDP0_REG WDTCSR
184 #define WDP1_REG WDTCSR
185 #define WDP2_REG WDTCSR
186 #define WDE_REG WDTCSR
187 #define WDCE_REG WDTCSR
188 #define WDP3_REG WDTCSR
189 #define WDIE_REG WDTCSR
190 #define WDIF_REG WDTCSR
193 #define EEDR0_REG EEDR
194 #define EEDR1_REG EEDR
195 #define EEDR2_REG EEDR
196 #define EEDR3_REG EEDR
197 #define EEDR4_REG EEDR
198 #define EEDR5_REG EEDR
199 #define EEDR6_REG EEDR
200 #define EEDR7_REG EEDR
203 #define OCR0B_0_REG OCR0B
204 #define OCR0B_1_REG OCR0B
205 #define OCR0B_2_REG OCR0B
206 #define OCR0B_3_REG OCR0B
207 #define OCR0B_4_REG OCR0B
208 #define OCR0B_5_REG OCR0B
209 #define OCR0B_6_REG OCR0B
210 #define OCR0B_7_REG OCR0B
213 #define SUSPI_REG UDINT
214 #define SOFI_REG UDINT
215 #define EORSTI_REG UDINT
216 #define WAKEUPI_REG UDINT
217 #define EORSMI_REG UDINT
218 #define UPRSMI_REG UDINT
221 #define EPRST0_REG UERST
222 #define EPRST1_REG UERST
223 #define EPRST2_REG UERST
224 #define EPRST3_REG UERST
225 #define EPRST4_REG UERST
226 #define EPRST5_REG UERST
227 #define EPRST6_REG UERST
230 #define ALLOC_REG UECFG1X
231 #define EPBK0_REG UECFG1X
232 #define EPBK1_REG UECFG1X
233 #define EPSIZE0_REG UECFG1X
234 #define EPSIZE1_REG UECFG1X
235 #define EPSIZE2_REG UECFG1X
238 #define OCR2B_0_REG OCR2B
239 #define OCR2B_1_REG OCR2B
240 #define OCR2B_2_REG OCR2B
241 #define OCR2B_3_REG OCR2B
242 #define OCR2B_4_REG OCR2B
243 #define OCR2B_5_REG OCR2B
244 #define OCR2B_6_REG OCR2B
245 #define OCR2B_7_REG OCR2B
248 #define OCR2A_0_REG OCR2A
249 #define OCR2A_1_REG OCR2A
250 #define OCR2A_2_REG OCR2A
251 #define OCR2A_3_REG OCR2A
252 #define OCR2A_4_REG OCR2A
253 #define OCR2A_5_REG OCR2A
254 #define OCR2A_6_REG OCR2A
255 #define OCR2A_7_REG OCR2A
258 #define SPDR0_REG SPDR
259 #define SPDR1_REG SPDR
260 #define SPDR2_REG SPDR
261 #define SPDR3_REG SPDR
262 #define SPDR4_REG SPDR
263 #define SPDR5_REG SPDR
264 #define SPDR6_REG SPDR
265 #define SPDR7_REG SPDR
268 #define SPI2X_REG SPSR
269 #define WCOL_REG SPSR
270 #define SPIF_REG SPSR
273 #define ICR1H0_REG ICR1H
274 #define ICR1H1_REG ICR1H
275 #define ICR1H2_REG ICR1H
276 #define ICR1H3_REG ICR1H
277 #define ICR1H4_REG ICR1H
278 #define ICR1H5_REG ICR1H
279 #define ICR1H6_REG ICR1H
280 #define ICR1H7_REG ICR1H
283 #define ICR1L0_REG ICR1L
284 #define ICR1L1_REG ICR1L
285 #define ICR1L2_REG ICR1L
286 #define ICR1L3_REG ICR1L
287 #define ICR1L4_REG ICR1L
288 #define ICR1L5_REG ICR1L
289 #define ICR1L6_REG ICR1L
290 #define ICR1L7_REG ICR1L
293 #define EPINT0_REG UEINT
294 #define EPINT1_REG UEINT
295 #define EPINT2_REG UEINT
296 #define EPINT3_REG UEINT
297 #define EPINT4_REG UEINT
298 #define EPINT5_REG UEINT
299 #define EPINT6_REG UEINT
302 #define TCNT1L0_REG TCNT1L
303 #define TCNT1L1_REG TCNT1L
304 #define TCNT1L2_REG TCNT1L
305 #define TCNT1L3_REG TCNT1L
306 #define TCNT1L4_REG TCNT1L
307 #define TCNT1L5_REG TCNT1L
308 #define TCNT1L6_REG TCNT1L
309 #define TCNT1L7_REG TCNT1L
312 #define PORTD0_REG PORTD
313 #define PORTD1_REG PORTD
314 #define PORTD2_REG PORTD
315 #define PORTD3_REG PORTD
316 #define PORTD4_REG PORTD
317 #define PORTD5_REG PORTD
318 #define PORTD6_REG PORTD
319 #define PORTD7_REG PORTD
322 #define PORTE0_REG PORTE
323 #define PORTE1_REG PORTE
324 #define PORTE2_REG PORTE
325 #define PORTE3_REG PORTE
326 #define PORTE4_REG PORTE
327 #define PORTE5_REG PORTE
328 #define PORTE6_REG PORTE
329 #define PORTE7_REG PORTE
332 #define TCNT1H0_REG TCNT1H
333 #define TCNT1H1_REG TCNT1H
334 #define TCNT1H2_REG TCNT1H
335 #define TCNT1H3_REG TCNT1H
336 #define TCNT1H4_REG TCNT1H
337 #define TCNT1H5_REG TCNT1H
338 #define TCNT1H6_REG TCNT1H
339 #define TCNT1H7_REG TCNT1H
342 #define PORTC0_REG PORTC
343 #define PORTC1_REG PORTC
344 #define PORTC2_REG PORTC
345 #define PORTC3_REG PORTC
346 #define PORTC4_REG PORTC
347 #define PORTC5_REG PORTC
348 #define PORTC6_REG PORTC
349 #define PORTC7_REG PORTC
352 #define PORTA0_REG PORTA
353 #define PORTA1_REG PORTA
354 #define PORTA2_REG PORTA
355 #define PORTA3_REG PORTA
356 #define PORTA4_REG PORTA
357 #define PORTA5_REG PORTA
358 #define PORTA6_REG PORTA
359 #define PORTA7_REG PORTA
362 #define INT0_REG EIMSK
363 #define INT1_REG EIMSK
364 #define INT2_REG EIMSK
365 #define INT3_REG EIMSK
366 #define INT4_REG EIMSK
367 #define INT5_REG EIMSK
368 #define INT6_REG EIMSK
369 #define INT7_REG EIMSK
372 #define UDR1_0_REG UDR1
373 #define UDR1_1_REG UDR1
374 #define UDR1_2_REG UDR1
375 #define UDR1_3_REG UDR1
376 #define UDR1_4_REG UDR1
377 #define UDR1_5_REG UDR1
378 #define UDR1_6_REG UDR1
379 #define UDR1_7_REG UDR1
382 #define ISC40_REG EICRB
383 #define ISC41_REG EICRB
384 #define ISC50_REG EICRB
385 #define ISC51_REG EICRB
386 #define ISC60_REG EICRB
387 #define ISC61_REG EICRB
388 #define ISC70_REG EICRB
389 #define ISC71_REG EICRB
392 #define UEDATX_0_REG UEDATX
393 #define UEDATX_1_REG UEDATX
394 #define UEDATX_2_REG UEDATX
395 #define UEDATX_3_REG UEDATX
396 #define UEDATX_4_REG UEDATX
397 #define UEDATX_5_REG UEDATX
398 #define UEDATX_6_REG UEDATX
399 #define UEDATX_7_REG UEDATX
402 #define ISC00_REG EICRA
403 #define ISC01_REG EICRA
404 #define ISC10_REG EICRA
405 #define ISC11_REG EICRA
406 #define ISC20_REG EICRA
407 #define ISC21_REG EICRA
408 #define ISC30_REG EICRA
409 #define ISC31_REG EICRA
412 #define EPDIR_REG UECFG0X
413 #define EPTYPE0_REG UECFG0X
414 #define EPTYPE1_REG UECFG0X
417 #define ADC0D_REG DIDR0
418 #define ADC1D_REG DIDR0
419 #define ADC2D_REG DIDR0
420 #define ADC3D_REG DIDR0
421 #define ADC4D_REG DIDR0
422 #define ADC5D_REG DIDR0
423 #define ADC6D_REG DIDR0
424 #define ADC7D_REG DIDR0
427 #define AIN0D_REG DIDR1
428 #define AIN1D_REG DIDR1
431 #define DDF0_REG DDRF
432 #define DDF1_REG DDRF
433 #define DDF2_REG DDRF
434 #define DDF3_REG DDRF
435 #define DDF4_REG DDRF
436 #define DDF5_REG DDRF
437 #define DDF6_REG DDRF
438 #define DDF7_REG DDRF
441 #define TCR2BUB_REG ASSR
442 #define TCR2AUB_REG ASSR
443 #define OCR2BUB_REG ASSR
444 #define OCR2AUB_REG ASSR
445 #define TCN2UB_REG ASSR
447 #define EXCLK_REG ASSR
450 #define CLKPS0_REG CLKPR
451 #define CLKPS1_REG CLKPR
452 #define CLKPS2_REG CLKPR
453 #define CLKPS3_REG CLKPR
454 #define CLKPCE_REG CLKPR
467 #define UENUM_0_REG UENUM
468 #define UENUM_1_REG UENUM
469 #define UENUM_2_REG UENUM
472 #define UBRR_0_REG UBRR1L
473 #define UBRR_1_REG UBRR1L
474 #define UBRR_2_REG UBRR1L
475 #define UBRR_3_REG UBRR1L
476 #define UBRR_4_REG UBRR1L
477 #define UBRR_5_REG UBRR1L
478 #define UBRR_6_REG UBRR1L
479 #define UBRR_7_REG UBRR1L
482 #define DDC0_REG DDRC
483 #define DDC1_REG DDRC
484 #define DDC2_REG DDRC
485 #define DDC3_REG DDRC
486 #define DDC4_REG DDRC
487 #define DDC5_REG DDRC
488 #define DDC6_REG DDRC
489 #define DDC7_REG DDRC
492 #define OCR3AL0_REG OCR3AL
493 #define OCR3AL1_REG OCR3AL
494 #define OCR3AL2_REG OCR3AL
495 #define OCR3AL3_REG OCR3AL
496 #define OCR3AL4_REG OCR3AL
497 #define OCR3AL5_REG OCR3AL
498 #define OCR3AL6_REG OCR3AL
499 #define OCR3AL7_REG OCR3AL
502 #define DDA0_REG DDRA
503 #define DDA1_REG DDRA
504 #define DDA2_REG DDRA
505 #define DDA3_REG DDRA
506 #define DDA4_REG DDRA
507 #define DDA5_REG DDRA
508 #define DDA6_REG DDRA
509 #define DDA7_REG DDRA
512 #define WGM10_REG TCCR1A
513 #define WGM11_REG TCCR1A
514 #define COM1C0_REG TCCR1A
515 #define COM1C1_REG TCCR1A
516 #define COM1B0_REG TCCR1A
517 #define COM1B1_REG TCCR1A
518 #define COM1A0_REG TCCR1A
519 #define COM1A1_REG TCCR1A
522 #define OCR3AH0_REG OCR3AH
523 #define OCR3AH1_REG OCR3AH
524 #define OCR3AH2_REG OCR3AH
525 #define OCR3AH3_REG OCR3AH
526 #define OCR3AH4_REG OCR3AH
527 #define OCR3AH5_REG OCR3AH
528 #define OCR3AH6_REG OCR3AH
529 #define OCR3AH7_REG OCR3AH
532 #define CS10_REG TCCR1B
533 #define CS11_REG TCCR1B
534 #define CS12_REG TCCR1B
535 #define WGM12_REG TCCR1B
536 #define WGM13_REG TCCR1B
537 #define ICES1_REG TCCR1B
538 #define ICNC1_REG TCCR1B
541 #define CAL0_REG OSCCAL
542 #define CAL1_REG OSCCAL
543 #define CAL2_REG OSCCAL
544 #define CAL3_REG OSCCAL
545 #define CAL4_REG OSCCAL
546 #define CAL5_REG OSCCAL
547 #define CAL6_REG OSCCAL
548 #define CAL7_REG OSCCAL
551 #define DDD0_REG DDRD
552 #define DDD1_REG DDRD
553 #define DDD2_REG DDRD
554 #define DDD3_REG DDRD
555 #define DDD4_REG DDRD
556 #define DDD5_REG DDRD
557 #define DDD6_REG DDRD
558 #define DDD7_REG DDRD
561 #define GPIOR10_REG GPIOR1
562 #define GPIOR11_REG GPIOR1
563 #define GPIOR12_REG GPIOR1
564 #define GPIOR13_REG GPIOR1
565 #define GPIOR14_REG GPIOR1
566 #define GPIOR15_REG GPIOR1
567 #define GPIOR16_REG GPIOR1
568 #define GPIOR17_REG GPIOR1
571 #define GPIOR00_REG GPIOR0
572 #define GPIOR01_REG GPIOR0
573 #define GPIOR02_REG GPIOR0
574 #define GPIOR03_REG GPIOR0
575 #define GPIOR04_REG GPIOR0
576 #define GPIOR05_REG GPIOR0
577 #define GPIOR06_REG GPIOR0
578 #define GPIOR07_REG GPIOR0
581 #define GPIOR20_REG GPIOR2
582 #define GPIOR21_REG GPIOR2
583 #define GPIOR22_REG GPIOR2
584 #define GPIOR23_REG GPIOR2
585 #define GPIOR24_REG GPIOR2
586 #define GPIOR25_REG GPIOR2
587 #define GPIOR26_REG GPIOR2
588 #define GPIOR27_REG GPIOR2
591 #define DETACH_REG UDCON
592 #define RMWKUP_REG UDCON
593 #define LSM_REG UDCON
596 #define PCIE0_REG PCICR
599 #define VBUSTI_REG USBINT
600 #define IDTI_REG USBINT
603 #define TCNT2_0_REG TCNT2
604 #define TCNT2_1_REG TCNT2
605 #define TCNT2_2_REG TCNT2
606 #define TCNT2_3_REG TCNT2
607 #define TCNT2_4_REG TCNT2
608 #define TCNT2_5_REG TCNT2
609 #define TCNT2_6_REG TCNT2
610 #define TCNT2_7_REG TCNT2
613 #define TCNT0_0_REG TCNT0
614 #define TCNT0_1_REG TCNT0
615 #define TCNT0_2_REG TCNT0
616 #define TCNT0_3_REG TCNT0
617 #define TCNT0_4_REG TCNT0
618 #define TCNT0_5_REG TCNT0
619 #define TCNT0_6_REG TCNT0
620 #define TCNT0_7_REG TCNT0
623 #define TWGCE_REG TWAR
624 #define TWA0_REG TWAR
625 #define TWA1_REG TWAR
626 #define TWA2_REG TWAR
627 #define TWA3_REG TWAR
628 #define TWA4_REG TWAR
629 #define TWA5_REG TWAR
630 #define TWA6_REG TWAR
633 #define UVREGE_REG UHWCON
634 #define UVCONE_REG UHWCON
635 #define UIDE_REG UHWCON
636 #define UIMOD_REG UHWCON
639 #define CS00_REG TCCR0B
640 #define CS01_REG TCCR0B
641 #define CS02_REG TCCR0B
642 #define WGM02_REG TCCR0B
643 #define FOC0B_REG TCCR0B
644 #define FOC0A_REG TCCR0B
647 #define FNCERR_REG UDMFN
650 #define WGM00_REG TCCR0A
651 #define WGM01_REG TCCR0A
652 #define COM0B0_REG TCCR0A
653 #define COM0B1_REG TCCR0A
654 #define COM0A0_REG TCCR0A
655 #define COM0A1_REG TCCR0A
658 #define TOV2_REG TIFR2
659 #define OCF2A_REG TIFR2
660 #define OCF2B_REG TIFR2
663 #define TOV3_REG TIFR3
664 #define OCF3A_REG TIFR3
665 #define OCF3B_REG TIFR3
666 #define OCF3C_REG TIFR3
667 #define ICF3_REG TIFR3
670 #define SPR0_REG SPCR
671 #define SPR1_REG SPCR
672 #define CPHA_REG SPCR
673 #define CPOL_REG SPCR
674 #define MSTR_REG SPCR
675 #define DORD_REG SPCR
677 #define SPIE_REG SPCR
680 #define TOV1_REG TIFR1
681 #define OCF1A_REG TIFR1
682 #define OCF1B_REG TIFR1
683 #define OCF1C_REG TIFR1
684 #define ICF1_REG TIFR1
687 #define EEAR8_REG EEARH
688 #define EEAR9_REG EEARH
689 #define EEAR10_REG EEARH
690 #define EEAR11_REG EEARH
693 #define UEBCLX_0_REG UEBCLX
694 #define UEBCLX_1_REG UEBCLX
695 #define UEBCLX_2_REG UEBCLX
696 #define UEBCLX_3_REG UEBCLX
697 #define UEBCLX_4_REG UEBCLX
698 #define UEBCLX_5_REG UEBCLX
699 #define UEBCLX_6_REG UEBCLX
700 #define UEBCLX_7_REG UEBCLX
703 #define OCR3CH0_REG OCR3CH
704 #define OCR3CH1_REG OCR3CH
705 #define OCR3CH2_REG OCR3CH
706 #define OCR3CH3_REG OCR3CH
707 #define OCR3CH4_REG OCR3CH
708 #define OCR3CH5_REG OCR3CH
709 #define OCR3CH6_REG OCR3CH
710 #define OCR3CH7_REG OCR3CH
713 #define CURRBK0_REG UESTA1X
714 #define CURRBK1_REG UESTA1X
715 #define CTRLDIR_REG UESTA1X
718 #define OCR3CL0_REG OCR3CL
719 #define OCR3CL1_REG OCR3CL
720 #define OCR3CL2_REG OCR3CL
721 #define OCR3CL3_REG OCR3CL
722 #define OCR3CL4_REG OCR3CL
723 #define OCR3CL5_REG OCR3CL
724 #define OCR3CL6_REG OCR3CL
725 #define OCR3CL7_REG OCR3CL
728 #define PSRSYNC_REG GTCCR
729 #define TSM_REG GTCCR
730 #define PSRASY_REG GTCCR
733 #define TWBR0_REG TWBR
734 #define TWBR1_REG TWBR
735 #define TWBR2_REG TWBR
736 #define TWBR3_REG TWBR
737 #define TWBR4_REG TWBR
738 #define TWBR5_REG TWBR
739 #define TWBR6_REG TWBR
740 #define TWBR7_REG TWBR
753 #define FOC3C_REG TCCR3C
754 #define FOC3B_REG TCCR3C
755 #define FOC3A_REG TCCR3C
758 #define CS30_REG TCCR3B
759 #define CS31_REG TCCR3B
760 #define CS32_REG TCCR3B
761 #define WGM32_REG TCCR3B
762 #define WGM33_REG TCCR3B
763 #define ICES3_REG TCCR3B
764 #define ICNC3_REG TCCR3B
767 #define WGM30_REG TCCR3A
768 #define WGM31_REG TCCR3A
769 #define COM3C0_REG TCCR3A
770 #define COM3C1_REG TCCR3A
771 #define COM3B0_REG TCCR3A
772 #define COM3B1_REG TCCR3A
773 #define COM3A0_REG TCCR3A
774 #define COM3A1_REG TCCR3A
777 #define TXINI_REG UEINTX
778 #define STALLEDI_REG UEINTX
779 #define RXOUTI_REG UEINTX
780 #define RXSTPI_REG UEINTX
781 #define NAKOUTI_REG UEINTX
782 #define RWAL_REG UEINTX
783 #define NAKINI_REG UEINTX
784 #define FIFOCON_REG UEINTX
787 #define OCR1BL0_REG OCR1BL
788 #define OCR1BL1_REG OCR1BL
789 #define OCR1BL2_REG OCR1BL
790 #define OCR1BL3_REG OCR1BL
791 #define OCR1BL4_REG OCR1BL
792 #define OCR1BL5_REG OCR1BL
793 #define OCR1BL6_REG OCR1BL
794 #define OCR1BL7_REG OCR1BL
797 #define TCNT3H0_REG TCNT3H
798 #define TCNT3H1_REG TCNT3H
799 #define TCNT3H2_REG TCNT3H
800 #define TCNT3H3_REG TCNT3H
801 #define TCNT3H4_REG TCNT3H
802 #define TCNT3H5_REG TCNT3H
803 #define TCNT3H6_REG TCNT3H
804 #define TCNT3H7_REG TCNT3H
807 #define OCR1BH0_REG OCR1BH
808 #define OCR1BH1_REG OCR1BH
809 #define OCR1BH2_REG OCR1BH
810 #define OCR1BH3_REG OCR1BH
811 #define OCR1BH4_REG OCR1BH
812 #define OCR1BH5_REG OCR1BH
813 #define OCR1BH6_REG OCR1BH
814 #define OCR1BH7_REG OCR1BH
817 #define TCNT3L0_REG TCNT3L
818 #define TCNT3L1_REG TCNT3L
819 #define TCNT3L2_REG TCNT3L
820 #define TCNT3L3_REG TCNT3L
821 #define TCNT3L4_REG TCNT3L
822 #define TCNT3L5_REG TCNT3L
823 #define TCNT3L6_REG TCNT3L
824 #define TCNT3L7_REG TCNT3L
837 #define VBUSTE_REG USBCON
838 #define IDTE_REG USBCON
839 #define OTGPADE_REG USBCON
840 #define FRZCLK_REG USBCON
841 #define HOST_REG USBCON
842 #define USBE_REG USBCON
845 #define JTRF_REG MCUSR
846 #define PORF_REG MCUSR
847 #define EXTRF_REG MCUSR
848 #define BORF_REG MCUSR
849 #define WDRF_REG MCUSR
852 #define EERE_REG EECR
853 #define EEPE_REG EECR
854 #define EEMPE_REG EECR
855 #define EERIE_REG EECR
856 #define EEPM0_REG EECR
857 #define EEPM1_REG EECR
866 #define TWIE_REG TWCR
867 #define TWEN_REG TWCR
868 #define TWWC_REG TWCR
869 #define TWSTO_REG TWCR
870 #define TWSTA_REG TWCR
871 #define TWEA_REG TWCR
872 #define TWINT_REG TWCR
875 #define PCIF0_REG PCIFR
878 #define WGM20_REG TCCR2A
879 #define WGM21_REG TCCR2A
880 #define COM2B0_REG TCCR2A
881 #define COM2B1_REG TCCR2A
882 #define COM2A0_REG TCCR2A
883 #define COM2A1_REG TCCR2A
886 #define CS20_REG TCCR2B
887 #define CS21_REG TCCR2B
888 #define CS22_REG TCCR2B
889 #define WGM22_REG TCCR2B
890 #define FOC2B_REG TCCR2B
891 #define FOC2A_REG TCCR2B
894 #define EPEN_REG UECONX
895 #define RSTDT_REG UECONX
896 #define STALLRQC_REG UECONX
897 #define STALLRQ_REG UECONX
900 #define TWPS0_REG TWSR
901 #define TWPS1_REG TWSR
902 #define TWS3_REG TWSR
903 #define TWS4_REG TWSR
904 #define TWS5_REG TWSR
905 #define TWS6_REG TWSR
906 #define TWS7_REG TWSR
909 #define EEAR0_REG EEARL
910 #define EEAR1_REG EEARL
911 #define EEAR2_REG EEARL
912 #define EEAR3_REG EEARL
913 #define EEAR4_REG EEARL
914 #define EEAR5_REG EEARL
915 #define EEAR6_REG EEARL
916 #define EEAR7_REG EEARL
919 #define JTD_REG MCUCR
920 #define IVCE_REG MCUCR
921 #define IVSEL_REG MCUCR
922 #define PUD_REG MCUCR
925 #define OCR1CL0_REG OCR1CL
926 #define OCR1CL1_REG OCR1CL
927 #define OCR1CL2_REG OCR1CL
928 #define OCR1CL3_REG OCR1CL
929 #define OCR1CL4_REG OCR1CL
930 #define OCR1CL5_REG OCR1CL
931 #define OCR1CL6_REG OCR1CL
932 #define OCR1CL7_REG OCR1CL
935 #define OCR1CH0_REG OCR1CH
936 #define OCR1CH1_REG OCR1CH
937 #define OCR1CH2_REG OCR1CH
938 #define OCR1CH3_REG OCR1CH
939 #define OCR1CH4_REG OCR1CH
940 #define OCR1CH5_REG OCR1CH
941 #define OCR1CH6_REG OCR1CH
942 #define OCR1CH7_REG OCR1CH
945 #define OCDR0_REG OCDR
946 #define OCDR1_REG OCDR
947 #define OCDR2_REG OCDR
948 #define OCDR3_REG OCDR
949 #define OCDR4_REG OCDR
950 #define OCDR5_REG OCDR
951 #define OCDR6_REG OCDR
952 #define OCDR7_REG OCDR
955 #define PINA0_REG PINA
956 #define PINA1_REG PINA
957 #define PINA2_REG PINA
958 #define PINA3_REG PINA
959 #define PINA4_REG PINA
960 #define PINA5_REG PINA
961 #define PINA6_REG PINA
962 #define PINA7_REG PINA
965 #define VBUS_REG USBSTA
966 #define ID_REG USBSTA
967 #define SPEED_REG USBSTA
970 #define TXINE_REG UEIENX
971 #define STALLEDE_REG UEIENX
972 #define RXOUTE_REG UEIENX
973 #define RXSTPE_REG UEIENX
974 #define NAKOUTE_REG UEIENX
975 #define NAKINE_REG UEIENX
976 #define FLERRE_REG UEIENX
979 #define TXB81_REG UCSR1B
980 #define RXB81_REG UCSR1B
981 #define UCSZ12_REG UCSR1B
982 #define TXEN1_REG UCSR1B
983 #define RXEN1_REG UCSR1B
984 #define UDRIE1_REG UCSR1B
985 #define TXCIE1_REG UCSR1B
986 #define RXCIE1_REG UCSR1B
989 #define UCPOL1_REG UCSR1C
990 #define UCSZ10_REG UCSR1C
991 #define UCSZ11_REG UCSR1C
992 #define USBS1_REG UCSR1C
993 #define UPM10_REG UCSR1C
994 #define UPM11_REG UCSR1C
995 #define UMSEL10_REG UCSR1C
996 #define UMSEL11_REG UCSR1C
999 #define MPCM1_REG UCSR1A
1000 #define U2X1_REG UCSR1A
1001 #define UPE1_REG UCSR1A
1002 #define DOR1_REG UCSR1A
1003 #define FE1_REG UCSR1A
1004 #define UDRE1_REG UCSR1A
1005 #define TXC1_REG UCSR1A
1006 #define RXC1_REG UCSR1A
1009 #define DDB0_REG DDRB
1010 #define DDB1_REG DDRB
1011 #define DDB2_REG DDRB
1012 #define DDB3_REG DDRB
1013 #define DDB4_REG DDRB
1014 #define DDB5_REG DDRB
1015 #define DDB6_REG DDRB
1016 #define DDB7_REG DDRB
1019 #define UDFNUML_0_REG UDFNUML
1020 #define UDFNUML_1_REG UDFNUML
1021 #define UDFNUML_2_REG UDFNUML
1022 #define UDFNUML_3_REG UDFNUML
1023 #define UDFNUML_4_REG UDFNUML
1024 #define UDFNUML_5_REG UDFNUML
1025 #define UDFNUML_6_REG UDFNUML
1026 #define UDFNUML_7_REG UDFNUML
1029 #define TWD0_REG TWDR
1030 #define TWD1_REG TWDR
1031 #define TWD2_REG TWDR
1032 #define TWD3_REG TWDR
1033 #define TWD4_REG TWDR
1034 #define TWD5_REG TWDR
1035 #define TWD6_REG TWDR
1036 #define TWD7_REG TWDR
1039 #define UDFNUMH_0_REG UDFNUMH
1040 #define UDFNUMH_1_REG UDFNUMH
1041 #define UDFNUMH_2_REG UDFNUMH
1044 #define TWAM0_REG TWAMR
1045 #define TWAM1_REG TWAMR
1046 #define TWAM2_REG TWAMR
1047 #define TWAM3_REG TWAMR
1048 #define TWAM4_REG TWAMR
1049 #define TWAM5_REG TWAMR
1050 #define TWAM6_REG TWAMR
1053 #define ADPS0_REG ADCSRA
1054 #define ADPS1_REG ADCSRA
1055 #define ADPS2_REG ADCSRA
1056 #define ADIE_REG ADCSRA
1057 #define ADIF_REG ADCSRA
1058 #define ADATE_REG ADCSRA
1059 #define ADSC_REG ADCSRA
1060 #define ADEN_REG ADCSRA
1063 #define ADTS0_REG ADCSRB
1064 #define ADTS1_REG ADCSRB
1065 #define ADTS2_REG ADCSRB
1066 #define ADHSM_REG ADCSRB
1067 #define ACME_REG ADCSRB
1070 #define PRADC_REG PRR0
1071 #define PRSPI_REG PRR0
1072 #define PRTIM1_REG PRR0
1073 #define PRTIM0_REG PRR0
1074 #define PRTIM2_REG PRR0
1075 #define PRTWI_REG PRR0
1078 #define UBRR_8_REG UBRR1H
1079 #define UBRR_9_REG UBRR1H
1080 #define UBRR_10_REG UBRR1H
1081 #define UBRR_11_REG UBRR1H
1084 #define OCROA_0_REG OCR0A
1085 #define OCROA_1_REG OCR0A
1086 #define OCROA_2_REG OCR0A
1087 #define OCROA_3_REG OCR0A
1088 #define OCROA_4_REG OCR0A
1089 #define OCROA_5_REG OCR0A
1090 #define OCROA_6_REG OCR0A
1091 #define OCROA_7_REG OCR0A
1094 #define ACIS0_REG ACSR
1095 #define ACIS1_REG ACSR
1096 #define ACIC_REG ACSR
1097 #define ACIE_REG ACSR
1098 #define ACI_REG ACSR
1099 #define ACO_REG ACSR
1100 #define ACBG_REG ACSR
1101 #define ACD_REG ACSR
1104 #define PORTF0_REG PORTF
1105 #define PORTF1_REG PORTF
1106 #define PORTF2_REG PORTF
1107 #define PORTF3_REG PORTF
1108 #define PORTF4_REG PORTF
1109 #define PORTF5_REG PORTF
1110 #define PORTF6_REG PORTF
1111 #define PORTF7_REG PORTF
1114 #define FOC1C_REG TCCR1C
1115 #define FOC1B_REG TCCR1C
1116 #define FOC1A_REG TCCR1C
1119 #define ICR3H0_REG ICR3H
1120 #define ICR3H1_REG ICR3H
1121 #define ICR3H2_REG ICR3H
1122 #define ICR3H3_REG ICR3H
1123 #define ICR3H4_REG ICR3H
1124 #define ICR3H5_REG ICR3H
1125 #define ICR3H6_REG ICR3H
1126 #define ICR3H7_REG ICR3H
1129 #define DDE0_REG DDRE
1130 #define DDE1_REG DDRE
1131 #define DDE2_REG DDRE
1132 #define DDE3_REG DDRE
1133 #define DDE4_REG DDRE
1134 #define DDE5_REG DDRE
1135 #define DDE6_REG DDRE
1136 #define DDE7_REG DDRE
1139 #define UADD0_REG UDADDR
1140 #define UADD1_REG UDADDR
1141 #define UADD2_REG UDADDR
1142 #define UADD3_REG UDADDR
1143 #define UADD4_REG UDADDR
1144 #define UADD5_REG UDADDR
1145 #define UADD6_REG UDADDR
1146 #define ADDEN_REG UDADDR
1149 #define ICR3L0_REG ICR3L
1150 #define ICR3L1_REG ICR3L
1151 #define ICR3L2_REG ICR3L
1152 #define ICR3L3_REG ICR3L
1153 #define ICR3L4_REG ICR3L
1154 #define ICR3L5_REG ICR3L
1155 #define ICR3L6_REG ICR3L
1156 #define ICR3L7_REG ICR3L
1159 #define SPMEN_REG SPMCSR
1160 #define PGERS_REG SPMCSR
1161 #define PGWRT_REG SPMCSR
1162 #define BLBSET_REG SPMCSR
1163 #define RWWSRE_REG SPMCSR
1164 #define SIGRD_REG SPMCSR
1165 #define RWWSB_REG SPMCSR
1166 #define SPMIE_REG SPMCSR
1169 #define NBUSYBK0_REG UESTA0X
1170 #define NBUSYBK1_REG UESTA0X
1171 #define DTSEQ0_REG UESTA0X
1172 #define DTSEQ1_REG UESTA0X
1173 #define UNDERFI_REG UESTA0X
1174 #define OVERFI_REG UESTA0X
1175 #define CFGOK_REG UESTA0X
1178 #define PORTB0_REG PORTB
1179 #define PORTB1_REG PORTB
1180 #define PORTB2_REG PORTB
1181 #define PORTB3_REG PORTB
1182 #define PORTB4_REG PORTB
1183 #define PORTB5_REG PORTB
1184 #define PORTB6_REG PORTB
1185 #define PORTB7_REG PORTB
1188 #define ADCL0_REG ADCL
1189 #define ADCL1_REG ADCL
1190 #define ADCL2_REG ADCL
1191 #define ADCL3_REG ADCL
1192 #define ADCL4_REG ADCL
1193 #define ADCL5_REG ADCL
1194 #define ADCL6_REG ADCL
1195 #define ADCL7_REG ADCL
1198 #define ADCH0_REG ADCH
1199 #define ADCH1_REG ADCH
1200 #define ADCH2_REG ADCH
1201 #define ADCH3_REG ADCH
1202 #define ADCH4_REG ADCH
1203 #define ADCH5_REG ADCH
1204 #define ADCH6_REG ADCH
1205 #define ADCH7_REG ADCH
1208 #define OCR3BL0_REG OCR3BL
1209 #define OCR3BL1_REG OCR3BL
1210 #define OCR3BL2_REG OCR3BL
1211 #define OCR3BL3_REG OCR3BL
1212 #define OCR3BL4_REG OCR3BL
1213 #define OCR3BL5_REG OCR3BL
1214 #define OCR3BL6_REG OCR3BL
1215 #define OCR3BL7_REG OCR3BL
1218 #define OCR3BH0_REG OCR3BH
1219 #define OCR3BH1_REG OCR3BH
1220 #define OCR3BH2_REG OCR3BH
1221 #define OCR3BH3_REG OCR3BH
1222 #define OCR3BH4_REG OCR3BH
1223 #define OCR3BH5_REG OCR3BH
1224 #define OCR3BH6_REG OCR3BH
1225 #define OCR3BH7_REG OCR3BH
1228 #define TOIE2_REG TIMSK2
1229 #define OCIE2A_REG TIMSK2
1230 #define OCIE2B_REG TIMSK2
1233 #define TOIE3_REG TIMSK3
1234 #define OCIE3A_REG TIMSK3
1235 #define OCIE3B_REG TIMSK3
1236 #define OCIE3C_REG TIMSK3
1237 #define ICIE3_REG TIMSK3
1240 #define TOIE0_REG TIMSK0
1241 #define OCIE0A_REG TIMSK0
1242 #define OCIE0B_REG TIMSK0
1245 #define TOIE1_REG TIMSK1
1246 #define OCIE1A_REG TIMSK1
1247 #define OCIE1B_REG TIMSK1
1248 #define OCIE1C_REG TIMSK1
1249 #define ICIE1_REG TIMSK1
1252 #define PLOCK_REG PLLCSR
1253 #define PLLE_REG PLLCSR
1254 #define PLLP0_REG PLLCSR
1255 #define PLLP1_REG PLLCSR
1256 #define PLLP2_REG PLLCSR
1259 #define PCINT0_REG PCMSK0
1260 #define PCINT1_REG PCMSK0
1261 #define PCINT2_REG PCMSK0
1262 #define PCINT3_REG PCMSK0
1263 #define PCINT4_REG PCMSK0
1264 #define PCINT5_REG PCMSK0
1265 #define PCINT6_REG PCMSK0
1266 #define PCINT7_REG PCMSK0
1269 #define XMM0_REG XMCRB
1270 #define XMM1_REG XMCRB
1271 #define XMM2_REG XMCRB
1272 #define XMBK_REG XMCRB
1275 #define SRW00_REG XMCRA
1276 #define SRW01_REG XMCRA
1277 #define SRW10_REG XMCRA
1278 #define SRW11_REG XMCRA
1279 #define SRL0_REG XMCRA
1280 #define SRL1_REG XMCRA
1281 #define SRL2_REG XMCRA
1282 #define SRE_REG XMCRA
1285 #define PINC0_REG PINC
1286 #define PINC1_REG PINC
1287 #define PINC2_REG PINC
1288 #define PINC3_REG PINC
1289 #define PINC4_REG PINC
1290 #define PINC5_REG PINC
1291 #define PINC6_REG PINC
1292 #define PINC7_REG PINC
1295 #define PINB0_REG PINB
1296 #define PINB1_REG PINB
1297 #define PINB2_REG PINB
1298 #define PINB3_REG PINB
1299 #define PINB4_REG PINB
1300 #define PINB5_REG PINB
1301 #define PINB6_REG PINB
1302 #define PINB7_REG PINB
1305 #define INTF0_REG EIFR
1306 #define INTF1_REG EIFR
1307 #define INTF2_REG EIFR
1308 #define INTF3_REG EIFR
1309 #define INTF4_REG EIFR
1310 #define INTF5_REG EIFR
1311 #define INTF6_REG EIFR
1312 #define INTF7_REG EIFR
1315 #define PINF0_REG PINF
1316 #define PINF1_REG PINF
1317 #define PINF2_REG PINF
1318 #define PINF3_REG PINF
1319 #define PINF4_REG PINF
1320 #define PINF5_REG PINF
1321 #define PINF6_REG PINF
1322 #define PINF7_REG PINF
1325 #define PINE0_REG PINE
1326 #define PINE1_REG PINE
1327 #define PINE2_REG PINE
1328 #define PINE3_REG PINE
1329 #define PINE4_REG PINE
1330 #define PINE5_REG PINE
1331 #define PINE6_REG PINE
1332 #define PINE7_REG PINE
1335 #define PIND0_REG PIND
1336 #define PIND1_REG PIND
1337 #define PIND2_REG PIND
1338 #define PIND3_REG PIND
1339 #define PIND4_REG PIND
1340 #define PIND5_REG PIND
1341 #define PIND6_REG PIND
1342 #define PIND7_REG PIND
1345 #define OCR1AH0_REG OCR1AH
1346 #define OCR1AH1_REG OCR1AH
1347 #define OCR1AH2_REG OCR1AH
1348 #define OCR1AH3_REG OCR1AH
1349 #define OCR1AH4_REG OCR1AH
1350 #define OCR1AH5_REG OCR1AH
1351 #define OCR1AH6_REG OCR1AH
1352 #define OCR1AH7_REG OCR1AH
1355 #define OCR1AL0_REG OCR1AL
1356 #define OCR1AL1_REG OCR1AL
1357 #define OCR1AL2_REG OCR1AL
1358 #define OCR1AL3_REG OCR1AL
1359 #define OCR1AL4_REG OCR1AL
1360 #define OCR1AL5_REG OCR1AL
1361 #define OCR1AL6_REG OCR1AL
1362 #define OCR1AL7_REG OCR1AL
1365 #define TOV0_REG TIFR0
1366 #define OCF0A_REG TIFR0
1367 #define OCF0B_REG TIFR0
1370 #define PRUSART1_REG PRR1
1371 #define PRTIM3_REG PRR1
1372 #define PRUSB_REG PRR1