2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER1_AVAILABLE
88 #define TIMER1A_AVAILABLE
89 #define TIMER1B_AVAILABLE
90 #define TIMER2_AVAILABLE
92 /* overflow interrupt number */
93 #define SIG_OVERFLOW0_NUM 0
94 #define SIG_OVERFLOW1_NUM 1
95 #define SIG_OVERFLOW2_NUM 2
96 #define SIG_OVERFLOW_TOTAL_NUM 3
98 /* output compare interrupt number */
99 #define SIG_OUTPUT_COMPARE0_NUM 0
100 #define SIG_OUTPUT_COMPARE1A_NUM 1
101 #define SIG_OUTPUT_COMPARE1B_NUM 2
102 #define SIG_OUTPUT_COMPARE2_NUM 3
103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
110 #define PWM_TOTAL_NUM 4
112 /* input capture interrupt number */
113 #define SIG_INPUT_CAPTURE1_NUM 0
114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
118 #define WDP0_REG WDTCR
119 #define WDP1_REG WDTCR
120 #define WDP2_REG WDTCR
121 #define WDE_REG WDTCR
122 #define WDCE_REG WDTCR
125 #define MUX0_REG ADMUX
126 #define MUX1_REG ADMUX
127 #define MUX2_REG ADMUX
128 #define MUX3_REG ADMUX
129 #define MUX4_REG ADMUX
130 #define ADLAR_REG ADMUX
131 #define REFS0_REG ADMUX
132 #define REFS1_REG ADMUX
135 #define EEDR0_REG EEDR
136 #define EEDR1_REG EEDR
137 #define EEDR2_REG EEDR
138 #define EEDR3_REG EEDR
139 #define EEDR4_REG EEDR
140 #define EEDR5_REG EEDR
141 #define EEDR6_REG EEDR
142 #define EEDR7_REG EEDR
145 #define OCR2A0_REG OCR2A
146 #define OCR2A1_REG OCR2A
147 #define OCR2A2_REG OCR2A
148 #define OCR2A3_REG OCR2A
149 #define OCR2A4_REG OCR2A
150 #define OCR2A5_REG OCR2A
151 #define OCR2A6_REG OCR2A
152 #define OCR2A7_REG OCR2A
155 #define SPDR0_REG SPDR
156 #define SPDR1_REG SPDR
157 #define SPDR2_REG SPDR
158 #define SPDR3_REG SPDR
159 #define SPDR4_REG SPDR
160 #define SPDR5_REG SPDR
161 #define SPDR6_REG SPDR
162 #define SPDR7_REG SPDR
165 #define SPI2X_REG SPSR
166 #define WCOL_REG SPSR
167 #define SPIF_REG SPSR
180 #define ICR1L0_REG ICR1L
181 #define ICR1L1_REG ICR1L
182 #define ICR1L2_REG ICR1L
183 #define ICR1L3_REG ICR1L
184 #define ICR1L4_REG ICR1L
185 #define ICR1L5_REG ICR1L
186 #define ICR1L6_REG ICR1L
187 #define ICR1L7_REG ICR1L
190 #define PRADC_REG PRR
191 #define PRUSART0_REG PRR
192 #define PRSPI_REG PRR
193 #define PRTIM1_REG PRR
194 #define PRLCD_REG PRR
197 #define MPCM0_REG UCSR0A
198 #define U2X0_REG UCSR0A
199 #define UPE0_REG UCSR0A
200 #define DOR0_REG UCSR0A
201 #define FE0_REG UCSR0A
202 #define UDRE0_REG UCSR0A
203 #define TXC0_REG UCSR0A
204 #define RXC0_REG UCSR0A
207 #define PORTG0_REG PORTG
208 #define PORTG1_REG PORTG
209 #define PORTG2_REG PORTG
210 #define PORTG3_REG PORTG
211 #define PORTG4_REG PORTG
214 #define UCPOL0_REG UCSR0C
215 #define UCSZ00_REG UCSR0C
216 #define UCSZ01_REG UCSR0C
217 #define USBS0_REG UCSR0C
218 #define UPM00_REG UCSR0C
219 #define UPM01_REG UCSR0C
220 #define UMSEL0_REG UCSR0C
223 #define USICNT0_REG USISR
224 #define USICNT1_REG USISR
225 #define USICNT2_REG USISR
226 #define USICNT3_REG USISR
227 #define USIDC_REG USISR
228 #define USIPF_REG USISR
229 #define USIOIF_REG USISR
230 #define USISIF_REG USISR
233 #define TCNT1H0_REG TCNT1H
234 #define TCNT1H1_REG TCNT1H
235 #define TCNT1H2_REG TCNT1H
236 #define TCNT1H3_REG TCNT1H
237 #define TCNT1H4_REG TCNT1H
238 #define TCNT1H5_REG TCNT1H
239 #define TCNT1H6_REG TCNT1H
240 #define TCNT1H7_REG TCNT1H
243 #define PORTC0_REG PORTC
244 #define PORTC1_REG PORTC
245 #define PORTC2_REG PORTC
246 #define PORTC3_REG PORTC
247 #define PORTC4_REG PORTC
248 #define PORTC5_REG PORTC
249 #define PORTC6_REG PORTC
250 #define PORTC7_REG PORTC
253 #define PORTA0_REG PORTA
254 #define PORTA1_REG PORTA
255 #define PORTA2_REG PORTA
256 #define PORTA3_REG PORTA
257 #define PORTA4_REG PORTA
258 #define PORTA5_REG PORTA
259 #define PORTA6_REG PORTA
260 #define PORTA7_REG PORTA
263 #define UDR00_REG UDR0
264 #define UDR01_REG UDR0
265 #define UDR02_REG UDR0
266 #define UDR03_REG UDR0
267 #define UDR04_REG UDR0
268 #define UDR05_REG UDR0
269 #define UDR06_REG UDR0
270 #define UDR07_REG UDR0
273 #define GPIOR20_REG GPIOR2
274 #define GPIOR21_REG GPIOR2
275 #define GPIOR22_REG GPIOR2
276 #define GPIOR23_REG GPIOR2
277 #define GPIOR24_REG GPIOR2
278 #define GPIOR25_REG GPIOR2
279 #define GPIOR26_REG GPIOR2
280 #define GPIOR27_REG GPIOR2
283 #define ISC00_REG EICRA
284 #define ISC01_REG EICRA
287 #define ADC0D_REG DIDR0
288 #define ADC1D_REG DIDR0
289 #define ADC2D_REG DIDR0
290 #define ADC3D_REG DIDR0
291 #define ADC4D_REG DIDR0
292 #define ADC5D_REG DIDR0
293 #define ADC6D_REG DIDR0
294 #define ADC7D_REG DIDR0
297 #define AIN0D_REG DIDR1
298 #define AIN1D_REG DIDR1
301 #define TCR2UB_REG ASSR
302 #define OCR2UB_REG ASSR
303 #define TCN2UB_REG ASSR
305 #define EXCLK_REG ASSR
308 #define CLKPS0_REG CLKPR
309 #define CLKPS1_REG CLKPR
310 #define CLKPS2_REG CLKPR
311 #define CLKPS3_REG CLKPR
312 #define CLKPCE_REG CLKPR
325 #define DDB0_REG DDRB
326 #define DDB1_REG DDRB
327 #define DDB2_REG DDRB
328 #define DDB3_REG DDRB
329 #define DDB4_REG DDRB
330 #define DDB5_REG DDRB
331 #define DDB6_REG DDRB
332 #define DDB7_REG DDRB
335 #define DDC0_REG DDRC
336 #define DDC1_REG DDRC
337 #define DDC2_REG DDRC
338 #define DDC3_REG DDRC
339 #define DDC4_REG DDRC
340 #define DDC5_REG DDRC
341 #define DDC6_REG DDRC
342 #define DDC7_REG DDRC
345 #define DDA0_REG DDRA
346 #define DDA1_REG DDRA
347 #define DDA2_REG DDRA
348 #define DDA3_REG DDRA
349 #define DDA4_REG DDRA
350 #define DDA5_REG DDRA
351 #define DDA6_REG DDRA
352 #define DDA7_REG DDRA
355 #define WGM10_REG TCCR1A
356 #define WGM11_REG TCCR1A
357 #define COM1B0_REG TCCR1A
358 #define COM1B1_REG TCCR1A
359 #define COM1A0_REG TCCR1A
360 #define COM1A1_REG TCCR1A
363 #define DDG0_REG DDRG
364 #define DDG1_REG DDRG
365 #define DDG2_REG DDRG
366 #define DDG3_REG DDRG
367 #define DDG4_REG DDRG
370 #define FOC1B_REG TCCR1C
371 #define FOC1A_REG TCCR1C
374 #define CS10_REG TCCR1B
375 #define CS11_REG TCCR1B
376 #define CS12_REG TCCR1B
377 #define WGM12_REG TCCR1B
378 #define WGM13_REG TCCR1B
379 #define ICES1_REG TCCR1B
380 #define ICNC1_REG TCCR1B
383 #define CAL0_REG OSCCAL
384 #define CAL1_REG OSCCAL
385 #define CAL2_REG OSCCAL
386 #define CAL3_REG OSCCAL
387 #define CAL4_REG OSCCAL
388 #define CAL5_REG OSCCAL
389 #define CAL6_REG OSCCAL
390 #define CAL7_REG OSCCAL
393 #define SEG024_REG LCDDR3
396 #define SEG016_REG LCDDR2
397 #define SEG017_REG LCDDR2
398 #define SEG018_REG LCDDR2
399 #define SEG019_REG LCDDR2
400 #define SEG020_REG LCDDR2
401 #define SEG021_REG LCDDR2
402 #define SEG022_REG LCDDR2
403 #define SEG023_REG LCDDR2
406 #define SEG008_REG LCDDR1
407 #define SEG009_REG LCDDR1
408 #define SEG010_REG LCDDR1
409 #define SEG011_REG LCDDR1
410 #define SEG012_REG LCDDR1
411 #define SEG013_REG LCDDR1
412 #define SEG014_REG LCDDR1
413 #define SEG015_REG LCDDR1
416 #define SEG000_REG LCDDR0
417 #define SEG001_REG LCDDR0
418 #define SEG002_REG LCDDR0
419 #define SEG003_REG LCDDR0
420 #define SEG004_REG LCDDR0
421 #define SEG005_REG LCDDR0
422 #define SEG006_REG LCDDR0
423 #define SEG007_REG LCDDR0
426 #define SEG116_REG LCDDR7
427 #define SEG117_REG LCDDR7
428 #define SEG118_REG LCDDR7
429 #define SEG119_REG LCDDR7
430 #define SEG120_REG LCDDR7
431 #define SEG121_REG LCDDR7
432 #define SEG122_REG LCDDR7
433 #define SEG123_REG LCDDR7
436 #define SEG108_REG LCDDR6
437 #define SEG109_REG LCDDR6
438 #define SEG110_REG LCDDR6
439 #define SEG111_REG LCDDR6
440 #define SEG112_REG LCDDR6
441 #define SEG113_REG LCDDR6
442 #define SEG114_REG LCDDR6
443 #define SEG115_REG LCDDR6
446 #define SEG100_REG LCDDR5
447 #define SEG101_REG LCDDR5
448 #define SEG102_REG LCDDR5
449 #define SEG103_REG LCDDR5
450 #define SEG104_REG LCDDR5
451 #define SEG105_REG LCDDR5
452 #define SEG106_REG LCDDR5
453 #define SEG107_REG LCDDR5
456 #define GPIOR10_REG GPIOR1
457 #define GPIOR11_REG GPIOR1
458 #define GPIOR12_REG GPIOR1
459 #define GPIOR13_REG GPIOR1
460 #define GPIOR14_REG GPIOR1
461 #define GPIOR15_REG GPIOR1
462 #define GPIOR16_REG GPIOR1
463 #define GPIOR17_REG GPIOR1
466 #define GPIOR00_REG GPIOR0
467 #define GPIOR01_REG GPIOR0
468 #define GPIOR02_REG GPIOR0
469 #define GPIOR03_REG GPIOR0
470 #define GPIOR04_REG GPIOR0
471 #define GPIOR05_REG GPIOR0
472 #define GPIOR06_REG GPIOR0
473 #define GPIOR07_REG GPIOR0
476 #define SEG124_REG LCDDR8
479 #define LCDBL_REG LCDCRA
480 #define LCDIE_REG LCDCRA
481 #define LCDIF_REG LCDCRA
482 #define LCDAB_REG LCDCRA
483 #define LCDEN_REG LCDCRA
486 #define DDE0_REG DDRE
487 #define DDE1_REG DDRE
488 #define DDE2_REG DDRE
489 #define DDE3_REG DDRE
490 #define DDE4_REG DDRE
491 #define DDE5_REG DDRE
492 #define DDE6_REG DDRE
493 #define DDE7_REG DDRE
496 #define TCNT2_0_REG TCNT2
497 #define TCNT2_1_REG TCNT2
498 #define TCNT2_2_REG TCNT2
499 #define TCNT2_3_REG TCNT2
500 #define TCNT2_4_REG TCNT2
501 #define TCNT2_5_REG TCNT2
502 #define TCNT2_6_REG TCNT2
503 #define TCNT2_7_REG TCNT2
506 #define TCNT0_0_REG TCNT0
507 #define TCNT0_1_REG TCNT0
508 #define TCNT0_2_REG TCNT0
509 #define TCNT0_3_REG TCNT0
510 #define TCNT0_4_REG TCNT0
511 #define TCNT0_5_REG TCNT0
512 #define TCNT0_6_REG TCNT0
513 #define TCNT0_7_REG TCNT0
516 #define CS00_REG TCCR0A
517 #define CS01_REG TCCR0A
518 #define CS02_REG TCCR0A
519 #define WGM01_REG TCCR0A
520 #define COM0A0_REG TCCR0A
521 #define COM0A1_REG TCCR0A
522 #define WGM00_REG TCCR0A
523 #define FOC0A_REG TCCR0A
526 #define TOV2_REG TIFR2
527 #define OCF2A_REG TIFR2
530 #define SPR0_REG SPCR
531 #define SPR1_REG SPCR
532 #define CPHA_REG SPCR
533 #define CPOL_REG SPCR
534 #define MSTR_REG SPCR
535 #define DORD_REG SPCR
537 #define SPIE_REG SPCR
540 #define TOV1_REG TIFR1
541 #define OCF1A_REG TIFR1
542 #define OCF1B_REG TIFR1
543 #define ICF1_REG TIFR1
546 #define PSR310_REG GTCCR
547 #define TSM_REG GTCCR
548 #define PSR2_REG GTCCR
551 #define ICR1H0_REG ICR1H
552 #define ICR1H1_REG ICR1H
553 #define ICR1H2_REG ICR1H
554 #define ICR1H3_REG ICR1H
555 #define ICR1H4_REG ICR1H
556 #define ICR1H5_REG ICR1H
557 #define ICR1H6_REG ICR1H
558 #define ICR1H7_REG ICR1H
561 #define LCDPM0_REG LCDCRB
562 #define LCDPM1_REG LCDCRB
563 #define LCDPM2_REG LCDCRB
564 #define LCDPM3_REG LCDCRB
565 #define LCDMUX0_REG LCDCRB
566 #define LCDMUX1_REG LCDCRB
567 #define LCD2B_REG LCDCRB
568 #define LCDCS_REG LCDCRB
571 #define SEG324_REG LCDDR18
574 #define SEG224_REG LCDDR13
577 #define SEG216_REG LCDDR12
578 #define SEG217_REG LCDDR12
579 #define SEG218_REG LCDDR12
580 #define SEG219_REG LCDDR12
581 #define SEG220_REG LCDDR12
582 #define SEG221_REG LCDDR12
583 #define SEG222_REG LCDDR12
584 #define SEG223_REG LCDDR12
587 #define SEG208_REG LCDDR11
588 #define SEG209_REG LCDDR11
589 #define SEG210_REG LCDDR11
590 #define SEG211_REG LCDDR11
591 #define SEG212_REG LCDDR11
592 #define SEG213_REG LCDDR11
593 #define SEG214_REG LCDDR11
594 #define SEG215_REG LCDDR11
597 #define SEG200_REG LCDDR10
598 #define SEG201_REG LCDDR10
599 #define SEG202_REG LCDDR10
600 #define SEG203_REG LCDDR10
601 #define SEG204_REG LCDDR10
602 #define SEG205_REG LCDDR10
603 #define SEG206_REG LCDDR10
604 #define SEG207_REG LCDDR10
607 #define SEG316_REG LCDDR17
608 #define SEG317_REG LCDDR17
609 #define SEG318_REG LCDDR17
610 #define SEG319_REG LCDDR17
611 #define SEG320_REG LCDDR17
612 #define SEG321_REG LCDDR17
613 #define SEG322_REG LCDDR17
614 #define SEG323_REG LCDDR17
617 #define SEG308_REG LCDDR16
618 #define SEG309_REG LCDDR16
619 #define SEG310_REG LCDDR16
620 #define SEG311_REG LCDDR16
621 #define SEG312_REG LCDDR16
622 #define SEG313_REG LCDDR16
623 #define SEG314_REG LCDDR16
624 #define SEG315_REG LCDDR16
627 #define SEG300_REG LCDDR15
628 #define SEG301_REG LCDDR15
629 #define SEG302_REG LCDDR15
630 #define SEG303_REG LCDDR15
631 #define SEG304_REG LCDDR15
632 #define SEG305_REG LCDDR15
633 #define SEG306_REG LCDDR15
634 #define SEG307_REG LCDDR15
637 #define OCR1BL0_REG OCR1BL
638 #define OCR1BL1_REG OCR1BL
639 #define OCR1BL2_REG OCR1BL
640 #define OCR1BL3_REG OCR1BL
641 #define OCR1BL4_REG OCR1BL
642 #define OCR1BL5_REG OCR1BL
643 #define OCR1BL6_REG OCR1BL
644 #define OCR1BL7_REG OCR1BL
647 #define OCR1BH0_REG OCR1BH
648 #define OCR1BH1_REG OCR1BH
649 #define OCR1BH2_REG OCR1BH
650 #define OCR1BH3_REG OCR1BH
651 #define OCR1BH4_REG OCR1BH
652 #define OCR1BH5_REG OCR1BH
653 #define OCR1BH6_REG OCR1BH
654 #define OCR1BH7_REG OCR1BH
667 #define PORF_REG MCUSR
668 #define EXTRF_REG MCUSR
669 #define BORF_REG MCUSR
670 #define WDRF_REG MCUSR
671 #define JTRF_REG MCUSR
674 #define EERE_REG EECR
675 #define EEWE_REG EECR
676 #define EEMWE_REG EECR
677 #define EERIE_REG EECR
686 #define CS20_REG TCCR2A
687 #define CS21_REG TCCR2A
688 #define CS22_REG TCCR2A
689 #define WGM21_REG TCCR2A
690 #define COM2A0_REG TCCR2A
691 #define COM2A1_REG TCCR2A
692 #define WGM20_REG TCCR2A
693 #define FOC2A_REG TCCR2A
696 #define UBRR8_REG UBRR0H
697 #define UBRR9_REG UBRR0H
698 #define UBRR10_REG UBRR0H
699 #define UBRR11_REG UBRR0H
702 #define UBRR0_REG UBRR0L
703 #define UBRR1_REG UBRR0L
704 #define UBRR2_REG UBRR0L
705 #define UBRR3_REG UBRR0L
706 #define UBRR4_REG UBRR0L
707 #define UBRR5_REG UBRR0L
708 #define UBRR6_REG UBRR0L
709 #define UBRR7_REG UBRR0L
712 #define EEAR8_REG EEARH
713 #define EEAR9_REG EEARH
714 #define EEAR10_REG EEARH
717 #define EEARL0_REG EEARL
718 #define EEARL1_REG EEARL
719 #define EEARL2_REG EEARL
720 #define EEARL3_REG EEARL
721 #define EEARL4_REG EEARL
722 #define EEARL5_REG EEARL
723 #define EEARL6_REG EEARL
724 #define EEARL7_REG EEARL
727 #define IVCE_REG MCUCR
728 #define IVSEL_REG MCUCR
729 #define PUD_REG MCUCR
730 #define JTD_REG MCUCR
733 #define OCDR0_REG OCDR
734 #define OCDR1_REG OCDR
735 #define OCDR2_REG OCDR
736 #define OCDR3_REG OCDR
737 #define OCDR4_REG OCDR
738 #define OCDR5_REG OCDR
739 #define OCDR6_REG OCDR
740 #define OCDR7_REG OCDR
743 #define PINA0_REG PINA
744 #define PINA1_REG PINA
745 #define PINA2_REG PINA
746 #define PINA3_REG PINA
747 #define PINA4_REG PINA
748 #define PINA5_REG PINA
749 #define PINA6_REG PINA
750 #define PINA7_REG PINA
753 #define PORTE0_REG PORTE
754 #define PORTE1_REG PORTE
755 #define PORTE2_REG PORTE
756 #define PORTE3_REG PORTE
757 #define PORTE4_REG PORTE
758 #define PORTE5_REG PORTE
759 #define PORTE6_REG PORTE
760 #define PORTE7_REG PORTE
763 #define LCDCC0_REG LCDCCR
764 #define LCDCC1_REG LCDCCR
765 #define LCDCC2_REG LCDCCR
766 #define LCDCC3_REG LCDCCR
767 #define LCDDC0_REG LCDCCR
768 #define LCDDC1_REG LCDCCR
769 #define LCDDC2_REG LCDCCR
772 #define PINE0_REG PINE
773 #define PINE1_REG PINE
774 #define PINE2_REG PINE
775 #define PINE3_REG PINE
776 #define PINE4_REG PINE
777 #define PINE5_REG PINE
778 #define PINE6_REG PINE
779 #define PINE7_REG PINE
782 #define ADPS0_REG ADCSRA
783 #define ADPS1_REG ADCSRA
784 #define ADPS2_REG ADCSRA
785 #define ADIE_REG ADCSRA
786 #define ADIF_REG ADCSRA
787 #define ADATE_REG ADCSRA
788 #define ADSC_REG ADCSRA
789 #define ADEN_REG ADCSRA
792 #define ADTS0_REG ADCSRB
793 #define ADTS1_REG ADCSRB
794 #define ADTS2_REG ADCSRB
795 #define ACME_REG ADCSRB
798 #define DDF0_REG DDRF
799 #define DDF1_REG DDRF
800 #define DDF2_REG DDRF
801 #define DDF3_REG DDRF
802 #define DDF4_REG DDRF
803 #define DDF5_REG DDRF
804 #define DDF6_REG DDRF
805 #define DDF7_REG DDRF
808 #define OCR0A0_REG OCR0A
809 #define OCR0A1_REG OCR0A
810 #define OCR0A2_REG OCR0A
811 #define OCR0A3_REG OCR0A
812 #define OCR0A4_REG OCR0A
813 #define OCR0A5_REG OCR0A
814 #define OCR0A6_REG OCR0A
815 #define OCR0A7_REG OCR0A
818 #define ACIS0_REG ACSR
819 #define ACIS1_REG ACSR
820 #define ACIC_REG ACSR
821 #define ACIE_REG ACSR
824 #define ACBG_REG ACSR
828 #define TCNT1L0_REG TCNT1L
829 #define TCNT1L1_REG TCNT1L
830 #define TCNT1L2_REG TCNT1L
831 #define TCNT1L3_REG TCNT1L
832 #define TCNT1L4_REG TCNT1L
833 #define TCNT1L5_REG TCNT1L
834 #define TCNT1L6_REG TCNT1L
835 #define TCNT1L7_REG TCNT1L
838 #define DDD0_REG DDRD
839 #define DDD1_REG DDRD
840 #define DDD2_REG DDRD
841 #define DDD3_REG DDRD
842 #define DDD4_REG DDRD
843 #define DDD5_REG DDRD
844 #define DDD6_REG DDRD
845 #define DDD7_REG DDRD
848 #define USITC_REG USICR
849 #define USICLK_REG USICR
850 #define USICS0_REG USICR
851 #define USICS1_REG USICR
852 #define USIWM0_REG USICR
853 #define USIWM1_REG USICR
854 #define USIOIE_REG USICR
855 #define USISIE_REG USICR
858 #define PORTD0_REG PORTD
859 #define PORTD1_REG PORTD
860 #define PORTD2_REG PORTD
861 #define PORTD3_REG PORTD
862 #define PORTD4_REG PORTD
863 #define PORTD5_REG PORTD
864 #define PORTD6_REG PORTD
865 #define PORTD7_REG PORTD
868 #define TXB80_REG UCSR0B
869 #define RXB80_REG UCSR0B
870 #define UCSZ02_REG UCSR0B
871 #define TXEN0_REG UCSR0B
872 #define RXEN0_REG UCSR0B
873 #define UDRIE0_REG UCSR0B
874 #define TXCIE0_REG UCSR0B
875 #define RXCIE0_REG UCSR0B
878 #define SPMEN_REG SPMCSR
879 #define PGERS_REG SPMCSR
880 #define PGWRT_REG SPMCSR
881 #define BLBSET_REG SPMCSR
882 #define RWWSRE_REG SPMCSR
883 #define RWWSB_REG SPMCSR
884 #define SPMIE_REG SPMCSR
887 #define PORTB0_REG PORTB
888 #define PORTB1_REG PORTB
889 #define PORTB2_REG PORTB
890 #define PORTB3_REG PORTB
891 #define PORTB4_REG PORTB
892 #define PORTB5_REG PORTB
893 #define PORTB6_REG PORTB
894 #define PORTB7_REG PORTB
897 #define ADCL0_REG ADCL
898 #define ADCL1_REG ADCL
899 #define ADCL2_REG ADCL
900 #define ADCL3_REG ADCL
901 #define ADCL4_REG ADCL
902 #define ADCL5_REG ADCL
903 #define ADCL6_REG ADCL
904 #define ADCL7_REG ADCL
907 #define ADCH0_REG ADCH
908 #define ADCH1_REG ADCH
909 #define ADCH2_REG ADCH
910 #define ADCH3_REG ADCH
911 #define ADCH4_REG ADCH
912 #define ADCH5_REG ADCH
913 #define ADCH6_REG ADCH
914 #define ADCH7_REG ADCH
917 #define LCDCD0_REG LCDFRR
918 #define LCDCD1_REG LCDFRR
919 #define LCDCD2_REG LCDFRR
920 #define LCDPS0_REG LCDFRR
921 #define LCDPS1_REG LCDFRR
922 #define LCDPS2_REG LCDFRR
925 #define TOIE2_REG TIMSK2
926 #define OCIE2A_REG TIMSK2
929 #define INT0_REG EIMSK
930 #define PCIE0_REG EIMSK
931 #define PCIE1_REG EIMSK
932 #define PCIE2_REG EIMSK
933 #define PCIE3_REG EIMSK
936 #define TOIE0_REG TIMSK0
937 #define OCIE0A_REG TIMSK0
940 #define TOIE1_REG TIMSK1
941 #define OCIE1A_REG TIMSK1
942 #define OCIE1B_REG TIMSK1
943 #define ICIE1_REG TIMSK1
946 #define PCINT0_REG PCMSK0
947 #define PCINT1_REG PCMSK0
948 #define PCINT2_REG PCMSK0
949 #define PCINT3_REG PCMSK0
950 #define PCINT4_REG PCMSK0
951 #define PCINT5_REG PCMSK0
952 #define PCINT6_REG PCMSK0
953 #define PCINT7_REG PCMSK0
956 #define PCINT8_REG PCMSK1
957 #define PCINT9_REG PCMSK1
958 #define PCINT10_REG PCMSK1
959 #define PCINT11_REG PCMSK1
960 #define PCINT12_REG PCMSK1
961 #define PCINT13_REG PCMSK1
962 #define PCINT14_REG PCMSK1
963 #define PCINT15_REG PCMSK1
966 #define PINC0_REG PINC
967 #define PINC1_REG PINC
968 #define PINC2_REG PINC
969 #define PINC3_REG PINC
970 #define PINC4_REG PINC
971 #define PINC5_REG PINC
972 #define PINC6_REG PINC
973 #define PINC7_REG PINC
976 #define PINB0_REG PINB
977 #define PINB1_REG PINB
978 #define PINB2_REG PINB
979 #define PINB3_REG PINB
980 #define PINB4_REG PINB
981 #define PINB5_REG PINB
982 #define PINB6_REG PINB
983 #define PINB7_REG PINB
986 #define INTF0_REG EIFR
987 #define PCIF0_REG EIFR
988 #define PCIF1_REG EIFR
989 #define PCIF2_REG EIFR
990 #define PCIF3_REG EIFR
993 #define PING0_REG PING
994 #define PING1_REG PING
995 #define PING2_REG PING
996 #define PING3_REG PING
997 #define PING4_REG PING
998 #define PING5_REG PING
1001 #define PINF0_REG PINF
1002 #define PINF1_REG PINF
1003 #define PINF2_REG PINF
1004 #define PINF3_REG PINF
1005 #define PINF4_REG PINF
1006 #define PINF5_REG PINF
1007 #define PINF6_REG PINF
1008 #define PINF7_REG PINF
1011 #define PORTF0_REG PORTF
1012 #define PORTF1_REG PORTF
1013 #define PORTF2_REG PORTF
1014 #define PORTF3_REG PORTF
1015 #define PORTF4_REG PORTF
1016 #define PORTF5_REG PORTF
1017 #define PORTF6_REG PORTF
1018 #define PORTF7_REG PORTF
1021 #define PIND0_REG PIND
1022 #define PIND1_REG PIND
1023 #define PIND2_REG PIND
1024 #define PIND3_REG PIND
1025 #define PIND4_REG PIND
1026 #define PIND5_REG PIND
1027 #define PIND6_REG PIND
1028 #define PIND7_REG PIND
1031 #define OCR1AH0_REG OCR1AH
1032 #define OCR1AH1_REG OCR1AH
1033 #define OCR1AH2_REG OCR1AH
1034 #define OCR1AH3_REG OCR1AH
1035 #define OCR1AH4_REG OCR1AH
1036 #define OCR1AH5_REG OCR1AH
1037 #define OCR1AH6_REG OCR1AH
1038 #define OCR1AH7_REG OCR1AH
1041 #define OCR1AL0_REG OCR1AL
1042 #define OCR1AL1_REG OCR1AL
1043 #define OCR1AL2_REG OCR1AL
1044 #define OCR1AL3_REG OCR1AL
1045 #define OCR1AL4_REG OCR1AL
1046 #define OCR1AL5_REG OCR1AL
1047 #define OCR1AL6_REG OCR1AL
1048 #define OCR1AL7_REG OCR1AL
1051 #define TOV0_REG TIFR0
1052 #define OCF0A_REG TIFR0
1055 #define USIDR0_REG USIDR
1056 #define USIDR1_REG USIDR
1057 #define USIDR2_REG USIDR
1058 #define USIDR3_REG USIDR
1059 #define USIDR4_REG USIDR
1060 #define USIDR5_REG USIDR
1061 #define USIDR6_REG USIDR
1062 #define USIDR7_REG USIDR