2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_2 2
50 #define TIMER1_PRESCALER_DIV_4 3
51 #define TIMER1_PRESCALER_DIV_8 4
52 #define TIMER1_PRESCALER_DIV_16 5
53 #define TIMER1_PRESCALER_DIV_32 6
54 #define TIMER1_PRESCALER_DIV_64 7
55 #define TIMER1_PRESCALER_DIV_128 8
56 #define TIMER1_PRESCALER_DIV_256 9
57 #define TIMER1_PRESCALER_DIV_512 10
58 #define TIMER1_PRESCALER_DIV_1024 11
59 #define TIMER1_PRESCALER_DIV_2048 12
60 #define TIMER1_PRESCALER_DIV_4096 13
61 #define TIMER1_PRESCALER_DIV_8192 14
62 #define TIMER1_PRESCALER_DIV_16384 15
64 #define TIMER1_PRESCALER_REG_0 0
65 #define TIMER1_PRESCALER_REG_1 1
66 #define TIMER1_PRESCALER_REG_2 2
67 #define TIMER1_PRESCALER_REG_3 4
68 #define TIMER1_PRESCALER_REG_4 8
69 #define TIMER1_PRESCALER_REG_5 16
70 #define TIMER1_PRESCALER_REG_6 32
71 #define TIMER1_PRESCALER_REG_7 64
72 #define TIMER1_PRESCALER_REG_8 128
73 #define TIMER1_PRESCALER_REG_9 256
74 #define TIMER1_PRESCALER_REG_10 512
75 #define TIMER1_PRESCALER_REG_11 1024
76 #define TIMER1_PRESCALER_REG_12 2048
77 #define TIMER1_PRESCALER_REG_13 4096
78 #define TIMER1_PRESCALER_REG_14 8192
79 #define TIMER1_PRESCALER_REG_15 16384
82 /* available timers */
83 #define TIMER0_AVAILABLE
84 #define TIMER0A_AVAILABLE
85 #define TIMER0B_AVAILABLE
86 #define TIMER1_AVAILABLE
87 #define TIMER1A_AVAILABLE
88 #define TIMER1B_AVAILABLE
90 /* overflow interrupt number */
91 #define SIG_OVERFLOW0_NUM 0
92 #define SIG_OVERFLOW1_NUM 1
93 #define SIG_OVERFLOW_TOTAL_NUM 2
95 /* output compare interrupt number */
96 #define SIG_OUTPUT_COMPARE0A_NUM 0
97 #define SIG_OUTPUT_COMPARE0B_NUM 1
98 #define SIG_OUTPUT_COMPARE1A_NUM 2
99 #define SIG_OUTPUT_COMPARE1B_NUM 3
100 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
107 #define PWM_TOTAL_NUM 4
109 /* input capture interrupt number */
110 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
114 #define CLKPS0_REG CLKPR
115 #define CLKPS1_REG CLKPR
116 #define CLKPS2_REG CLKPR
117 #define CLKPS3_REG CLKPR
118 #define CLKPCE_REG CLKPR
121 #define WDP0_REG WDTCR
122 #define WDP1_REG WDTCR
123 #define WDP2_REG WDTCR
124 #define WDE_REG WDTCR
125 #define WDCE_REG WDTCR
126 #define WDP3_REG WDTCR
127 #define WDIE_REG WDTCR
128 #define WDIF_REG WDTCR
131 #define PCIE_REG GIMSK
132 #define INT0_REG GIMSK
135 #define AIN0D_REG DIDR0
136 #define AIN1D_REG DIDR0
137 #define ADC1D_REG DIDR0
138 #define ADC3D_REG DIDR0
139 #define ADC2D_REG DIDR0
140 #define ADC0D_REG DIDR0
143 #define MUX0_REG ADMUX
144 #define MUX1_REG ADMUX
145 #define MUX2_REG ADMUX
146 #define MUX3_REG ADMUX
147 #define REFS2_REG ADMUX
148 #define ADLAR_REG ADMUX
149 #define REFS0_REG ADMUX
150 #define REFS1_REG ADMUX
153 #define CS10_REG TCCR1
154 #define CS11_REG TCCR1
155 #define CS12_REG TCCR1
156 #define CS13_REG TCCR1
157 #define COM1A0_REG TCCR1
158 #define COM1A1_REG TCCR1
159 #define PWM1A_REG TCCR1
160 #define CTC1_REG TCCR1
173 #define DDB0_REG DDRB
174 #define DDB1_REG DDRB
175 #define DDB2_REG DDRB
176 #define DDB3_REG DDRB
177 #define DDB4_REG DDRB
178 #define DDB5_REG DDRB
181 #define EEDR0_REG EEDR
182 #define EEDR1_REG EEDR
183 #define EEDR2_REG EEDR
184 #define EEDR3_REG EEDR
185 #define EEDR4_REG EEDR
186 #define EEDR5_REG EEDR
187 #define EEDR6_REG EEDR
188 #define EEDR7_REG EEDR
191 #define ISC00_REG MCUCR
192 #define ISC01_REG MCUCR
193 #define SM0_REG MCUCR
194 #define SM1_REG MCUCR
196 #define PUD_REG MCUCR
199 #define PSR0_REG GTCCR
200 #define TSM_REG GTCCR
201 #define PSR1_REG GTCCR
202 #define FOC1A_REG GTCCR
203 #define FOC1B_REG GTCCR
204 #define COM1B0_REG GTCCR
205 #define COM1B1_REG GTCCR
206 #define PWM1B_REG GTCCR
209 #define DTPS0_REG DTPS
210 #define DTPS1_REG DTPS
213 #define PCIF_REG GIFR
214 #define INTF0_REG GIFR
217 #define TOIE0_REG TIMSK
218 #define OCIE0B_REG TIMSK
219 #define OCIE0A_REG TIMSK
220 #define TOIE1_REG TIMSK
221 #define OCIE1B_REG TIMSK
222 #define OCIE1A_REG TIMSK
225 #define ADPS0_REG ADCSRA
226 #define ADPS1_REG ADCSRA
227 #define ADPS2_REG ADCSRA
228 #define ADIE_REG ADCSRA
229 #define ADIF_REG ADCSRA
230 #define ADATE_REG ADCSRA
231 #define ADSC_REG ADCSRA
232 #define ADEN_REG ADCSRA
235 /* #define DTVL0_REG DT1B */ /* dup in DT1A */
236 /* #define DTVL1_REG DT1B */ /* dup in DT1A */
237 /* #define DTVL2_REG DT1B */ /* dup in DT1A */
238 /* #define DTVL3_REG DT1B */ /* dup in DT1A */
239 /* #define DTVH0_REG DT1B */ /* dup in DT1A */
240 /* #define DTVH1_REG DT1B */ /* dup in DT1A */
241 /* #define DTVH2_REG DT1B */ /* dup in DT1A */
242 /* #define DTVH3_REG DT1B */ /* dup in DT1A */
245 /* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
246 /* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
247 /* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
248 /* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
249 /* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
250 /* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
251 /* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
252 /* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
255 /* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
256 /* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
257 /* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
258 /* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
259 /* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
260 /* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
261 /* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
262 /* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
275 #define PRADC_REG PRR
276 #define PRUSI_REG PRR
277 #define PRTIM0_REG PRR
278 #define PRTIM1_REG PRR
281 #define GPIOR10_REG GPIOR1
282 #define GPIOR11_REG GPIOR1
283 #define GPIOR12_REG GPIOR1
284 #define GPIOR13_REG GPIOR1
285 #define GPIOR14_REG GPIOR1
286 #define GPIOR15_REG GPIOR1
287 #define GPIOR16_REG GPIOR1
288 #define GPIOR17_REG GPIOR1
291 #define GPIOR00_REG GPIOR0
292 #define GPIOR01_REG GPIOR0
293 #define GPIOR02_REG GPIOR0
294 #define GPIOR03_REG GPIOR0
295 #define GPIOR04_REG GPIOR0
296 #define GPIOR05_REG GPIOR0
297 #define GPIOR06_REG GPIOR0
298 #define GPIOR07_REG GPIOR0
301 #define GPIOR20_REG GPIOR2
302 #define GPIOR21_REG GPIOR2
303 #define GPIOR22_REG GPIOR2
304 #define GPIOR23_REG GPIOR2
305 #define GPIOR24_REG GPIOR2
306 #define GPIOR25_REG GPIOR2
307 #define GPIOR26_REG GPIOR2
308 #define GPIOR27_REG GPIOR2
311 #define PORF_REG MCUSR
312 #define EXTRF_REG MCUSR
313 #define BORF_REG MCUSR
314 #define WDRF_REG MCUSR
317 #define EERE_REG EECR
318 #define EEPE_REG EECR
319 #define EEMPE_REG EECR
320 #define EERIE_REG EECR
321 #define EEPM0_REG EECR
322 #define EEPM1_REG EECR
325 #define PCINT0_REG PCMSK
326 #define PCINT1_REG PCMSK
327 #define PCINT2_REG PCMSK
328 #define PCINT3_REG PCMSK
329 #define PCINT4_REG PCMSK
330 #define PCINT5_REG PCMSK
333 #define SPMEN_REG SPMCSR
334 #define PGERS_REG SPMCSR
335 #define PGWRT_REG SPMCSR
336 #define RFLB_REG SPMCSR
337 #define CTPB_REG SPMCSR
340 #define CAL0_REG OSCCAL
341 #define CAL1_REG OSCCAL
342 #define CAL2_REG OSCCAL
343 #define CAL3_REG OSCCAL
344 #define CAL4_REG OSCCAL
345 #define CAL5_REG OSCCAL
346 #define CAL6_REG OSCCAL
347 #define CAL7_REG OSCCAL
350 #define ADCL0_REG ADCL
351 #define ADCL1_REG ADCL
352 #define ADCL2_REG ADCL
353 #define ADCL3_REG ADCL
354 #define ADCL4_REG ADCL
355 #define ADCL5_REG ADCL
356 #define ADCL6_REG ADCL
357 #define ADCL7_REG ADCL
360 #define USICNT0_REG USISR
361 #define USICNT1_REG USISR
362 #define USICNT2_REG USISR
363 #define USICNT3_REG USISR
364 #define USIDC_REG USISR
365 #define USIPF_REG USISR
366 #define USIOIF_REG USISR
367 #define USISIF_REG USISR
370 #define PORTB0_REG PORTB
371 #define PORTB1_REG PORTB
372 #define PORTB2_REG PORTB
373 #define PORTB3_REG PORTB
374 #define PORTB4_REG PORTB
375 #define PORTB5_REG PORTB
378 #define ADCH0_REG ADCH
379 #define ADCH1_REG ADCH
380 #define ADCH2_REG ADCH
381 #define ADCH3_REG ADCH
382 #define ADCH4_REG ADCH
383 #define ADCH5_REG ADCH
384 #define ADCH6_REG ADCH
385 #define ADCH7_REG ADCH
388 #define TCNT0_0_REG TCNT0
389 #define TCNT0_1_REG TCNT0
390 #define TCNT0_2_REG TCNT0
391 #define TCNT0_3_REG TCNT0
392 #define TCNT0_4_REG TCNT0
393 #define TCNT0_5_REG TCNT0
394 #define TCNT0_6_REG TCNT0
395 #define TCNT0_7_REG TCNT0
398 #define TCNT1_0_REG TCNT1
399 #define TCNT1_1_REG TCNT1
400 #define TCNT1_2_REG TCNT1
401 #define TCNT1_3_REG TCNT1
402 #define TCNT1_4_REG TCNT1
403 #define TCNT1_5_REG TCNT1
404 #define TCNT1_6_REG TCNT1
405 #define TCNT1_7_REG TCNT1
408 #define CS00_REG TCCR0B
409 #define CS01_REG TCCR0B
410 #define CS02_REG TCCR0B
411 #define WGM02_REG TCCR0B
412 #define FOC0B_REG TCCR0B
413 #define FOC0A_REG TCCR0B
416 #define TOV0_REG TIFR
417 #define OCF0B_REG TIFR
418 #define OCF0A_REG TIFR
419 #define TOV1_REG TIFR
420 #define OCF1B_REG TIFR
421 #define OCF1A_REG TIFR
424 #define WGM00_REG TCCR0A
425 #define WGM01_REG TCCR0A
426 #define COM0B0_REG TCCR0A
427 #define COM0B1_REG TCCR0A
428 #define COM0A0_REG TCCR0A
429 #define COM0A1_REG TCCR0A
432 #define EEAR8_REG EEARH
435 #define PLOCK_REG PLLCSR
436 #define PLLE_REG PLLCSR
437 #define PCKE_REG PLLCSR
438 #define LSM_REG PLLCSR
441 #define USITC_REG USICR
442 #define USICLK_REG USICR
443 #define USICS0_REG USICR
444 #define USICS1_REG USICR
445 #define USIWM0_REG USICR
446 #define USIWM1_REG USICR
447 #define USIOIE_REG USICR
448 #define USISIE_REG USICR
451 #define EEAR0_REG EEARL
452 #define EEAR1_REG EEARL
453 #define EEAR2_REG EEARL
454 #define EEAR3_REG EEARL
455 #define EEAR4_REG EEARL
456 #define EEAR5_REG EEARL
457 #define EEAR6_REG EEARL
458 #define EEAR7_REG EEARL
461 #define DWDR0_REG DWDR
462 #define DWDR1_REG DWDR
463 #define DWDR2_REG DWDR
464 #define DWDR3_REG DWDR
465 #define DWDR4_REG DWDR
466 #define DWDR5_REG DWDR
467 #define DWDR6_REG DWDR
468 #define DWDR7_REG DWDR
471 #define ACME_REG ADCSRB
472 #define ADTS0_REG ADCSRB
473 #define ADTS1_REG ADCSRB
474 #define ADTS2_REG ADCSRB
475 #define IPR_REG ADCSRB
476 #define BIN_REG ADCSRB
479 #define OCR1B0_REG OCR1B
480 #define OCR1B1_REG OCR1B
481 #define OCR1B2_REG OCR1B
482 #define OCR1B3_REG OCR1B
483 #define OCR1B4_REG OCR1B
484 #define OCR1B5_REG OCR1B
485 #define OCR1B6_REG OCR1B
486 #define OCR1B7_REG OCR1B
489 #define OCR1C0_REG OCR1C
490 #define OCR1C1_REG OCR1C
491 #define OCR1C2_REG OCR1C
492 #define OCR1C3_REG OCR1C
493 #define OCR1C4_REG OCR1C
494 #define OCR1C5_REG OCR1C
495 #define OCR1C6_REG OCR1C
496 #define OCR1C7_REG OCR1C
499 /* #define DTVL0_REG DT1A */ /* dup in DT1B */
500 /* #define DTVL1_REG DT1A */ /* dup in DT1B */
501 /* #define DTVL2_REG DT1A */ /* dup in DT1B */
502 /* #define DTVL3_REG DT1A */ /* dup in DT1B */
503 /* #define DTVH0_REG DT1A */ /* dup in DT1B */
504 /* #define DTVH1_REG DT1A */ /* dup in DT1B */
505 /* #define DTVH2_REG DT1A */ /* dup in DT1B */
506 /* #define DTVH3_REG DT1A */ /* dup in DT1B */
509 #define OCR1A0_REG OCR1A
510 #define OCR1A1_REG OCR1A
511 #define OCR1A2_REG OCR1A
512 #define OCR1A3_REG OCR1A
513 #define OCR1A4_REG OCR1A
514 #define OCR1A5_REG OCR1A
515 #define OCR1A6_REG OCR1A
516 #define OCR1A7_REG OCR1A
519 #define ACIS0_REG ACSR
520 #define ACIS1_REG ACSR
521 #define ACIE_REG ACSR
524 #define ACBG_REG ACSR
528 #define PINB0_REG PINB
529 #define PINB1_REG PINB
530 #define PINB2_REG PINB
531 #define PINB3_REG PINB
532 #define PINB4_REG PINB
533 #define PINB5_REG PINB
536 #define USIBR0_REG USIBR
537 #define USIBR1_REG USIBR
538 #define USIBR2_REG USIBR
539 #define USIBR3_REG USIBR
540 #define USIBR4_REG USIBR
541 #define USIBR5_REG USIBR
542 #define USIBR6_REG USIBR
543 #define USIBR7_REG USIBR
546 #define USIDR0_REG USIDR
547 #define USIDR1_REG USIDR
548 #define USIDR2_REG USIDR
549 #define USIDR3_REG USIDR
550 #define USIDR4_REG USIDR
551 #define USIDR5_REG USIDR
552 #define USIDR6_REG USIDR
553 #define USIDR7_REG USIDR
556 #define MOSI_PORT PORTB
558 #define DI_PORT PORTB
560 #define SDA_PORT PORTB
562 #define AIN0_PORT PORTB
564 #define OC0A_PORT PORTB
566 #define OC1A_PORT PORTB
568 #define AREF_PORT PORTB
570 #define PCINT0_PORT PORTB
573 #define MISO_PORT PORTB
575 #define DO_PORT PORTB
577 #define AIN1_PORT PORTB
579 #define OC0B_PORT PORTB
581 #define OC1A_PORT PORTB
583 #define PCINT1_PORT PORTB
586 #define SCK_PORT PORTB
588 #define USCK_PORT PORTB
590 #define SCL_PORT PORTB
592 #define ADC1_PORT PORTB
594 #define T0_PORT PORTB
596 #define INT0_PORT PORTB
598 #define PCINT2_PORT PORTB
601 #define ADC3_PORT PORTB
603 #define OC1B_PORT PORTB
605 #define XTAL1_PORT PORTB
607 #define PCINT4_PORT PORTB
610 #define ADC2_PORT PORTB
612 #define OC1B_PORT PORTB
614 #define XTAL2_PORT PORTB
616 #define PCINT3_PORT PORTB
619 #define RESET_PORT PORTB
621 #define ADC0_PORT PORTB
623 #define PCINT5_PORT PORTB
625 #define dW_PORT PORTB