2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
68 /* overflow interrupt number */
69 #define SIG_OVERFLOW_TOTAL_NUM 0
71 /* output compare interrupt number */
72 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
75 #define PWM_TOTAL_NUM 0
77 /* input capture interrupt number */
78 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
82 #define CLKPS0_REG CLKPR
83 #define CLKPS1_REG CLKPR
84 #define CLKPS2_REG CLKPR
85 #define CLKPS3_REG CLKPR
86 #define CLKPCE_REG CLKPR
89 #define ACIS0_REG ACSR
90 #define ACIS1_REG ACSR
99 #define PCIE0_REG GIMSK
100 #define PCIE1_REG GIMSK
101 #define INT0_REG GIMSK
104 #define ICR1H0_REG ICR1H
105 #define ICR1H1_REG ICR1H
106 #define ICR1H2_REG ICR1H
107 #define ICR1H3_REG ICR1H
108 #define ICR1H4_REG ICR1H
109 #define ICR1H5_REG ICR1H
110 #define ICR1H6_REG ICR1H
111 #define ICR1H7_REG ICR1H
114 #define MUX0_REG ADMUX
115 #define MUX1_REG ADMUX
116 #define MUX2_REG ADMUX
117 #define MUX3_REG ADMUX
118 #define MUX4_REG ADMUX
119 #define MUX5_REG ADMUX
120 #define REFS0_REG ADMUX
121 #define REFS1_REG ADMUX
134 #define DDB0_REG DDRB
135 #define DDB1_REG DDRB
136 #define DDB2_REG DDRB
137 #define DDB3_REG DDRB
140 #define WDP0_REG WDTCSR
141 #define WDP1_REG WDTCSR
142 #define WDP2_REG WDTCSR
143 #define WDE_REG WDTCSR
144 #define WDCE_REG WDTCSR
145 #define WDP3_REG WDTCSR
146 #define WDIE_REG WDTCSR
147 #define WDIF_REG WDTCSR
150 #define EEDR0_REG EEDR
151 #define EEDR1_REG EEDR
152 #define EEDR2_REG EEDR
153 #define EEDR3_REG EEDR
154 #define EEDR4_REG EEDR
155 #define EEDR5_REG EEDR
156 #define EEDR6_REG EEDR
157 #define EEDR7_REG EEDR
160 #define DDA0_REG DDRA
161 #define DDA1_REG DDRA
162 #define DDA2_REG DDRA
163 #define DDA3_REG DDRA
164 #define DDA4_REG DDRA
165 #define DDA5_REG DDRA
166 #define DDA6_REG DDRA
167 #define DDA7_REG DDRA
170 #define WGM10_REG TCCR1A
171 #define WGM11_REG TCCR1A
172 #define COM1B0_REG TCCR1A
173 #define COM1B1_REG TCCR1A
174 #define COM1A0_REG TCCR1A
175 #define COM1A1_REG TCCR1A
178 #define PSR10_REG GTCCR
179 #define TSM_REG GTCCR
182 #define CS10_REG TCCR1B
183 #define CS11_REG TCCR1B
184 #define CS12_REG TCCR1B
185 #define WGM12_REG TCCR1B
186 #define WGM13_REG TCCR1B
187 #define ICES1_REG TCCR1B
188 #define ICNC1_REG TCCR1B
191 #define PCIF0_REG GIFR
192 #define PCIF1_REG GIFR
193 #define INTF0_REG GIFR
196 #define CAL0_REG OSCCAL
197 #define CAL1_REG OSCCAL
198 #define CAL2_REG OSCCAL
199 #define CAL3_REG OSCCAL
200 #define CAL4_REG OSCCAL
201 #define CAL5_REG OSCCAL
202 #define CAL6_REG OSCCAL
203 #define CAL7_REG OSCCAL
206 #define ADPS0_REG ADCSRA
207 #define ADPS1_REG ADCSRA
208 #define ADPS2_REG ADCSRA
209 #define ADIE_REG ADCSRA
210 #define ADIF_REG ADCSRA
211 #define ADATE_REG ADCSRA
212 #define ADSC_REG ADCSRA
213 #define ADEN_REG ADCSRA
216 #define ACME_REG ADCSRB
217 #define ADTS0_REG ADCSRB
218 #define ADTS1_REG ADCSRB
219 #define ADTS2_REG ADCSRB
220 #define ADLAR_REG ADCSRB
221 #define BIN_REG ADCSRB
224 /* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
225 /* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
226 /* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
227 /* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
228 /* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
229 /* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
230 /* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
231 /* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
234 /* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
235 /* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
236 /* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
237 /* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
238 /* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
239 /* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
240 /* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
241 /* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
247 /* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
248 /* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
249 /* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
250 /* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
251 /* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
252 /* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
253 /* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
254 /* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
267 /* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
268 /* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
269 /* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
270 /* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
271 /* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
272 /* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
273 /* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
274 /* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
277 #define PRADC_REG PRR
278 #define PRUSI_REG PRR
279 #define PRTIM0_REG PRR
280 #define PRTIM1_REG PRR
283 #define GPIOR10_REG GPIOR1
284 #define GPIOR11_REG GPIOR1
285 #define GPIOR12_REG GPIOR1
286 #define GPIOR13_REG GPIOR1
287 #define GPIOR14_REG GPIOR1
288 #define GPIOR15_REG GPIOR1
289 #define GPIOR16_REG GPIOR1
290 #define GPIOR17_REG GPIOR1
293 #define ICR1L0_REG ICR1L
294 #define ICR1L1_REG ICR1L
295 #define ICR1L2_REG ICR1L
296 #define ICR1L3_REG ICR1L
297 #define ICR1L4_REG ICR1L
298 #define ICR1L5_REG ICR1L
299 #define ICR1L6_REG ICR1L
300 #define ICR1L7_REG ICR1L
303 #define GPIOR20_REG GPIOR2
304 #define GPIOR21_REG GPIOR2
305 #define GPIOR22_REG GPIOR2
306 #define GPIOR23_REG GPIOR2
307 #define GPIOR24_REG GPIOR2
308 #define GPIOR25_REG GPIOR2
309 #define GPIOR26_REG GPIOR2
310 #define GPIOR27_REG GPIOR2
313 #define PORF_REG MCUSR
314 #define EXTRF_REG MCUSR
315 #define BORF_REG MCUSR
316 #define WDRF_REG MCUSR
319 #define EERE_REG EECR
320 #define EEPE_REG EECR
321 #define EEMPE_REG EECR
322 #define EERIE_REG EECR
323 #define EEPM0_REG EECR
324 #define EEPM1_REG EECR
327 #define SPMEN_REG SPMCSR
328 #define PGERS_REG SPMCSR
329 #define PGWRT_REG SPMCSR
330 #define RFLB_REG SPMCSR
331 #define CTPB_REG SPMCSR
334 #define TCNT1L0_REG TCNT1L
335 #define TCNT1L1_REG TCNT1L
336 #define TCNT1L2_REG TCNT1L
337 #define TCNT1L3_REG TCNT1L
338 #define TCNT1L4_REG TCNT1L
339 #define TCNT1L5_REG TCNT1L
340 #define TCNT1L6_REG TCNT1L
341 #define TCNT1L7_REG TCNT1L
344 #define PORTB0_REG PORTB
345 #define PORTB1_REG PORTB
346 #define PORTB2_REG PORTB
347 #define PORTB3_REG PORTB
350 #define ADCL0_REG ADCL
351 #define ADCL1_REG ADCL
352 #define ADCL2_REG ADCL
353 #define ADCL3_REG ADCL
354 #define ADCL4_REG ADCL
355 #define ADCL5_REG ADCL
356 #define ADCL6_REG ADCL
357 #define ADCL7_REG ADCL
360 #define USICNT0_REG USISR
361 #define USICNT1_REG USISR
362 #define USICNT2_REG USISR
363 #define USICNT3_REG USISR
364 #define USIDC_REG USISR
365 #define USIPF_REG USISR
366 #define USIOIF_REG USISR
367 #define USISIF_REG USISR
370 #define TCNT1H0_REG TCNT1H
371 #define TCNT1H1_REG TCNT1H
372 #define TCNT1H2_REG TCNT1H
373 #define TCNT1H3_REG TCNT1H
374 #define TCNT1H4_REG TCNT1H
375 #define TCNT1H5_REG TCNT1H
376 #define TCNT1H6_REG TCNT1H
377 #define TCNT1H7_REG TCNT1H
380 #define ADCH0_REG ADCH
381 #define ADCH1_REG ADCH
382 #define ADCH2_REG ADCH
383 #define ADCH3_REG ADCH
384 #define ADCH4_REG ADCH
385 #define ADCH5_REG ADCH
386 #define ADCH6_REG ADCH
387 #define ADCH7_REG ADCH
390 #define PORTA0_REG PORTA
391 #define PORTA1_REG PORTA
392 #define PORTA2_REG PORTA
393 #define PORTA3_REG PORTA
394 #define PORTA4_REG PORTA
395 #define PORTA5_REG PORTA
396 #define PORTA6_REG PORTA
397 #define PORTA7_REG PORTA
400 #define TCNT0_0_REG TCNT0
401 #define TCNT0_1_REG TCNT0
402 #define TCNT0_2_REG TCNT0
403 #define TCNT0_3_REG TCNT0
404 #define TCNT0_4_REG TCNT0
405 #define TCNT0_5_REG TCNT0
406 #define TCNT0_6_REG TCNT0
407 #define TCNT0_7_REG TCNT0
410 #define GPIOR00_REG GPIOR0
411 #define GPIOR01_REG GPIOR0
412 #define GPIOR02_REG GPIOR0
413 #define GPIOR03_REG GPIOR0
414 #define GPIOR04_REG GPIOR0
415 #define GPIOR05_REG GPIOR0
416 #define GPIOR06_REG GPIOR0
417 #define GPIOR07_REG GPIOR0
420 #define PCINT0_REG PCMSK0
421 #define PCINT1_REG PCMSK0
422 #define PCINT2_REG PCMSK0
423 #define PCINT3_REG PCMSK0
424 #define PCINT4_REG PCMSK0
425 #define PCINT5_REG PCMSK0
426 #define PCINT6_REG PCMSK0
427 #define PCINT7_REG PCMSK0
430 #define TOIE0_REG TIMSK0
431 #define OCIE0A_REG TIMSK0
432 #define OCIE0B_REG TIMSK0
435 #define TOIE1_REG TIMSK1
436 #define OCIE1A_REG TIMSK1
437 #define OCIE1B_REG TIMSK1
438 #define ICIE1_REG TIMSK1
441 #define CS00_REG TCCR0B
442 #define CS01_REG TCCR0B
443 #define CS02_REG TCCR0B
444 #define WGM02_REG TCCR0B
445 #define FOC0B_REG TCCR0B
446 #define FOC0A_REG TCCR0B
449 #define FOC1B_REG TCCR1C
450 #define FOC1A_REG TCCR1C
453 #define WGM00_REG TCCR0A
454 #define WGM01_REG TCCR0A
455 #define COM0B0_REG TCCR0A
456 #define COM0B1_REG TCCR0A
457 #define COM0A0_REG TCCR0A
458 #define COM0A1_REG TCCR0A
461 #define EEAR8_REG EEARH
464 #define USITC_REG USICR
465 #define USICLK_REG USICR
466 #define USICS0_REG USICR
467 #define USICS1_REG USICR
468 #define USIWM0_REG USICR
469 #define USIWM1_REG USICR
470 #define USIOIE_REG USICR
471 #define USISIE_REG USICR
474 #define EEAR0_REG EEARL
475 #define EEAR1_REG EEARL
476 #define EEAR2_REG EEARL
477 #define EEAR3_REG EEARL
478 #define EEAR4_REG EEARL
479 #define EEAR5_REG EEARL
480 #define EEAR6_REG EEARL
481 #define EEAR7_REG EEARL
484 #define PCINT8_REG PCMSK1
485 #define PCINT9_REG PCMSK1
486 #define PCINT10_REG PCMSK1
487 #define PCINT11_REG PCMSK1
490 #define PINB0_REG PINB
491 #define PINB1_REG PINB
492 #define PINB2_REG PINB
493 #define PINB3_REG PINB
496 #define PINA0_REG PINA
497 #define PINA1_REG PINA
498 #define PINA2_REG PINA
499 #define PINA3_REG PINA
500 #define PINA4_REG PINA
501 #define PINA5_REG PINA
502 #define PINA6_REG PINA
503 #define PINA7_REG PINA
506 #define ADC0D_REG DIDR0
507 #define ADC1D_REG DIDR0
508 #define ADC2D_REG DIDR0
509 #define ADC3D_REG DIDR0
510 #define ADC4D_REG DIDR0
511 #define ADC5D_REG DIDR0
512 #define ADC6D_REG DIDR0
513 #define ADC7D_REG DIDR0
516 #define ISC00_REG MCUCR
517 #define ISC01_REG MCUCR
518 #define SM0_REG MCUCR
519 #define SM1_REG MCUCR
521 #define PUD_REG MCUCR
524 /* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
525 /* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
526 /* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
527 /* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
528 /* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
529 /* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
530 /* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
531 /* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
534 /* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
535 /* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
536 /* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
537 /* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
538 /* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
539 /* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
540 /* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
541 /* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
544 #define USIDR0_REG USIDR
545 #define USIDR1_REG USIDR
546 #define USIDR2_REG USIDR
547 #define USIDR3_REG USIDR
548 #define USIDR4_REG USIDR
549 #define USIDR5_REG USIDR
550 #define USIDR6_REG USIDR
551 #define USIDR7_REG USIDR
554 #define USIBR0_REG USIBR
555 #define USIBR1_REG USIBR
556 #define USIBR2_REG USIBR
557 #define USIBR3_REG USIBR
558 #define USIBR4_REG USIBR
559 #define USIBR5_REG USIBR
560 #define USIBR6_REG USIBR
561 #define USIBR7_REG USIBR
564 #define TOV0_REG TIFR0
565 #define OCF0A_REG TIFR0
566 #define OCF0B_REG TIFR0
569 #define TOV1_REG TIFR1
570 #define OCF1A_REG TIFR1
571 #define OCF1B_REG TIFR1
572 #define ICF1_REG TIFR1
575 #define ADC0_PORT PORTA
577 #define AREF_PORT PORTA
579 #define PCINT0_PORT PORTA
582 #define ADC1_PORT PORTA
584 #define AIN0_PORT PORTA
586 #define PCINT1_PORT PORTA
589 #define ADC2_PORT PORTA
591 #define AIN1_PORT PORTA
593 #define PCINT2_PORT PORTA
596 #define ADC3_PORT PORTA
598 #define T0_PORT PORTA
600 #define PCINT3_PORT PORTA
603 #define ADC4_PORT PORTA
605 #define USCK_PORT PORTA
607 #define SCL_PORT PORTA
609 #define T1_PORT PORTA
611 #define PCINT4_PORT PORTA
614 #define ADC5_PORT PORTA
616 #define DO_PORT PORTA
618 #define MISO_PORT PORTA
620 #define OC1B_PORT PORTA
622 #define PCINT5_PORT PORTA
625 #define PCINT6_PORT PORTA
627 #define OC1A_PORT PORTA
629 #define DI_PORT PORTA
631 #define SDA_PORT PORTA
633 #define MOSI_PORT PORTA
635 #define ADC6_PORT PORTA
638 #define PCINT7_PORT PORTA
640 #define ICP1_PORT PORTA
642 #define OC0B_PORT PORTA
644 #define ADC7_PORT PORTA
647 #define PCINT8_PORT PORTB
649 #define XTAL1_PORT PORTB
652 #define PCINT9_PORT PORTB
654 #define XTAL2_PORT PORTB
657 #define PCINT10_PORT PORTB
658 #define PCINT10_BIT 2
659 #define INT0_PORT PORTB
661 #define OC0A_PORT PORTB
663 #define CKOUT_PORT PORTB
666 #define PCINT11_PORT PORTB
667 #define PCINT11_BIT 3
668 #define RESET_PORT PORTB
670 #define dW_PORT PORTB