1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_common.h>
9 #include <rte_byteorder.h>
13 #define A64_REG_MASK(r) ((r) & 0x1f)
14 #define A64_INVALID_OP_CODE (0xffffffff)
16 #define TMP_REG_1 (EBPF_REG_10 + 1)
17 #define TMP_REG_2 (EBPF_REG_10 + 2)
18 #define TMP_REG_3 (EBPF_REG_10 + 3)
20 #define EBPF_FP (EBPF_REG_10)
21 #define EBPF_OP_GET(op) (BPF_OP(op) >> 4)
29 #define check_imm(n, val) (((val) >= 0) ? !!((val) >> (n)) : !!((~val) >> (n)))
30 #define mask_imm(n, val) ((val) & ((1 << (n)) - 1))
33 uint32_t off; /* eBPF to arm64 insn offset mapping for jump */
34 uint8_t off_to_b; /* Offset to branch instruction delta */
38 size_t stack_sz; /* Stack size */
39 uint32_t *ins; /* ARM64 instructions. NULL if first pass */
40 struct ebpf_a64_map *map; /* eBPF to arm64 insn mapping for jump */
41 uint32_t idx; /* Current instruction index */
42 uint32_t program_start; /* Program index, Just after prologue */
43 uint32_t program_sz; /* Program size. Found in first pass */
44 uint8_t foundcall; /* Found EBPF_CALL class code in eBPF pgm */
48 check_immr_imms(bool is64, uint8_t immr, uint8_t imms)
50 const unsigned int width = is64 ? 64 : 32;
52 if (immr >= width || imms >= width)
59 check_mov_hw(bool is64, const uint8_t val)
61 if (val == 16 || val == 0)
63 else if (is64 && val != 64 && val != 48 && val != 32)
72 return (r > 31) ? 1 : 0;
76 is_first_pass(struct a64_jit_ctx *ctx)
78 return (ctx->ins == NULL);
82 check_invalid_args(struct a64_jit_ctx *ctx, uint32_t limit)
86 if (is_first_pass(ctx))
89 for (idx = 0; idx < limit; idx++) {
90 if (rte_le_to_cpu_32(ctx->ins[idx]) == A64_INVALID_OP_CODE) {
92 "%s: invalid opcode at %u;\n", __func__, idx);
99 /* Emit an instruction */
101 emit_insn(struct a64_jit_ctx *ctx, uint32_t insn, int error)
104 insn = A64_INVALID_OP_CODE;
107 ctx->ins[ctx->idx] = rte_cpu_to_le_32(insn);
113 emit_ret(struct a64_jit_ctx *ctx)
115 emit_insn(ctx, 0xd65f03c0, 0);
119 emit_add_sub_imm(struct a64_jit_ctx *ctx, bool is64, bool sub, uint8_t rd,
120 uint8_t rn, int16_t imm12)
124 imm = mask_imm(12, imm12);
125 insn = (!!is64) << 31;
126 insn |= (!!sub) << 30;
133 check_reg(rd) || check_reg(rn) || check_imm(12, imm12));
137 emit_add_imm_64(struct a64_jit_ctx *ctx, uint8_t rd, uint8_t rn, uint16_t imm12)
139 emit_add_sub_imm(ctx, 1, 0, rd, rn, imm12);
143 emit_sub_imm_64(struct a64_jit_ctx *ctx, uint8_t rd, uint8_t rn, uint16_t imm12)
145 emit_add_sub_imm(ctx, 1, 1, rd, rn, imm12);
149 emit_mov(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rn)
151 emit_add_sub_imm(ctx, is64, 0, rd, rn, 0);
155 emit_mov_64(struct a64_jit_ctx *ctx, uint8_t rd, uint8_t rn)
157 emit_mov(ctx, 1, rd, rn);
161 emit_ls_pair_64(struct a64_jit_ctx *ctx, uint8_t rt, uint8_t rt2, uint8_t rn,
162 bool push, bool load, bool pre_index)
166 insn = (!!load) << 22;
167 insn |= (!!pre_index) << 24;
173 insn |= 0x7e << 15; /* 0x7e means -2 with imm7 */
177 emit_insn(ctx, insn, check_reg(rn) || check_reg(rt) || check_reg(rt2));
181 /* Emit stp rt, rt2, [sp, #-16]! */
183 emit_stack_push(struct a64_jit_ctx *ctx, uint8_t rt, uint8_t rt2)
185 emit_ls_pair_64(ctx, rt, rt2, A64_SP, 1, 0, 1);
188 /* Emit ldp rt, rt2, [sp, #16] */
190 emit_stack_pop(struct a64_jit_ctx *ctx, uint8_t rt, uint8_t rt2)
192 emit_ls_pair_64(ctx, rt, rt2, A64_SP, 0, 1, 0);
199 mov_imm(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t type,
200 uint16_t imm16, uint8_t shift)
204 insn = (!!is64) << 31;
207 insn |= (shift/16) << 21;
211 emit_insn(ctx, insn, check_reg(rd) || check_mov_hw(is64, shift));
215 emit_mov_imm32(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint32_t val)
217 uint16_t upper = val >> 16;
218 uint16_t lower = val & 0xffff;
220 /* Positive number */
221 if ((val & 1UL << 31) == 0) {
222 mov_imm(ctx, is64, rd, A64_MOVZ, lower, 0);
224 mov_imm(ctx, is64, rd, A64_MOVK, upper, 16);
225 } else { /* Negative number */
226 if (upper == 0xffff) {
227 mov_imm(ctx, is64, rd, A64_MOVN, ~lower, 0);
229 mov_imm(ctx, is64, rd, A64_MOVN, ~upper, 16);
231 mov_imm(ctx, is64, rd, A64_MOVK, lower, 0);
237 u16_blocks_weight(const uint64_t val, bool one)
239 return (((val >> 0) & 0xffff) == (one ? 0xffff : 0x0000)) +
240 (((val >> 16) & 0xffff) == (one ? 0xffff : 0x0000)) +
241 (((val >> 32) & 0xffff) == (one ? 0xffff : 0x0000)) +
242 (((val >> 48) & 0xffff) == (one ? 0xffff : 0x0000));
246 emit_mov_imm(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint64_t val)
248 uint64_t nval = ~val;
252 return emit_mov_imm32(ctx, 0, rd, (uint32_t)(val & 0xffffffff));
254 /* Find MOVN or MOVZ first */
255 movn = u16_blocks_weight(val, true) > u16_blocks_weight(val, false);
256 /* Find shift right value */
257 sr = movn ? rte_fls_u64(nval) - 1 : rte_fls_u64(val) - 1;
258 sr = RTE_ALIGN_FLOOR(sr, 16);
262 mov_imm(ctx, 1, rd, A64_MOVN, (nval >> sr) & 0xffff, sr);
264 mov_imm(ctx, 1, rd, A64_MOVZ, (val >> sr) & 0xffff, sr);
268 if (((val >> sr) & 0xffff) != (movn ? 0xffff : 0x0000))
269 mov_imm(ctx, 1, rd, A64_MOVK, (val >> sr) & 0xffff, sr);
275 #define A64_SUB 0x258
277 emit_add_sub(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rn,
278 uint8_t rm, uint16_t op)
282 insn = (!!is64) << 31;
283 insn |= op << 21; /* shift == 0 */
288 emit_insn(ctx, insn, check_reg(rd) || check_reg(rm));
292 emit_add(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
294 emit_add_sub(ctx, is64, rd, rd, rm, A64_ADD);
298 emit_sub(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
300 emit_add_sub(ctx, is64, rd, rd, rm, A64_SUB);
304 emit_neg(struct a64_jit_ctx *ctx, bool is64, uint8_t rd)
306 emit_add_sub(ctx, is64, rd, A64_ZR, rd, A64_SUB);
310 emit_mul(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
314 insn = (!!is64) << 31;
317 insn |= A64_ZR << 10;
321 emit_insn(ctx, insn, check_reg(rd) || check_reg(rm));
329 emit_data_process_two_src(struct a64_jit_ctx *ctx, bool is64, uint8_t rd,
330 uint8_t rn, uint8_t rm, uint16_t op)
335 insn = (!!is64) << 31;
342 emit_insn(ctx, insn, check_reg(rd) || check_reg(rm));
346 emit_div(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
348 emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_UDIV);
352 emit_lslv(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
354 emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_LSLV);
358 emit_lsrv(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
360 emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_LSRV);
364 emit_asrv(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
366 emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_ASRV);
372 emit_bitfield(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rn,
373 uint8_t immr, uint8_t imms, uint16_t op)
378 insn = (!!is64) << 31;
380 insn |= 1 << 22; /* Set N bit when is64 is set */
388 emit_insn(ctx, insn, check_reg(rd) || check_reg(rn) ||
389 check_immr_imms(is64, immr, imms));
392 emit_lsl(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t imm)
394 const unsigned int width = is64 ? 64 : 32;
397 immr = (width - imm) & (width - 1);
398 imms = width - 1 - imm;
400 emit_bitfield(ctx, is64, rd, rd, immr, imms, A64_UBFM);
404 emit_lsr(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t imm)
406 emit_bitfield(ctx, is64, rd, rd, imm, is64 ? 63 : 31, A64_UBFM);
410 emit_asr(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t imm)
412 emit_bitfield(ctx, is64, rd, rd, imm, is64 ? 63 : 31, A64_SBFM);
419 emit_logical(struct a64_jit_ctx *ctx, bool is64, uint8_t rd,
420 uint8_t rm, uint16_t op)
424 insn = (!!is64) << 31;
431 emit_insn(ctx, insn, check_reg(rd) || check_reg(rm));
435 emit_or(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
437 emit_logical(ctx, is64, rd, rm, A64_OR);
441 emit_and(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
443 emit_logical(ctx, is64, rd, rm, A64_AND);
447 emit_xor(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm)
449 emit_logical(ctx, is64, rd, rm, A64_XOR);
453 emit_msub(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rn,
454 uint8_t rm, uint8_t ra)
458 insn = (!!is64) << 31;
466 emit_insn(ctx, insn, check_reg(rd) || check_reg(rn) || check_reg(rm) ||
471 emit_mod(struct a64_jit_ctx *ctx, bool is64, uint8_t tmp, uint8_t rd,
474 emit_data_process_two_src(ctx, is64, tmp, rd, rm, A64_UDIV);
475 emit_msub(ctx, is64, rd, tmp, rm, rd);
479 emit_zero_extend(struct a64_jit_ctx *ctx, uint8_t rd, int32_t imm)
483 /* Zero-extend 16 bits into 64 bits */
484 emit_bitfield(ctx, 1, rd, rd, 0, 15, A64_UBFM);
487 /* Zero-extend 32 bits into 64 bits */
488 emit_bitfield(ctx, 1, rd, rd, 0, 31, A64_UBFM);
494 emit_insn(ctx, 0, 1);
499 emit_rev(struct a64_jit_ctx *ctx, uint8_t rd, int32_t imm)
510 emit_insn(ctx, insn, check_reg(rd));
511 emit_zero_extend(ctx, rd, 16);
515 emit_insn(ctx, insn, check_reg(rd));
516 /* Upper 32 bits already cleared */
520 emit_insn(ctx, insn, check_reg(rd));
524 emit_insn(ctx, insn, 1);
531 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
539 emit_be(struct a64_jit_ctx *ctx, uint8_t rd, int32_t imm)
542 emit_zero_extend(ctx, rd, imm);
544 emit_rev(ctx, rd, imm);
548 emit_le(struct a64_jit_ctx *ctx, uint8_t rd, int32_t imm)
551 emit_rev(ctx, rd, imm);
553 emit_zero_extend(ctx, rd, imm);
557 ebpf_to_a64_reg(struct a64_jit_ctx *ctx, uint8_t reg)
559 const uint32_t ebpf2a64_has_call[] = {
560 /* Map A64 R7 register as EBPF return register */
561 [EBPF_REG_0] = A64_R(7),
562 /* Map A64 arguments register as EBPF arguments register */
563 [EBPF_REG_1] = A64_R(0),
564 [EBPF_REG_2] = A64_R(1),
565 [EBPF_REG_3] = A64_R(2),
566 [EBPF_REG_4] = A64_R(3),
567 [EBPF_REG_5] = A64_R(4),
568 /* Map A64 callee save register as EBPF callee save register */
569 [EBPF_REG_6] = A64_R(19),
570 [EBPF_REG_7] = A64_R(20),
571 [EBPF_REG_8] = A64_R(21),
572 [EBPF_REG_9] = A64_R(22),
573 [EBPF_FP] = A64_R(25),
574 /* Map A64 scratch registers as temporary storage */
575 [TMP_REG_1] = A64_R(9),
576 [TMP_REG_2] = A64_R(10),
577 [TMP_REG_3] = A64_R(11),
580 const uint32_t ebpf2a64_no_call[] = {
581 /* Map A64 R7 register as EBPF return register */
582 [EBPF_REG_0] = A64_R(7),
583 /* Map A64 arguments register as EBPF arguments register */
584 [EBPF_REG_1] = A64_R(0),
585 [EBPF_REG_2] = A64_R(1),
586 [EBPF_REG_3] = A64_R(2),
587 [EBPF_REG_4] = A64_R(3),
588 [EBPF_REG_5] = A64_R(4),
590 * EBPF program does not have EBPF_CALL op code,
591 * Map A64 scratch registers as EBPF callee save registers.
593 [EBPF_REG_6] = A64_R(9),
594 [EBPF_REG_7] = A64_R(10),
595 [EBPF_REG_8] = A64_R(11),
596 [EBPF_REG_9] = A64_R(12),
597 /* Map A64 FP register as EBPF FP register */
599 /* Map remaining A64 scratch registers as temporary storage */
600 [TMP_REG_1] = A64_R(13),
601 [TMP_REG_2] = A64_R(14),
602 [TMP_REG_3] = A64_R(15),
606 return ebpf2a64_has_call[reg];
608 return ebpf2a64_no_call[reg];
612 * Procedure call standard for the arm64
613 * -------------------------------------
614 * R0..R7 - Parameter/result registers
615 * R8 - Indirect result location register
616 * R9..R15 - Scratch registers
617 * R15 - Platform Register
618 * R16 - First intra-procedure-call scratch register
619 * R17 - Second intra-procedure-call temporary register
620 * R19-R28 - Callee saved registers
621 * R29 - Frame pointer
622 * R30 - Link register
623 * R31 - Stack pointer
626 emit_prologue_has_call(struct a64_jit_ctx *ctx)
628 uint8_t r6, r7, r8, r9, fp;
630 r6 = ebpf_to_a64_reg(ctx, EBPF_REG_6);
631 r7 = ebpf_to_a64_reg(ctx, EBPF_REG_7);
632 r8 = ebpf_to_a64_reg(ctx, EBPF_REG_8);
633 r9 = ebpf_to_a64_reg(ctx, EBPF_REG_9);
634 fp = ebpf_to_a64_reg(ctx, EBPF_FP);
637 * eBPF prog stack layout
640 * eBPF prologue 0:+-----+ <= original A64_SP
642 * -16:+-----+ <= current A64_FP
643 * Callee saved registers | ... |
644 * EBPF_FP => -64:+-----+
646 * eBPF prog stack | ... |
648 * (EBPF_FP - bpf->stack_sz)=> +-----+
649 * Pad for A64_SP 16B alignment| PAD |
650 * (EBPF_FP - ctx->stack_sz)=> +-----+ <= current A64_SP
652 * | ... | Function call stack
657 emit_stack_push(ctx, A64_FP, A64_LR);
658 emit_mov_64(ctx, A64_FP, A64_SP);
659 emit_stack_push(ctx, r6, r7);
660 emit_stack_push(ctx, r8, r9);
662 * There is no requirement to save A64_R(28) in stack. Doing it here,
663 * because, A64_SP needs be to 16B aligned and STR vs STP
664 * takes same number of cycles(typically).
666 emit_stack_push(ctx, fp, A64_R(28));
667 emit_mov_64(ctx, fp, A64_SP);
669 emit_sub_imm_64(ctx, A64_SP, A64_SP, ctx->stack_sz);
673 emit_epilogue_has_call(struct a64_jit_ctx *ctx)
675 uint8_t r6, r7, r8, r9, fp, r0;
677 r6 = ebpf_to_a64_reg(ctx, EBPF_REG_6);
678 r7 = ebpf_to_a64_reg(ctx, EBPF_REG_7);
679 r8 = ebpf_to_a64_reg(ctx, EBPF_REG_8);
680 r9 = ebpf_to_a64_reg(ctx, EBPF_REG_9);
681 fp = ebpf_to_a64_reg(ctx, EBPF_FP);
682 r0 = ebpf_to_a64_reg(ctx, EBPF_REG_0);
685 emit_add_imm_64(ctx, A64_SP, A64_SP, ctx->stack_sz);
686 emit_stack_pop(ctx, fp, A64_R(28));
687 emit_stack_pop(ctx, r8, r9);
688 emit_stack_pop(ctx, r6, r7);
689 emit_stack_pop(ctx, A64_FP, A64_LR);
690 emit_mov_64(ctx, A64_R(0), r0);
695 emit_prologue_no_call(struct a64_jit_ctx *ctx)
698 * eBPF prog stack layout without EBPF_CALL opcode
701 * eBPF prologue(EBPF_FP) 0:+-----+ <= original A64_SP/current A64_FP
704 * eBPF prog stack | |
706 * (EBPF_FP - bpf->stack_sz)=> +-----+
707 * Pad for A64_SP 16B alignment| PAD |
708 * (EBPF_FP - ctx->stack_sz)=> +-----+ <= current A64_SP
710 * | ... | Function call stack
716 emit_mov_64(ctx, A64_FP, A64_SP);
717 emit_sub_imm_64(ctx, A64_SP, A64_SP, ctx->stack_sz);
722 emit_epilogue_no_call(struct a64_jit_ctx *ctx)
725 emit_add_imm_64(ctx, A64_SP, A64_SP, ctx->stack_sz);
726 emit_mov_64(ctx, A64_R(0), ebpf_to_a64_reg(ctx, EBPF_REG_0));
731 emit_prologue(struct a64_jit_ctx *ctx)
734 emit_prologue_has_call(ctx);
736 emit_prologue_no_call(ctx);
738 ctx->program_start = ctx->idx;
742 emit_epilogue(struct a64_jit_ctx *ctx)
744 ctx->program_sz = ctx->idx - ctx->program_start;
747 emit_epilogue_has_call(ctx);
749 emit_epilogue_no_call(ctx);
753 emit_cbnz(struct a64_jit_ctx *ctx, bool is64, uint8_t rt, int32_t imm19)
757 imm = mask_imm(19, imm19);
758 insn = (!!is64) << 31;
763 emit_insn(ctx, insn, check_reg(rt) || check_imm(19, imm19));
767 emit_b(struct a64_jit_ctx *ctx, int32_t imm26)
771 imm = mask_imm(26, imm26);
775 emit_insn(ctx, insn, check_imm(26, imm26));
779 emit_return_zero_if_src_zero(struct a64_jit_ctx *ctx, bool is64, uint8_t src)
781 uint8_t r0 = ebpf_to_a64_reg(ctx, EBPF_REG_0);
782 uint16_t jump_to_epilogue;
784 emit_cbnz(ctx, is64, src, 3);
785 emit_mov_imm(ctx, is64, r0, 0);
786 jump_to_epilogue = (ctx->program_start + ctx->program_sz) - ctx->idx;
787 emit_b(ctx, jump_to_epilogue);
791 check_program_has_call(struct a64_jit_ctx *ctx, struct rte_bpf *bpf)
793 const struct ebpf_insn *ins;
797 for (i = 0; i != bpf->prm.nb_ins; i++) {
798 ins = bpf->prm.ins + i;
803 case (BPF_JMP | EBPF_CALL):
811 * Walk through eBPF code and translate them to arm64 one.
814 emit(struct a64_jit_ctx *ctx, struct rte_bpf *bpf)
816 uint8_t op, dst, src, tmp1, tmp2;
817 const struct ebpf_insn *ins;
823 /* Reset context fields */
825 /* arm64 SP must be aligned to 16 */
826 ctx->stack_sz = RTE_ALIGN_MUL_CEIL(bpf->stack_sz, 16);
827 tmp1 = ebpf_to_a64_reg(ctx, TMP_REG_1);
828 tmp2 = ebpf_to_a64_reg(ctx, TMP_REG_2);
832 for (i = 0; i != bpf->prm.nb_ins; i++) {
834 ins = bpf->prm.ins + i;
838 dst = ebpf_to_a64_reg(ctx, ins->dst_reg);
839 src = ebpf_to_a64_reg(ctx, ins->src_reg);
840 is64 = (BPF_CLASS(op) == EBPF_ALU64);
844 case (BPF_ALU | EBPF_MOV | BPF_X):
845 case (EBPF_ALU64 | EBPF_MOV | BPF_X):
846 emit_mov(ctx, is64, dst, src);
849 case (BPF_ALU | EBPF_MOV | BPF_K):
850 case (EBPF_ALU64 | EBPF_MOV | BPF_K):
851 emit_mov_imm(ctx, is64, dst, imm);
854 case (BPF_ALU | BPF_ADD | BPF_X):
855 case (EBPF_ALU64 | BPF_ADD | BPF_X):
856 emit_add(ctx, is64, dst, src);
859 case (BPF_ALU | BPF_ADD | BPF_K):
860 case (EBPF_ALU64 | BPF_ADD | BPF_K):
861 emit_mov_imm(ctx, is64, tmp1, imm);
862 emit_add(ctx, is64, dst, tmp1);
865 case (BPF_ALU | BPF_SUB | BPF_X):
866 case (EBPF_ALU64 | BPF_SUB | BPF_X):
867 emit_sub(ctx, is64, dst, src);
870 case (BPF_ALU | BPF_SUB | BPF_K):
871 case (EBPF_ALU64 | BPF_SUB | BPF_K):
872 emit_mov_imm(ctx, is64, tmp1, imm);
873 emit_sub(ctx, is64, dst, tmp1);
876 case (BPF_ALU | BPF_MUL | BPF_X):
877 case (EBPF_ALU64 | BPF_MUL | BPF_X):
878 emit_mul(ctx, is64, dst, src);
881 case (BPF_ALU | BPF_MUL | BPF_K):
882 case (EBPF_ALU64 | BPF_MUL | BPF_K):
883 emit_mov_imm(ctx, is64, tmp1, imm);
884 emit_mul(ctx, is64, dst, tmp1);
887 case (BPF_ALU | BPF_DIV | BPF_X):
888 case (EBPF_ALU64 | BPF_DIV | BPF_X):
889 emit_return_zero_if_src_zero(ctx, is64, src);
890 emit_div(ctx, is64, dst, src);
893 case (BPF_ALU | BPF_DIV | BPF_K):
894 case (EBPF_ALU64 | BPF_DIV | BPF_K):
895 emit_mov_imm(ctx, is64, tmp1, imm);
896 emit_div(ctx, is64, dst, tmp1);
899 case (BPF_ALU | BPF_MOD | BPF_X):
900 case (EBPF_ALU64 | BPF_MOD | BPF_X):
901 emit_return_zero_if_src_zero(ctx, is64, src);
902 emit_mod(ctx, is64, tmp1, dst, src);
905 case (BPF_ALU | BPF_MOD | BPF_K):
906 case (EBPF_ALU64 | BPF_MOD | BPF_K):
907 emit_mov_imm(ctx, is64, tmp1, imm);
908 emit_mod(ctx, is64, tmp2, dst, tmp1);
911 case (BPF_ALU | BPF_OR | BPF_X):
912 case (EBPF_ALU64 | BPF_OR | BPF_X):
913 emit_or(ctx, is64, dst, src);
916 case (BPF_ALU | BPF_OR | BPF_K):
917 case (EBPF_ALU64 | BPF_OR | BPF_K):
918 emit_mov_imm(ctx, is64, tmp1, imm);
919 emit_or(ctx, is64, dst, tmp1);
922 case (BPF_ALU | BPF_AND | BPF_X):
923 case (EBPF_ALU64 | BPF_AND | BPF_X):
924 emit_and(ctx, is64, dst, src);
927 case (BPF_ALU | BPF_AND | BPF_K):
928 case (EBPF_ALU64 | BPF_AND | BPF_K):
929 emit_mov_imm(ctx, is64, tmp1, imm);
930 emit_and(ctx, is64, dst, tmp1);
933 case (BPF_ALU | BPF_XOR | BPF_X):
934 case (EBPF_ALU64 | BPF_XOR | BPF_X):
935 emit_xor(ctx, is64, dst, src);
938 case (BPF_ALU | BPF_XOR | BPF_K):
939 case (EBPF_ALU64 | BPF_XOR | BPF_K):
940 emit_mov_imm(ctx, is64, tmp1, imm);
941 emit_xor(ctx, is64, dst, tmp1);
944 case (BPF_ALU | BPF_NEG):
945 case (EBPF_ALU64 | BPF_NEG):
946 emit_neg(ctx, is64, dst);
949 case BPF_ALU | BPF_LSH | BPF_X:
950 case EBPF_ALU64 | BPF_LSH | BPF_X:
951 emit_lslv(ctx, is64, dst, src);
954 case BPF_ALU | BPF_LSH | BPF_K:
955 case EBPF_ALU64 | BPF_LSH | BPF_K:
956 emit_lsl(ctx, is64, dst, imm);
959 case BPF_ALU | BPF_RSH | BPF_X:
960 case EBPF_ALU64 | BPF_RSH | BPF_X:
961 emit_lsrv(ctx, is64, dst, src);
964 case BPF_ALU | BPF_RSH | BPF_K:
965 case EBPF_ALU64 | BPF_RSH | BPF_K:
966 emit_lsr(ctx, is64, dst, imm);
968 /* dst >>= src (arithmetic) */
969 case BPF_ALU | EBPF_ARSH | BPF_X:
970 case EBPF_ALU64 | EBPF_ARSH | BPF_X:
971 emit_asrv(ctx, is64, dst, src);
973 /* dst >>= imm (arithmetic) */
974 case BPF_ALU | EBPF_ARSH | BPF_K:
975 case EBPF_ALU64 | EBPF_ARSH | BPF_K:
976 emit_asr(ctx, is64, dst, imm);
978 /* dst = be##imm(dst) */
979 case (BPF_ALU | EBPF_END | EBPF_TO_BE):
980 emit_be(ctx, dst, imm);
982 /* dst = le##imm(dst) */
983 case (BPF_ALU | EBPF_END | EBPF_TO_LE):
984 emit_le(ctx, dst, imm);
987 case (BPF_JMP | EBPF_EXIT):
992 "%s(%p): invalid opcode %#x at pc: %u;\n",
993 __func__, bpf, ins->code, i);
997 rc = check_invalid_args(ctx, ctx->idx);
1003 * Produce a native ISA version of the given BPF code.
1006 bpf_jit_arm64(struct rte_bpf *bpf)
1008 struct a64_jit_ctx ctx;
1012 /* Init JIT context */
1013 memset(&ctx, 0, sizeof(ctx));
1015 /* Find eBPF program has call class or not */
1016 check_program_has_call(&ctx, bpf);
1018 /* First pass to calculate total code size and valid jump offsets */
1019 rc = emit(&ctx, bpf);
1023 size = ctx.idx * sizeof(uint32_t);
1024 /* Allocate JIT program memory */
1025 ctx.ins = mmap(NULL, size, PROT_READ | PROT_WRITE,
1026 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
1027 if (ctx.ins == MAP_FAILED) {
1032 /* Second pass to generate code */
1033 rc = emit(&ctx, bpf);
1037 rc = mprotect(ctx.ins, size, PROT_READ | PROT_EXEC) != 0;
1043 /* Flush the icache */
1044 __builtin___clear_cache(ctx.ins, ctx.ins + ctx.idx);
1046 bpf->jit.func = (void *)ctx.ins;
1052 munmap(ctx.ins, size);