lib/librte_eal/arm/include/rte_atomic_64.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015 Cavium, Inc
   3  * Copyright(c) 2020 Arm Limited
   4  */
   5
   6 #ifndef _RTE_ATOMIC_ARM64_H_
   7 #define _RTE_ATOMIC_ARM64_H_
   8
   9 #ifndef RTE_FORCE_INTRINSICS
  10 #  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
  11 #endif
  12
  13 #ifdef __cplusplus
  14 extern "C" {
  15 #endif
  16
  17 #include "generic/rte_atomic.h"
  18 #include <rte_branch_prediction.h>
  19 #include <rte_compat.h>
  20 #include <rte_debug.h>
  21
  22 #define rte_mb() asm volatile("dmb osh" : : : "memory")
  23
  24 #define rte_wmb() asm volatile("dmb oshst" : : : "memory")
  25
  26 #define rte_rmb() asm volatile("dmb oshld" : : : "memory")
  27
  28 #define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
  29
  30 #define rte_smp_wmb() asm volatile("dmb ishst" : : : "memory")
  31
  32 #define rte_smp_rmb() asm volatile("dmb ishld" : : : "memory")
  33
  34 #define rte_io_mb() rte_mb()
  35
  36 #define rte_io_wmb() rte_wmb()
  37
  38 #define rte_io_rmb() rte_rmb()
  39
  40 static __rte_always_inline void
  41 rte_atomic_thread_fence(int memorder)
  42 {
  43         __atomic_thread_fence(memorder);
  44 }
  45
  46 /*------------------------ 128 bit atomic operations -------------------------*/
  47
  48 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
  49 #define __ATOMIC128_CAS_OP(cas_op_name, op_string)                          \
  50 static __rte_noinline rte_int128_t                                          \
  51 cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)      \
  52 {                                                                           \
  53         /* caspX instructions register pair must start from even-numbered
  54          * register at operand 1.
  55          * So, specify registers for local variables here.
  56          */                                                                 \
  57         register uint64_t x0 __asm("x0") = (uint64_t)old.val[0];            \
  58         register uint64_t x1 __asm("x1") = (uint64_t)old.val[1];            \
  59         register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0];        \
  60         register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1];        \
  61         asm volatile(                                                       \
  62                 op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]"   \
  63                 : [old0] "+r" (x0),                                         \
  64                 [old1] "+r" (x1)                                            \
  65                 : [upd0] "r" (x2),                                          \
  66                 [upd1] "r" (x3),                                            \
  67                 [dst] "r" (dst)                                             \
  68                 : "memory");                                                \
  69         old.val[0] = x0;                                                    \
  70         old.val[1] = x1;                                                    \
  71         return old;                                                         \
  72 }
  73
  74 __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp")
  75 __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
  76 __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
  77 __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
  78
  79 #undef __ATOMIC128_CAS_OP
  80
  81 #endif
  82
  83 __rte_experimental
  84 static inline int
  85 rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
  86                 const rte_int128_t *src, unsigned int weak, int success,
  87                 int failure)
  88 {
  89         /* Always do strong CAS */
  90         RTE_SET_USED(weak);
  91         /* Ignore memory ordering for failure, memory order for
  92          * success must be stronger or equal
  93          */
  94         RTE_SET_USED(failure);
  95         /* Find invalid memory order */
  96         RTE_ASSERT(success == __ATOMIC_RELAXED ||
  97                 success == __ATOMIC_ACQUIRE ||
  98                 success == __ATOMIC_RELEASE ||
  99                 success == __ATOMIC_ACQ_REL ||
 100                 success == __ATOMIC_SEQ_CST);
 101
 102         rte_int128_t expected = *exp;
 103         rte_int128_t desired = *src;
 104         rte_int128_t old;
 105
 106 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
 107         if (success == __ATOMIC_RELAXED)
 108                 old = __cas_128_relaxed(dst, expected, desired);
 109         else if (success == __ATOMIC_ACQUIRE)
 110                 old = __cas_128_acquire(dst, expected, desired);
 111         else if (success == __ATOMIC_RELEASE)
 112                 old = __cas_128_release(dst, expected, desired);
 113         else
 114                 old = __cas_128_acq_rel(dst, expected, desired);
 115 #else
 116 #define __HAS_ACQ(mo) ((mo) != __ATOMIC_RELAXED && (mo) != __ATOMIC_RELEASE)
 117 #define __HAS_RLS(mo) ((mo) == __ATOMIC_RELEASE || (mo) == __ATOMIC_ACQ_REL || \
 118                 (mo) == __ATOMIC_SEQ_CST)
 119
 120         int ldx_mo = __HAS_ACQ(success) ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED;
 121         int stx_mo = __HAS_RLS(success) ? __ATOMIC_RELEASE : __ATOMIC_RELAXED;
 122
 123 #undef __HAS_ACQ
 124 #undef __HAS_RLS
 125
 126         uint32_t ret = 1;
 127
 128         /* ldx128 can not guarantee atomic,
 129          * Must write back src or old to verify atomicity of ldx128;
 130          */
 131         do {
 132
 133 #define __LOAD_128(op_string, src, dst) { \
 134         asm volatile(                     \
 135                 op_string " %0, %1, %2"   \
 136                 : "=&r" (dst.val[0]),     \
 137                   "=&r" (dst.val[1])      \
 138                 : "Q" (src->val[0])       \
 139                 : "memory"); }
 140
 141                 if (ldx_mo == __ATOMIC_RELAXED)
 142                         __LOAD_128("ldxp", dst, old)
 143                 else
 144                         __LOAD_128("ldaxp", dst, old)
 145
 146 #undef __LOAD_128
 147
 148 #define __STORE_128(op_string, dst, src, ret) { \
 149         asm volatile(                           \
 150                 op_string " %w0, %1, %2, %3"    \
 151                 : "=&r" (ret)                   \
 152                 : "r" (src.val[0]),             \
 153                   "r" (src.val[1]),             \
 154                   "Q" (dst->val[0])             \
 155                 : "memory"); }
 156
 157                 if (likely(old.int128 == expected.int128)) {
 158                         if (stx_mo == __ATOMIC_RELAXED)
 159                                 __STORE_128("stxp", dst, desired, ret)
 160                         else
 161                                 __STORE_128("stlxp", dst, desired, ret)
 162                 } else {
 163                         /* In the failure case (since 'weak' is ignored and only
 164                          * weak == 0 is implemented), expected should contain
 165                          * the atomically read value of dst. This means, 'old'
 166                          * needs to be stored back to ensure it was read
 167                          * atomically.
 168                          */
 169                         if (stx_mo == __ATOMIC_RELAXED)
 170                                 __STORE_128("stxp", dst, old, ret)
 171                         else
 172                                 __STORE_128("stlxp", dst, old, ret)
 173                 }
 174
 175 #undef __STORE_128
 176
 177         } while (unlikely(ret));
 178 #endif
 179
 180         /* Unconditionally updating expected removes an 'if' statement.
 181          * expected should already be in register if not in the cache.
 182          */
 183         *exp = old;
 184
 185         return (old.int128 == expected.int128);
 186 }
 187
 188 #ifdef __cplusplus
 189 }
 190 #endif
 191
 192 #endif /* _RTE_ATOMIC_ARM64_H_ */