1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
10 * I/O device memory operations
12 * This file defines the generic API for I/O device memory read/write operations
16 #include <rte_common.h>
17 #include <rte_atomic.h>
22 * Read a 8-bit value from I/O device memory address *addr*.
24 * The relaxed version does not have additional I/O memory barrier, useful in
25 * accessing the device registers of integrated controllers which implicitly
26 * strongly ordered with respect to memory access.
29 * I/O memory address to read the value from
34 rte_read8_relaxed(const volatile void *addr);
37 * Read a 16-bit value from I/O device memory address *addr*.
39 * The relaxed version does not have additional I/O memory barrier, useful in
40 * accessing the device registers of integrated controllers which implicitly
41 * strongly ordered with respect to memory access.
44 * I/O memory address to read the value from
48 static inline uint16_t
49 rte_read16_relaxed(const volatile void *addr);
52 * Read a 32-bit value from I/O device memory address *addr*.
54 * The relaxed version does not have additional I/O memory barrier, useful in
55 * accessing the device registers of integrated controllers which implicitly
56 * strongly ordered with respect to memory access.
59 * I/O memory address to read the value from
63 static inline uint32_t
64 rte_read32_relaxed(const volatile void *addr);
67 * Read a 64-bit value from I/O device memory address *addr*.
69 * The relaxed version does not have additional I/O memory barrier, useful in
70 * accessing the device registers of integrated controllers which implicitly
71 * strongly ordered with respect to memory access.
74 * I/O memory address to read the value from
78 static inline uint64_t
79 rte_read64_relaxed(const volatile void *addr);
82 * Write a 8-bit value to I/O device memory address *addr*.
84 * The relaxed version does not have additional I/O memory barrier, useful in
85 * accessing the device registers of integrated controllers which implicitly
86 * strongly ordered with respect to memory access.
91 * I/O memory address to write the value to
95 rte_write8_relaxed(uint8_t value, volatile void *addr);
98 * Write a 16-bit value to I/O device memory address *addr*.
100 * The relaxed version does not have additional I/O memory barrier, useful in
101 * accessing the device registers of integrated controllers which implicitly
102 * strongly ordered with respect to memory access.
107 * I/O memory address to write the value to
110 rte_write16_relaxed(uint16_t value, volatile void *addr);
113 * Write a 32-bit value to I/O device memory address *addr*.
115 * The relaxed version does not have additional I/O memory barrier, useful in
116 * accessing the device registers of integrated controllers which implicitly
117 * strongly ordered with respect to memory access.
122 * I/O memory address to write the value to
125 rte_write32_relaxed(uint32_t value, volatile void *addr);
128 * Write a 64-bit value to I/O device memory address *addr*.
130 * The relaxed version does not have additional I/O memory barrier, useful in
131 * accessing the device registers of integrated controllers which implicitly
132 * strongly ordered with respect to memory access.
137 * I/O memory address to write the value to
140 rte_write64_relaxed(uint64_t value, volatile void *addr);
143 * Read a 8-bit value from I/O device memory address *addr*.
146 * I/O memory address to read the value from
150 static inline uint8_t
151 rte_read8(const volatile void *addr);
154 * Read a 16-bit value from I/O device memory address *addr*.
158 * I/O memory address to read the value from
162 static inline uint16_t
163 rte_read16(const volatile void *addr);
166 * Read a 32-bit value from I/O device memory address *addr*.
169 * I/O memory address to read the value from
173 static inline uint32_t
174 rte_read32(const volatile void *addr);
177 * Read a 64-bit value from I/O device memory address *addr*.
180 * I/O memory address to read the value from
184 static inline uint64_t
185 rte_read64(const volatile void *addr);
188 * Write a 8-bit value to I/O device memory address *addr*.
193 * I/O memory address to write the value to
197 rte_write8(uint8_t value, volatile void *addr);
200 * Write a 16-bit value to I/O device memory address *addr*.
205 * I/O memory address to write the value to
208 rte_write16(uint16_t value, volatile void *addr);
211 * Write a 32-bit value to I/O device memory address *addr*.
216 * I/O memory address to write the value to
219 rte_write32(uint32_t value, volatile void *addr);
222 * Write a 64-bit value to I/O device memory address *addr*.
227 * I/O memory address to write the value to
230 rte_write64(uint64_t value, volatile void *addr);
233 * Write a 32-bit value to I/O device memory address addr using write
234 * combining memory write protocol. Depending on the platform write combining
235 * may not be available and/or may be treated as a hint and the behavior may
236 * fallback to a regular store.
241 * I/O memory address to write the value to
245 rte_write32_wc(uint32_t value, volatile void *addr);
248 * Write a 32-bit value to I/O device memory address addr using write
249 * combining memory write protocol. Depending on the platform write combining
250 * may not be available and/or may be treated as a hint and the behavior may
251 * fallback to a regular store.
253 * The relaxed version does not have additional I/O memory barrier, useful in
254 * accessing the device registers of integrated controllers which implicitly
255 * strongly ordered with respect to memory access.
260 * I/O memory address to write the value to
264 rte_write32_wc_relaxed(uint32_t value, volatile void *addr);
266 #endif /* __DOXYGEN__ */
268 #ifndef RTE_OVERRIDE_IO_H
270 static __rte_always_inline uint8_t
271 rte_read8_relaxed(const volatile void *addr)
273 return *(const volatile uint8_t *)addr;
276 static __rte_always_inline uint16_t
277 rte_read16_relaxed(const volatile void *addr)
279 return *(const volatile uint16_t *)addr;
282 static __rte_always_inline uint32_t
283 rte_read32_relaxed(const volatile void *addr)
285 return *(const volatile uint32_t *)addr;
288 static __rte_always_inline uint64_t
289 rte_read64_relaxed(const volatile void *addr)
291 return *(const volatile uint64_t *)addr;
294 static __rte_always_inline void
295 rte_write8_relaxed(uint8_t value, volatile void *addr)
297 *(volatile uint8_t *)addr = value;
300 static __rte_always_inline void
301 rte_write16_relaxed(uint16_t value, volatile void *addr)
303 *(volatile uint16_t *)addr = value;
306 static __rte_always_inline void
307 rte_write32_relaxed(uint32_t value, volatile void *addr)
309 *(volatile uint32_t *)addr = value;
312 static __rte_always_inline void
313 rte_write64_relaxed(uint64_t value, volatile void *addr)
315 *(volatile uint64_t *)addr = value;
318 static __rte_always_inline uint8_t
319 rte_read8(const volatile void *addr)
322 val = rte_read8_relaxed(addr);
327 static __rte_always_inline uint16_t
328 rte_read16(const volatile void *addr)
331 val = rte_read16_relaxed(addr);
336 static __rte_always_inline uint32_t
337 rte_read32(const volatile void *addr)
340 val = rte_read32_relaxed(addr);
345 static __rte_always_inline uint64_t
346 rte_read64(const volatile void *addr)
349 val = rte_read64_relaxed(addr);
354 static __rte_always_inline void
355 rte_write8(uint8_t value, volatile void *addr)
358 rte_write8_relaxed(value, addr);
361 static __rte_always_inline void
362 rte_write16(uint16_t value, volatile void *addr)
365 rte_write16_relaxed(value, addr);
368 static __rte_always_inline void
369 rte_write32(uint32_t value, volatile void *addr)
372 rte_write32_relaxed(value, addr);
375 static __rte_always_inline void
376 rte_write64(uint64_t value, volatile void *addr)
379 rte_write64_relaxed(value, addr);
382 #ifndef RTE_NATIVE_WRITE32_WC
383 static __rte_always_inline void
384 rte_write32_wc(uint32_t value, volatile void *addr)
386 rte_write32(value, addr);
389 static __rte_always_inline void
390 rte_write32_wc_relaxed(uint32_t value, volatile void *addr)
392 rte_write32_relaxed(value, addr);
394 #endif /* RTE_NATIVE_WRITE32_WC */
396 #endif /* RTE_OVERRIDE_IO_H */
398 #endif /* _RTE_IO_H_ */