4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
35 #ifdef CONFIG_XEN_DOM0
38 #include <rte_pci_dev_features.h>
41 #define PCI_SYS_FILE_BUF_SIZE 10
42 #define PCI_DEV_CAP_REG 0xA4
43 #define PCI_DEV_CTRL_REG 0xA8
44 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
45 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
46 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
50 * A structure describing the private information for a uio device.
52 struct rte_uio_pci_dev {
55 enum rte_intr_mode mode;
58 static char *intr_mode = NULL;
59 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
61 static inline struct rte_uio_pci_dev *
62 igbuio_get_uio_pci_dev(struct uio_info *info)
64 return container_of(info, struct rte_uio_pci_dev, info);
68 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34)
69 static int pci_num_vf(struct pci_dev *dev)
78 } *iov = (struct iov *)dev->sriov;
83 return iov->nr_virtfn;
88 show_max_vfs(struct device *dev, struct device_attribute *attr,
91 return snprintf(buf, 10, "%u\n",
92 pci_num_vf(container_of(dev, struct pci_dev, dev)));
96 store_max_vfs(struct device *dev, struct device_attribute *attr,
97 const char *buf, size_t count)
100 unsigned long max_vfs;
101 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
103 if (0 != strict_strtoul(buf, 0, &max_vfs))
107 pci_disable_sriov(pdev);
108 else if (0 == pci_num_vf(pdev))
109 err = pci_enable_sriov(pdev, max_vfs);
110 else /* do nothing if change max_vfs number */
113 return err ? err : count;
116 #ifdef RTE_PCI_CONFIG
118 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
120 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
123 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
124 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
125 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
128 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
129 PCI_DEV_CTRL_REG, &val);
131 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
132 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
136 store_extended_tag(struct device *dev,
137 struct device_attribute *attr,
141 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
142 uint32_t val = 0, enable;
144 if (strncmp(buf, "on", 2) == 0)
146 else if (strncmp(buf, "off", 3) == 0)
151 pci_cfg_access_lock(pci_dev);
152 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
153 PCI_DEV_CAP_REG, &val);
154 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
155 pci_cfg_access_unlock(pci_dev);
160 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
161 PCI_DEV_CTRL_REG, &val);
163 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
165 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
166 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
167 PCI_DEV_CTRL_REG, val);
168 pci_cfg_access_unlock(pci_dev);
174 show_max_read_request_size(struct device *dev,
175 struct device_attribute *attr,
178 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
179 int val = pcie_get_readrq(pci_dev);
181 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
185 store_max_read_request_size(struct device *dev,
186 struct device_attribute *attr,
190 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
191 unsigned long size = 0;
194 if (strict_strtoul(buf, 0, &size) != 0)
197 ret = pcie_set_readrq(pci_dev, (int)size);
205 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
206 #ifdef RTE_PCI_CONFIG
207 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
209 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
210 show_max_read_request_size, store_max_read_request_size);
213 static struct attribute *dev_attrs[] = {
214 &dev_attr_max_vfs.attr,
215 #ifdef RTE_PCI_CONFIG
216 &dev_attr_extended_tag.attr,
217 &dev_attr_max_read_request_size.attr,
222 static const struct attribute_group dev_attr_grp = {
226 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
227 /* Check if INTX works to control irq's.
228 * Set's INTX_DISABLE flag and reads it back
230 static bool pci_intx_mask_supported(struct pci_dev *pdev)
232 bool mask_supported = false;
235 pci_block_user_cfg_access(pdev);
236 pci_read_config_word(pdev, PCI_COMMAND, &orig);
237 pci_write_config_word(pdev, PCI_COMMAND,
238 orig ^ PCI_COMMAND_INTX_DISABLE);
239 pci_read_config_word(pdev, PCI_COMMAND, &new);
241 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
242 dev_err(&pdev->dev, "Command register changed from "
243 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
244 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
245 mask_supported = true;
246 pci_write_config_word(pdev, PCI_COMMAND, orig);
248 pci_unblock_user_cfg_access(pdev);
250 return mask_supported;
253 static bool pci_check_and_mask_intx(struct pci_dev *pdev)
258 pci_block_user_cfg_access(pdev);
259 pci_read_config_dword(pdev, PCI_COMMAND, &status);
261 /* interrupt is not ours, goes to out */
262 pending = (((status >> 16) & PCI_STATUS_INTERRUPT) != 0);
268 new = old & (~PCI_COMMAND_INTX_DISABLE);
270 new = old | PCI_COMMAND_INTX_DISABLE;
273 pci_write_config_word(pdev, PCI_COMMAND, new);
275 pci_unblock_user_cfg_access(pdev);
282 * It masks the msix on/off of generating MSI-X messages.
285 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
287 u32 mask_bits = desc->masked;
288 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
289 PCI_MSIX_ENTRY_VECTOR_CTRL;
292 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
294 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
296 if (mask_bits != desc->masked) {
297 writel(mask_bits, desc->mask_base + offset);
298 readl(desc->mask_base);
299 desc->masked = mask_bits;
304 igbuio_msi_mask_irq(struct irq_data *data, u32 enable)
306 struct msi_desc *desc = irq_data_get_msi(data);
307 u32 mask_bits = desc->masked;
308 unsigned offset = data->irq - desc->dev->irq;
309 u32 mask = 1 << offset;
310 u32 flag = enable << offset;
315 if (desc->msi_attrib.maskbit && mask_bits != desc->masked) {
316 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
317 desc->masked = mask_bits;
322 * This is the irqcontrol callback to be registered to uio_info.
323 * It can be used to disable/enable interrupt from user space processes.
326 * pointer to uio_info.
328 * state value. 1 to enable interrupt, 0 to disable interrupt.
332 * - On failure, a negative value.
335 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
337 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
338 struct pci_dev *pdev = udev->pdev;
340 pci_cfg_access_lock(pdev);
341 if (udev->mode == RTE_INTR_MODE_LEGACY)
342 pci_intx(pdev, !!irq_state);
343 else if (udev->mode == RTE_INTR_MODE_MSI) {
344 struct irq_data *data = irq_get_irq_data(pdev->irq);
346 igbuio_msi_mask_irq(data, !!irq_state);
347 } else if (udev->mode == RTE_INTR_MODE_MSIX) {
348 struct msi_desc *desc;
350 list_for_each_entry(desc, &pdev->msi_list, list)
351 igbuio_msix_mask_irq(desc, irq_state);
353 pci_cfg_access_unlock(pdev);
359 * This is interrupt handler which will check if the interrupt is for the right device.
360 * If yes, disable it here and will be enable later.
363 igbuio_pci_irqhandler(int irq, struct uio_info *info)
365 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
367 /* Legacy mode need to mask in hardware */
368 if (udev->mode == RTE_INTR_MODE_LEGACY &&
369 !pci_check_and_mask_intx(udev->pdev))
372 /* Message signal mode, no share IRQ and automasked */
376 #ifdef CONFIG_XEN_DOM0
378 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
382 idx = (int)vma->vm_pgoff;
383 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
384 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
386 return remap_pfn_range(vma,
388 info->mem[idx].addr >> PAGE_SHIFT,
389 vma->vm_end - vma->vm_start,
394 * This is uio device mmap method which will use igbuio mmap for Xen
398 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
402 if (vma->vm_pgoff >= MAX_UIO_MAPS)
405 if (info->mem[vma->vm_pgoff].size == 0)
408 idx = (int)vma->vm_pgoff;
409 switch (info->mem[idx].memtype) {
411 return igbuio_dom0_mmap_phys(info, vma);
412 case UIO_MEM_LOGICAL:
413 case UIO_MEM_VIRTUAL:
420 /* Remap pci resources described by bar #pci_bar in uio resource n. */
422 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
423 int n, int pci_bar, const char *name)
425 unsigned long addr, len;
428 if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
431 addr = pci_resource_start(dev, pci_bar);
432 len = pci_resource_len(dev, pci_bar);
433 if (addr == 0 || len == 0)
435 internal_addr = ioremap(addr, len);
436 if (internal_addr == NULL)
438 info->mem[n].name = name;
439 info->mem[n].addr = addr;
440 info->mem[n].internal_addr = internal_addr;
441 info->mem[n].size = len;
442 info->mem[n].memtype = UIO_MEM_PHYS;
446 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
448 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
449 int n, int pci_bar, const char *name)
451 unsigned long addr, len;
453 if (sizeof(info->port) / sizeof(info->port[0]) <= n)
456 addr = pci_resource_start(dev, pci_bar);
457 len = pci_resource_len(dev, pci_bar);
458 if (addr == 0 || len == 0)
461 info->port[n].name = name;
462 info->port[n].start = addr;
463 info->port[n].size = len;
464 info->port[n].porttype = UIO_PORT_X86;
469 /* Unmap previously ioremap'd resources */
471 igbuio_pci_release_iomem(struct uio_info *info)
475 for (i = 0; i < MAX_UIO_MAPS; i++) {
476 if (info->mem[i].internal_addr)
477 iounmap(info->mem[i].internal_addr);
482 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
484 int i, iom, iop, ret;
486 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
498 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
499 if (pci_resource_len(dev, i) != 0 &&
500 pci_resource_start(dev, i) != 0) {
501 flags = pci_resource_flags(dev, i);
502 if (flags & IORESOURCE_MEM) {
503 ret = igbuio_pci_setup_iomem(dev, info, iom,
508 } else if (flags & IORESOURCE_IO) {
509 ret = igbuio_pci_setup_ioport(dev, info, iop,
518 return (iom != 0) ? ret : -ENOENT;
521 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
526 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
528 struct rte_uio_pci_dev *udev;
529 struct msix_entry msix_entry;
532 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
537 * enable device: ask low-level code to enable I/O and
540 err = pci_enable_device(dev);
542 dev_err(&dev->dev, "Cannot enable PCI device\n");
547 * reserve device's PCI memory regions for use by this
550 err = pci_request_regions(dev, "igb_uio");
552 dev_err(&dev->dev, "Cannot request regions\n");
556 /* enable bus mastering on the device */
559 /* remap IO memory */
560 err = igbuio_setup_bars(dev, &udev->info);
562 goto fail_release_iomem;
564 /* set 64-bit DMA mask */
565 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
567 dev_err(&dev->dev, "Cannot set DMA mask\n");
568 goto fail_release_iomem;
571 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
573 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
574 goto fail_release_iomem;
578 udev->info.name = "igb_uio";
579 udev->info.version = "0.1";
580 udev->info.handler = igbuio_pci_irqhandler;
581 udev->info.irqcontrol = igbuio_pci_irqcontrol;
582 udev->info.irq = dev->irq;
583 #ifdef CONFIG_XEN_DOM0
584 /* check if the driver run on Xen Dom0 */
585 if (xen_initial_domain())
586 udev->info.mmap = igbuio_dom0_pci_mmap;
588 udev->info.priv = udev;
591 switch (igbuio_intr_mode_preferred) {
592 case RTE_INTR_MODE_NONE:
595 case RTE_INTR_MODE_MSIX:
596 /* Only 1 msi-x vector needed */
597 msix_entry.entry = 0;
598 if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
599 dev_dbg(&dev->dev, "using MSI-X");
600 udev->info.irq = msix_entry.vector;
601 udev->mode = RTE_INTR_MODE_MSIX;
604 /* fall back to MSI */
605 case RTE_INTR_MODE_MSI:
606 if (pci_enable_msi(dev) == 0) {
607 dev_dbg(&dev->dev, "using MSI");
608 udev->mode = RTE_INTR_MODE_MSI;
611 /* fall back to INTX */
612 case RTE_INTR_MODE_LEGACY:
613 if (pci_intx_mask_supported(dev)) {
614 dev_dbg(&dev->dev, "using INTX");
615 udev->info.irq_flags = IRQF_SHARED;
616 udev->mode = RTE_INTR_MODE_LEGACY;
618 dev_err(&dev->dev, "PCI INTX mask not supported\n");
620 goto fail_release_iomem;
624 dev_err(&dev->dev, "invalid IRQ mode %u",
625 igbuio_intr_mode_preferred);
627 goto fail_release_iomem;
630 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
632 goto fail_release_iomem;
634 /* register uio driver */
635 err = uio_register_device(&dev->dev, &udev->info);
637 goto fail_remove_group;
639 pci_set_drvdata(dev, udev);
641 dev_info(&dev->dev, "uio device registered with irq %lx\n",
647 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
649 igbuio_pci_release_iomem(&udev->info);
650 if (udev->mode == RTE_INTR_MODE_MSIX)
651 pci_disable_msix(udev->pdev);
652 else if (udev->mode == RTE_INTR_MODE_MSI)
653 pci_disable_msi(udev->pdev);
654 pci_release_regions(dev);
656 pci_disable_device(dev);
664 igbuio_pci_remove(struct pci_dev *dev)
666 struct uio_info *info = pci_get_drvdata(dev);
667 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
669 if (info->priv == NULL) {
670 pr_notice("Not igbuio device\n");
674 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
675 uio_unregister_device(info);
676 igbuio_pci_release_iomem(info);
677 if (udev->mode == RTE_INTR_MODE_MSIX)
678 pci_disable_msix(dev);
679 else if (udev->mode == RTE_INTR_MODE_MSI)
680 pci_disable_msi(dev);
681 pci_release_regions(dev);
682 pci_disable_device(dev);
683 pci_set_drvdata(dev, NULL);
688 igbuio_config_intr_mode(char *intr_str)
691 pr_info("Use MSIX interrupt by default\n");
695 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
696 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
697 pr_info("Use MSIX interrupt\n");
698 } else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
699 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
700 pr_info("Use MSI interrupt\n");
701 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
702 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
703 pr_info("Use legacy interrupt\n");
705 pr_info("Error: bad parameter - %s\n", intr_str);
712 static struct pci_driver igbuio_pci_driver = {
715 .probe = igbuio_pci_probe,
716 .remove = igbuio_pci_remove,
720 igbuio_pci_init_module(void)
724 ret = igbuio_config_intr_mode(intr_mode);
728 return pci_register_driver(&igbuio_pci_driver);
732 igbuio_pci_exit_module(void)
734 pci_unregister_driver(&igbuio_pci_driver);
737 module_init(igbuio_pci_init_module);
738 module_exit(igbuio_pci_exit_module);
740 module_param(intr_mode, charp, S_IRUGO);
741 MODULE_PARM_DESC(intr_mode,
742 "igb_uio interrupt mode (default=msix):\n"
743 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
744 " " RTE_INTR_MODE_MSI_NAME " Use MSI interrupt\n"
745 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
748 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
749 MODULE_LICENSE("GPL");
750 MODULE_AUTHOR("Intel Corporation");