3 * Copyright (c) 2010-2012, Intel Corporation
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 * GNU GPL V2: http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
23 #include <linux/device.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/uio_driver.h>
28 #include <linux/msi.h>
29 #include <linux/version.h>
31 /* Some function names changes between 3.2.0 and 3.3.0... */
32 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
33 #define PCI_LOCK pci_block_user_cfg_access
34 #define PCI_UNLOCK pci_unblock_user_cfg_access
36 #define PCI_LOCK pci_cfg_access_lock
37 #define PCI_UNLOCK pci_cfg_access_unlock
41 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
42 * but none of them in kernel 2.6.35.
44 #ifndef PCI_MSIX_ENTRY_SIZE
45 #define PCI_MSIX_ENTRY_SIZE 16
46 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
47 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
48 #define PCI_MSIX_ENTRY_DATA 8
49 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
50 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
53 #define IGBUIO_NUM_MSI_VECTORS 1
56 enum igbuio_intr_mode {
57 IGBUIO_LEGACY_INTR_MODE = 0,
59 IGBUIO_MSIX_INTR_MODE,
64 * A structure describing the private information for a uio device.
66 struct rte_uio_pci_dev {
69 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
70 enum igbuio_intr_mode mode;
72 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
75 static const enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
77 /* PCI device id table */
78 static struct pci_device_id igbuio_pci_ids[] = {
79 #define RTE_PCI_DEV_ID_DECL(vend, dev) {PCI_DEVICE(vend, dev)},
80 #include <rte_pci_dev_ids.h>
84 static inline struct rte_uio_pci_dev *
85 igbuio_get_uio_pci_dev(struct uio_info *info)
87 return container_of(info, struct rte_uio_pci_dev, info);
91 * It masks the msix on/off of generating MSI-X messages.
94 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
96 uint32_t mask_bits = desc->masked;
97 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
98 PCI_MSIX_ENTRY_VECTOR_CTRL;
101 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
103 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
105 if (mask_bits != desc->masked) {
106 writel(mask_bits, desc->mask_base + offset);
107 readl(desc->mask_base);
108 desc->masked = mask_bits;
115 * This function sets/clears the masks for generating LSC interrupts.
118 * The pointer to struct uio_info.
120 * The on/off flag of masking LSC.
122 * -On success, zero value.
123 * -On failure, a negative value.
126 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
128 struct pci_dev *pdev = udev->pdev;
130 if (udev->mode == IGBUIO_MSIX_INTR_MODE) {
131 struct msi_desc *desc;
133 list_for_each_entry(desc, &pdev->msi_list, list) {
134 igbuio_msix_mask_irq(desc, state);
137 else if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
141 pci_read_config_dword(pdev, PCI_COMMAND, &status);
144 new = old & (~PCI_COMMAND_INTX_DISABLE);
146 new = old | PCI_COMMAND_INTX_DISABLE;
149 pci_write_config_word(pdev, PCI_COMMAND, new);
156 * This is the irqcontrol callback to be registered to uio_info.
157 * It can be used to disable/enable interrupt from user space processes.
160 * pointer to uio_info.
162 * state value. 1 to enable interrupt, 0 to disable interrupt.
166 * - On failure, a negative value.
169 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
172 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
173 struct pci_dev *pdev = udev->pdev;
175 spin_lock_irqsave(&udev->lock, flags);
178 igbuio_set_interrupt_mask(udev, irq_state);
181 spin_unlock_irqrestore(&udev->lock, flags);
187 * This is interrupt handler which will check if the interrupt is for the right device.
188 * If yes, disable it here and will be enable later.
191 igbuio_pci_irqhandler(int irq, struct uio_info *info)
193 irqreturn_t ret = IRQ_NONE;
195 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
196 struct pci_dev *pdev = udev->pdev;
197 uint32_t cmd_status_dword;
200 spin_lock_irqsave(&udev->lock, flags);
201 /* block userspace PCI config reads/writes */
204 /* for legacy mode, interrupt maybe shared */
205 if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
206 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
207 status = cmd_status_dword >> 16;
208 /* interrupt is not ours, goes to out */
209 if (!(status & PCI_STATUS_INTERRUPT))
213 igbuio_set_interrupt_mask(udev, 0);
216 /* unblock userspace PCI config reads/writes */
218 spin_unlock_irqrestore(&udev->lock, flags);
219 printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
224 /* Remap pci resources described by bar #pci_bar in uio resource n. */
226 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
227 int n, int pci_bar, const char *name)
229 unsigned long addr, len;
232 addr = pci_resource_start(dev, pci_bar);
233 len = pci_resource_len(dev, pci_bar);
234 if (addr == 0 || len == 0)
236 internal_addr = ioremap(addr, len);
237 if (internal_addr == NULL)
239 info->mem[n].name = name;
240 info->mem[n].addr = addr;
241 info->mem[n].internal_addr = internal_addr;
242 info->mem[n].size = len;
243 info->mem[n].memtype = UIO_MEM_PHYS;
247 /* Unmap previously ioremap'd resources */
249 igbuio_pci_release_iomem(struct uio_info *info)
252 for (i = 0; i < MAX_UIO_MAPS; i++) {
253 if (info->mem[i].internal_addr)
254 iounmap(info->mem[i].internal_addr);
259 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
261 struct rte_uio_pci_dev *udev;
263 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
268 * enable device: ask low-level code to enable I/O and
271 if (pci_enable_device(dev)) {
272 printk(KERN_ERR "Cannot enable PCI device\n");
276 /* XXX should we use 64 bits ? */
277 /* set 32-bit DMA mask */
278 if (pci_set_dma_mask(dev,(uint64_t)0xffffffff)) {
279 printk(KERN_ERR "Cannot set DMA mask\n");
284 * reserve device's PCI memory regions for use by this
287 if (pci_request_regions(dev, "igb_uio")) {
288 printk(KERN_ERR "Cannot request regions\n");
292 /* enable bus mastering on the device */
295 /* remap IO memory */
296 if (igbuio_pci_setup_iomem(dev, &udev->info, 0, 0, "config"))
297 goto fail_release_regions;
300 udev->info.name = "Intel IGB UIO";
301 udev->info.version = "0.1";
302 udev->info.handler = igbuio_pci_irqhandler;
303 udev->info.irqcontrol = igbuio_pci_irqcontrol;
304 udev->info.priv = udev;
306 udev->mode = 0; /* set the default value for interrupt mode */
307 spin_lock_init(&udev->lock);
309 /* check if it need to try msix first */
310 if (igbuio_intr_mode_preferred == IGBUIO_MSIX_INTR_MODE) {
313 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
314 udev->msix_entries[vector].entry = vector;
316 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
317 udev->mode = IGBUIO_MSIX_INTR_MODE;
320 pci_disable_msix(udev->pdev);
321 printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
324 switch (udev->mode) {
325 case IGBUIO_MSIX_INTR_MODE:
326 udev->info.irq_flags = 0;
327 udev->info.irq = udev->msix_entries[0].vector;
329 case IGBUIO_MSI_INTR_MODE:
331 case IGBUIO_LEGACY_INTR_MODE:
332 udev->info.irq_flags = IRQF_SHARED;
333 udev->info.irq = dev->irq;
339 pci_set_drvdata(dev, udev);
340 igbuio_pci_irqcontrol(&udev->info, 0);
342 /* register uio driver */
343 if (uio_register_device(&dev->dev, &udev->info))
344 goto fail_release_iomem;
346 printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
351 igbuio_pci_release_iomem(&udev->info);
352 if (udev->mode == IGBUIO_MSIX_INTR_MODE)
353 pci_disable_msix(udev->pdev);
354 fail_release_regions:
355 pci_release_regions(dev);
357 pci_disable_device(dev);
365 igbuio_pci_remove(struct pci_dev *dev)
367 struct uio_info *info = pci_get_drvdata(dev);
369 uio_unregister_device(info);
370 if (((struct rte_uio_pci_dev *)info->priv)->mode == IGBUIO_MSIX_INTR_MODE)
371 pci_disable_msix(dev);
372 pci_release_regions(dev);
373 pci_disable_device(dev);
374 pci_set_drvdata(dev, NULL);
378 static struct pci_driver igbuio_pci_driver = {
380 .id_table = igbuio_pci_ids,
381 .probe = igbuio_pci_probe,
382 .remove = igbuio_pci_remove,
386 igbuio_pci_init_module(void)
388 return pci_register_driver(&igbuio_pci_driver);
392 igbuio_pci_exit_module(void)
394 pci_unregister_driver(&igbuio_pci_driver);
397 module_init(igbuio_pci_init_module);
398 module_exit(igbuio_pci_exit_module);
400 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
401 MODULE_LICENSE("GPL");
402 MODULE_AUTHOR("Intel Corporation");