4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #include <linux/device.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/uio_driver.h>
30 #include <linux/msi.h>
31 #include <linux/version.h>
33 #ifdef CONFIG_XEN_DOM0
36 #include <rte_pci_dev_features.h>
39 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
40 * but none of them in kernel 2.6.35.
42 #ifndef PCI_MSIX_ENTRY_SIZE
43 #define PCI_MSIX_ENTRY_SIZE 16
44 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
45 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
46 #define PCI_MSIX_ENTRY_DATA 8
47 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
48 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
51 #define IGBUIO_NUM_MSI_VECTORS 1
54 * A structure describing the private information for a uio device.
56 struct rte_uio_pci_dev {
59 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
60 enum rte_intr_mode mode;
62 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
65 static char *intr_mode = NULL;
66 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
68 /* PCI device id table */
69 static struct pci_device_id igbuio_pci_ids[] = {
70 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {PCI_DEVICE(vend, dev)},
71 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {PCI_DEVICE(vend, dev)},
72 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {PCI_DEVICE(vend, dev)},
73 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {PCI_DEVICE(vend, dev)},
74 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {PCI_DEVICE(vend, dev)},
75 #ifdef RTE_LIBRTE_VIRTIO_PMD
76 #define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev) {PCI_DEVICE(vend, dev)},
78 #ifdef RTE_LIBRTE_VMXNET3_PMD
79 #define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {PCI_DEVICE(vend, dev)},
81 #include <rte_pci_dev_ids.h>
85 MODULE_DEVICE_TABLE(pci, igbuio_pci_ids);
87 static inline struct rte_uio_pci_dev *
88 igbuio_get_uio_pci_dev(struct uio_info *info)
90 return container_of(info, struct rte_uio_pci_dev, info);
94 int local_pci_num_vf(struct pci_dev *dev)
96 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
105 } *iov = (struct iov*)dev->sriov;
110 return iov->nr_virtfn;
112 return pci_num_vf(dev);
117 show_max_vfs(struct device *dev, struct device_attribute *attr,
120 return snprintf(buf, 10, "%u\n", local_pci_num_vf(
121 container_of(dev, struct pci_dev, dev)));
125 store_max_vfs(struct device *dev, struct device_attribute *attr,
126 const char *buf, size_t count)
129 unsigned long max_vfs;
130 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
132 if (0 != strict_strtoul(buf, 0, &max_vfs))
136 pci_disable_sriov(pdev);
137 else if (0 == local_pci_num_vf(pdev))
138 err = pci_enable_sriov(pdev, max_vfs);
139 else /* do nothing if change max_vfs number */
142 return err ? err : count;
145 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
146 static struct attribute *dev_attrs[] = {
147 &dev_attr_max_vfs.attr,
151 static const struct attribute_group dev_attr_grp = {
156 pci_lock(struct pci_dev * pdev)
158 /* Some function names changes between 3.2.0 and 3.3.0... */
159 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
160 pci_block_user_cfg_access(pdev);
163 return pci_cfg_access_trylock(pdev);
168 pci_unlock(struct pci_dev * pdev)
170 /* Some function names changes between 3.2.0 and 3.3.0... */
171 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
172 pci_unblock_user_cfg_access(pdev);
174 pci_cfg_access_unlock(pdev);
179 * It masks the msix on/off of generating MSI-X messages.
182 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
184 uint32_t mask_bits = desc->masked;
185 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
186 PCI_MSIX_ENTRY_VECTOR_CTRL;
189 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
191 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
193 if (mask_bits != desc->masked) {
194 writel(mask_bits, desc->mask_base + offset);
195 readl(desc->mask_base);
196 desc->masked = mask_bits;
203 * This function sets/clears the masks for generating LSC interrupts.
206 * The pointer to struct uio_info.
208 * The on/off flag of masking LSC.
210 * -On success, zero value.
211 * -On failure, a negative value.
214 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
216 struct pci_dev *pdev = udev->pdev;
218 if (udev->mode == RTE_INTR_MODE_MSIX) {
219 struct msi_desc *desc;
221 list_for_each_entry(desc, &pdev->msi_list, list) {
222 igbuio_msix_mask_irq(desc, state);
224 } else if (udev->mode == RTE_INTR_MODE_LEGACY) {
228 pci_read_config_dword(pdev, PCI_COMMAND, &status);
231 new = old & (~PCI_COMMAND_INTX_DISABLE);
233 new = old | PCI_COMMAND_INTX_DISABLE;
236 pci_write_config_word(pdev, PCI_COMMAND, new);
243 * This is the irqcontrol callback to be registered to uio_info.
244 * It can be used to disable/enable interrupt from user space processes.
247 * pointer to uio_info.
249 * state value. 1 to enable interrupt, 0 to disable interrupt.
253 * - On failure, a negative value.
256 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
259 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
260 struct pci_dev *pdev = udev->pdev;
262 spin_lock_irqsave(&udev->lock, flags);
263 if (!pci_lock(pdev)) {
264 spin_unlock_irqrestore(&udev->lock, flags);
268 igbuio_set_interrupt_mask(udev, irq_state);
271 spin_unlock_irqrestore(&udev->lock, flags);
277 * This is interrupt handler which will check if the interrupt is for the right device.
278 * If yes, disable it here and will be enable later.
281 igbuio_pci_irqhandler(int irq, struct uio_info *info)
283 irqreturn_t ret = IRQ_NONE;
285 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
286 struct pci_dev *pdev = udev->pdev;
287 uint32_t cmd_status_dword;
290 spin_lock_irqsave(&udev->lock, flags);
291 /* block userspace PCI config reads/writes */
295 /* for legacy mode, interrupt maybe shared */
296 if (udev->mode == RTE_INTR_MODE_LEGACY) {
297 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
298 status = cmd_status_dword >> 16;
299 /* interrupt is not ours, goes to out */
300 if (!(status & PCI_STATUS_INTERRUPT))
304 igbuio_set_interrupt_mask(udev, 0);
307 /* unblock userspace PCI config reads/writes */
310 spin_unlock_irqrestore(&udev->lock, flags);
311 printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
316 #ifdef CONFIG_XEN_DOM0
318 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
321 idx = (int)vma->vm_pgoff;
322 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
323 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
325 return remap_pfn_range(vma,
327 info->mem[idx].addr >> PAGE_SHIFT,
328 vma->vm_end - vma->vm_start,
333 * This is uio device mmap method which will use igbuio mmap for Xen
337 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
341 if (vma->vm_pgoff >= MAX_UIO_MAPS)
343 if(info->mem[vma->vm_pgoff].size == 0)
346 idx = (int)vma->vm_pgoff;
347 switch (info->mem[idx].memtype) {
349 return igbuio_dom0_mmap_phys(info, vma);
350 case UIO_MEM_LOGICAL:
351 case UIO_MEM_VIRTUAL:
358 /* Remap pci resources described by bar #pci_bar in uio resource n. */
360 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
361 int n, int pci_bar, const char *name)
363 unsigned long addr, len;
366 if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
369 addr = pci_resource_start(dev, pci_bar);
370 len = pci_resource_len(dev, pci_bar);
371 if (addr == 0 || len == 0)
373 internal_addr = ioremap(addr, len);
374 if (internal_addr == NULL)
376 info->mem[n].name = name;
377 info->mem[n].addr = addr;
378 info->mem[n].internal_addr = internal_addr;
379 info->mem[n].size = len;
380 info->mem[n].memtype = UIO_MEM_PHYS;
384 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
386 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
387 int n, int pci_bar, const char *name)
389 unsigned long addr, len;
391 if (sizeof(info->port) / sizeof (info->port[0]) <= n)
394 addr = pci_resource_start(dev, pci_bar);
395 len = pci_resource_len(dev, pci_bar);
396 if (addr == 0 || len == 0)
399 info->port[n].name = name;
400 info->port[n].start = addr;
401 info->port[n].size = len;
402 info->port[n].porttype = UIO_PORT_X86;
407 /* Unmap previously ioremap'd resources */
409 igbuio_pci_release_iomem(struct uio_info *info)
412 for (i = 0; i < MAX_UIO_MAPS; i++) {
413 if (info->mem[i].internal_addr)
414 iounmap(info->mem[i].internal_addr);
419 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
421 int i, iom, iop, ret;
423 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
435 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
436 if (pci_resource_len(dev, i) != 0 &&
437 pci_resource_start(dev, i) != 0) {
438 flags = pci_resource_flags(dev, i);
439 if (flags & IORESOURCE_MEM) {
440 if ((ret = igbuio_pci_setup_iomem(dev, info,
441 iom, i, bar_names[i])) != 0)
444 } else if (flags & IORESOURCE_IO) {
445 if ((ret = igbuio_pci_setup_ioport(dev, info,
446 iop, i, bar_names[i])) != 0)
453 return ((iom != 0) ? ret : ENOENT);
456 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
461 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
463 struct rte_uio_pci_dev *udev;
465 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
470 * enable device: ask low-level code to enable I/O and
473 if (pci_enable_device(dev)) {
474 printk(KERN_ERR "Cannot enable PCI device\n");
479 * reserve device's PCI memory regions for use by this
482 if (pci_request_regions(dev, "igb_uio")) {
483 printk(KERN_ERR "Cannot request regions\n");
487 /* enable bus mastering on the device */
490 /* remap IO memory */
491 if (igbuio_setup_bars(dev, &udev->info))
492 goto fail_release_iomem;
494 /* set 64-bit DMA mask */
495 if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
496 printk(KERN_ERR "Cannot set DMA mask\n");
497 goto fail_release_iomem;
498 } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
499 printk(KERN_ERR "Cannot set consistent DMA mask\n");
500 goto fail_release_iomem;
504 udev->info.name = "Intel IGB UIO";
505 udev->info.version = "0.1";
506 udev->info.handler = igbuio_pci_irqhandler;
507 udev->info.irqcontrol = igbuio_pci_irqcontrol;
508 #ifdef CONFIG_XEN_DOM0
509 /* check if the driver run on Xen Dom0 */
510 if (xen_initial_domain())
511 udev->info.mmap = igbuio_dom0_pci_mmap;
513 udev->info.priv = udev;
515 udev->mode = RTE_INTR_MODE_LEGACY;
516 spin_lock_init(&udev->lock);
518 /* check if it need to try msix first */
519 if (igbuio_intr_mode_preferred == RTE_INTR_MODE_MSIX) {
522 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
523 udev->msix_entries[vector].entry = vector;
525 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
526 udev->mode = RTE_INTR_MODE_MSIX;
529 pci_disable_msix(udev->pdev);
530 printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
533 switch (udev->mode) {
534 case RTE_INTR_MODE_MSIX:
535 udev->info.irq_flags = 0;
536 udev->info.irq = udev->msix_entries[0].vector;
538 case RTE_INTR_MODE_MSI:
540 case RTE_INTR_MODE_LEGACY:
541 udev->info.irq_flags = IRQF_SHARED;
542 udev->info.irq = dev->irq;
548 pci_set_drvdata(dev, udev);
549 igbuio_pci_irqcontrol(&udev->info, 0);
551 if (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))
552 goto fail_release_iomem;
554 /* register uio driver */
555 if (uio_register_device(&dev->dev, &udev->info))
556 goto fail_release_iomem;
558 printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
563 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
564 igbuio_pci_release_iomem(&udev->info);
565 if (udev->mode == RTE_INTR_MODE_MSIX)
566 pci_disable_msix(udev->pdev);
567 pci_release_regions(dev);
569 pci_disable_device(dev);
577 igbuio_pci_remove(struct pci_dev *dev)
579 struct uio_info *info = pci_get_drvdata(dev);
581 if (info->priv == NULL) {
582 printk(KERN_DEBUG "Not igbuio device\n");
586 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
587 uio_unregister_device(info);
588 igbuio_pci_release_iomem(info);
589 if (((struct rte_uio_pci_dev *)info->priv)->mode ==
591 pci_disable_msix(dev);
592 pci_release_regions(dev);
593 pci_disable_device(dev);
594 pci_set_drvdata(dev, NULL);
599 igbuio_config_intr_mode(char *intr_str)
602 printk(KERN_INFO "Use MSIX interrupt by default\n");
606 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
607 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
608 printk(KERN_INFO "Use MSIX interrupt\n");
609 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
610 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
611 printk(KERN_INFO "Use legacy interrupt\n");
613 printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
620 static struct pci_driver igbuio_pci_driver = {
622 .id_table = igbuio_pci_ids,
623 .probe = igbuio_pci_probe,
624 .remove = igbuio_pci_remove,
628 igbuio_pci_init_module(void)
632 ret = igbuio_config_intr_mode(intr_mode);
636 return pci_register_driver(&igbuio_pci_driver);
640 igbuio_pci_exit_module(void)
642 pci_unregister_driver(&igbuio_pci_driver);
645 module_init(igbuio_pci_init_module);
646 module_exit(igbuio_pci_exit_module);
648 module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
649 MODULE_PARM_DESC(intr_mode,
650 "igb_uio interrupt mode (default=msix):\n"
651 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
652 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
655 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
656 MODULE_LICENSE("GPL");
657 MODULE_AUTHOR("Intel Corporation");