4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/uio_driver.h>
31 #include <linux/msi.h>
32 #include <linux/version.h>
35 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
36 * but none of them in kernel 2.6.35.
38 #ifndef PCI_MSIX_ENTRY_SIZE
39 #define PCI_MSIX_ENTRY_SIZE 16
40 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
41 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
42 #define PCI_MSIX_ENTRY_DATA 8
43 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
44 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
47 #define IGBUIO_NUM_MSI_VECTORS 1
50 enum igbuio_intr_mode {
51 IGBUIO_LEGACY_INTR_MODE = 0,
53 IGBUIO_MSIX_INTR_MODE,
58 * A structure describing the private information for a uio device.
60 struct rte_uio_pci_dev {
63 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
64 enum igbuio_intr_mode mode;
66 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
69 static char *intr_mode = NULL;
70 static enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
72 /* PCI device id table */
73 static struct pci_device_id igbuio_pci_ids[] = {
74 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {PCI_DEVICE(vend, dev)},
75 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {PCI_DEVICE(vend, dev)},
76 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {PCI_DEVICE(vend, dev)},
77 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {PCI_DEVICE(vend, dev)},
78 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {PCI_DEVICE(vend, dev)},
79 #include <rte_pci_dev_ids.h>
83 MODULE_DEVICE_TABLE(pci, igbuio_pci_ids);
85 static inline struct rte_uio_pci_dev *
86 igbuio_get_uio_pci_dev(struct uio_info *info)
88 return container_of(info, struct rte_uio_pci_dev, info);
92 pci_lock(struct pci_dev * pdev)
94 /* Some function names changes between 3.2.0 and 3.3.0... */
95 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
96 pci_block_user_cfg_access(pdev);
99 return pci_cfg_access_trylock(pdev);
104 pci_unlock(struct pci_dev * pdev)
106 /* Some function names changes between 3.2.0 and 3.3.0... */
107 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
108 pci_unblock_user_cfg_access(pdev);
110 pci_cfg_access_unlock(pdev);
115 * It masks the msix on/off of generating MSI-X messages.
118 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
120 uint32_t mask_bits = desc->masked;
121 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
122 PCI_MSIX_ENTRY_VECTOR_CTRL;
125 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
127 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
129 if (mask_bits != desc->masked) {
130 writel(mask_bits, desc->mask_base + offset);
131 readl(desc->mask_base);
132 desc->masked = mask_bits;
139 * This function sets/clears the masks for generating LSC interrupts.
142 * The pointer to struct uio_info.
144 * The on/off flag of masking LSC.
146 * -On success, zero value.
147 * -On failure, a negative value.
150 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
152 struct pci_dev *pdev = udev->pdev;
154 if (udev->mode == IGBUIO_MSIX_INTR_MODE) {
155 struct msi_desc *desc;
157 list_for_each_entry(desc, &pdev->msi_list, list) {
158 igbuio_msix_mask_irq(desc, state);
161 else if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
165 pci_read_config_dword(pdev, PCI_COMMAND, &status);
168 new = old & (~PCI_COMMAND_INTX_DISABLE);
170 new = old | PCI_COMMAND_INTX_DISABLE;
173 pci_write_config_word(pdev, PCI_COMMAND, new);
180 * This is the irqcontrol callback to be registered to uio_info.
181 * It can be used to disable/enable interrupt from user space processes.
184 * pointer to uio_info.
186 * state value. 1 to enable interrupt, 0 to disable interrupt.
190 * - On failure, a negative value.
193 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
196 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
197 struct pci_dev *pdev = udev->pdev;
199 spin_lock_irqsave(&udev->lock, flags);
200 if (!pci_lock(pdev)) {
201 spin_unlock_irqrestore(&udev->lock, flags);
205 igbuio_set_interrupt_mask(udev, irq_state);
208 spin_unlock_irqrestore(&udev->lock, flags);
214 * This is interrupt handler which will check if the interrupt is for the right device.
215 * If yes, disable it here and will be enable later.
218 igbuio_pci_irqhandler(int irq, struct uio_info *info)
220 irqreturn_t ret = IRQ_NONE;
222 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
223 struct pci_dev *pdev = udev->pdev;
224 uint32_t cmd_status_dword;
227 spin_lock_irqsave(&udev->lock, flags);
228 /* block userspace PCI config reads/writes */
232 /* for legacy mode, interrupt maybe shared */
233 if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
234 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
235 status = cmd_status_dword >> 16;
236 /* interrupt is not ours, goes to out */
237 if (!(status & PCI_STATUS_INTERRUPT))
241 igbuio_set_interrupt_mask(udev, 0);
244 /* unblock userspace PCI config reads/writes */
247 spin_unlock_irqrestore(&udev->lock, flags);
248 printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
253 /* Remap pci resources described by bar #pci_bar in uio resource n. */
255 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
256 int n, int pci_bar, const char *name)
258 unsigned long addr, len;
261 if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
264 addr = pci_resource_start(dev, pci_bar);
265 len = pci_resource_len(dev, pci_bar);
266 if (addr == 0 || len == 0)
268 internal_addr = ioremap(addr, len);
269 if (internal_addr == NULL)
271 info->mem[n].name = name;
272 info->mem[n].addr = addr;
273 info->mem[n].internal_addr = internal_addr;
274 info->mem[n].size = len;
275 info->mem[n].memtype = UIO_MEM_PHYS;
279 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
281 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
282 int n, int pci_bar, const char *name)
284 unsigned long addr, len;
286 if (sizeof(info->port) / sizeof (info->port[0]) <= n)
289 addr = pci_resource_start(dev, pci_bar);
290 len = pci_resource_len(dev, pci_bar);
291 if (addr == 0 || len == 0)
294 info->port[n].name = name;
295 info->port[n].start = addr;
296 info->port[n].size = len;
297 info->port[n].porttype = UIO_PORT_X86;
302 /* Unmap previously ioremap'd resources */
304 igbuio_pci_release_iomem(struct uio_info *info)
307 for (i = 0; i < MAX_UIO_MAPS; i++) {
308 if (info->mem[i].internal_addr)
309 iounmap(info->mem[i].internal_addr);
314 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
316 int i, iom, iop, ret;
318 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
330 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
331 if (pci_resource_len(dev, i) != 0 &&
332 pci_resource_start(dev, i) != 0) {
333 flags = pci_resource_flags(dev, i);
334 if (flags & IORESOURCE_MEM) {
335 if ((ret = igbuio_pci_setup_iomem(dev, info,
336 iom, i, bar_names[i])) != 0)
339 } else if (flags & IORESOURCE_IO) {
340 if ((ret = igbuio_pci_setup_ioport(dev, info,
341 iop, i, bar_names[i])) != 0)
348 return ((iom != 0) ? ret : ENOENT);
351 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
356 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
358 struct rte_uio_pci_dev *udev;
360 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
365 * enable device: ask low-level code to enable I/O and
368 if (pci_enable_device(dev)) {
369 printk(KERN_ERR "Cannot enable PCI device\n");
374 * reserve device's PCI memory regions for use by this
377 if (pci_request_regions(dev, "igb_uio")) {
378 printk(KERN_ERR "Cannot request regions\n");
382 /* enable bus mastering on the device */
385 /* remap IO memory */
386 if (igbuio_setup_bars(dev, &udev->info))
387 goto fail_release_iomem;
389 /* set 64-bit DMA mask */
390 if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
391 printk(KERN_ERR "Cannot set DMA mask\n");
392 goto fail_release_iomem;
393 } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
394 printk(KERN_ERR "Cannot set consistent DMA mask\n");
395 goto fail_release_iomem;
399 udev->info.name = "Intel IGB UIO";
400 udev->info.version = "0.1";
401 udev->info.handler = igbuio_pci_irqhandler;
402 udev->info.irqcontrol = igbuio_pci_irqcontrol;
403 udev->info.priv = udev;
405 udev->mode = 0; /* set the default value for interrupt mode */
406 spin_lock_init(&udev->lock);
408 /* check if it need to try msix first */
409 if (igbuio_intr_mode_preferred == IGBUIO_MSIX_INTR_MODE) {
412 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
413 udev->msix_entries[vector].entry = vector;
415 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
416 udev->mode = IGBUIO_MSIX_INTR_MODE;
419 pci_disable_msix(udev->pdev);
420 printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
423 switch (udev->mode) {
424 case IGBUIO_MSIX_INTR_MODE:
425 udev->info.irq_flags = 0;
426 udev->info.irq = udev->msix_entries[0].vector;
428 case IGBUIO_MSI_INTR_MODE:
430 case IGBUIO_LEGACY_INTR_MODE:
431 udev->info.irq_flags = IRQF_SHARED;
432 udev->info.irq = dev->irq;
438 pci_set_drvdata(dev, udev);
439 igbuio_pci_irqcontrol(&udev->info, 0);
441 /* register uio driver */
442 if (uio_register_device(&dev->dev, &udev->info))
443 goto fail_release_iomem;
445 printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
450 igbuio_pci_release_iomem(&udev->info);
451 if (udev->mode == IGBUIO_MSIX_INTR_MODE)
452 pci_disable_msix(udev->pdev);
453 pci_release_regions(dev);
455 pci_disable_device(dev);
463 igbuio_pci_remove(struct pci_dev *dev)
465 struct uio_info *info = pci_get_drvdata(dev);
467 if (info->priv == NULL) {
468 printk(KERN_DEBUG "Not igbuio device\n");
472 uio_unregister_device(info);
473 igbuio_pci_release_iomem(info);
474 if (((struct rte_uio_pci_dev *)info->priv)->mode ==
475 IGBUIO_MSIX_INTR_MODE)
476 pci_disable_msix(dev);
477 pci_release_regions(dev);
478 pci_disable_device(dev);
479 pci_set_drvdata(dev, NULL);
484 igbuio_config_intr_mode(char *intr_str)
487 printk(KERN_INFO "Use MSIX interrupt by default\n");
491 if (!strcmp(intr_str, "msix")) {
492 igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
493 printk(KERN_INFO "Use MSIX interrupt\n");
494 } else if (!strcmp(intr_str, "legacy")) {
495 igbuio_intr_mode_preferred = IGBUIO_LEGACY_INTR_MODE;
496 printk(KERN_INFO "Use legacy interrupt\n");
498 printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
505 static struct pci_driver igbuio_pci_driver = {
507 .id_table = igbuio_pci_ids,
508 .probe = igbuio_pci_probe,
509 .remove = igbuio_pci_remove,
513 igbuio_pci_init_module(void)
517 ret = igbuio_config_intr_mode(intr_mode);
521 return pci_register_driver(&igbuio_pci_driver);
525 igbuio_pci_exit_module(void)
527 pci_unregister_driver(&igbuio_pci_driver);
530 module_init(igbuio_pci_init_module);
531 module_exit(igbuio_pci_exit_module);
533 module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
534 MODULE_PARM_DESC(intr_mode,
535 "igb_uio interrupt mode (default=msix):\n"
536 " msix Use MSIX interrupt\n"
537 " legacy Use Legacy interrupt\n"
540 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
541 MODULE_LICENSE("GPL");
542 MODULE_AUTHOR("Intel Corporation");