lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include "e1000_osdep.h"
  32 #include "e1000_regs.h"
  33 #include "e1000_defines.h"
  34
  35 struct e1000_hw;
  36
  37 #define E1000_DEV_ID_82576                      0x10C9
  38 #define E1000_DEV_ID_82576_FIBER                0x10E6
  39 #define E1000_DEV_ID_82576_SERDES               0x10E7
  40 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
  41 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
  42 #define E1000_DEV_ID_82576_NS                   0x150A
  43 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
  44 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
  45 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
  46 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
  47 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
  48 #define E1000_DEV_ID_82580_COPPER               0x150E
  49 #define E1000_DEV_ID_82580_FIBER                0x150F
  50 #define E1000_DEV_ID_82580_SERDES               0x1510
  51 #define E1000_DEV_ID_82580_SGMII                0x1511
  52 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
  53 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
  54 #define E1000_DEV_ID_I350_COPPER                0x1521
  55 #define E1000_DEV_ID_I350_FIBER                 0x1522
  56 #define E1000_DEV_ID_I350_SERDES                0x1523
  57 #define E1000_DEV_ID_I350_SGMII                 0x1524
  58 #define E1000_DEV_ID_I350_DA4                   0x1546
  59 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
  60 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
  61 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
  62 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
  63 #define E1000_REVISION_0        0
  64 #define E1000_REVISION_1        1
  65 #define E1000_REVISION_2        2
  66 #define E1000_REVISION_3        3
  67 #define E1000_REVISION_4        4
  68
  69 #define E1000_FUNC_0            0
  70 #define E1000_FUNC_1            1
  71 #define E1000_FUNC_2            2
  72 #define E1000_FUNC_3            3
  73
  74 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
  75 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
  76 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
  77 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
  78
  79 enum e1000_mac_type {
  80         e1000_undefined = 0,
  81         e1000_82575,
  82         e1000_82576,
  83         e1000_82580,
  84         e1000_i350,
  85         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  86 };
  87
  88 enum e1000_media_type {
  89         e1000_media_type_unknown = 0,
  90         e1000_media_type_copper = 1,
  91         e1000_media_type_fiber = 2,
  92         e1000_media_type_internal_serdes = 3,
  93         e1000_num_media_types
  94 };
  95
  96 enum e1000_nvm_type {
  97         e1000_nvm_unknown = 0,
  98         e1000_nvm_none,
  99         e1000_nvm_eeprom_spi,
 100         e1000_nvm_flash_hw,
 101         e1000_nvm_flash_sw
 102 };
 103
 104 enum e1000_nvm_override {
 105         e1000_nvm_override_none = 0,
 106         e1000_nvm_override_spi_small,
 107         e1000_nvm_override_spi_large,
 108 };
 109
 110 enum e1000_phy_type {
 111         e1000_phy_unknown = 0,
 112         e1000_phy_none,
 113         e1000_phy_m88,
 114         e1000_phy_igp,
 115         e1000_phy_igp_2,
 116         e1000_phy_gg82563,
 117         e1000_phy_igp_3,
 118         e1000_phy_ife,
 119         e1000_phy_82580,
 120         e1000_phy_vf,
 121 };
 122
 123 enum e1000_bus_type {
 124         e1000_bus_type_unknown = 0,
 125         e1000_bus_type_pci,
 126         e1000_bus_type_pcix,
 127         e1000_bus_type_pci_express,
 128         e1000_bus_type_reserved
 129 };
 130
 131 enum e1000_bus_speed {
 132         e1000_bus_speed_unknown = 0,
 133         e1000_bus_speed_33,
 134         e1000_bus_speed_66,
 135         e1000_bus_speed_100,
 136         e1000_bus_speed_120,
 137         e1000_bus_speed_133,
 138         e1000_bus_speed_2500,
 139         e1000_bus_speed_5000,
 140         e1000_bus_speed_reserved
 141 };
 142
 143 enum e1000_bus_width {
 144         e1000_bus_width_unknown = 0,
 145         e1000_bus_width_pcie_x1,
 146         e1000_bus_width_pcie_x2,
 147         e1000_bus_width_pcie_x4 = 4,
 148         e1000_bus_width_pcie_x8 = 8,
 149         e1000_bus_width_32,
 150         e1000_bus_width_64,
 151         e1000_bus_width_reserved
 152 };
 153
 154 enum e1000_1000t_rx_status {
 155         e1000_1000t_rx_status_not_ok = 0,
 156         e1000_1000t_rx_status_ok,
 157         e1000_1000t_rx_status_undefined = 0xFF
 158 };
 159
 160 enum e1000_rev_polarity {
 161         e1000_rev_polarity_normal = 0,
 162         e1000_rev_polarity_reversed,
 163         e1000_rev_polarity_undefined = 0xFF
 164 };
 165
 166 enum e1000_fc_mode {
 167         e1000_fc_none = 0,
 168         e1000_fc_rx_pause,
 169         e1000_fc_tx_pause,
 170         e1000_fc_full,
 171         e1000_fc_default = 0xFF
 172 };
 173
 174 enum e1000_ms_type {
 175         e1000_ms_hw_default = 0,
 176         e1000_ms_force_master,
 177         e1000_ms_force_slave,
 178         e1000_ms_auto
 179 };
 180
 181 enum e1000_smart_speed {
 182         e1000_smart_speed_default = 0,
 183         e1000_smart_speed_on,
 184         e1000_smart_speed_off
 185 };
 186
 187 enum e1000_serdes_link_state {
 188         e1000_serdes_link_down = 0,
 189         e1000_serdes_link_autoneg_progress,
 190         e1000_serdes_link_autoneg_complete,
 191         e1000_serdes_link_forced_up
 192 };
 193
 194 #ifndef __le16
 195 #define __le16 u16
 196 #endif
 197 #ifndef __le32
 198 #define __le32 u32
 199 #endif
 200 #ifndef __le64
 201 #define __le64 u64
 202 #endif
 203 /* Receive Descriptor */
 204 struct e1000_rx_desc {
 205         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 206         __le16 length;      /* Length of data DMAed into data buffer */
 207         __le16 csum; /* Packet checksum */
 208         u8  status;  /* Descriptor status */
 209         u8  errors;  /* Descriptor Errors */
 210         __le16 special;
 211 };
 212
 213 /* Receive Descriptor - Extended */
 214 union e1000_rx_desc_extended {
 215         struct {
 216                 __le64 buffer_addr;
 217                 __le64 reserved;
 218         } read;
 219         struct {
 220                 struct {
 221                         __le32 mrq; /* Multiple Rx Queues */
 222                         union {
 223                                 __le32 rss; /* RSS Hash */
 224                                 struct {
 225                                         __le16 ip_id;  /* IP id */
 226                                         __le16 csum;   /* Packet Checksum */
 227                                 } csum_ip;
 228                         } hi_dword;
 229                 } lower;
 230                 struct {
 231                         __le32 status_error;  /* ext status/error */
 232                         __le16 length;
 233                         __le16 vlan; /* VLAN tag */
 234                 } upper;
 235         } wb;  /* writeback */
 236 };
 237
 238 #define MAX_PS_BUFFERS 4
 239 /* Receive Descriptor - Packet Split */
 240 union e1000_rx_desc_packet_split {
 241         struct {
 242                 /* one buffer for protocol header(s), three data buffers */
 243                 __le64 buffer_addr[MAX_PS_BUFFERS];
 244         } read;
 245         struct {
 246                 struct {
 247                         __le32 mrq;  /* Multiple Rx Queues */
 248                         union {
 249                                 __le32 rss; /* RSS Hash */
 250                                 struct {
 251                                         __le16 ip_id;    /* IP id */
 252                                         __le16 csum;     /* Packet Checksum */
 253                                 } csum_ip;
 254                         } hi_dword;
 255                 } lower;
 256                 struct {
 257                         __le32 status_error;  /* ext status/error */
 258                         __le16 length0;  /* length of buffer 0 */
 259                         __le16 vlan;  /* VLAN tag */
 260                 } middle;
 261                 struct {
 262                         __le16 header_status;
 263                         __le16 length[3];     /* length of buffers 1-3 */
 264                 } upper;
 265                 __le64 reserved;
 266         } wb; /* writeback */
 267 };
 268
 269 /* Transmit Descriptor */
 270 struct e1000_tx_desc {
 271         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 272         union {
 273                 __le32 data;
 274                 struct {
 275                         __le16 length;  /* Data buffer length */
 276                         u8 cso;  /* Checksum offset */
 277                         u8 cmd;  /* Descriptor control */
 278                 } flags;
 279         } lower;
 280         union {
 281                 __le32 data;
 282                 struct {
 283                         u8 status; /* Descriptor status */
 284                         u8 css;  /* Checksum start */
 285                         __le16 special;
 286                 } fields;
 287         } upper;
 288 };
 289
 290 /* Offload Context Descriptor */
 291 struct e1000_context_desc {
 292         union {
 293                 __le32 ip_config;
 294                 struct {
 295                         u8 ipcss;  /* IP checksum start */
 296                         u8 ipcso;  /* IP checksum offset */
 297                         __le16 ipcse;  /* IP checksum end */
 298                 } ip_fields;
 299         } lower_setup;
 300         union {
 301                 __le32 tcp_config;
 302                 struct {
 303                         u8 tucss;  /* TCP checksum start */
 304                         u8 tucso;  /* TCP checksum offset */
 305                         __le16 tucse;  /* TCP checksum end */
 306                 } tcp_fields;
 307         } upper_setup;
 308         __le32 cmd_and_length;
 309         union {
 310                 __le32 data;
 311                 struct {
 312                         u8 status;  /* Descriptor status */
 313                         u8 hdr_len;  /* Header length */
 314                         __le16 mss;  /* Maximum segment size */
 315                 } fields;
 316         } tcp_seg_setup;
 317 };
 318
 319 /* Offload data descriptor */
 320 struct e1000_data_desc {
 321         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 322         union {
 323                 __le32 data;
 324                 struct {
 325                         __le16 length;  /* Data buffer length */
 326                         u8 typ_len_ext;
 327                         u8 cmd;
 328                 } flags;
 329         } lower;
 330         union {
 331                 __le32 data;
 332                 struct {
 333                         u8 status;  /* Descriptor status */
 334                         u8 popts;  /* Packet Options */
 335                         __le16 special;
 336                 } fields;
 337         } upper;
 338 };
 339
 340 /* Statistics counters collected by the MAC */
 341 struct e1000_hw_stats {
 342         u64 crcerrs;
 343         u64 algnerrc;
 344         u64 symerrs;
 345         u64 rxerrc;
 346         u64 mpc;
 347         u64 scc;
 348         u64 ecol;
 349         u64 mcc;
 350         u64 latecol;
 351         u64 colc;
 352         u64 dc;
 353         u64 tncrs;
 354         u64 sec;
 355         u64 cexterr;
 356         u64 rlec;
 357         u64 xonrxc;
 358         u64 xontxc;
 359         u64 xoffrxc;
 360         u64 xofftxc;
 361         u64 fcruc;
 362         u64 prc64;
 363         u64 prc127;
 364         u64 prc255;
 365         u64 prc511;
 366         u64 prc1023;
 367         u64 prc1522;
 368         u64 gprc;
 369         u64 bprc;
 370         u64 mprc;
 371         u64 gptc;
 372         u64 gorc;
 373         u64 gotc;
 374         u64 rnbc;
 375         u64 ruc;
 376         u64 rfc;
 377         u64 roc;
 378         u64 rjc;
 379         u64 mgprc;
 380         u64 mgpdc;
 381         u64 mgptc;
 382         u64 tor;
 383         u64 tot;
 384         u64 tpr;
 385         u64 tpt;
 386         u64 ptc64;
 387         u64 ptc127;
 388         u64 ptc255;
 389         u64 ptc511;
 390         u64 ptc1023;
 391         u64 ptc1522;
 392         u64 mptc;
 393         u64 bptc;
 394         u64 tsctc;
 395         u64 tsctfc;
 396         u64 iac;
 397         u64 icrxptc;
 398         u64 icrxatc;
 399         u64 ictxptc;
 400         u64 ictxatc;
 401         u64 ictxqec;
 402         u64 ictxqmtc;
 403         u64 icrxdmtc;
 404         u64 icrxoc;
 405         u64 cbtmpc;
 406         u64 htdpmc;
 407         u64 cbrdpc;
 408         u64 cbrmpc;
 409         u64 rpthc;
 410         u64 hgptc;
 411         u64 htcbdpc;
 412         u64 hgorc;
 413         u64 hgotc;
 414         u64 lenerrs;
 415         u64 scvpc;
 416         u64 hrmpc;
 417         u64 doosync;
 418         u64 o2bgptc;
 419         u64 o2bspc;
 420         u64 b2ospc;
 421         u64 b2ogprc;
 422 };
 423
 424
 425 struct e1000_phy_stats {
 426         u32 idle_errors;
 427         u32 receive_errors;
 428 };
 429
 430 struct e1000_host_mng_dhcp_cookie {
 431         u32 signature;
 432         u8  status;
 433         u8  reserved0;
 434         u16 vlan_id;
 435         u32 reserved1;
 436         u16 reserved2;
 437         u8  reserved3;
 438         u8  checksum;
 439 };
 440
 441 /* Host Interface "Rev 1" */
 442 struct e1000_host_command_header {
 443         u8 command_id;
 444         u8 command_length;
 445         u8 command_options;
 446         u8 checksum;
 447 };
 448
 449 #define E1000_HI_MAX_DATA_LENGTH        252
 450 struct e1000_host_command_info {
 451         struct e1000_host_command_header command_header;
 452         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 453 };
 454
 455 /* Host Interface "Rev 2" */
 456 struct e1000_host_mng_command_header {
 457         u8  command_id;
 458         u8  checksum;
 459         u16 reserved1;
 460         u16 reserved2;
 461         u16 command_length;
 462 };
 463
 464 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 465 struct e1000_host_mng_command_info {
 466         struct e1000_host_mng_command_header command_header;
 467         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 468 };
 469
 470 #include "e1000_mac.h"
 471 #include "e1000_phy.h"
 472 #include "e1000_nvm.h"
 473 #include "e1000_manage.h"
 474 #include "e1000_mbx.h"
 475
 476 struct e1000_mac_operations {
 477         /* Function pointers for the MAC. */
 478         s32  (*init_params)(struct e1000_hw *);
 479         s32  (*id_led_init)(struct e1000_hw *);
 480         s32  (*blink_led)(struct e1000_hw *);
 481         s32  (*check_for_link)(struct e1000_hw *);
 482         bool (*check_mng_mode)(struct e1000_hw *hw);
 483         s32  (*cleanup_led)(struct e1000_hw *);
 484         void (*clear_hw_cntrs)(struct e1000_hw *);
 485         void (*clear_vfta)(struct e1000_hw *);
 486         s32  (*get_bus_info)(struct e1000_hw *);
 487         void (*set_lan_id)(struct e1000_hw *);
 488         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 489         s32  (*led_on)(struct e1000_hw *);
 490         s32  (*led_off)(struct e1000_hw *);
 491         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 492         s32  (*reset_hw)(struct e1000_hw *);
 493         s32  (*init_hw)(struct e1000_hw *);
 494         void (*shutdown_serdes)(struct e1000_hw *);
 495         void (*power_up_serdes)(struct e1000_hw *);
 496         s32  (*setup_link)(struct e1000_hw *);
 497         s32  (*setup_physical_interface)(struct e1000_hw *);
 498         s32  (*setup_led)(struct e1000_hw *);
 499         void (*write_vfta)(struct e1000_hw *, u32, u32);
 500         void (*config_collision_dist)(struct e1000_hw *);
 501         void (*rar_set)(struct e1000_hw *, u8*, u32);
 502         s32  (*read_mac_addr)(struct e1000_hw *);
 503         s32  (*validate_mdi_setting)(struct e1000_hw *);
 504         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 505         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 506                                      struct e1000_host_mng_command_header*);
 507         s32  (*mng_enable_host_if)(struct e1000_hw *);
 508         s32  (*wait_autoneg)(struct e1000_hw *);
 509         s32 (*get_thermal_sensor_data)(struct e1000_hw *);
 510         s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
 511         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 512         void (*release_swfw_sync)(struct e1000_hw *, u16);
 513 };
 514
 515 /*
 516  * When to use various PHY register access functions:
 517  *
 518  *                 Func   Caller
 519  *   Function      Does   Does    When to use
 520  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 521  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 522  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 523  *                                on different pages
 524  *   X_reg_page    A      L,P     for multiple accesses of different regs
 525  *                                on the same page
 526  *
 527  * Where X=[read|write], L=locking, P=sets page, A=register access
 528  *
 529  */
 530 struct e1000_phy_operations {
 531         s32  (*init_params)(struct e1000_hw *);
 532         s32  (*acquire)(struct e1000_hw *);
 533         s32  (*check_polarity)(struct e1000_hw *);
 534         s32  (*check_reset_block)(struct e1000_hw *);
 535         s32  (*commit)(struct e1000_hw *);
 536         s32  (*force_speed_duplex)(struct e1000_hw *);
 537         s32  (*get_cfg_done)(struct e1000_hw *hw);
 538         s32  (*get_cable_length)(struct e1000_hw *);
 539         s32  (*get_info)(struct e1000_hw *);
 540         s32  (*set_page)(struct e1000_hw *, u16);
 541         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 542         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 543         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 544         void (*release)(struct e1000_hw *);
 545         s32  (*reset)(struct e1000_hw *);
 546         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 547         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 548         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 549         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 550         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 551         void (*power_up)(struct e1000_hw *);
 552         void (*power_down)(struct e1000_hw *);
 553         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 554         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 555 };
 556
 557 struct e1000_nvm_operations {
 558         s32  (*init_params)(struct e1000_hw *);
 559         s32  (*acquire)(struct e1000_hw *);
 560         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 561         void (*release)(struct e1000_hw *);
 562         void (*reload)(struct e1000_hw *);
 563         s32  (*update)(struct e1000_hw *);
 564         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 565         s32  (*validate)(struct e1000_hw *);
 566         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 567 };
 568
 569 #define E1000_MAX_SENSORS               3
 570
 571 struct e1000_thermal_diode_data {
 572         u8 location;
 573         u8 temp;
 574         u8 caution_thresh;
 575         u8 max_op_thresh;
 576 };
 577
 578 struct e1000_thermal_sensor_data {
 579         struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
 580 };
 581
 582 struct e1000_mac_info {
 583         struct e1000_mac_operations ops;
 584         u8 addr[ETH_ADDR_LEN];
 585         u8 perm_addr[ETH_ADDR_LEN];
 586
 587         enum e1000_mac_type type;
 588
 589         u32 collision_delta;
 590         u32 ledctl_default;
 591         u32 ledctl_mode1;
 592         u32 ledctl_mode2;
 593         u32 mc_filter_type;
 594         u32 tx_packet_delta;
 595         u32 txcw;
 596
 597         u16 current_ifs_val;
 598         u16 ifs_max_val;
 599         u16 ifs_min_val;
 600         u16 ifs_ratio;
 601         u16 ifs_step_size;
 602         u16 mta_reg_count;
 603         u16 uta_reg_count;
 604
 605         /* Maximum size of the MTA register table in all supported adapters */
 606         #define MAX_MTA_REG 128
 607         u32 mta_shadow[MAX_MTA_REG];
 608         u16 rar_entry_count;
 609
 610         u8  forced_speed_duplex;
 611
 612         bool adaptive_ifs;
 613         bool has_fwsm;
 614         bool arc_subsystem_valid;
 615         bool asf_firmware_present;
 616         bool autoneg;
 617         bool autoneg_failed;
 618         bool get_link_status;
 619         bool in_ifs_mode;
 620         enum e1000_serdes_link_state serdes_link_state;
 621         bool serdes_has_link;
 622         bool tx_pkt_filtering;
 623         struct e1000_thermal_sensor_data thermal_sensor_data;
 624 };
 625
 626 struct e1000_phy_info {
 627         struct e1000_phy_operations ops;
 628         enum e1000_phy_type type;
 629
 630         enum e1000_1000t_rx_status local_rx;
 631         enum e1000_1000t_rx_status remote_rx;
 632         enum e1000_ms_type ms_type;
 633         enum e1000_ms_type original_ms_type;
 634         enum e1000_rev_polarity cable_polarity;
 635         enum e1000_smart_speed smart_speed;
 636
 637         u32 addr;
 638         u32 id;
 639         u32 reset_delay_us; /* in usec */
 640         u32 revision;
 641
 642         enum e1000_media_type media_type;
 643
 644         u16 autoneg_advertised;
 645         u16 autoneg_mask;
 646         u16 cable_length;
 647         u16 max_cable_length;
 648         u16 min_cable_length;
 649
 650         u8 mdix;
 651
 652         bool disable_polarity_correction;
 653         bool is_mdix;
 654         bool polarity_correction;
 655         bool reset_disable;
 656         bool speed_downgraded;
 657         bool autoneg_wait_to_complete;
 658 };
 659
 660 struct e1000_nvm_info {
 661         struct e1000_nvm_operations ops;
 662         enum e1000_nvm_type type;
 663         enum e1000_nvm_override override;
 664
 665         u32 flash_bank_size;
 666         u32 flash_base_addr;
 667
 668         u16 word_size;
 669         u16 delay_usec;
 670         u16 address_bits;
 671         u16 opcode_bits;
 672         u16 page_size;
 673 };
 674
 675 struct e1000_bus_info {
 676         enum e1000_bus_type type;
 677         enum e1000_bus_speed speed;
 678         enum e1000_bus_width width;
 679
 680         u16 func;
 681         u16 pci_cmd_word;
 682 };
 683
 684 struct e1000_fc_info {
 685         u32 high_water;  /* Flow control high-water mark */
 686         u32 low_water;  /* Flow control low-water mark */
 687         u16 pause_time;  /* Flow control pause timer */
 688         u16 refresh_time;  /* Flow control refresh timer */
 689         bool send_xon;  /* Flow control send XON */
 690         bool strict_ieee;  /* Strict IEEE mode */
 691         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 692         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 693 };
 694
 695 struct e1000_mbx_operations {
 696         s32 (*init_params)(struct e1000_hw *hw);
 697         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 698         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 699         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 700         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 701         s32 (*check_for_msg)(struct e1000_hw *, u16);
 702         s32 (*check_for_ack)(struct e1000_hw *, u16);
 703         s32 (*check_for_rst)(struct e1000_hw *, u16);
 704 };
 705
 706 struct e1000_mbx_stats {
 707         u32 msgs_tx;
 708         u32 msgs_rx;
 709
 710         u32 acks;
 711         u32 reqs;
 712         u32 rsts;
 713 };
 714
 715 struct e1000_mbx_info {
 716         struct e1000_mbx_operations ops;
 717         struct e1000_mbx_stats stats;
 718         u32 timeout;
 719         u32 usec_delay;
 720         u16 size;
 721 };
 722
 723 struct e1000_dev_spec_82575 {
 724         bool sgmii_active;
 725         bool global_device_reset;
 726         bool eee_disable;
 727         bool module_plugged;
 728         u32 mtu;
 729 };
 730
 731 struct e1000_dev_spec_vf {
 732         u32 vf_number;
 733         u32 v2p_mailbox;
 734 };
 735
 736 struct e1000_hw {
 737         void *back;
 738
 739         u8 __iomem *hw_addr;
 740         u8 __iomem *flash_address;
 741         unsigned long io_base;
 742
 743         struct e1000_mac_info  mac;
 744         struct e1000_fc_info   fc;
 745         struct e1000_phy_info  phy;
 746         struct e1000_nvm_info  nvm;
 747         struct e1000_bus_info  bus;
 748         struct e1000_mbx_info mbx;
 749         struct e1000_host_mng_dhcp_cookie mng_cookie;
 750
 751         union {
 752                 struct e1000_dev_spec_82575 _82575;
 753                 struct e1000_dev_spec_vf vf;
 754         } dev_spec;
 755
 756         u16 device_id;
 757         u16 subsystem_vendor_id;
 758         u16 subsystem_device_id;
 759         u16 vendor_id;
 760
 761         u8  revision_id;
 762 };
 763
 764 #include "e1000_82575.h"
 765
 766 /* These functions must be implemented by drivers */
 767 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 768 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 769
 770 #endif