1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "e1000_api.h"
30 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
33 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
34 * @hw: pointer to the HW structure
36 * Setups up the function pointers to no-op functions
38 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
40 struct e1000_nvm_info *nvm = &hw->nvm;
41 DEBUGFUNC("e1000_init_nvm_ops_generic");
43 /* Initialize function pointers */
44 nvm->ops.init_params = e1000_null_ops_generic;
45 nvm->ops.acquire = e1000_null_ops_generic;
46 nvm->ops.read = e1000_null_read_nvm;
47 nvm->ops.release = e1000_null_nvm_generic;
48 nvm->ops.reload = e1000_reload_nvm_generic;
49 nvm->ops.update = e1000_null_ops_generic;
50 nvm->ops.valid_led_default = e1000_null_led_default;
51 nvm->ops.validate = e1000_null_ops_generic;
52 nvm->ops.write = e1000_null_write_nvm;
56 * e1000_null_nvm_read - No-op function, return 0
57 * @hw: pointer to the HW structure
59 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
61 DEBUGFUNC("e1000_null_read_nvm");
66 * e1000_null_nvm_generic - No-op function, return void
67 * @hw: pointer to the HW structure
69 void e1000_null_nvm_generic(struct e1000_hw *hw)
71 DEBUGFUNC("e1000_null_nvm_generic");
76 * e1000_null_led_default - No-op function, return 0
77 * @hw: pointer to the HW structure
79 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
81 DEBUGFUNC("e1000_null_led_default");
86 * e1000_null_write_nvm - No-op function, return 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
91 DEBUGFUNC("e1000_null_write_nvm");
96 * e1000_raise_eec_clk - Raise EEPROM clock
97 * @hw: pointer to the HW structure
98 * @eecd: pointer to the EEPROM
100 * Enable/Raise the EEPROM clock bit.
102 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
104 *eecd = *eecd | E1000_EECD_SK;
105 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
106 E1000_WRITE_FLUSH(hw);
107 usec_delay(hw->nvm.delay_usec);
111 * e1000_lower_eec_clk - Lower EEPROM clock
112 * @hw: pointer to the HW structure
113 * @eecd: pointer to the EEPROM
115 * Clear/Lower the EEPROM clock bit.
117 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
119 *eecd = *eecd & ~E1000_EECD_SK;
120 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
121 E1000_WRITE_FLUSH(hw);
122 usec_delay(hw->nvm.delay_usec);
126 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
127 * @hw: pointer to the HW structure
128 * @data: data to send to the EEPROM
129 * @count: number of bits to shift out
131 * We need to shift 'count' bits out to the EEPROM. So, the value in the
132 * "data" parameter will be shifted out to the EEPROM one bit at a time.
133 * In order to do this, "data" must be broken down into bits.
135 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
137 struct e1000_nvm_info *nvm = &hw->nvm;
138 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
141 DEBUGFUNC("e1000_shift_out_eec_bits");
143 mask = 0x01 << (count - 1);
144 if (nvm->type == e1000_nvm_eeprom_spi)
145 eecd |= E1000_EECD_DO;
148 eecd &= ~E1000_EECD_DI;
151 eecd |= E1000_EECD_DI;
153 E1000_WRITE_REG(hw, E1000_EECD, eecd);
154 E1000_WRITE_FLUSH(hw);
156 usec_delay(nvm->delay_usec);
158 e1000_raise_eec_clk(hw, &eecd);
159 e1000_lower_eec_clk(hw, &eecd);
164 eecd &= ~E1000_EECD_DI;
165 E1000_WRITE_REG(hw, E1000_EECD, eecd);
169 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
170 * @hw: pointer to the HW structure
171 * @count: number of bits to shift in
173 * In order to read a register from the EEPROM, we need to shift 'count' bits
174 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
175 * the EEPROM (setting the SK bit), and then reading the value of the data out
176 * "DO" bit. During this "shifting in" process the data in "DI" bit should
179 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
185 DEBUGFUNC("e1000_shift_in_eec_bits");
187 eecd = E1000_READ_REG(hw, E1000_EECD);
189 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
192 for (i = 0; i < count; i++) {
194 e1000_raise_eec_clk(hw, &eecd);
196 eecd = E1000_READ_REG(hw, E1000_EECD);
198 eecd &= ~E1000_EECD_DI;
199 if (eecd & E1000_EECD_DO)
202 e1000_lower_eec_clk(hw, &eecd);
209 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
210 * @hw: pointer to the HW structure
211 * @ee_reg: EEPROM flag for polling
213 * Polls the EEPROM status bit for either read or write completion based
214 * upon the value of 'ee_reg'.
216 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
218 u32 attempts = 100000;
221 DEBUGFUNC("e1000_poll_eerd_eewr_done");
223 for (i = 0; i < attempts; i++) {
224 if (ee_reg == E1000_NVM_POLL_READ)
225 reg = E1000_READ_REG(hw, E1000_EERD);
227 reg = E1000_READ_REG(hw, E1000_EEWR);
229 if (reg & E1000_NVM_RW_REG_DONE)
230 return E1000_SUCCESS;
235 return -E1000_ERR_NVM;
239 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
240 * @hw: pointer to the HW structure
242 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
243 * Return successful if access grant bit set, else clear the request for
244 * EEPROM access and return -E1000_ERR_NVM (-1).
246 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
248 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
249 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
251 DEBUGFUNC("e1000_acquire_nvm_generic");
253 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
254 eecd = E1000_READ_REG(hw, E1000_EECD);
257 if (eecd & E1000_EECD_GNT)
260 eecd = E1000_READ_REG(hw, E1000_EECD);
265 eecd &= ~E1000_EECD_REQ;
266 E1000_WRITE_REG(hw, E1000_EECD, eecd);
267 DEBUGOUT("Could not acquire NVM grant\n");
268 return -E1000_ERR_NVM;
271 return E1000_SUCCESS;
275 * e1000_standby_nvm - Return EEPROM to standby state
276 * @hw: pointer to the HW structure
278 * Return the EEPROM to a standby state.
280 static void e1000_standby_nvm(struct e1000_hw *hw)
282 struct e1000_nvm_info *nvm = &hw->nvm;
283 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
285 DEBUGFUNC("e1000_standby_nvm");
287 if (nvm->type == e1000_nvm_eeprom_spi) {
288 /* Toggle CS to flush commands */
289 eecd |= E1000_EECD_CS;
290 E1000_WRITE_REG(hw, E1000_EECD, eecd);
291 E1000_WRITE_FLUSH(hw);
292 usec_delay(nvm->delay_usec);
293 eecd &= ~E1000_EECD_CS;
294 E1000_WRITE_REG(hw, E1000_EECD, eecd);
295 E1000_WRITE_FLUSH(hw);
296 usec_delay(nvm->delay_usec);
301 * e1000_stop_nvm - Terminate EEPROM command
302 * @hw: pointer to the HW structure
304 * Terminates the current command by inverting the EEPROM's chip select pin.
306 static void e1000_stop_nvm(struct e1000_hw *hw)
310 DEBUGFUNC("e1000_stop_nvm");
312 eecd = E1000_READ_REG(hw, E1000_EECD);
313 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
315 eecd |= E1000_EECD_CS;
316 e1000_lower_eec_clk(hw, &eecd);
321 * e1000_release_nvm_generic - Release exclusive access to EEPROM
322 * @hw: pointer to the HW structure
324 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
326 void e1000_release_nvm_generic(struct e1000_hw *hw)
330 DEBUGFUNC("e1000_release_nvm_generic");
334 eecd = E1000_READ_REG(hw, E1000_EECD);
335 eecd &= ~E1000_EECD_REQ;
336 E1000_WRITE_REG(hw, E1000_EECD, eecd);
340 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
341 * @hw: pointer to the HW structure
343 * Setups the EEPROM for reading and writing.
345 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
347 struct e1000_nvm_info *nvm = &hw->nvm;
348 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
351 DEBUGFUNC("e1000_ready_nvm_eeprom");
353 if (nvm->type == e1000_nvm_eeprom_spi) {
354 u16 timeout = NVM_MAX_RETRY_SPI;
356 /* Clear SK and CS */
357 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
358 E1000_WRITE_REG(hw, E1000_EECD, eecd);
359 E1000_WRITE_FLUSH(hw);
363 * Read "Status Register" repeatedly until the LSB is cleared.
364 * The EEPROM will signal that the command has been completed
365 * by clearing bit 0 of the internal status register. If it's
366 * not cleared within 'timeout', then error out.
369 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
370 hw->nvm.opcode_bits);
371 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
372 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
376 e1000_standby_nvm(hw);
381 DEBUGOUT("SPI NVM Status error\n");
382 return -E1000_ERR_NVM;
386 return E1000_SUCCESS;
390 * e1000_read_nvm_spi - Read EEPROM's using SPI
391 * @hw: pointer to the HW structure
392 * @offset: offset of word in the EEPROM to read
393 * @words: number of words to read
394 * @data: word read from the EEPROM
396 * Reads a 16 bit word from the EEPROM.
398 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
400 struct e1000_nvm_info *nvm = &hw->nvm;
404 u8 read_opcode = NVM_READ_OPCODE_SPI;
406 DEBUGFUNC("e1000_read_nvm_spi");
409 * A check for invalid values: offset too large, too many words,
410 * and not enough words.
412 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
414 DEBUGOUT("nvm parameter(s) out of bounds\n");
415 return -E1000_ERR_NVM;
418 ret_val = nvm->ops.acquire(hw);
422 ret_val = e1000_ready_nvm_eeprom(hw);
426 e1000_standby_nvm(hw);
428 if ((nvm->address_bits == 8) && (offset >= 128))
429 read_opcode |= NVM_A8_OPCODE_SPI;
431 /* Send the READ command (opcode + addr) */
432 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
433 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
436 * Read the data. SPI NVMs increment the address with each byte
437 * read and will roll over if reading beyond the end. This allows
438 * us to read the whole NVM from any offset
440 for (i = 0; i < words; i++) {
441 word_in = e1000_shift_in_eec_bits(hw, 16);
442 data[i] = (word_in >> 8) | (word_in << 8);
446 nvm->ops.release(hw);
452 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
453 * @hw: pointer to the HW structure
454 * @offset: offset of word in the EEPROM to read
455 * @words: number of words to read
456 * @data: word read from the EEPROM
458 * Reads a 16 bit word from the EEPROM using the EERD register.
460 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
462 struct e1000_nvm_info *nvm = &hw->nvm;
464 s32 ret_val = E1000_SUCCESS;
466 DEBUGFUNC("e1000_read_nvm_eerd");
469 * A check for invalid values: offset too large, too many words,
470 * too many words for the offset, and not enough words.
472 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
474 DEBUGOUT("nvm parameter(s) out of bounds\n");
475 return -E1000_ERR_NVM;
478 for (i = 0; i < words; i++) {
479 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
480 E1000_NVM_RW_REG_START;
482 E1000_WRITE_REG(hw, E1000_EERD, eerd);
483 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
487 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
488 E1000_NVM_RW_REG_DATA);
495 * e1000_write_nvm_spi - Write to EEPROM using SPI
496 * @hw: pointer to the HW structure
497 * @offset: offset within the EEPROM to be written to
498 * @words: number of words to write
499 * @data: 16 bit word(s) to be written to the EEPROM
501 * Writes data to EEPROM at offset using SPI interface.
503 * If e1000_update_nvm_checksum is not called after this function , the
504 * EEPROM will most likely contain an invalid checksum.
506 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
508 struct e1000_nvm_info *nvm = &hw->nvm;
512 DEBUGFUNC("e1000_write_nvm_spi");
515 * A check for invalid values: offset too large, too many words,
516 * and not enough words.
518 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
520 DEBUGOUT("nvm parameter(s) out of bounds\n");
521 return -E1000_ERR_NVM;
524 ret_val = nvm->ops.acquire(hw);
528 while (widx < words) {
529 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
531 ret_val = e1000_ready_nvm_eeprom(hw);
535 e1000_standby_nvm(hw);
537 /* Send the WRITE ENABLE command (8 bit opcode) */
538 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
541 e1000_standby_nvm(hw);
544 * Some SPI eeproms use the 8th address bit embedded in the
547 if ((nvm->address_bits == 8) && (offset >= 128))
548 write_opcode |= NVM_A8_OPCODE_SPI;
550 /* Send the Write command (8-bit opcode + addr) */
551 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
552 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
555 /* Loop to allow for up to whole page write of eeprom */
556 while (widx < words) {
557 u16 word_out = data[widx];
558 word_out = (word_out >> 8) | (word_out << 8);
559 e1000_shift_out_eec_bits(hw, word_out, 16);
562 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
563 e1000_standby_nvm(hw);
571 nvm->ops.release(hw);
577 * e1000_read_pba_string_generic - Read device part number
578 * @hw: pointer to the HW structure
579 * @pba_num: pointer to device part number
580 * @pba_num_size: size of part number buffer
582 * Reads the product board assembly (PBA) number from the EEPROM and stores
583 * the value in pba_num.
585 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
594 DEBUGFUNC("e1000_read_pba_string_generic");
596 if (pba_num == NULL) {
597 DEBUGOUT("PBA string buffer was null\n");
598 return -E1000_ERR_INVALID_ARGUMENT;
601 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
603 DEBUGOUT("NVM Read Error\n");
607 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
609 DEBUGOUT("NVM Read Error\n");
614 * if nvm_data is not ptr guard the PBA must be in legacy format which
615 * means pba_ptr is actually our second data word for the PBA number
616 * and we can decode it into an ascii string
618 if (nvm_data != NVM_PBA_PTR_GUARD) {
619 DEBUGOUT("NVM PBA number is not stored as string\n");
621 /* we will need 11 characters to store the PBA */
622 if (pba_num_size < 11) {
623 DEBUGOUT("PBA string buffer too small\n");
624 return E1000_ERR_NO_SPACE;
627 /* extract hex string from data and pba_ptr */
628 pba_num[0] = (nvm_data >> 12) & 0xF;
629 pba_num[1] = (nvm_data >> 8) & 0xF;
630 pba_num[2] = (nvm_data >> 4) & 0xF;
631 pba_num[3] = nvm_data & 0xF;
632 pba_num[4] = (pba_ptr >> 12) & 0xF;
633 pba_num[5] = (pba_ptr >> 8) & 0xF;
636 pba_num[8] = (pba_ptr >> 4) & 0xF;
637 pba_num[9] = pba_ptr & 0xF;
639 /* put a null character on the end of our string */
642 /* switch all the data but the '-' to hex char */
643 for (offset = 0; offset < 10; offset++) {
644 if (pba_num[offset] < 0xA)
645 pba_num[offset] += '0';
646 else if (pba_num[offset] < 0x10)
647 pba_num[offset] += 'A' - 0xA;
650 return E1000_SUCCESS;
653 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
655 DEBUGOUT("NVM Read Error\n");
659 if (length == 0xFFFF || length == 0) {
660 DEBUGOUT("NVM PBA number section invalid length\n");
661 return -E1000_ERR_NVM_PBA_SECTION;
663 /* check if pba_num buffer is big enough */
664 if (pba_num_size < (((u32)length * 2) - 1)) {
665 DEBUGOUT("PBA string buffer too small\n");
666 return -E1000_ERR_NO_SPACE;
669 /* trim pba length from start of string */
673 for (offset = 0; offset < length; offset++) {
674 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
676 DEBUGOUT("NVM Read Error\n");
679 pba_num[offset * 2] = (u8)(nvm_data >> 8);
680 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
682 pba_num[offset * 2] = '\0';
684 return E1000_SUCCESS;
688 * e1000_read_pba_length_generic - Read device part number length
689 * @hw: pointer to the HW structure
690 * @pba_num_size: size of part number buffer
692 * Reads the product board assembly (PBA) number length from the EEPROM and
693 * stores the value in pba_num_size.
695 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
702 DEBUGFUNC("e1000_read_pba_length_generic");
704 if (pba_num_size == NULL) {
705 DEBUGOUT("PBA buffer size was null\n");
706 return -E1000_ERR_INVALID_ARGUMENT;
709 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
711 DEBUGOUT("NVM Read Error\n");
715 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
717 DEBUGOUT("NVM Read Error\n");
721 /* if data is not ptr guard the PBA must be in legacy format */
722 if (nvm_data != NVM_PBA_PTR_GUARD) {
724 return E1000_SUCCESS;
727 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
729 DEBUGOUT("NVM Read Error\n");
733 if (length == 0xFFFF || length == 0) {
734 DEBUGOUT("NVM PBA number section invalid length\n");
735 return -E1000_ERR_NVM_PBA_SECTION;
739 * Convert from length in u16 values to u8 chars, add 1 for NULL,
740 * and subtract 2 because length field is included in length.
742 *pba_num_size = ((u32)length * 2) - 1;
744 return E1000_SUCCESS;
748 * e1000_read_mac_addr_generic - Read device MAC address
749 * @hw: pointer to the HW structure
751 * Reads the device MAC address from the EEPROM and stores the value.
752 * Since devices with two ports use the same EEPROM, we increment the
753 * last bit in the MAC address for the second port.
755 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
761 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
762 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
764 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
765 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
767 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
768 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
770 for (i = 0; i < ETH_ADDR_LEN; i++)
771 hw->mac.addr[i] = hw->mac.perm_addr[i];
773 return E1000_SUCCESS;
777 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
778 * @hw: pointer to the HW structure
780 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
781 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
783 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
789 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
791 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
792 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
794 DEBUGOUT("NVM Read Error\n");
797 checksum += nvm_data;
800 if (checksum != (u16) NVM_SUM) {
801 DEBUGOUT("NVM Checksum Invalid\n");
802 return -E1000_ERR_NVM;
805 return E1000_SUCCESS;
809 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
810 * @hw: pointer to the HW structure
812 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
813 * up to the checksum. Then calculates the EEPROM checksum and writes the
814 * value to the EEPROM.
816 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
822 DEBUGFUNC("e1000_update_nvm_checksum");
824 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
825 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
827 DEBUGOUT("NVM Read Error while updating checksum.\n");
830 checksum += nvm_data;
832 checksum = (u16) NVM_SUM - checksum;
833 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
835 DEBUGOUT("NVM Write Error while updating checksum.\n");
841 * e1000_reload_nvm_generic - Reloads EEPROM
842 * @hw: pointer to the HW structure
844 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
845 * extended control register.
847 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
851 DEBUGFUNC("e1000_reload_nvm_generic");
854 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
855 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
856 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
857 E1000_WRITE_FLUSH(hw);