1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
16 #include <netinet/in.h>
18 #include <rte_byteorder.h>
20 #include <rte_debug.h>
21 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memcpy.h>
24 #include <rte_memzone.h>
25 #include <rte_launch.h>
27 #include <rte_per_lcore.h>
28 #include <rte_lcore.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_common.h>
31 #include <rte_mempool.h>
32 #include <rte_malloc.h>
34 #include <rte_errno.h>
35 #include <rte_spinlock.h>
36 #include <rte_string_fns.h>
37 #include <rte_kvargs.h>
38 #include <rte_class.h>
39 #include <rte_ether.h>
40 #include <rte_telemetry.h>
42 #include "rte_ethdev_trace.h"
43 #include "rte_ethdev.h"
44 #include "rte_ethdev_driver.h"
45 #include "ethdev_profile.h"
46 #include "ethdev_private.h"
48 static const char *MZ_RTE_ETH_DEV_DATA = "rte_eth_dev_data";
49 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS];
51 /* spinlock for eth device callbacks */
52 static rte_spinlock_t rte_eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER;
54 /* spinlock for add/remove rx callbacks */
55 static rte_spinlock_t rte_eth_rx_cb_lock = RTE_SPINLOCK_INITIALIZER;
57 /* spinlock for add/remove tx callbacks */
58 static rte_spinlock_t rte_eth_tx_cb_lock = RTE_SPINLOCK_INITIALIZER;
60 /* spinlock for shared data allocation */
61 static rte_spinlock_t rte_eth_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
63 /* store statistics names and its offset in stats structure */
64 struct rte_eth_xstats_name_off {
65 char name[RTE_ETH_XSTATS_NAME_SIZE];
69 /* Shared memory between primary and secondary processes. */
71 uint64_t next_owner_id;
72 rte_spinlock_t ownership_lock;
73 struct rte_eth_dev_data data[RTE_MAX_ETHPORTS];
74 } *rte_eth_dev_shared_data;
76 static const struct rte_eth_xstats_name_off rte_stats_strings[] = {
77 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)},
78 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)},
79 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)},
80 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)},
81 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)},
82 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)},
83 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)},
84 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats,
88 #define RTE_NB_STATS RTE_DIM(rte_stats_strings)
90 static const struct rte_eth_xstats_name_off rte_rxq_stats_strings[] = {
91 {"packets", offsetof(struct rte_eth_stats, q_ipackets)},
92 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)},
93 {"errors", offsetof(struct rte_eth_stats, q_errors)},
96 #define RTE_NB_RXQ_STATS RTE_DIM(rte_rxq_stats_strings)
98 static const struct rte_eth_xstats_name_off rte_txq_stats_strings[] = {
99 {"packets", offsetof(struct rte_eth_stats, q_opackets)},
100 {"bytes", offsetof(struct rte_eth_stats, q_obytes)},
102 #define RTE_NB_TXQ_STATS RTE_DIM(rte_txq_stats_strings)
104 #define RTE_RX_OFFLOAD_BIT2STR(_name) \
105 { DEV_RX_OFFLOAD_##_name, #_name }
107 #define RTE_ETH_RX_OFFLOAD_BIT2STR(_name) \
108 { RTE_ETH_RX_OFFLOAD_##_name, #_name }
110 static const struct {
113 } rte_rx_offload_names[] = {
114 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP),
115 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM),
116 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM),
117 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM),
118 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO),
119 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP),
120 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
121 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP),
122 RTE_RX_OFFLOAD_BIT2STR(HEADER_SPLIT),
123 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER),
124 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND),
125 RTE_RX_OFFLOAD_BIT2STR(JUMBO_FRAME),
126 RTE_RX_OFFLOAD_BIT2STR(SCATTER),
127 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP),
128 RTE_RX_OFFLOAD_BIT2STR(SECURITY),
129 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC),
130 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM),
131 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
132 RTE_RX_OFFLOAD_BIT2STR(RSS_HASH),
133 RTE_ETH_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT),
136 #undef RTE_RX_OFFLOAD_BIT2STR
137 #undef RTE_ETH_RX_OFFLOAD_BIT2STR
139 #define RTE_TX_OFFLOAD_BIT2STR(_name) \
140 { DEV_TX_OFFLOAD_##_name, #_name }
142 static const struct {
145 } rte_tx_offload_names[] = {
146 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT),
147 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM),
148 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM),
149 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM),
150 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM),
151 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO),
152 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO),
153 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
154 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT),
155 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO),
156 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO),
157 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO),
158 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO),
159 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT),
160 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE),
161 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS),
162 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE),
163 RTE_TX_OFFLOAD_BIT2STR(SECURITY),
164 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO),
165 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO),
166 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
167 RTE_TX_OFFLOAD_BIT2STR(SEND_ON_TIMESTAMP),
170 #undef RTE_TX_OFFLOAD_BIT2STR
173 * The user application callback description.
175 * It contains callback address to be registered by user application,
176 * the pointer to the parameters for callback, and the event type.
178 struct rte_eth_dev_callback {
179 TAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */
180 rte_eth_dev_cb_fn cb_fn; /**< Callback address */
181 void *cb_arg; /**< Parameter for callback */
182 void *ret_param; /**< Return parameter */
183 enum rte_eth_event_type event; /**< Interrupt event type */
184 uint32_t active; /**< Callback is executing */
193 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str)
196 struct rte_devargs devargs = {.args = NULL};
197 const char *bus_param_key;
198 char *bus_str = NULL;
199 char *cls_str = NULL;
202 memset(iter, 0, sizeof(*iter));
205 * The devargs string may use various syntaxes:
206 * - 0000:08:00.0,representor=[1-3]
207 * - pci:0000:06:00.0,representor=[0,5]
208 * - class=eth,mac=00:11:22:33:44:55
209 * A new syntax is in development (not yet supported):
210 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z
214 * Handle pure class filter (i.e. without any bus-level argument),
215 * from future new syntax.
216 * rte_devargs_parse() is not yet supporting the new syntax,
217 * that's why this simple case is temporarily parsed here.
219 #define iter_anybus_str "class=eth,"
220 if (strncmp(devargs_str, iter_anybus_str,
221 strlen(iter_anybus_str)) == 0) {
222 iter->cls_str = devargs_str + strlen(iter_anybus_str);
226 /* Split bus, device and parameters. */
227 ret = rte_devargs_parse(&devargs, devargs_str);
232 * Assume parameters of old syntax can match only at ethdev level.
233 * Extra parameters will be ignored, thanks to "+" prefix.
235 str_size = strlen(devargs.args) + 2;
236 cls_str = malloc(str_size);
237 if (cls_str == NULL) {
241 ret = snprintf(cls_str, str_size, "+%s", devargs.args);
242 if (ret != str_size - 1) {
246 iter->cls_str = cls_str;
247 free(devargs.args); /* allocated by rte_devargs_parse() */
250 iter->bus = devargs.bus;
251 if (iter->bus->dev_iterate == NULL) {
256 /* Convert bus args to new syntax for use with new API dev_iterate. */
257 if (strcmp(iter->bus->name, "vdev") == 0) {
258 bus_param_key = "name";
259 } else if (strcmp(iter->bus->name, "pci") == 0) {
260 bus_param_key = "addr";
265 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2;
266 bus_str = malloc(str_size);
267 if (bus_str == NULL) {
271 ret = snprintf(bus_str, str_size, "%s=%s",
272 bus_param_key, devargs.name);
273 if (ret != str_size - 1) {
277 iter->bus_str = bus_str;
280 iter->cls = rte_class_find_by_name("eth");
285 RTE_ETHDEV_LOG(ERR, "Bus %s does not support iterating.\n",
294 rte_eth_iterator_next(struct rte_dev_iterator *iter)
296 if (iter->cls == NULL) /* invalid ethdev iterator */
297 return RTE_MAX_ETHPORTS;
299 do { /* loop to try all matching rte_device */
300 /* If not pure ethdev filter and */
301 if (iter->bus != NULL &&
302 /* not in middle of rte_eth_dev iteration, */
303 iter->class_device == NULL) {
304 /* get next rte_device to try. */
305 iter->device = iter->bus->dev_iterate(
306 iter->device, iter->bus_str, iter);
307 if (iter->device == NULL)
308 break; /* no more rte_device candidate */
310 /* A device is matching bus part, need to check ethdev part. */
311 iter->class_device = iter->cls->dev_iterate(
312 iter->class_device, iter->cls_str, iter);
313 if (iter->class_device != NULL)
314 return eth_dev_to_id(iter->class_device); /* match */
315 } while (iter->bus != NULL); /* need to try next rte_device */
317 /* No more ethdev port to iterate. */
318 rte_eth_iterator_cleanup(iter);
319 return RTE_MAX_ETHPORTS;
323 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter)
325 if (iter->bus_str == NULL)
326 return; /* nothing to free in pure class filter */
327 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */
328 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */
329 memset(iter, 0, sizeof(*iter));
333 rte_eth_find_next(uint16_t port_id)
335 while (port_id < RTE_MAX_ETHPORTS &&
336 rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)
339 if (port_id >= RTE_MAX_ETHPORTS)
340 return RTE_MAX_ETHPORTS;
346 * Macro to iterate over all valid ports for internal usage.
347 * Note: RTE_ETH_FOREACH_DEV is different because filtering owned ports.
349 #define RTE_ETH_FOREACH_VALID_DEV(port_id) \
350 for (port_id = rte_eth_find_next(0); \
351 port_id < RTE_MAX_ETHPORTS; \
352 port_id = rte_eth_find_next(port_id + 1))
355 rte_eth_find_next_of(uint16_t port_id, const struct rte_device *parent)
357 port_id = rte_eth_find_next(port_id);
358 while (port_id < RTE_MAX_ETHPORTS &&
359 rte_eth_devices[port_id].device != parent)
360 port_id = rte_eth_find_next(port_id + 1);
366 rte_eth_find_next_sibling(uint16_t port_id, uint16_t ref_port_id)
368 RTE_ETH_VALID_PORTID_OR_ERR_RET(ref_port_id, RTE_MAX_ETHPORTS);
369 return rte_eth_find_next_of(port_id,
370 rte_eth_devices[ref_port_id].device);
374 rte_eth_dev_shared_data_prepare(void)
376 const unsigned flags = 0;
377 const struct rte_memzone *mz;
379 rte_spinlock_lock(&rte_eth_shared_data_lock);
381 if (rte_eth_dev_shared_data == NULL) {
382 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
383 /* Allocate port data and ownership shared memory. */
384 mz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA,
385 sizeof(*rte_eth_dev_shared_data),
386 rte_socket_id(), flags);
388 mz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA);
390 rte_panic("Cannot allocate ethdev shared data\n");
392 rte_eth_dev_shared_data = mz->addr;
393 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
394 rte_eth_dev_shared_data->next_owner_id =
395 RTE_ETH_DEV_NO_OWNER + 1;
396 rte_spinlock_init(&rte_eth_dev_shared_data->ownership_lock);
397 memset(rte_eth_dev_shared_data->data, 0,
398 sizeof(rte_eth_dev_shared_data->data));
402 rte_spinlock_unlock(&rte_eth_shared_data_lock);
406 is_allocated(const struct rte_eth_dev *ethdev)
408 return ethdev->data->name[0] != '\0';
411 static struct rte_eth_dev *
412 _rte_eth_dev_allocated(const char *name)
416 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
417 if (rte_eth_devices[i].data != NULL &&
418 strcmp(rte_eth_devices[i].data->name, name) == 0)
419 return &rte_eth_devices[i];
425 rte_eth_dev_allocated(const char *name)
427 struct rte_eth_dev *ethdev;
429 rte_eth_dev_shared_data_prepare();
431 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
433 ethdev = _rte_eth_dev_allocated(name);
435 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
441 rte_eth_dev_find_free_port(void)
445 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
446 /* Using shared name field to find a free port. */
447 if (rte_eth_dev_shared_data->data[i].name[0] == '\0') {
448 RTE_ASSERT(rte_eth_devices[i].state ==
453 return RTE_MAX_ETHPORTS;
456 static struct rte_eth_dev *
457 eth_dev_get(uint16_t port_id)
459 struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];
461 eth_dev->data = &rte_eth_dev_shared_data->data[port_id];
467 rte_eth_dev_allocate(const char *name)
470 struct rte_eth_dev *eth_dev = NULL;
473 name_len = strnlen(name, RTE_ETH_NAME_MAX_LEN);
475 RTE_ETHDEV_LOG(ERR, "Zero length Ethernet device name\n");
479 if (name_len >= RTE_ETH_NAME_MAX_LEN) {
480 RTE_ETHDEV_LOG(ERR, "Ethernet device name is too long\n");
484 rte_eth_dev_shared_data_prepare();
486 /* Synchronize port creation between primary and secondary threads. */
487 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
489 if (_rte_eth_dev_allocated(name) != NULL) {
491 "Ethernet device with name %s already allocated\n",
496 port_id = rte_eth_dev_find_free_port();
497 if (port_id == RTE_MAX_ETHPORTS) {
499 "Reached maximum number of Ethernet ports\n");
503 eth_dev = eth_dev_get(port_id);
504 strlcpy(eth_dev->data->name, name, sizeof(eth_dev->data->name));
505 eth_dev->data->port_id = port_id;
506 eth_dev->data->mtu = RTE_ETHER_MTU;
507 pthread_mutex_init(ð_dev->data->flow_ops_mutex, NULL);
510 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
516 * Attach to a port already registered by the primary process, which
517 * makes sure that the same device would have the same port id both
518 * in the primary and secondary process.
521 rte_eth_dev_attach_secondary(const char *name)
524 struct rte_eth_dev *eth_dev = NULL;
526 rte_eth_dev_shared_data_prepare();
528 /* Synchronize port attachment to primary port creation and release. */
529 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
531 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
532 if (strcmp(rte_eth_dev_shared_data->data[i].name, name) == 0)
535 if (i == RTE_MAX_ETHPORTS) {
537 "Device %s is not driven by the primary process\n",
540 eth_dev = eth_dev_get(i);
541 RTE_ASSERT(eth_dev->data->port_id == i);
544 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
549 rte_eth_dev_release_port(struct rte_eth_dev *eth_dev)
554 rte_eth_dev_shared_data_prepare();
556 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
557 rte_eth_dev_callback_process(eth_dev,
558 RTE_ETH_EVENT_DESTROY, NULL);
560 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
562 eth_dev->state = RTE_ETH_DEV_UNUSED;
563 eth_dev->device = NULL;
564 eth_dev->process_private = NULL;
565 eth_dev->intr_handle = NULL;
566 eth_dev->rx_pkt_burst = NULL;
567 eth_dev->tx_pkt_burst = NULL;
568 eth_dev->tx_pkt_prepare = NULL;
569 eth_dev->rx_queue_count = NULL;
570 eth_dev->rx_descriptor_done = NULL;
571 eth_dev->rx_descriptor_status = NULL;
572 eth_dev->tx_descriptor_status = NULL;
573 eth_dev->dev_ops = NULL;
575 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
576 rte_free(eth_dev->data->rx_queues);
577 rte_free(eth_dev->data->tx_queues);
578 rte_free(eth_dev->data->mac_addrs);
579 rte_free(eth_dev->data->hash_mac_addrs);
580 rte_free(eth_dev->data->dev_private);
581 pthread_mutex_destroy(ð_dev->data->flow_ops_mutex);
582 memset(eth_dev->data, 0, sizeof(struct rte_eth_dev_data));
585 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
591 rte_eth_dev_is_valid_port(uint16_t port_id)
593 if (port_id >= RTE_MAX_ETHPORTS ||
594 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED))
601 rte_eth_is_valid_owner_id(uint64_t owner_id)
603 if (owner_id == RTE_ETH_DEV_NO_OWNER ||
604 rte_eth_dev_shared_data->next_owner_id <= owner_id)
610 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id)
612 port_id = rte_eth_find_next(port_id);
613 while (port_id < RTE_MAX_ETHPORTS &&
614 rte_eth_devices[port_id].data->owner.id != owner_id)
615 port_id = rte_eth_find_next(port_id + 1);
621 rte_eth_dev_owner_new(uint64_t *owner_id)
623 rte_eth_dev_shared_data_prepare();
625 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
627 *owner_id = rte_eth_dev_shared_data->next_owner_id++;
629 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
634 _rte_eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id,
635 const struct rte_eth_dev_owner *new_owner)
637 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
638 struct rte_eth_dev_owner *port_owner;
640 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) {
641 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
646 if (!rte_eth_is_valid_owner_id(new_owner->id) &&
647 !rte_eth_is_valid_owner_id(old_owner_id)) {
649 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64"\n",
650 old_owner_id, new_owner->id);
654 port_owner = &rte_eth_devices[port_id].data->owner;
655 if (port_owner->id != old_owner_id) {
657 "Cannot set owner to port %u already owned by %s_%016"PRIX64"\n",
658 port_id, port_owner->name, port_owner->id);
662 /* can not truncate (same structure) */
663 strlcpy(port_owner->name, new_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN);
665 port_owner->id = new_owner->id;
667 RTE_ETHDEV_LOG(DEBUG, "Port %u owner is %s_%016"PRIx64"\n",
668 port_id, new_owner->name, new_owner->id);
674 rte_eth_dev_owner_set(const uint16_t port_id,
675 const struct rte_eth_dev_owner *owner)
679 rte_eth_dev_shared_data_prepare();
681 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
683 ret = _rte_eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner);
685 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
690 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id)
692 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner)
693 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""};
696 rte_eth_dev_shared_data_prepare();
698 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
700 ret = _rte_eth_dev_owner_set(port_id, owner_id, &new_owner);
702 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
707 rte_eth_dev_owner_delete(const uint64_t owner_id)
712 rte_eth_dev_shared_data_prepare();
714 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
716 if (rte_eth_is_valid_owner_id(owner_id)) {
717 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)
718 if (rte_eth_devices[port_id].data->owner.id == owner_id)
719 memset(&rte_eth_devices[port_id].data->owner, 0,
720 sizeof(struct rte_eth_dev_owner));
721 RTE_ETHDEV_LOG(NOTICE,
722 "All port owners owned by %016"PRIx64" identifier have removed\n",
726 "Invalid owner id=%016"PRIx64"\n",
731 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
737 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner)
740 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
742 rte_eth_dev_shared_data_prepare();
744 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
746 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) {
747 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
751 rte_memcpy(owner, ðdev->data->owner, sizeof(*owner));
754 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
759 rte_eth_dev_socket_id(uint16_t port_id)
761 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
762 return rte_eth_devices[port_id].data->numa_node;
766 rte_eth_dev_get_sec_ctx(uint16_t port_id)
768 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
769 return rte_eth_devices[port_id].security_ctx;
773 rte_eth_dev_count_avail(void)
780 RTE_ETH_FOREACH_DEV(p)
787 rte_eth_dev_count_total(void)
789 uint16_t port, count = 0;
791 RTE_ETH_FOREACH_VALID_DEV(port)
798 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name)
802 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
805 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
809 /* shouldn't check 'rte_eth_devices[i].data',
810 * because it might be overwritten by VDEV PMD */
811 tmp = rte_eth_dev_shared_data->data[port_id].name;
817 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id)
822 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
826 RTE_ETH_FOREACH_VALID_DEV(pid)
827 if (!strcmp(name, rte_eth_dev_shared_data->data[pid].name)) {
836 eth_err(uint16_t port_id, int ret)
840 if (rte_eth_dev_is_removed(port_id))
846 rte_eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
848 uint16_t old_nb_queues = dev->data->nb_rx_queues;
852 if (dev->data->rx_queues == NULL && nb_queues != 0) { /* first time configuration */
853 dev->data->rx_queues = rte_zmalloc("ethdev->rx_queues",
854 sizeof(dev->data->rx_queues[0]) * nb_queues,
855 RTE_CACHE_LINE_SIZE);
856 if (dev->data->rx_queues == NULL) {
857 dev->data->nb_rx_queues = 0;
860 } else if (dev->data->rx_queues != NULL && nb_queues != 0) { /* re-configure */
861 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
863 rxq = dev->data->rx_queues;
865 for (i = nb_queues; i < old_nb_queues; i++)
866 (*dev->dev_ops->rx_queue_release)(rxq[i]);
867 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
868 RTE_CACHE_LINE_SIZE);
871 if (nb_queues > old_nb_queues) {
872 uint16_t new_qs = nb_queues - old_nb_queues;
874 memset(rxq + old_nb_queues, 0,
875 sizeof(rxq[0]) * new_qs);
878 dev->data->rx_queues = rxq;
880 } else if (dev->data->rx_queues != NULL && nb_queues == 0) {
881 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
883 rxq = dev->data->rx_queues;
885 for (i = nb_queues; i < old_nb_queues; i++)
886 (*dev->dev_ops->rx_queue_release)(rxq[i]);
888 rte_free(dev->data->rx_queues);
889 dev->data->rx_queues = NULL;
891 dev->data->nb_rx_queues = nb_queues;
896 eth_dev_validate_rx_queue(const struct rte_eth_dev *dev, uint16_t rx_queue_id)
900 if (rx_queue_id >= dev->data->nb_rx_queues) {
901 port_id = dev->data->port_id;
903 "Invalid Rx queue_id=%u of device with port_id=%u\n",
904 rx_queue_id, port_id);
908 if (dev->data->rx_queues[rx_queue_id] == NULL) {
909 port_id = dev->data->port_id;
911 "Queue %u of device with port_id=%u has not been setup\n",
912 rx_queue_id, port_id);
920 eth_dev_validate_tx_queue(const struct rte_eth_dev *dev, uint16_t tx_queue_id)
924 if (tx_queue_id >= dev->data->nb_tx_queues) {
925 port_id = dev->data->port_id;
927 "Invalid Tx queue_id=%u of device with port_id=%u\n",
928 tx_queue_id, port_id);
932 if (dev->data->tx_queues[tx_queue_id] == NULL) {
933 port_id = dev->data->port_id;
935 "Queue %u of device with port_id=%u has not been setup\n",
936 tx_queue_id, port_id);
944 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id)
946 struct rte_eth_dev *dev;
949 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
951 dev = &rte_eth_devices[port_id];
952 if (!dev->data->dev_started) {
954 "Port %u must be started before start any queue\n",
959 ret = eth_dev_validate_rx_queue(dev, rx_queue_id);
963 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP);
965 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
967 "Can't start Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
968 rx_queue_id, port_id);
972 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
974 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
975 rx_queue_id, port_id);
979 return eth_err(port_id, dev->dev_ops->rx_queue_start(dev,
985 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id)
987 struct rte_eth_dev *dev;
990 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
992 dev = &rte_eth_devices[port_id];
994 ret = eth_dev_validate_rx_queue(dev, rx_queue_id);
998 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP);
1000 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
1001 RTE_ETHDEV_LOG(INFO,
1002 "Can't stop Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1003 rx_queue_id, port_id);
1007 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
1008 RTE_ETHDEV_LOG(INFO,
1009 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
1010 rx_queue_id, port_id);
1014 return eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id));
1019 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id)
1021 struct rte_eth_dev *dev;
1024 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1026 dev = &rte_eth_devices[port_id];
1027 if (!dev->data->dev_started) {
1029 "Port %u must be started before start any queue\n",
1034 ret = eth_dev_validate_tx_queue(dev, tx_queue_id);
1038 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP);
1040 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
1041 RTE_ETHDEV_LOG(INFO,
1042 "Can't start Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1043 tx_queue_id, port_id);
1047 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
1048 RTE_ETHDEV_LOG(INFO,
1049 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
1050 tx_queue_id, port_id);
1054 return eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id));
1058 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id)
1060 struct rte_eth_dev *dev;
1063 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1065 dev = &rte_eth_devices[port_id];
1067 ret = eth_dev_validate_tx_queue(dev, tx_queue_id);
1071 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP);
1073 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
1074 RTE_ETHDEV_LOG(INFO,
1075 "Can't stop Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1076 tx_queue_id, port_id);
1080 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
1081 RTE_ETHDEV_LOG(INFO,
1082 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
1083 tx_queue_id, port_id);
1087 return eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id));
1092 rte_eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
1094 uint16_t old_nb_queues = dev->data->nb_tx_queues;
1098 if (dev->data->tx_queues == NULL && nb_queues != 0) { /* first time configuration */
1099 dev->data->tx_queues = rte_zmalloc("ethdev->tx_queues",
1100 sizeof(dev->data->tx_queues[0]) * nb_queues,
1101 RTE_CACHE_LINE_SIZE);
1102 if (dev->data->tx_queues == NULL) {
1103 dev->data->nb_tx_queues = 0;
1106 } else if (dev->data->tx_queues != NULL && nb_queues != 0) { /* re-configure */
1107 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1109 txq = dev->data->tx_queues;
1111 for (i = nb_queues; i < old_nb_queues; i++)
1112 (*dev->dev_ops->tx_queue_release)(txq[i]);
1113 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1114 RTE_CACHE_LINE_SIZE);
1117 if (nb_queues > old_nb_queues) {
1118 uint16_t new_qs = nb_queues - old_nb_queues;
1120 memset(txq + old_nb_queues, 0,
1121 sizeof(txq[0]) * new_qs);
1124 dev->data->tx_queues = txq;
1126 } else if (dev->data->tx_queues != NULL && nb_queues == 0) {
1127 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1129 txq = dev->data->tx_queues;
1131 for (i = nb_queues; i < old_nb_queues; i++)
1132 (*dev->dev_ops->tx_queue_release)(txq[i]);
1134 rte_free(dev->data->tx_queues);
1135 dev->data->tx_queues = NULL;
1137 dev->data->nb_tx_queues = nb_queues;
1142 rte_eth_speed_bitflag(uint32_t speed, int duplex)
1145 case ETH_SPEED_NUM_10M:
1146 return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD;
1147 case ETH_SPEED_NUM_100M:
1148 return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD;
1149 case ETH_SPEED_NUM_1G:
1150 return ETH_LINK_SPEED_1G;
1151 case ETH_SPEED_NUM_2_5G:
1152 return ETH_LINK_SPEED_2_5G;
1153 case ETH_SPEED_NUM_5G:
1154 return ETH_LINK_SPEED_5G;
1155 case ETH_SPEED_NUM_10G:
1156 return ETH_LINK_SPEED_10G;
1157 case ETH_SPEED_NUM_20G:
1158 return ETH_LINK_SPEED_20G;
1159 case ETH_SPEED_NUM_25G:
1160 return ETH_LINK_SPEED_25G;
1161 case ETH_SPEED_NUM_40G:
1162 return ETH_LINK_SPEED_40G;
1163 case ETH_SPEED_NUM_50G:
1164 return ETH_LINK_SPEED_50G;
1165 case ETH_SPEED_NUM_56G:
1166 return ETH_LINK_SPEED_56G;
1167 case ETH_SPEED_NUM_100G:
1168 return ETH_LINK_SPEED_100G;
1169 case ETH_SPEED_NUM_200G:
1170 return ETH_LINK_SPEED_200G;
1177 rte_eth_dev_rx_offload_name(uint64_t offload)
1179 const char *name = "UNKNOWN";
1182 for (i = 0; i < RTE_DIM(rte_rx_offload_names); ++i) {
1183 if (offload == rte_rx_offload_names[i].offload) {
1184 name = rte_rx_offload_names[i].name;
1193 rte_eth_dev_tx_offload_name(uint64_t offload)
1195 const char *name = "UNKNOWN";
1198 for (i = 0; i < RTE_DIM(rte_tx_offload_names); ++i) {
1199 if (offload == rte_tx_offload_names[i].offload) {
1200 name = rte_tx_offload_names[i].name;
1209 check_lro_pkt_size(uint16_t port_id, uint32_t config_size,
1210 uint32_t max_rx_pkt_len, uint32_t dev_info_size)
1214 if (dev_info_size == 0) {
1215 if (config_size != max_rx_pkt_len) {
1216 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size"
1217 " %u != %u is not allowed\n",
1218 port_id, config_size, max_rx_pkt_len);
1221 } else if (config_size > dev_info_size) {
1222 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u "
1223 "> max allowed value %u\n", port_id, config_size,
1226 } else if (config_size < RTE_ETHER_MIN_LEN) {
1227 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u "
1228 "< min allowed value %u\n", port_id, config_size,
1229 (unsigned int)RTE_ETHER_MIN_LEN);
1236 * Validate offloads that are requested through rte_eth_dev_configure against
1237 * the offloads successfully set by the ethernet device.
1240 * The port identifier of the Ethernet device.
1241 * @param req_offloads
1242 * The offloads that have been requested through `rte_eth_dev_configure`.
1243 * @param set_offloads
1244 * The offloads successfully set by the ethernet device.
1245 * @param offload_type
1246 * The offload type i.e. Rx/Tx string.
1247 * @param offload_name
1248 * The function that prints the offload name.
1250 * - (0) if validation successful.
1251 * - (-EINVAL) if requested offload has been silently disabled.
1255 validate_offloads(uint16_t port_id, uint64_t req_offloads,
1256 uint64_t set_offloads, const char *offload_type,
1257 const char *(*offload_name)(uint64_t))
1259 uint64_t offloads_diff = req_offloads ^ set_offloads;
1263 while (offloads_diff != 0) {
1264 /* Check if any offload is requested but not enabled. */
1265 offload = 1ULL << __builtin_ctzll(offloads_diff);
1266 if (offload & req_offloads) {
1268 "Port %u failed to enable %s offload %s\n",
1269 port_id, offload_type, offload_name(offload));
1273 /* Check if offload couldn't be disabled. */
1274 if (offload & set_offloads) {
1275 RTE_ETHDEV_LOG(DEBUG,
1276 "Port %u %s offload %s is not requested but enabled\n",
1277 port_id, offload_type, offload_name(offload));
1280 offloads_diff &= ~offload;
1287 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,
1288 const struct rte_eth_conf *dev_conf)
1290 struct rte_eth_dev *dev;
1291 struct rte_eth_dev_info dev_info;
1292 struct rte_eth_conf orig_conf;
1296 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1298 dev = &rte_eth_devices[port_id];
1300 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP);
1302 if (dev->data->dev_started) {
1304 "Port %u must be stopped to allow configuration\n",
1309 /* Store original config, as rollback required on failure */
1310 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf));
1313 * Copy the dev_conf parameter into the dev structure.
1314 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get
1316 if (dev_conf != &dev->data->dev_conf)
1317 memcpy(&dev->data->dev_conf, dev_conf,
1318 sizeof(dev->data->dev_conf));
1320 ret = rte_eth_dev_info_get(port_id, &dev_info);
1324 /* If number of queues specified by application for both Rx and Tx is
1325 * zero, use driver preferred values. This cannot be done individually
1326 * as it is valid for either Tx or Rx (but not both) to be zero.
1327 * If driver does not provide any preferred valued, fall back on
1330 if (nb_rx_q == 0 && nb_tx_q == 0) {
1331 nb_rx_q = dev_info.default_rxportconf.nb_queues;
1333 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES;
1334 nb_tx_q = dev_info.default_txportconf.nb_queues;
1336 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES;
1339 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) {
1341 "Number of RX queues requested (%u) is greater than max supported(%d)\n",
1342 nb_rx_q, RTE_MAX_QUEUES_PER_PORT);
1347 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) {
1349 "Number of TX queues requested (%u) is greater than max supported(%d)\n",
1350 nb_tx_q, RTE_MAX_QUEUES_PER_PORT);
1356 * Check that the numbers of RX and TX queues are not greater
1357 * than the maximum number of RX and TX queues supported by the
1358 * configured device.
1360 if (nb_rx_q > dev_info.max_rx_queues) {
1361 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u\n",
1362 port_id, nb_rx_q, dev_info.max_rx_queues);
1367 if (nb_tx_q > dev_info.max_tx_queues) {
1368 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u\n",
1369 port_id, nb_tx_q, dev_info.max_tx_queues);
1374 /* Check that the device supports requested interrupts */
1375 if ((dev_conf->intr_conf.lsc == 1) &&
1376 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) {
1377 RTE_ETHDEV_LOG(ERR, "Driver %s does not support lsc\n",
1378 dev->device->driver->name);
1382 if ((dev_conf->intr_conf.rmv == 1) &&
1383 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) {
1384 RTE_ETHDEV_LOG(ERR, "Driver %s does not support rmv\n",
1385 dev->device->driver->name);
1391 * If jumbo frames are enabled, check that the maximum RX packet
1392 * length is supported by the configured device.
1394 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1395 if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen) {
1397 "Ethdev port_id=%u max_rx_pkt_len %u > max valid value %u\n",
1398 port_id, dev_conf->rxmode.max_rx_pkt_len,
1399 dev_info.max_rx_pktlen);
1402 } else if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN) {
1404 "Ethdev port_id=%u max_rx_pkt_len %u < min valid value %u\n",
1405 port_id, dev_conf->rxmode.max_rx_pkt_len,
1406 (unsigned int)RTE_ETHER_MIN_LEN);
1411 if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN ||
1412 dev_conf->rxmode.max_rx_pkt_len > RTE_ETHER_MAX_LEN)
1413 /* Use default value */
1414 dev->data->dev_conf.rxmode.max_rx_pkt_len =
1419 * If LRO is enabled, check that the maximum aggregated packet
1420 * size is supported by the configured device.
1422 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1423 if (dev_conf->rxmode.max_lro_pkt_size == 0)
1424 dev->data->dev_conf.rxmode.max_lro_pkt_size =
1425 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1426 ret = check_lro_pkt_size(port_id,
1427 dev->data->dev_conf.rxmode.max_lro_pkt_size,
1428 dev->data->dev_conf.rxmode.max_rx_pkt_len,
1429 dev_info.max_lro_pkt_size);
1434 /* Any requested offloading must be within its device capabilities */
1435 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) !=
1436 dev_conf->rxmode.offloads) {
1438 "Ethdev port_id=%u requested Rx offloads 0x%"PRIx64" doesn't match Rx offloads "
1439 "capabilities 0x%"PRIx64" in %s()\n",
1440 port_id, dev_conf->rxmode.offloads,
1441 dev_info.rx_offload_capa,
1446 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) !=
1447 dev_conf->txmode.offloads) {
1449 "Ethdev port_id=%u requested Tx offloads 0x%"PRIx64" doesn't match Tx offloads "
1450 "capabilities 0x%"PRIx64" in %s()\n",
1451 port_id, dev_conf->txmode.offloads,
1452 dev_info.tx_offload_capa,
1458 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf =
1459 rte_eth_rss_hf_refine(dev_conf->rx_adv_conf.rss_conf.rss_hf);
1461 /* Check that device supports requested rss hash functions. */
1462 if ((dev_info.flow_type_rss_offloads |
1463 dev_conf->rx_adv_conf.rss_conf.rss_hf) !=
1464 dev_info.flow_type_rss_offloads) {
1466 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
1467 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf,
1468 dev_info.flow_type_rss_offloads);
1473 /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */
1474 if (((dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) &&
1475 (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_RSS_HASH)) {
1477 "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested\n",
1479 rte_eth_dev_rx_offload_name(DEV_RX_OFFLOAD_RSS_HASH));
1485 * Setup new number of RX/TX queues and reconfigure device.
1487 diag = rte_eth_dev_rx_queue_config(dev, nb_rx_q);
1490 "Port%u rte_eth_dev_rx_queue_config = %d\n",
1496 diag = rte_eth_dev_tx_queue_config(dev, nb_tx_q);
1499 "Port%u rte_eth_dev_tx_queue_config = %d\n",
1501 rte_eth_dev_rx_queue_config(dev, 0);
1506 diag = (*dev->dev_ops->dev_configure)(dev);
1508 RTE_ETHDEV_LOG(ERR, "Port%u dev_configure = %d\n",
1510 ret = eth_err(port_id, diag);
1514 /* Initialize Rx profiling if enabled at compilation time. */
1515 diag = __rte_eth_dev_profile_init(port_id, dev);
1517 RTE_ETHDEV_LOG(ERR, "Port%u __rte_eth_dev_profile_init = %d\n",
1519 ret = eth_err(port_id, diag);
1523 /* Validate Rx offloads. */
1524 diag = validate_offloads(port_id,
1525 dev_conf->rxmode.offloads,
1526 dev->data->dev_conf.rxmode.offloads, "Rx",
1527 rte_eth_dev_rx_offload_name);
1533 /* Validate Tx offloads. */
1534 diag = validate_offloads(port_id,
1535 dev_conf->txmode.offloads,
1536 dev->data->dev_conf.txmode.offloads, "Tx",
1537 rte_eth_dev_tx_offload_name);
1543 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, 0);
1546 rte_eth_dev_rx_queue_config(dev, 0);
1547 rte_eth_dev_tx_queue_config(dev, 0);
1549 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf));
1551 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, ret);
1556 rte_eth_dev_internal_reset(struct rte_eth_dev *dev)
1558 if (dev->data->dev_started) {
1559 RTE_ETHDEV_LOG(ERR, "Port %u must be stopped to allow reset\n",
1560 dev->data->port_id);
1564 rte_eth_dev_rx_queue_config(dev, 0);
1565 rte_eth_dev_tx_queue_config(dev, 0);
1567 memset(&dev->data->dev_conf, 0, sizeof(dev->data->dev_conf));
1571 rte_eth_dev_mac_restore(struct rte_eth_dev *dev,
1572 struct rte_eth_dev_info *dev_info)
1574 struct rte_ether_addr *addr;
1579 /* replay MAC address configuration including default MAC */
1580 addr = &dev->data->mac_addrs[0];
1581 if (*dev->dev_ops->mac_addr_set != NULL)
1582 (*dev->dev_ops->mac_addr_set)(dev, addr);
1583 else if (*dev->dev_ops->mac_addr_add != NULL)
1584 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool);
1586 if (*dev->dev_ops->mac_addr_add != NULL) {
1587 for (i = 1; i < dev_info->max_mac_addrs; i++) {
1588 addr = &dev->data->mac_addrs[i];
1590 /* skip zero address */
1591 if (rte_is_zero_ether_addr(addr))
1595 pool_mask = dev->data->mac_pool_sel[i];
1598 if (pool_mask & 1ULL)
1599 (*dev->dev_ops->mac_addr_add)(dev,
1603 } while (pool_mask);
1609 rte_eth_dev_config_restore(struct rte_eth_dev *dev,
1610 struct rte_eth_dev_info *dev_info, uint16_t port_id)
1614 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR))
1615 rte_eth_dev_mac_restore(dev, dev_info);
1617 /* replay promiscuous configuration */
1619 * use callbacks directly since we don't need port_id check and
1620 * would like to bypass the same value set
1622 if (rte_eth_promiscuous_get(port_id) == 1 &&
1623 *dev->dev_ops->promiscuous_enable != NULL) {
1624 ret = eth_err(port_id,
1625 (*dev->dev_ops->promiscuous_enable)(dev));
1626 if (ret != 0 && ret != -ENOTSUP) {
1628 "Failed to enable promiscuous mode for device (port %u): %s\n",
1629 port_id, rte_strerror(-ret));
1632 } else if (rte_eth_promiscuous_get(port_id) == 0 &&
1633 *dev->dev_ops->promiscuous_disable != NULL) {
1634 ret = eth_err(port_id,
1635 (*dev->dev_ops->promiscuous_disable)(dev));
1636 if (ret != 0 && ret != -ENOTSUP) {
1638 "Failed to disable promiscuous mode for device (port %u): %s\n",
1639 port_id, rte_strerror(-ret));
1644 /* replay all multicast configuration */
1646 * use callbacks directly since we don't need port_id check and
1647 * would like to bypass the same value set
1649 if (rte_eth_allmulticast_get(port_id) == 1 &&
1650 *dev->dev_ops->allmulticast_enable != NULL) {
1651 ret = eth_err(port_id,
1652 (*dev->dev_ops->allmulticast_enable)(dev));
1653 if (ret != 0 && ret != -ENOTSUP) {
1655 "Failed to enable allmulticast mode for device (port %u): %s\n",
1656 port_id, rte_strerror(-ret));
1659 } else if (rte_eth_allmulticast_get(port_id) == 0 &&
1660 *dev->dev_ops->allmulticast_disable != NULL) {
1661 ret = eth_err(port_id,
1662 (*dev->dev_ops->allmulticast_disable)(dev));
1663 if (ret != 0 && ret != -ENOTSUP) {
1665 "Failed to disable allmulticast mode for device (port %u): %s\n",
1666 port_id, rte_strerror(-ret));
1675 rte_eth_dev_start(uint16_t port_id)
1677 struct rte_eth_dev *dev;
1678 struct rte_eth_dev_info dev_info;
1682 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1684 dev = &rte_eth_devices[port_id];
1686 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP);
1688 if (dev->data->dev_started != 0) {
1689 RTE_ETHDEV_LOG(INFO,
1690 "Device with port_id=%"PRIu16" already started\n",
1695 ret = rte_eth_dev_info_get(port_id, &dev_info);
1699 /* Lets restore MAC now if device does not support live change */
1700 if (*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR)
1701 rte_eth_dev_mac_restore(dev, &dev_info);
1703 diag = (*dev->dev_ops->dev_start)(dev);
1705 dev->data->dev_started = 1;
1707 return eth_err(port_id, diag);
1709 ret = rte_eth_dev_config_restore(dev, &dev_info, port_id);
1712 "Error during restoring configuration for device (port %u): %s\n",
1713 port_id, rte_strerror(-ret));
1714 rte_eth_dev_stop(port_id);
1718 if (dev->data->dev_conf.intr_conf.lsc == 0) {
1719 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
1720 (*dev->dev_ops->link_update)(dev, 0);
1723 rte_ethdev_trace_start(port_id);
1728 rte_eth_dev_stop(uint16_t port_id)
1730 struct rte_eth_dev *dev;
1732 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1733 dev = &rte_eth_devices[port_id];
1735 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_stop);
1737 if (dev->data->dev_started == 0) {
1738 RTE_ETHDEV_LOG(INFO,
1739 "Device with port_id=%"PRIu16" already stopped\n",
1744 dev->data->dev_started = 0;
1745 (*dev->dev_ops->dev_stop)(dev);
1746 rte_ethdev_trace_stop(port_id);
1750 rte_eth_dev_set_link_up(uint16_t port_id)
1752 struct rte_eth_dev *dev;
1754 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1756 dev = &rte_eth_devices[port_id];
1758 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP);
1759 return eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev));
1763 rte_eth_dev_set_link_down(uint16_t port_id)
1765 struct rte_eth_dev *dev;
1767 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1769 dev = &rte_eth_devices[port_id];
1771 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP);
1772 return eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev));
1776 rte_eth_dev_close(uint16_t port_id)
1778 struct rte_eth_dev *dev;
1779 int firsterr, binerr;
1780 int *lasterr = &firsterr;
1782 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1783 dev = &rte_eth_devices[port_id];
1785 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_close, -ENOTSUP);
1786 *lasterr = (*dev->dev_ops->dev_close)(dev);
1790 rte_ethdev_trace_close(port_id);
1791 *lasterr = rte_eth_dev_release_port(dev);
1793 return eth_err(port_id, firsterr);
1797 rte_eth_dev_reset(uint16_t port_id)
1799 struct rte_eth_dev *dev;
1802 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1803 dev = &rte_eth_devices[port_id];
1805 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_reset, -ENOTSUP);
1807 rte_eth_dev_stop(port_id);
1808 ret = dev->dev_ops->dev_reset(dev);
1810 return eth_err(port_id, ret);
1814 rte_eth_dev_is_removed(uint16_t port_id)
1816 struct rte_eth_dev *dev;
1819 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
1821 dev = &rte_eth_devices[port_id];
1823 if (dev->state == RTE_ETH_DEV_REMOVED)
1826 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->is_removed, 0);
1828 ret = dev->dev_ops->is_removed(dev);
1830 /* Device is physically removed. */
1831 dev->state = RTE_ETH_DEV_REMOVED;
1837 rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg,
1838 uint16_t n_seg, uint32_t *mbp_buf_size,
1839 const struct rte_eth_dev_info *dev_info)
1841 const struct rte_eth_rxseg_capa *seg_capa = &dev_info->rx_seg_capa;
1842 struct rte_mempool *mp_first;
1843 uint32_t offset_mask;
1846 if (n_seg > seg_capa->max_nseg) {
1848 "Requested Rx segments %u exceed supported %u\n",
1849 n_seg, seg_capa->max_nseg);
1853 * Check the sizes and offsets against buffer sizes
1854 * for each segment specified in extended configuration.
1856 mp_first = rx_seg[0].mp;
1857 offset_mask = (1u << seg_capa->offset_align_log2) - 1;
1858 for (seg_idx = 0; seg_idx < n_seg; seg_idx++) {
1859 struct rte_mempool *mpl = rx_seg[seg_idx].mp;
1860 uint32_t length = rx_seg[seg_idx].length;
1861 uint32_t offset = rx_seg[seg_idx].offset;
1864 RTE_ETHDEV_LOG(ERR, "null mempool pointer\n");
1867 if (seg_idx != 0 && mp_first != mpl &&
1868 seg_capa->multi_pools == 0) {
1869 RTE_ETHDEV_LOG(ERR, "Receiving to multiple pools is not supported\n");
1873 if (seg_capa->offset_allowed == 0) {
1874 RTE_ETHDEV_LOG(ERR, "Rx segmentation with offset is not supported\n");
1877 if (offset & offset_mask) {
1878 RTE_ETHDEV_LOG(ERR, "Rx segmentation invalid offset alignment %u, %u\n",
1880 seg_capa->offset_align_log2);
1884 if (mpl->private_data_size <
1885 sizeof(struct rte_pktmbuf_pool_private)) {
1887 "%s private_data_size %u < %u\n",
1888 mpl->name, mpl->private_data_size,
1889 (unsigned int)sizeof
1890 (struct rte_pktmbuf_pool_private));
1893 offset += seg_idx != 0 ? 0 : RTE_PKTMBUF_HEADROOM;
1894 *mbp_buf_size = rte_pktmbuf_data_room_size(mpl);
1895 length = length != 0 ? length : *mbp_buf_size;
1896 if (*mbp_buf_size < length + offset) {
1898 "%s mbuf_data_room_size %u < %u (segment length=%u + segment offset=%u)\n",
1899 mpl->name, *mbp_buf_size,
1900 length + offset, length, offset);
1908 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
1909 uint16_t nb_rx_desc, unsigned int socket_id,
1910 const struct rte_eth_rxconf *rx_conf,
1911 struct rte_mempool *mp)
1914 uint32_t mbp_buf_size;
1915 struct rte_eth_dev *dev;
1916 struct rte_eth_dev_info dev_info;
1917 struct rte_eth_rxconf local_conf;
1920 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1922 dev = &rte_eth_devices[port_id];
1923 if (rx_queue_id >= dev->data->nb_rx_queues) {
1924 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
1928 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP);
1930 ret = rte_eth_dev_info_get(port_id, &dev_info);
1935 /* Single pool configuration check. */
1936 if (rx_conf != NULL && rx_conf->rx_nseg != 0) {
1938 "Ambiguous segment configuration\n");
1942 * Check the size of the mbuf data buffer, this value
1943 * must be provided in the private data of the memory pool.
1944 * First check that the memory pool(s) has a valid private data.
1946 if (mp->private_data_size <
1947 sizeof(struct rte_pktmbuf_pool_private)) {
1948 RTE_ETHDEV_LOG(ERR, "%s private_data_size %u < %u\n",
1949 mp->name, mp->private_data_size,
1951 sizeof(struct rte_pktmbuf_pool_private));
1954 mbp_buf_size = rte_pktmbuf_data_room_size(mp);
1955 if (mbp_buf_size < dev_info.min_rx_bufsize +
1956 RTE_PKTMBUF_HEADROOM) {
1958 "%s mbuf_data_room_size %u < %u (RTE_PKTMBUF_HEADROOM=%u + min_rx_bufsize(dev)=%u)\n",
1959 mp->name, mbp_buf_size,
1960 RTE_PKTMBUF_HEADROOM +
1961 dev_info.min_rx_bufsize,
1962 RTE_PKTMBUF_HEADROOM,
1963 dev_info.min_rx_bufsize);
1967 const struct rte_eth_rxseg_split *rx_seg =
1968 (const struct rte_eth_rxseg_split *)rx_conf->rx_seg;
1969 uint16_t n_seg = rx_conf->rx_nseg;
1971 /* Extended multi-segment configuration check. */
1972 if (rx_conf == NULL || rx_conf->rx_seg == NULL || rx_conf->rx_nseg == 0) {
1974 "Memory pool is null and no extended configuration provided\n");
1977 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) {
1978 ret = rte_eth_rx_queue_check_split(rx_seg, n_seg,
1984 RTE_ETHDEV_LOG(ERR, "No Rx segmentation offload configured\n");
1989 /* Use default specified by driver, if nb_rx_desc is zero */
1990 if (nb_rx_desc == 0) {
1991 nb_rx_desc = dev_info.default_rxportconf.ring_size;
1992 /* If driver default is also zero, fall back on EAL default */
1993 if (nb_rx_desc == 0)
1994 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE;
1997 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max ||
1998 nb_rx_desc < dev_info.rx_desc_lim.nb_min ||
1999 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) {
2002 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
2003 nb_rx_desc, dev_info.rx_desc_lim.nb_max,
2004 dev_info.rx_desc_lim.nb_min,
2005 dev_info.rx_desc_lim.nb_align);
2009 if (dev->data->dev_started &&
2010 !(dev_info.dev_capa &
2011 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP))
2014 if (dev->data->dev_started &&
2015 (dev->data->rx_queue_state[rx_queue_id] !=
2016 RTE_ETH_QUEUE_STATE_STOPPED))
2019 rxq = dev->data->rx_queues;
2020 if (rxq[rx_queue_id]) {
2021 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
2023 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
2024 rxq[rx_queue_id] = NULL;
2027 if (rx_conf == NULL)
2028 rx_conf = &dev_info.default_rxconf;
2030 local_conf = *rx_conf;
2033 * If an offloading has already been enabled in
2034 * rte_eth_dev_configure(), it has been enabled on all queues,
2035 * so there is no need to enable it in this queue again.
2036 * The local_conf.offloads input to underlying PMD only carries
2037 * those offloadings which are only enabled on this queue and
2038 * not enabled on all queues.
2040 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads;
2043 * New added offloadings for this queue are those not enabled in
2044 * rte_eth_dev_configure() and they must be per-queue type.
2045 * A pure per-port offloading can't be enabled on a queue while
2046 * disabled on another queue. A pure per-port offloading can't
2047 * be enabled for any queue as new added one if it hasn't been
2048 * enabled in rte_eth_dev_configure().
2050 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) !=
2051 local_conf.offloads) {
2053 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
2054 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
2055 port_id, rx_queue_id, local_conf.offloads,
2056 dev_info.rx_queue_offload_capa,
2062 * If LRO is enabled, check that the maximum aggregated packet
2063 * size is supported by the configured device.
2065 if (local_conf.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
2066 if (dev->data->dev_conf.rxmode.max_lro_pkt_size == 0)
2067 dev->data->dev_conf.rxmode.max_lro_pkt_size =
2068 dev->data->dev_conf.rxmode.max_rx_pkt_len;
2069 int ret = check_lro_pkt_size(port_id,
2070 dev->data->dev_conf.rxmode.max_lro_pkt_size,
2071 dev->data->dev_conf.rxmode.max_rx_pkt_len,
2072 dev_info.max_lro_pkt_size);
2077 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc,
2078 socket_id, &local_conf, mp);
2080 if (!dev->data->min_rx_buf_size ||
2081 dev->data->min_rx_buf_size > mbp_buf_size)
2082 dev->data->min_rx_buf_size = mbp_buf_size;
2085 rte_ethdev_trace_rxq_setup(port_id, rx_queue_id, nb_rx_desc, mp,
2087 return eth_err(port_id, ret);
2091 rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
2092 uint16_t nb_rx_desc,
2093 const struct rte_eth_hairpin_conf *conf)
2096 struct rte_eth_dev *dev;
2097 struct rte_eth_hairpin_cap cap;
2102 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2104 dev = &rte_eth_devices[port_id];
2105 if (rx_queue_id >= dev->data->nb_rx_queues) {
2106 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
2109 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
2112 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_hairpin_queue_setup,
2114 /* if nb_rx_desc is zero use max number of desc from the driver. */
2115 if (nb_rx_desc == 0)
2116 nb_rx_desc = cap.max_nb_desc;
2117 if (nb_rx_desc > cap.max_nb_desc) {
2119 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu",
2120 nb_rx_desc, cap.max_nb_desc);
2123 if (conf->peer_count > cap.max_rx_2_tx) {
2125 "Invalid value for number of peers for Rx queue(=%u), should be: <= %hu",
2126 conf->peer_count, cap.max_rx_2_tx);
2129 if (conf->peer_count == 0) {
2131 "Invalid value for number of peers for Rx queue(=%u), should be: > 0",
2135 for (i = 0, count = 0; i < dev->data->nb_rx_queues &&
2136 cap.max_nb_queues != UINT16_MAX; i++) {
2137 if (i == rx_queue_id || rte_eth_dev_is_rx_hairpin_queue(dev, i))
2140 if (count > cap.max_nb_queues) {
2141 RTE_ETHDEV_LOG(ERR, "To many Rx hairpin queues max is %d",
2145 if (dev->data->dev_started)
2147 rxq = dev->data->rx_queues;
2148 if (rxq[rx_queue_id] != NULL) {
2149 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
2151 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
2152 rxq[rx_queue_id] = NULL;
2154 ret = (*dev->dev_ops->rx_hairpin_queue_setup)(dev, rx_queue_id,
2157 dev->data->rx_queue_state[rx_queue_id] =
2158 RTE_ETH_QUEUE_STATE_HAIRPIN;
2159 return eth_err(port_id, ret);
2163 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
2164 uint16_t nb_tx_desc, unsigned int socket_id,
2165 const struct rte_eth_txconf *tx_conf)
2167 struct rte_eth_dev *dev;
2168 struct rte_eth_dev_info dev_info;
2169 struct rte_eth_txconf local_conf;
2173 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2175 dev = &rte_eth_devices[port_id];
2176 if (tx_queue_id >= dev->data->nb_tx_queues) {
2177 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
2181 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP);
2183 ret = rte_eth_dev_info_get(port_id, &dev_info);
2187 /* Use default specified by driver, if nb_tx_desc is zero */
2188 if (nb_tx_desc == 0) {
2189 nb_tx_desc = dev_info.default_txportconf.ring_size;
2190 /* If driver default is zero, fall back on EAL default */
2191 if (nb_tx_desc == 0)
2192 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE;
2194 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max ||
2195 nb_tx_desc < dev_info.tx_desc_lim.nb_min ||
2196 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) {
2198 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
2199 nb_tx_desc, dev_info.tx_desc_lim.nb_max,
2200 dev_info.tx_desc_lim.nb_min,
2201 dev_info.tx_desc_lim.nb_align);
2205 if (dev->data->dev_started &&
2206 !(dev_info.dev_capa &
2207 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP))
2210 if (dev->data->dev_started &&
2211 (dev->data->tx_queue_state[tx_queue_id] !=
2212 RTE_ETH_QUEUE_STATE_STOPPED))
2215 txq = dev->data->tx_queues;
2216 if (txq[tx_queue_id]) {
2217 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
2219 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
2220 txq[tx_queue_id] = NULL;
2223 if (tx_conf == NULL)
2224 tx_conf = &dev_info.default_txconf;
2226 local_conf = *tx_conf;
2229 * If an offloading has already been enabled in
2230 * rte_eth_dev_configure(), it has been enabled on all queues,
2231 * so there is no need to enable it in this queue again.
2232 * The local_conf.offloads input to underlying PMD only carries
2233 * those offloadings which are only enabled on this queue and
2234 * not enabled on all queues.
2236 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads;
2239 * New added offloadings for this queue are those not enabled in
2240 * rte_eth_dev_configure() and they must be per-queue type.
2241 * A pure per-port offloading can't be enabled on a queue while
2242 * disabled on another queue. A pure per-port offloading can't
2243 * be enabled for any queue as new added one if it hasn't been
2244 * enabled in rte_eth_dev_configure().
2246 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) !=
2247 local_conf.offloads) {
2249 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
2250 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
2251 port_id, tx_queue_id, local_conf.offloads,
2252 dev_info.tx_queue_offload_capa,
2257 rte_ethdev_trace_txq_setup(port_id, tx_queue_id, nb_tx_desc, tx_conf);
2258 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev,
2259 tx_queue_id, nb_tx_desc, socket_id, &local_conf));
2263 rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
2264 uint16_t nb_tx_desc,
2265 const struct rte_eth_hairpin_conf *conf)
2267 struct rte_eth_dev *dev;
2268 struct rte_eth_hairpin_cap cap;
2274 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2275 dev = &rte_eth_devices[port_id];
2276 if (tx_queue_id >= dev->data->nb_tx_queues) {
2277 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
2280 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
2283 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_hairpin_queue_setup,
2285 /* if nb_rx_desc is zero use max number of desc from the driver. */
2286 if (nb_tx_desc == 0)
2287 nb_tx_desc = cap.max_nb_desc;
2288 if (nb_tx_desc > cap.max_nb_desc) {
2290 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu",
2291 nb_tx_desc, cap.max_nb_desc);
2294 if (conf->peer_count > cap.max_tx_2_rx) {
2296 "Invalid value for number of peers for Tx queue(=%u), should be: <= %hu",
2297 conf->peer_count, cap.max_tx_2_rx);
2300 if (conf->peer_count == 0) {
2302 "Invalid value for number of peers for Tx queue(=%u), should be: > 0",
2306 for (i = 0, count = 0; i < dev->data->nb_tx_queues &&
2307 cap.max_nb_queues != UINT16_MAX; i++) {
2308 if (i == tx_queue_id || rte_eth_dev_is_tx_hairpin_queue(dev, i))
2311 if (count > cap.max_nb_queues) {
2312 RTE_ETHDEV_LOG(ERR, "To many Tx hairpin queues max is %d",
2316 if (dev->data->dev_started)
2318 txq = dev->data->tx_queues;
2319 if (txq[tx_queue_id] != NULL) {
2320 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
2322 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
2323 txq[tx_queue_id] = NULL;
2325 ret = (*dev->dev_ops->tx_hairpin_queue_setup)
2326 (dev, tx_queue_id, nb_tx_desc, conf);
2328 dev->data->tx_queue_state[tx_queue_id] =
2329 RTE_ETH_QUEUE_STATE_HAIRPIN;
2330 return eth_err(port_id, ret);
2334 rte_eth_hairpin_bind(uint16_t tx_port, uint16_t rx_port)
2336 struct rte_eth_dev *dev;
2339 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV);
2340 dev = &rte_eth_devices[tx_port];
2341 if (dev->data->dev_started == 0) {
2342 RTE_ETHDEV_LOG(ERR, "Tx port %d is not started\n", tx_port);
2346 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_bind, -ENOTSUP);
2347 ret = (*dev->dev_ops->hairpin_bind)(dev, rx_port);
2349 RTE_ETHDEV_LOG(ERR, "Failed to bind hairpin Tx %d"
2350 " to Rx %d (%d - all ports)\n",
2351 tx_port, rx_port, RTE_MAX_ETHPORTS);
2357 rte_eth_hairpin_unbind(uint16_t tx_port, uint16_t rx_port)
2359 struct rte_eth_dev *dev;
2362 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV);
2363 dev = &rte_eth_devices[tx_port];
2364 if (dev->data->dev_started == 0) {
2365 RTE_ETHDEV_LOG(ERR, "Tx port %d is already stopped\n", tx_port);
2369 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_unbind, -ENOTSUP);
2370 ret = (*dev->dev_ops->hairpin_unbind)(dev, rx_port);
2372 RTE_ETHDEV_LOG(ERR, "Failed to unbind hairpin Tx %d"
2373 " from Rx %d (%d - all ports)\n",
2374 tx_port, rx_port, RTE_MAX_ETHPORTS);
2380 rte_eth_hairpin_get_peer_ports(uint16_t port_id, uint16_t *peer_ports,
2381 size_t len, uint32_t direction)
2383 struct rte_eth_dev *dev;
2386 if (peer_ports == NULL || len == 0)
2389 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2390 dev = &rte_eth_devices[port_id];
2391 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_get_peer_ports,
2394 ret = (*dev->dev_ops->hairpin_get_peer_ports)(dev, peer_ports,
2397 RTE_ETHDEV_LOG(ERR, "Failed to get %d hairpin peer %s ports\n",
2398 port_id, direction ? "Rx" : "Tx");
2404 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent,
2405 void *userdata __rte_unused)
2407 rte_pktmbuf_free_bulk(pkts, unsent);
2411 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent,
2414 uint64_t *count = userdata;
2416 rte_pktmbuf_free_bulk(pkts, unsent);
2421 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer,
2422 buffer_tx_error_fn cbfn, void *userdata)
2424 buffer->error_callback = cbfn;
2425 buffer->error_userdata = userdata;
2430 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size)
2437 buffer->size = size;
2438 if (buffer->error_callback == NULL) {
2439 ret = rte_eth_tx_buffer_set_err_callback(
2440 buffer, rte_eth_tx_buffer_drop_callback, NULL);
2447 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt)
2449 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2452 /* Validate Input Data. Bail if not valid or not supported. */
2453 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2454 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_done_cleanup, -ENOTSUP);
2456 /* Call driver to free pending mbufs. */
2457 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id],
2459 return eth_err(port_id, ret);
2463 rte_eth_promiscuous_enable(uint16_t port_id)
2465 struct rte_eth_dev *dev;
2468 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2469 dev = &rte_eth_devices[port_id];
2471 if (dev->data->promiscuous == 1)
2474 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_enable, -ENOTSUP);
2476 diag = (*dev->dev_ops->promiscuous_enable)(dev);
2477 dev->data->promiscuous = (diag == 0) ? 1 : 0;
2479 return eth_err(port_id, diag);
2483 rte_eth_promiscuous_disable(uint16_t port_id)
2485 struct rte_eth_dev *dev;
2488 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2489 dev = &rte_eth_devices[port_id];
2491 if (dev->data->promiscuous == 0)
2494 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_disable, -ENOTSUP);
2496 dev->data->promiscuous = 0;
2497 diag = (*dev->dev_ops->promiscuous_disable)(dev);
2499 dev->data->promiscuous = 1;
2501 return eth_err(port_id, diag);
2505 rte_eth_promiscuous_get(uint16_t port_id)
2507 struct rte_eth_dev *dev;
2509 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2511 dev = &rte_eth_devices[port_id];
2512 return dev->data->promiscuous;
2516 rte_eth_allmulticast_enable(uint16_t port_id)
2518 struct rte_eth_dev *dev;
2521 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2522 dev = &rte_eth_devices[port_id];
2524 if (dev->data->all_multicast == 1)
2527 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_enable, -ENOTSUP);
2528 diag = (*dev->dev_ops->allmulticast_enable)(dev);
2529 dev->data->all_multicast = (diag == 0) ? 1 : 0;
2531 return eth_err(port_id, diag);
2535 rte_eth_allmulticast_disable(uint16_t port_id)
2537 struct rte_eth_dev *dev;
2540 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2541 dev = &rte_eth_devices[port_id];
2543 if (dev->data->all_multicast == 0)
2546 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_disable, -ENOTSUP);
2547 dev->data->all_multicast = 0;
2548 diag = (*dev->dev_ops->allmulticast_disable)(dev);
2550 dev->data->all_multicast = 1;
2552 return eth_err(port_id, diag);
2556 rte_eth_allmulticast_get(uint16_t port_id)
2558 struct rte_eth_dev *dev;
2560 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2562 dev = &rte_eth_devices[port_id];
2563 return dev->data->all_multicast;
2567 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link)
2569 struct rte_eth_dev *dev;
2571 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2572 dev = &rte_eth_devices[port_id];
2574 if (dev->data->dev_conf.intr_conf.lsc &&
2575 dev->data->dev_started)
2576 rte_eth_linkstatus_get(dev, eth_link);
2578 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
2579 (*dev->dev_ops->link_update)(dev, 1);
2580 *eth_link = dev->data->dev_link;
2587 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link)
2589 struct rte_eth_dev *dev;
2591 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2592 dev = &rte_eth_devices[port_id];
2594 if (dev->data->dev_conf.intr_conf.lsc &&
2595 dev->data->dev_started)
2596 rte_eth_linkstatus_get(dev, eth_link);
2598 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
2599 (*dev->dev_ops->link_update)(dev, 0);
2600 *eth_link = dev->data->dev_link;
2607 rte_eth_link_speed_to_str(uint32_t link_speed)
2609 switch (link_speed) {
2610 case ETH_SPEED_NUM_NONE: return "None";
2611 case ETH_SPEED_NUM_10M: return "10 Mbps";
2612 case ETH_SPEED_NUM_100M: return "100 Mbps";
2613 case ETH_SPEED_NUM_1G: return "1 Gbps";
2614 case ETH_SPEED_NUM_2_5G: return "2.5 Gbps";
2615 case ETH_SPEED_NUM_5G: return "5 Gbps";
2616 case ETH_SPEED_NUM_10G: return "10 Gbps";
2617 case ETH_SPEED_NUM_20G: return "20 Gbps";
2618 case ETH_SPEED_NUM_25G: return "25 Gbps";
2619 case ETH_SPEED_NUM_40G: return "40 Gbps";
2620 case ETH_SPEED_NUM_50G: return "50 Gbps";
2621 case ETH_SPEED_NUM_56G: return "56 Gbps";
2622 case ETH_SPEED_NUM_100G: return "100 Gbps";
2623 case ETH_SPEED_NUM_200G: return "200 Gbps";
2624 case ETH_SPEED_NUM_UNKNOWN: return "Unknown";
2625 default: return "Invalid";
2630 rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link)
2632 if (eth_link->link_status == ETH_LINK_DOWN)
2633 return snprintf(str, len, "Link down");
2635 return snprintf(str, len, "Link up at %s %s %s",
2636 rte_eth_link_speed_to_str(eth_link->link_speed),
2637 (eth_link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
2639 (eth_link->link_autoneg == ETH_LINK_AUTONEG) ?
2640 "Autoneg" : "Fixed");
2644 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
2646 struct rte_eth_dev *dev;
2648 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2650 dev = &rte_eth_devices[port_id];
2651 memset(stats, 0, sizeof(*stats));
2653 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP);
2654 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;
2655 return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats));
2659 rte_eth_stats_reset(uint16_t port_id)
2661 struct rte_eth_dev *dev;
2664 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2665 dev = &rte_eth_devices[port_id];
2667 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_reset, -ENOTSUP);
2668 ret = (*dev->dev_ops->stats_reset)(dev);
2670 return eth_err(port_id, ret);
2672 dev->data->rx_mbuf_alloc_failed = 0;
2678 get_xstats_basic_count(struct rte_eth_dev *dev)
2680 uint16_t nb_rxqs, nb_txqs;
2683 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2684 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2686 count = RTE_NB_STATS;
2687 count += nb_rxqs * RTE_NB_RXQ_STATS;
2688 count += nb_txqs * RTE_NB_TXQ_STATS;
2694 get_xstats_count(uint16_t port_id)
2696 struct rte_eth_dev *dev;
2699 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2700 dev = &rte_eth_devices[port_id];
2701 if (dev->dev_ops->xstats_get_names_by_id != NULL) {
2702 count = (*dev->dev_ops->xstats_get_names_by_id)(dev, NULL,
2705 return eth_err(port_id, count);
2707 if (dev->dev_ops->xstats_get_names != NULL) {
2708 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0);
2710 return eth_err(port_id, count);
2715 count += get_xstats_basic_count(dev);
2721 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name,
2724 int cnt_xstats, idx_xstat;
2726 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2729 RTE_ETHDEV_LOG(ERR, "Id pointer is NULL\n");
2734 RTE_ETHDEV_LOG(ERR, "xstat_name pointer is NULL\n");
2739 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL);
2740 if (cnt_xstats < 0) {
2741 RTE_ETHDEV_LOG(ERR, "Cannot get count of xstats\n");
2745 /* Get id-name lookup table */
2746 struct rte_eth_xstat_name xstats_names[cnt_xstats];
2748 if (cnt_xstats != rte_eth_xstats_get_names_by_id(
2749 port_id, xstats_names, cnt_xstats, NULL)) {
2750 RTE_ETHDEV_LOG(ERR, "Cannot get xstats lookup\n");
2754 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) {
2755 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) {
2764 /* retrieve basic stats names */
2766 rte_eth_basic_stats_get_names(struct rte_eth_dev *dev,
2767 struct rte_eth_xstat_name *xstats_names)
2769 int cnt_used_entries = 0;
2770 uint32_t idx, id_queue;
2773 for (idx = 0; idx < RTE_NB_STATS; idx++) {
2774 strlcpy(xstats_names[cnt_used_entries].name,
2775 rte_stats_strings[idx].name,
2776 sizeof(xstats_names[0].name));
2779 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2780 for (id_queue = 0; id_queue < num_q; id_queue++) {
2781 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) {
2782 snprintf(xstats_names[cnt_used_entries].name,
2783 sizeof(xstats_names[0].name),
2785 id_queue, rte_rxq_stats_strings[idx].name);
2790 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2791 for (id_queue = 0; id_queue < num_q; id_queue++) {
2792 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) {
2793 snprintf(xstats_names[cnt_used_entries].name,
2794 sizeof(xstats_names[0].name),
2796 id_queue, rte_txq_stats_strings[idx].name);
2800 return cnt_used_entries;
2803 /* retrieve ethdev extended statistics names */
2805 rte_eth_xstats_get_names_by_id(uint16_t port_id,
2806 struct rte_eth_xstat_name *xstats_names, unsigned int size,
2809 struct rte_eth_xstat_name *xstats_names_copy;
2810 unsigned int no_basic_stat_requested = 1;
2811 unsigned int no_ext_stat_requested = 1;
2812 unsigned int expected_entries;
2813 unsigned int basic_count;
2814 struct rte_eth_dev *dev;
2818 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2819 dev = &rte_eth_devices[port_id];
2821 basic_count = get_xstats_basic_count(dev);
2822 ret = get_xstats_count(port_id);
2825 expected_entries = (unsigned int)ret;
2827 /* Return max number of stats if no ids given */
2830 return expected_entries;
2831 else if (xstats_names && size < expected_entries)
2832 return expected_entries;
2835 if (ids && !xstats_names)
2838 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) {
2839 uint64_t ids_copy[size];
2841 for (i = 0; i < size; i++) {
2842 if (ids[i] < basic_count) {
2843 no_basic_stat_requested = 0;
2848 * Convert ids to xstats ids that PMD knows.
2849 * ids known by user are basic + extended stats.
2851 ids_copy[i] = ids[i] - basic_count;
2854 if (no_basic_stat_requested)
2855 return (*dev->dev_ops->xstats_get_names_by_id)(dev,
2856 xstats_names, ids_copy, size);
2859 /* Retrieve all stats */
2861 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names,
2863 if (num_stats < 0 || num_stats > (int)expected_entries)
2866 return expected_entries;
2869 xstats_names_copy = calloc(expected_entries,
2870 sizeof(struct rte_eth_xstat_name));
2872 if (!xstats_names_copy) {
2873 RTE_ETHDEV_LOG(ERR, "Can't allocate memory\n");
2878 for (i = 0; i < size; i++) {
2879 if (ids[i] >= basic_count) {
2880 no_ext_stat_requested = 0;
2886 /* Fill xstats_names_copy structure */
2887 if (ids && no_ext_stat_requested) {
2888 rte_eth_basic_stats_get_names(dev, xstats_names_copy);
2890 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy,
2893 free(xstats_names_copy);
2899 for (i = 0; i < size; i++) {
2900 if (ids[i] >= expected_entries) {
2901 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
2902 free(xstats_names_copy);
2905 xstats_names[i] = xstats_names_copy[ids[i]];
2908 free(xstats_names_copy);
2913 rte_eth_xstats_get_names(uint16_t port_id,
2914 struct rte_eth_xstat_name *xstats_names,
2917 struct rte_eth_dev *dev;
2918 int cnt_used_entries;
2919 int cnt_expected_entries;
2920 int cnt_driver_entries;
2922 cnt_expected_entries = get_xstats_count(port_id);
2923 if (xstats_names == NULL || cnt_expected_entries < 0 ||
2924 (int)size < cnt_expected_entries)
2925 return cnt_expected_entries;
2927 /* port_id checked in get_xstats_count() */
2928 dev = &rte_eth_devices[port_id];
2930 cnt_used_entries = rte_eth_basic_stats_get_names(
2933 if (dev->dev_ops->xstats_get_names != NULL) {
2934 /* If there are any driver-specific xstats, append them
2937 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)(
2939 xstats_names + cnt_used_entries,
2940 size - cnt_used_entries);
2941 if (cnt_driver_entries < 0)
2942 return eth_err(port_id, cnt_driver_entries);
2943 cnt_used_entries += cnt_driver_entries;
2946 return cnt_used_entries;
2951 rte_eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats)
2953 struct rte_eth_dev *dev;
2954 struct rte_eth_stats eth_stats;
2955 unsigned int count = 0, i, q;
2956 uint64_t val, *stats_ptr;
2957 uint16_t nb_rxqs, nb_txqs;
2960 ret = rte_eth_stats_get(port_id, ð_stats);
2964 dev = &rte_eth_devices[port_id];
2966 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2967 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2970 for (i = 0; i < RTE_NB_STATS; i++) {
2971 stats_ptr = RTE_PTR_ADD(ð_stats,
2972 rte_stats_strings[i].offset);
2974 xstats[count++].value = val;
2978 for (q = 0; q < nb_rxqs; q++) {
2979 for (i = 0; i < RTE_NB_RXQ_STATS; i++) {
2980 stats_ptr = RTE_PTR_ADD(ð_stats,
2981 rte_rxq_stats_strings[i].offset +
2982 q * sizeof(uint64_t));
2984 xstats[count++].value = val;
2989 for (q = 0; q < nb_txqs; q++) {
2990 for (i = 0; i < RTE_NB_TXQ_STATS; i++) {
2991 stats_ptr = RTE_PTR_ADD(ð_stats,
2992 rte_txq_stats_strings[i].offset +
2993 q * sizeof(uint64_t));
2995 xstats[count++].value = val;
3001 /* retrieve ethdev extended statistics */
3003 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids,
3004 uint64_t *values, unsigned int size)
3006 unsigned int no_basic_stat_requested = 1;
3007 unsigned int no_ext_stat_requested = 1;
3008 unsigned int num_xstats_filled;
3009 unsigned int basic_count;
3010 uint16_t expected_entries;
3011 struct rte_eth_dev *dev;
3015 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3016 ret = get_xstats_count(port_id);
3019 expected_entries = (uint16_t)ret;
3020 struct rte_eth_xstat xstats[expected_entries];
3021 dev = &rte_eth_devices[port_id];
3022 basic_count = get_xstats_basic_count(dev);
3024 /* Return max number of stats if no ids given */
3027 return expected_entries;
3028 else if (values && size < expected_entries)
3029 return expected_entries;
3035 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) {
3036 unsigned int basic_count = get_xstats_basic_count(dev);
3037 uint64_t ids_copy[size];
3039 for (i = 0; i < size; i++) {
3040 if (ids[i] < basic_count) {
3041 no_basic_stat_requested = 0;
3046 * Convert ids to xstats ids that PMD knows.
3047 * ids known by user are basic + extended stats.
3049 ids_copy[i] = ids[i] - basic_count;
3052 if (no_basic_stat_requested)
3053 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy,
3058 for (i = 0; i < size; i++) {
3059 if (ids[i] >= basic_count) {
3060 no_ext_stat_requested = 0;
3066 /* Fill the xstats structure */
3067 if (ids && no_ext_stat_requested)
3068 ret = rte_eth_basic_stats_get(port_id, xstats);
3070 ret = rte_eth_xstats_get(port_id, xstats, expected_entries);
3074 num_xstats_filled = (unsigned int)ret;
3076 /* Return all stats */
3078 for (i = 0; i < num_xstats_filled; i++)
3079 values[i] = xstats[i].value;
3080 return expected_entries;
3084 for (i = 0; i < size; i++) {
3085 if (ids[i] >= expected_entries) {
3086 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
3089 values[i] = xstats[ids[i]].value;
3095 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats,
3098 struct rte_eth_dev *dev;
3099 unsigned int count = 0, i;
3100 signed int xcount = 0;
3101 uint16_t nb_rxqs, nb_txqs;
3104 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
3106 dev = &rte_eth_devices[port_id];
3108 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
3109 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
3111 /* Return generic statistics */
3112 count = RTE_NB_STATS + (nb_rxqs * RTE_NB_RXQ_STATS) +
3113 (nb_txqs * RTE_NB_TXQ_STATS);
3115 /* implemented by the driver */
3116 if (dev->dev_ops->xstats_get != NULL) {
3117 /* Retrieve the xstats from the driver at the end of the
3120 xcount = (*dev->dev_ops->xstats_get)(dev,
3121 xstats ? xstats + count : NULL,
3122 (n > count) ? n - count : 0);
3125 return eth_err(port_id, xcount);
3128 if (n < count + xcount || xstats == NULL)
3129 return count + xcount;
3131 /* now fill the xstats structure */
3132 ret = rte_eth_basic_stats_get(port_id, xstats);
3137 for (i = 0; i < count; i++)
3139 /* add an offset to driver-specific stats */
3140 for ( ; i < count + xcount; i++)
3141 xstats[i].id += count;
3143 return count + xcount;
3146 /* reset ethdev extended statistics */
3148 rte_eth_xstats_reset(uint16_t port_id)
3150 struct rte_eth_dev *dev;
3152 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3153 dev = &rte_eth_devices[port_id];
3155 /* implemented by the driver */
3156 if (dev->dev_ops->xstats_reset != NULL)
3157 return eth_err(port_id, (*dev->dev_ops->xstats_reset)(dev));
3159 /* fallback to default */
3160 return rte_eth_stats_reset(port_id);
3164 set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id, uint8_t stat_idx,
3167 struct rte_eth_dev *dev;
3169 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3171 dev = &rte_eth_devices[port_id];
3173 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP);
3175 if (is_rx && (queue_id >= dev->data->nb_rx_queues))
3178 if (!is_rx && (queue_id >= dev->data->nb_tx_queues))
3181 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
3184 return (*dev->dev_ops->queue_stats_mapping_set)
3185 (dev, queue_id, stat_idx, is_rx);
3190 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id,
3193 return eth_err(port_id, set_queue_stats_mapping(port_id, tx_queue_id,
3194 stat_idx, STAT_QMAP_TX));
3199 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id,
3202 return eth_err(port_id, set_queue_stats_mapping(port_id, rx_queue_id,
3203 stat_idx, STAT_QMAP_RX));
3207 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size)
3209 struct rte_eth_dev *dev;
3211 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3212 dev = &rte_eth_devices[port_id];
3214 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fw_version_get, -ENOTSUP);
3215 return eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev,
3216 fw_version, fw_size));
3220 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info)
3222 struct rte_eth_dev *dev;
3223 const struct rte_eth_desc_lim lim = {
3224 .nb_max = UINT16_MAX,
3227 .nb_seg_max = UINT16_MAX,
3228 .nb_mtu_seg_max = UINT16_MAX,
3233 * Init dev_info before port_id check since caller does not have
3234 * return status and does not know if get is successful or not.
3236 memset(dev_info, 0, sizeof(struct rte_eth_dev_info));
3237 dev_info->switch_info.domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
3239 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3240 dev = &rte_eth_devices[port_id];
3242 dev_info->rx_desc_lim = lim;
3243 dev_info->tx_desc_lim = lim;
3244 dev_info->device = dev->device;
3245 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3246 dev_info->max_mtu = UINT16_MAX;
3248 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);
3249 diag = (*dev->dev_ops->dev_infos_get)(dev, dev_info);
3251 /* Cleanup already filled in device information */
3252 memset(dev_info, 0, sizeof(struct rte_eth_dev_info));
3253 return eth_err(port_id, diag);
3256 /* Maximum number of queues should be <= RTE_MAX_QUEUES_PER_PORT */
3257 dev_info->max_rx_queues = RTE_MIN(dev_info->max_rx_queues,
3258 RTE_MAX_QUEUES_PER_PORT);
3259 dev_info->max_tx_queues = RTE_MIN(dev_info->max_tx_queues,
3260 RTE_MAX_QUEUES_PER_PORT);
3262 dev_info->driver_name = dev->device->driver->name;
3263 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3264 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3266 dev_info->dev_flags = &dev->data->dev_flags;
3272 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,
3273 uint32_t *ptypes, int num)
3276 struct rte_eth_dev *dev;
3277 const uint32_t *all_ptypes;
3279 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3280 dev = &rte_eth_devices[port_id];
3281 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_supported_ptypes_get, 0);
3282 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
3287 for (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i)
3288 if (all_ptypes[i] & ptype_mask) {
3290 ptypes[j] = all_ptypes[i];
3298 rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask,
3299 uint32_t *set_ptypes, unsigned int num)
3301 const uint32_t valid_ptype_masks[] = {
3305 RTE_PTYPE_TUNNEL_MASK,
3306 RTE_PTYPE_INNER_L2_MASK,
3307 RTE_PTYPE_INNER_L3_MASK,
3308 RTE_PTYPE_INNER_L4_MASK,
3310 const uint32_t *all_ptypes;
3311 struct rte_eth_dev *dev;
3312 uint32_t unused_mask;
3316 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3317 dev = &rte_eth_devices[port_id];
3319 if (num > 0 && set_ptypes == NULL)
3322 if (*dev->dev_ops->dev_supported_ptypes_get == NULL ||
3323 *dev->dev_ops->dev_ptypes_set == NULL) {
3328 if (ptype_mask == 0) {
3329 ret = (*dev->dev_ops->dev_ptypes_set)(dev,
3334 unused_mask = ptype_mask;
3335 for (i = 0; i < RTE_DIM(valid_ptype_masks); i++) {
3336 uint32_t mask = ptype_mask & valid_ptype_masks[i];
3337 if (mask && mask != valid_ptype_masks[i]) {
3341 unused_mask &= ~valid_ptype_masks[i];
3349 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
3350 if (all_ptypes == NULL) {
3356 * Accommodate as many set_ptypes as possible. If the supplied
3357 * set_ptypes array is insufficient fill it partially.
3359 for (i = 0, j = 0; set_ptypes != NULL &&
3360 (all_ptypes[i] != RTE_PTYPE_UNKNOWN); ++i) {
3361 if (ptype_mask & all_ptypes[i]) {
3363 set_ptypes[j] = all_ptypes[i];
3371 if (set_ptypes != NULL && j < num)
3372 set_ptypes[j] = RTE_PTYPE_UNKNOWN;
3374 return (*dev->dev_ops->dev_ptypes_set)(dev, ptype_mask);
3378 set_ptypes[0] = RTE_PTYPE_UNKNOWN;
3384 rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr)
3386 struct rte_eth_dev *dev;
3388 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3389 dev = &rte_eth_devices[port_id];
3390 rte_ether_addr_copy(&dev->data->mac_addrs[0], mac_addr);
3396 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu)
3398 struct rte_eth_dev *dev;
3400 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3402 dev = &rte_eth_devices[port_id];
3403 *mtu = dev->data->mtu;
3408 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu)
3411 struct rte_eth_dev_info dev_info;
3412 struct rte_eth_dev *dev;
3414 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3415 dev = &rte_eth_devices[port_id];
3416 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP);
3419 * Check if the device supports dev_infos_get, if it does not
3420 * skip min_mtu/max_mtu validation here as this requires values
3421 * that are populated within the call to rte_eth_dev_info_get()
3422 * which relies on dev->dev_ops->dev_infos_get.
3424 if (*dev->dev_ops->dev_infos_get != NULL) {
3425 ret = rte_eth_dev_info_get(port_id, &dev_info);
3429 if (mtu < dev_info.min_mtu || mtu > dev_info.max_mtu)
3433 ret = (*dev->dev_ops->mtu_set)(dev, mtu);
3435 dev->data->mtu = mtu;
3437 return eth_err(port_id, ret);
3441 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on)
3443 struct rte_eth_dev *dev;
3446 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3447 dev = &rte_eth_devices[port_id];
3448 if (!(dev->data->dev_conf.rxmode.offloads &
3449 DEV_RX_OFFLOAD_VLAN_FILTER)) {
3450 RTE_ETHDEV_LOG(ERR, "Port %u: vlan-filtering disabled\n",
3455 if (vlan_id > 4095) {
3456 RTE_ETHDEV_LOG(ERR, "Port_id=%u invalid vlan_id=%u > 4095\n",
3460 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP);
3462 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on);
3464 struct rte_vlan_filter_conf *vfc;
3468 vfc = &dev->data->vlan_filter_conf;
3469 vidx = vlan_id / 64;
3470 vbit = vlan_id % 64;
3473 vfc->ids[vidx] |= UINT64_C(1) << vbit;
3475 vfc->ids[vidx] &= ~(UINT64_C(1) << vbit);
3478 return eth_err(port_id, ret);
3482 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id,
3485 struct rte_eth_dev *dev;
3487 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3488 dev = &rte_eth_devices[port_id];
3489 if (rx_queue_id >= dev->data->nb_rx_queues) {
3490 RTE_ETHDEV_LOG(ERR, "Invalid rx_queue_id=%u\n", rx_queue_id);
3494 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
3495 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on);
3501 rte_eth_dev_set_vlan_ether_type(uint16_t port_id,
3502 enum rte_vlan_type vlan_type,
3505 struct rte_eth_dev *dev;
3507 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3508 dev = &rte_eth_devices[port_id];
3509 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP);
3511 return eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type,
3516 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask)
3518 struct rte_eth_dev_info dev_info;
3519 struct rte_eth_dev *dev;
3523 uint64_t orig_offloads;
3524 uint64_t dev_offloads;
3525 uint64_t new_offloads;
3527 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3528 dev = &rte_eth_devices[port_id];
3530 /* save original values in case of failure */
3531 orig_offloads = dev->data->dev_conf.rxmode.offloads;
3532 dev_offloads = orig_offloads;
3534 /* check which option changed by application */
3535 cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD);
3536 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
3539 dev_offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
3541 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
3542 mask |= ETH_VLAN_STRIP_MASK;
3545 cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD);
3546 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER);
3549 dev_offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
3551 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_FILTER;
3552 mask |= ETH_VLAN_FILTER_MASK;
3555 cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD);
3556 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND);
3559 dev_offloads |= DEV_RX_OFFLOAD_VLAN_EXTEND;
3561 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_EXTEND;
3562 mask |= ETH_VLAN_EXTEND_MASK;
3565 cur = !!(offload_mask & ETH_QINQ_STRIP_OFFLOAD);
3566 org = !!(dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP);
3569 dev_offloads |= DEV_RX_OFFLOAD_QINQ_STRIP;
3571 dev_offloads &= ~DEV_RX_OFFLOAD_QINQ_STRIP;
3572 mask |= ETH_QINQ_STRIP_MASK;
3579 ret = rte_eth_dev_info_get(port_id, &dev_info);
3583 /* Rx VLAN offloading must be within its device capabilities */
3584 if ((dev_offloads & dev_info.rx_offload_capa) != dev_offloads) {
3585 new_offloads = dev_offloads & ~orig_offloads;
3587 "Ethdev port_id=%u requested new added VLAN offloads "
3588 "0x%" PRIx64 " must be within Rx offloads capabilities "
3589 "0x%" PRIx64 " in %s()\n",
3590 port_id, new_offloads, dev_info.rx_offload_capa,
3595 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP);
3596 dev->data->dev_conf.rxmode.offloads = dev_offloads;
3597 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask);
3599 /* hit an error restore original values */
3600 dev->data->dev_conf.rxmode.offloads = orig_offloads;
3603 return eth_err(port_id, ret);
3607 rte_eth_dev_get_vlan_offload(uint16_t port_id)
3609 struct rte_eth_dev *dev;
3610 uint64_t *dev_offloads;
3613 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3614 dev = &rte_eth_devices[port_id];
3615 dev_offloads = &dev->data->dev_conf.rxmode.offloads;
3617 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3618 ret |= ETH_VLAN_STRIP_OFFLOAD;
3620 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3621 ret |= ETH_VLAN_FILTER_OFFLOAD;
3623 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3624 ret |= ETH_VLAN_EXTEND_OFFLOAD;
3626 if (*dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
3627 ret |= ETH_QINQ_STRIP_OFFLOAD;
3633 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on)
3635 struct rte_eth_dev *dev;
3637 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3638 dev = &rte_eth_devices[port_id];
3639 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP);
3641 return eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on));
3645 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
3647 struct rte_eth_dev *dev;
3649 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3650 dev = &rte_eth_devices[port_id];
3651 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP);
3652 memset(fc_conf, 0, sizeof(*fc_conf));
3653 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf));
3657 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
3659 struct rte_eth_dev *dev;
3661 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3662 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) {
3663 RTE_ETHDEV_LOG(ERR, "Invalid send_xon, only 0/1 allowed\n");
3667 dev = &rte_eth_devices[port_id];
3668 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP);
3669 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf));
3673 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,
3674 struct rte_eth_pfc_conf *pfc_conf)
3676 struct rte_eth_dev *dev;
3678 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3679 if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) {
3680 RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n");
3684 dev = &rte_eth_devices[port_id];
3685 /* High water, low water validation are device specific */
3686 if (*dev->dev_ops->priority_flow_ctrl_set)
3687 return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set)
3693 rte_eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,
3701 num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE;
3702 for (i = 0; i < num; i++) {
3703 if (reta_conf[i].mask)
3711 rte_eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf,
3715 uint16_t i, idx, shift;
3721 RTE_ETHDEV_LOG(ERR, "No receive queue is available\n");
3725 for (i = 0; i < reta_size; i++) {
3726 idx = i / RTE_RETA_GROUP_SIZE;
3727 shift = i % RTE_RETA_GROUP_SIZE;
3728 if ((reta_conf[idx].mask & (1ULL << shift)) &&
3729 (reta_conf[idx].reta[shift] >= max_rxq)) {
3731 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n",
3733 reta_conf[idx].reta[shift], max_rxq);
3742 rte_eth_dev_rss_reta_update(uint16_t port_id,
3743 struct rte_eth_rss_reta_entry64 *reta_conf,
3746 struct rte_eth_dev *dev;
3749 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3750 /* Check mask bits */
3751 ret = rte_eth_check_reta_mask(reta_conf, reta_size);
3755 dev = &rte_eth_devices[port_id];
3757 /* Check entry value */
3758 ret = rte_eth_check_reta_entry(reta_conf, reta_size,
3759 dev->data->nb_rx_queues);
3763 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP);
3764 return eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf,
3769 rte_eth_dev_rss_reta_query(uint16_t port_id,
3770 struct rte_eth_rss_reta_entry64 *reta_conf,
3773 struct rte_eth_dev *dev;
3776 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3778 /* Check mask bits */
3779 ret = rte_eth_check_reta_mask(reta_conf, reta_size);
3783 dev = &rte_eth_devices[port_id];
3784 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP);
3785 return eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf,
3790 rte_eth_dev_rss_hash_update(uint16_t port_id,
3791 struct rte_eth_rss_conf *rss_conf)
3793 struct rte_eth_dev *dev;
3794 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, };
3797 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3799 ret = rte_eth_dev_info_get(port_id, &dev_info);
3803 rss_conf->rss_hf = rte_eth_rss_hf_refine(rss_conf->rss_hf);
3805 dev = &rte_eth_devices[port_id];
3806 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) !=
3807 dev_info.flow_type_rss_offloads) {
3809 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
3810 port_id, rss_conf->rss_hf,
3811 dev_info.flow_type_rss_offloads);
3814 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP);
3815 return eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev,
3820 rte_eth_dev_rss_hash_conf_get(uint16_t port_id,
3821 struct rte_eth_rss_conf *rss_conf)
3823 struct rte_eth_dev *dev;
3825 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3826 dev = &rte_eth_devices[port_id];
3827 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP);
3828 return eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev,
3833 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,
3834 struct rte_eth_udp_tunnel *udp_tunnel)
3836 struct rte_eth_dev *dev;
3838 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3839 if (udp_tunnel == NULL) {
3840 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3844 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3845 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3849 dev = &rte_eth_devices[port_id];
3850 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_add, -ENOTSUP);
3851 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev,
3856 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,
3857 struct rte_eth_udp_tunnel *udp_tunnel)
3859 struct rte_eth_dev *dev;
3861 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3862 dev = &rte_eth_devices[port_id];
3864 if (udp_tunnel == NULL) {
3865 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3869 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3870 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3874 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_del, -ENOTSUP);
3875 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev,
3880 rte_eth_led_on(uint16_t port_id)
3882 struct rte_eth_dev *dev;
3884 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3885 dev = &rte_eth_devices[port_id];
3886 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP);
3887 return eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev));
3891 rte_eth_led_off(uint16_t port_id)
3893 struct rte_eth_dev *dev;
3895 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3896 dev = &rte_eth_devices[port_id];
3897 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP);
3898 return eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev));
3902 rte_eth_fec_get_capability(uint16_t port_id,
3903 struct rte_eth_fec_capa *speed_fec_capa,
3906 struct rte_eth_dev *dev;
3909 if (speed_fec_capa == NULL && num > 0)
3912 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3913 dev = &rte_eth_devices[port_id];
3914 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get_capability, -ENOTSUP);
3915 ret = (*dev->dev_ops->fec_get_capability)(dev, speed_fec_capa, num);
3921 rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa)
3923 struct rte_eth_dev *dev;
3925 if (fec_capa == NULL)
3928 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3929 dev = &rte_eth_devices[port_id];
3930 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get, -ENOTSUP);
3931 return eth_err(port_id, (*dev->dev_ops->fec_get)(dev, fec_capa));
3935 rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa)
3937 struct rte_eth_dev *dev;
3939 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3940 dev = &rte_eth_devices[port_id];
3941 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_set, -ENOTSUP);
3942 return eth_err(port_id, (*dev->dev_ops->fec_set)(dev, fec_capa));
3946 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
3950 get_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr)
3952 struct rte_eth_dev_info dev_info;
3953 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3957 ret = rte_eth_dev_info_get(port_id, &dev_info);
3961 for (i = 0; i < dev_info.max_mac_addrs; i++)
3962 if (memcmp(addr, &dev->data->mac_addrs[i],
3963 RTE_ETHER_ADDR_LEN) == 0)
3969 static const struct rte_ether_addr null_mac_addr;
3972 rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr,
3975 struct rte_eth_dev *dev;
3980 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3981 dev = &rte_eth_devices[port_id];
3982 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP);
3984 if (rte_is_zero_ether_addr(addr)) {
3985 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
3989 if (pool >= ETH_64_POOLS) {
3990 RTE_ETHDEV_LOG(ERR, "Pool id must be 0-%d\n", ETH_64_POOLS - 1);
3994 index = get_mac_addr_index(port_id, addr);
3996 index = get_mac_addr_index(port_id, &null_mac_addr);
3998 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
4003 pool_mask = dev->data->mac_pool_sel[index];
4005 /* Check if both MAC address and pool is already there, and do nothing */
4006 if (pool_mask & (1ULL << pool))
4011 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool);
4014 /* Update address in NIC data structure */
4015 rte_ether_addr_copy(addr, &dev->data->mac_addrs[index]);
4017 /* Update pool bitmap in NIC data structure */
4018 dev->data->mac_pool_sel[index] |= (1ULL << pool);
4021 return eth_err(port_id, ret);
4025 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *addr)
4027 struct rte_eth_dev *dev;
4030 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4031 dev = &rte_eth_devices[port_id];
4032 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP);
4034 index = get_mac_addr_index(port_id, addr);
4037 "Port %u: Cannot remove default MAC address\n",
4040 } else if (index < 0)
4041 return 0; /* Do nothing if address wasn't found */
4044 (*dev->dev_ops->mac_addr_remove)(dev, index);
4046 /* Update address in NIC data structure */
4047 rte_ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]);
4049 /* reset pool bitmap */
4050 dev->data->mac_pool_sel[index] = 0;
4056 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *addr)
4058 struct rte_eth_dev *dev;
4061 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4063 if (!rte_is_valid_assigned_ether_addr(addr))
4066 dev = &rte_eth_devices[port_id];
4067 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP);
4069 ret = (*dev->dev_ops->mac_addr_set)(dev, addr);
4073 /* Update default address in NIC data structure */
4074 rte_ether_addr_copy(addr, &dev->data->mac_addrs[0]);
4081 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
4085 get_hash_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr)
4087 struct rte_eth_dev_info dev_info;
4088 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4092 ret = rte_eth_dev_info_get(port_id, &dev_info);
4096 if (!dev->data->hash_mac_addrs)
4099 for (i = 0; i < dev_info.max_hash_mac_addrs; i++)
4100 if (memcmp(addr, &dev->data->hash_mac_addrs[i],
4101 RTE_ETHER_ADDR_LEN) == 0)
4108 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr,
4113 struct rte_eth_dev *dev;
4115 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4117 dev = &rte_eth_devices[port_id];
4118 if (rte_is_zero_ether_addr(addr)) {
4119 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
4124 index = get_hash_mac_addr_index(port_id, addr);
4125 /* Check if it's already there, and do nothing */
4126 if ((index >= 0) && on)
4132 "Port %u: the MAC address was not set in UTA\n",
4137 index = get_hash_mac_addr_index(port_id, &null_mac_addr);
4139 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
4145 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP);
4146 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on);
4148 /* Update address in NIC data structure */
4150 rte_ether_addr_copy(addr,
4151 &dev->data->hash_mac_addrs[index]);
4153 rte_ether_addr_copy(&null_mac_addr,
4154 &dev->data->hash_mac_addrs[index]);
4157 return eth_err(port_id, ret);
4161 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on)
4163 struct rte_eth_dev *dev;
4165 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4167 dev = &rte_eth_devices[port_id];
4169 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP);
4170 return eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev,
4174 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,
4177 struct rte_eth_dev *dev;
4178 struct rte_eth_dev_info dev_info;
4179 struct rte_eth_link link;
4182 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4184 ret = rte_eth_dev_info_get(port_id, &dev_info);
4188 dev = &rte_eth_devices[port_id];
4189 link = dev->data->dev_link;
4191 if (queue_idx > dev_info.max_tx_queues) {
4193 "Set queue rate limit:port %u: invalid queue id=%u\n",
4194 port_id, queue_idx);
4198 if (tx_rate > link.link_speed) {
4200 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d\n",
4201 tx_rate, link.link_speed);
4205 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP);
4206 return eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev,
4207 queue_idx, tx_rate));
4211 rte_eth_mirror_rule_set(uint16_t port_id,
4212 struct rte_eth_mirror_conf *mirror_conf,
4213 uint8_t rule_id, uint8_t on)
4215 struct rte_eth_dev *dev;
4217 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4218 if (mirror_conf->rule_type == 0) {
4219 RTE_ETHDEV_LOG(ERR, "Mirror rule type can not be 0\n");
4223 if (mirror_conf->dst_pool >= ETH_64_POOLS) {
4224 RTE_ETHDEV_LOG(ERR, "Invalid dst pool, pool id must be 0-%d\n",
4229 if ((mirror_conf->rule_type & (ETH_MIRROR_VIRTUAL_POOL_UP |
4230 ETH_MIRROR_VIRTUAL_POOL_DOWN)) &&
4231 (mirror_conf->pool_mask == 0)) {
4233 "Invalid mirror pool, pool mask can not be 0\n");
4237 if ((mirror_conf->rule_type & ETH_MIRROR_VLAN) &&
4238 mirror_conf->vlan.vlan_mask == 0) {
4240 "Invalid vlan mask, vlan mask can not be 0\n");
4244 dev = &rte_eth_devices[port_id];
4245 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_set, -ENOTSUP);
4247 return eth_err(port_id, (*dev->dev_ops->mirror_rule_set)(dev,
4248 mirror_conf, rule_id, on));
4252 rte_eth_mirror_rule_reset(uint16_t port_id, uint8_t rule_id)
4254 struct rte_eth_dev *dev;
4256 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4258 dev = &rte_eth_devices[port_id];
4259 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_reset, -ENOTSUP);
4261 return eth_err(port_id, (*dev->dev_ops->mirror_rule_reset)(dev,
4265 RTE_INIT(eth_dev_init_cb_lists)
4269 for (i = 0; i < RTE_MAX_ETHPORTS; i++)
4270 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs);
4274 rte_eth_dev_callback_register(uint16_t port_id,
4275 enum rte_eth_event_type event,
4276 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
4278 struct rte_eth_dev *dev;
4279 struct rte_eth_dev_callback *user_cb;
4280 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */
4286 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
4287 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
4291 if (port_id == RTE_ETH_ALL) {
4293 last_port = RTE_MAX_ETHPORTS - 1;
4295 next_port = last_port = port_id;
4298 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4301 dev = &rte_eth_devices[next_port];
4303 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) {
4304 if (user_cb->cb_fn == cb_fn &&
4305 user_cb->cb_arg == cb_arg &&
4306 user_cb->event == event) {
4311 /* create a new callback. */
4312 if (user_cb == NULL) {
4313 user_cb = rte_zmalloc("INTR_USER_CALLBACK",
4314 sizeof(struct rte_eth_dev_callback), 0);
4315 if (user_cb != NULL) {
4316 user_cb->cb_fn = cb_fn;
4317 user_cb->cb_arg = cb_arg;
4318 user_cb->event = event;
4319 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs),
4322 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4323 rte_eth_dev_callback_unregister(port_id, event,
4329 } while (++next_port <= last_port);
4331 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4336 rte_eth_dev_callback_unregister(uint16_t port_id,
4337 enum rte_eth_event_type event,
4338 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
4341 struct rte_eth_dev *dev;
4342 struct rte_eth_dev_callback *cb, *next;
4343 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */
4349 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
4350 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
4354 if (port_id == RTE_ETH_ALL) {
4356 last_port = RTE_MAX_ETHPORTS - 1;
4358 next_port = last_port = port_id;
4361 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4364 dev = &rte_eth_devices[next_port];
4366 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL;
4369 next = TAILQ_NEXT(cb, next);
4371 if (cb->cb_fn != cb_fn || cb->event != event ||
4372 (cb_arg != (void *)-1 && cb->cb_arg != cb_arg))
4376 * if this callback is not executing right now,
4379 if (cb->active == 0) {
4380 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next);
4386 } while (++next_port <= last_port);
4388 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4393 rte_eth_dev_callback_process(struct rte_eth_dev *dev,
4394 enum rte_eth_event_type event, void *ret_param)
4396 struct rte_eth_dev_callback *cb_lst;
4397 struct rte_eth_dev_callback dev_cb;
4400 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4401 TAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) {
4402 if (cb_lst->cb_fn == NULL || cb_lst->event != event)
4406 if (ret_param != NULL)
4407 dev_cb.ret_param = ret_param;
4409 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4410 rc = dev_cb.cb_fn(dev->data->port_id, dev_cb.event,
4411 dev_cb.cb_arg, dev_cb.ret_param);
4412 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4415 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4420 rte_eth_dev_probing_finish(struct rte_eth_dev *dev)
4425 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_NEW, NULL);
4427 dev->state = RTE_ETH_DEV_ATTACHED;
4431 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data)
4434 struct rte_eth_dev *dev;
4435 struct rte_intr_handle *intr_handle;
4439 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4441 dev = &rte_eth_devices[port_id];
4443 if (!dev->intr_handle) {
4444 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4448 intr_handle = dev->intr_handle;
4449 if (!intr_handle->intr_vec) {
4450 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4454 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
4455 vec = intr_handle->intr_vec[qid];
4456 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
4457 if (rc && rc != -EEXIST) {
4459 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
4460 port_id, qid, op, epfd, vec);
4468 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id)
4470 struct rte_intr_handle *intr_handle;
4471 struct rte_eth_dev *dev;
4472 unsigned int efd_idx;
4476 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
4478 dev = &rte_eth_devices[port_id];
4480 if (queue_id >= dev->data->nb_rx_queues) {
4481 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
4485 if (!dev->intr_handle) {
4486 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4490 intr_handle = dev->intr_handle;
4491 if (!intr_handle->intr_vec) {
4492 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4496 vec = intr_handle->intr_vec[queue_id];
4497 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ?
4498 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec;
4499 fd = intr_handle->efds[efd_idx];
4505 eth_dma_mzone_name(char *name, size_t len, uint16_t port_id, uint16_t queue_id,
4506 const char *ring_name)
4508 return snprintf(name, len, "eth_p%d_q%d_%s",
4509 port_id, queue_id, ring_name);
4512 const struct rte_memzone *
4513 rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name,
4514 uint16_t queue_id, size_t size, unsigned align,
4517 char z_name[RTE_MEMZONE_NAMESIZE];
4518 const struct rte_memzone *mz;
4521 rc = eth_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,
4522 queue_id, ring_name);
4523 if (rc >= RTE_MEMZONE_NAMESIZE) {
4524 RTE_ETHDEV_LOG(ERR, "ring name too long\n");
4525 rte_errno = ENAMETOOLONG;
4529 mz = rte_memzone_lookup(z_name);
4531 if ((socket_id != SOCKET_ID_ANY && socket_id != mz->socket_id) ||
4533 ((uintptr_t)mz->addr & (align - 1)) != 0) {
4535 "memzone %s does not justify the requested attributes\n",
4543 return rte_memzone_reserve_aligned(z_name, size, socket_id,
4544 RTE_MEMZONE_IOVA_CONTIG, align);
4548 rte_eth_dma_zone_free(const struct rte_eth_dev *dev, const char *ring_name,
4551 char z_name[RTE_MEMZONE_NAMESIZE];
4552 const struct rte_memzone *mz;
4555 rc = eth_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,
4556 queue_id, ring_name);
4557 if (rc >= RTE_MEMZONE_NAMESIZE) {
4558 RTE_ETHDEV_LOG(ERR, "ring name too long\n");
4559 return -ENAMETOOLONG;
4562 mz = rte_memzone_lookup(z_name);
4564 rc = rte_memzone_free(mz);
4572 rte_eth_dev_create(struct rte_device *device, const char *name,
4573 size_t priv_data_size,
4574 ethdev_bus_specific_init ethdev_bus_specific_init,
4575 void *bus_init_params,
4576 ethdev_init_t ethdev_init, void *init_params)
4578 struct rte_eth_dev *ethdev;
4581 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL);
4583 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
4584 ethdev = rte_eth_dev_allocate(name);
4588 if (priv_data_size) {
4589 ethdev->data->dev_private = rte_zmalloc_socket(
4590 name, priv_data_size, RTE_CACHE_LINE_SIZE,
4593 if (!ethdev->data->dev_private) {
4595 "failed to allocate private data\n");
4601 ethdev = rte_eth_dev_attach_secondary(name);
4604 "secondary process attach failed, ethdev doesn't exist\n");
4609 ethdev->device = device;
4611 if (ethdev_bus_specific_init) {
4612 retval = ethdev_bus_specific_init(ethdev, bus_init_params);
4615 "ethdev bus specific initialisation failed\n");
4620 retval = ethdev_init(ethdev, init_params);
4622 RTE_ETHDEV_LOG(ERR, "ethdev initialisation failed\n");
4626 rte_eth_dev_probing_finish(ethdev);
4631 rte_eth_dev_release_port(ethdev);
4636 rte_eth_dev_destroy(struct rte_eth_dev *ethdev,
4637 ethdev_uninit_t ethdev_uninit)
4641 ethdev = rte_eth_dev_allocated(ethdev->data->name);
4645 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_uninit, -EINVAL);
4647 ret = ethdev_uninit(ethdev);
4651 return rte_eth_dev_release_port(ethdev);
4655 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id,
4656 int epfd, int op, void *data)
4659 struct rte_eth_dev *dev;
4660 struct rte_intr_handle *intr_handle;
4663 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4665 dev = &rte_eth_devices[port_id];
4666 if (queue_id >= dev->data->nb_rx_queues) {
4667 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
4671 if (!dev->intr_handle) {
4672 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4676 intr_handle = dev->intr_handle;
4677 if (!intr_handle->intr_vec) {
4678 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4682 vec = intr_handle->intr_vec[queue_id];
4683 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
4684 if (rc && rc != -EEXIST) {
4686 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
4687 port_id, queue_id, op, epfd, vec);
4695 rte_eth_dev_rx_intr_enable(uint16_t port_id,
4698 struct rte_eth_dev *dev;
4701 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4703 dev = &rte_eth_devices[port_id];
4705 ret = eth_dev_validate_rx_queue(dev, queue_id);
4709 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP);
4710 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev,
4715 rte_eth_dev_rx_intr_disable(uint16_t port_id,
4718 struct rte_eth_dev *dev;
4721 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4723 dev = &rte_eth_devices[port_id];
4725 ret = eth_dev_validate_rx_queue(dev, queue_id);
4729 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP);
4730 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev,
4736 rte_eth_dev_filter_supported(uint16_t port_id,
4737 enum rte_filter_type filter_type)
4739 struct rte_eth_dev *dev;
4741 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4743 dev = &rte_eth_devices[port_id];
4744 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);
4745 return (*dev->dev_ops->filter_ctrl)(dev, filter_type,
4746 RTE_ETH_FILTER_NOP, NULL);
4750 rte_eth_dev_filter_ctrl(uint16_t port_id, enum rte_filter_type filter_type,
4751 enum rte_filter_op filter_op, void *arg)
4753 struct rte_eth_dev *dev;
4755 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4757 dev = &rte_eth_devices[port_id];
4758 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);
4759 return eth_err(port_id, (*dev->dev_ops->filter_ctrl)(dev, filter_type,
4763 const struct rte_eth_rxtx_callback *
4764 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id,
4765 rte_rx_callback_fn fn, void *user_param)
4767 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4768 rte_errno = ENOTSUP;
4771 struct rte_eth_dev *dev;
4773 /* check input parameters */
4774 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4775 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
4779 dev = &rte_eth_devices[port_id];
4780 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
4784 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4792 cb->param = user_param;
4794 rte_spinlock_lock(&rte_eth_rx_cb_lock);
4795 /* Add the callbacks in fifo order. */
4796 struct rte_eth_rxtx_callback *tail =
4797 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
4800 /* Stores to cb->fn and cb->param should complete before
4801 * cb is visible to data plane.
4804 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id],
4805 cb, __ATOMIC_RELEASE);
4810 /* Stores to cb->fn and cb->param should complete before
4811 * cb is visible to data plane.
4813 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE);
4815 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
4820 const struct rte_eth_rxtx_callback *
4821 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id,
4822 rte_rx_callback_fn fn, void *user_param)
4824 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4825 rte_errno = ENOTSUP;
4828 /* check input parameters */
4829 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4830 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
4835 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4843 cb->param = user_param;
4845 rte_spinlock_lock(&rte_eth_rx_cb_lock);
4846 /* Add the callbacks at first position */
4847 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
4848 /* Stores to cb->fn, cb->param and cb->next should complete before
4849 * cb is visible to data plane threads.
4852 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id],
4853 cb, __ATOMIC_RELEASE);
4854 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
4859 const struct rte_eth_rxtx_callback *
4860 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id,
4861 rte_tx_callback_fn fn, void *user_param)
4863 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4864 rte_errno = ENOTSUP;
4867 struct rte_eth_dev *dev;
4869 /* check input parameters */
4870 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4871 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) {
4876 dev = &rte_eth_devices[port_id];
4877 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
4882 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4890 cb->param = user_param;
4892 rte_spinlock_lock(&rte_eth_tx_cb_lock);
4893 /* Add the callbacks in fifo order. */
4894 struct rte_eth_rxtx_callback *tail =
4895 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id];
4898 /* Stores to cb->fn and cb->param should complete before
4899 * cb is visible to data plane.
4902 &rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id],
4903 cb, __ATOMIC_RELEASE);
4908 /* Stores to cb->fn and cb->param should complete before
4909 * cb is visible to data plane.
4911 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE);
4913 rte_spinlock_unlock(&rte_eth_tx_cb_lock);
4919 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id,
4920 const struct rte_eth_rxtx_callback *user_cb)
4922 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4925 /* Check input parameters. */
4926 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
4927 if (user_cb == NULL ||
4928 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues)
4931 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4932 struct rte_eth_rxtx_callback *cb;
4933 struct rte_eth_rxtx_callback **prev_cb;
4936 rte_spinlock_lock(&rte_eth_rx_cb_lock);
4937 prev_cb = &dev->post_rx_burst_cbs[queue_id];
4938 for (; *prev_cb != NULL; prev_cb = &cb->next) {
4940 if (cb == user_cb) {
4941 /* Remove the user cb from the callback list. */
4942 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED);
4947 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
4953 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id,
4954 const struct rte_eth_rxtx_callback *user_cb)
4956 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4959 /* Check input parameters. */
4960 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
4961 if (user_cb == NULL ||
4962 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues)
4965 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4967 struct rte_eth_rxtx_callback *cb;
4968 struct rte_eth_rxtx_callback **prev_cb;
4970 rte_spinlock_lock(&rte_eth_tx_cb_lock);
4971 prev_cb = &dev->pre_tx_burst_cbs[queue_id];
4972 for (; *prev_cb != NULL; prev_cb = &cb->next) {
4974 if (cb == user_cb) {
4975 /* Remove the user cb from the callback list. */
4976 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED);
4981 rte_spinlock_unlock(&rte_eth_tx_cb_lock);
4987 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id,
4988 struct rte_eth_rxq_info *qinfo)
4990 struct rte_eth_dev *dev;
4992 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4997 dev = &rte_eth_devices[port_id];
4998 if (queue_id >= dev->data->nb_rx_queues) {
4999 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
5003 if (dev->data->rx_queues == NULL ||
5004 dev->data->rx_queues[queue_id] == NULL) {
5006 "Rx queue %"PRIu16" of device with port_id=%"
5007 PRIu16" has not been setup\n",
5012 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
5013 RTE_ETHDEV_LOG(INFO,
5014 "Can't get hairpin Rx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
5019 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP);
5021 memset(qinfo, 0, sizeof(*qinfo));
5022 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo);
5027 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id,
5028 struct rte_eth_txq_info *qinfo)
5030 struct rte_eth_dev *dev;
5032 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5037 dev = &rte_eth_devices[port_id];
5038 if (queue_id >= dev->data->nb_tx_queues) {
5039 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
5043 if (dev->data->tx_queues == NULL ||
5044 dev->data->tx_queues[queue_id] == NULL) {
5046 "Tx queue %"PRIu16" of device with port_id=%"
5047 PRIu16" has not been setup\n",
5052 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
5053 RTE_ETHDEV_LOG(INFO,
5054 "Can't get hairpin Tx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
5059 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP);
5061 memset(qinfo, 0, sizeof(*qinfo));
5062 dev->dev_ops->txq_info_get(dev, queue_id, qinfo);
5068 rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
5069 struct rte_eth_burst_mode *mode)
5071 struct rte_eth_dev *dev;
5073 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5078 dev = &rte_eth_devices[port_id];
5080 if (queue_id >= dev->data->nb_rx_queues) {
5081 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
5085 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_burst_mode_get, -ENOTSUP);
5086 memset(mode, 0, sizeof(*mode));
5087 return eth_err(port_id,
5088 dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode));
5092 rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
5093 struct rte_eth_burst_mode *mode)
5095 struct rte_eth_dev *dev;
5097 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5102 dev = &rte_eth_devices[port_id];
5104 if (queue_id >= dev->data->nb_tx_queues) {
5105 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
5109 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_burst_mode_get, -ENOTSUP);
5110 memset(mode, 0, sizeof(*mode));
5111 return eth_err(port_id,
5112 dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode));
5116 rte_eth_dev_set_mc_addr_list(uint16_t port_id,
5117 struct rte_ether_addr *mc_addr_set,
5118 uint32_t nb_mc_addr)
5120 struct rte_eth_dev *dev;
5122 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5124 dev = &rte_eth_devices[port_id];
5125 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP);
5126 return eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev,
5127 mc_addr_set, nb_mc_addr));
5131 rte_eth_timesync_enable(uint16_t port_id)
5133 struct rte_eth_dev *dev;
5135 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5136 dev = &rte_eth_devices[port_id];
5138 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP);
5139 return eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev));
5143 rte_eth_timesync_disable(uint16_t port_id)
5145 struct rte_eth_dev *dev;
5147 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5148 dev = &rte_eth_devices[port_id];
5150 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP);
5151 return eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev));
5155 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp,
5158 struct rte_eth_dev *dev;
5160 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5161 dev = &rte_eth_devices[port_id];
5163 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP);
5164 return eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp)
5165 (dev, timestamp, flags));
5169 rte_eth_timesync_read_tx_timestamp(uint16_t port_id,
5170 struct timespec *timestamp)
5172 struct rte_eth_dev *dev;
5174 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5175 dev = &rte_eth_devices[port_id];
5177 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP);
5178 return eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp)
5183 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta)
5185 struct rte_eth_dev *dev;
5187 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5188 dev = &rte_eth_devices[port_id];
5190 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_adjust_time, -ENOTSUP);
5191 return eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev,
5196 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp)
5198 struct rte_eth_dev *dev;
5200 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5201 dev = &rte_eth_devices[port_id];
5203 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_time, -ENOTSUP);
5204 return eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev,
5209 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp)
5211 struct rte_eth_dev *dev;
5213 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5214 dev = &rte_eth_devices[port_id];
5216 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_write_time, -ENOTSUP);
5217 return eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev,
5222 rte_eth_read_clock(uint16_t port_id, uint64_t *clock)
5224 struct rte_eth_dev *dev;
5226 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5227 dev = &rte_eth_devices[port_id];
5229 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->read_clock, -ENOTSUP);
5230 return eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock));
5234 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)
5236 struct rte_eth_dev *dev;
5238 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5240 dev = &rte_eth_devices[port_id];
5241 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP);
5242 return eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info));
5246 rte_eth_dev_get_eeprom_length(uint16_t port_id)
5248 struct rte_eth_dev *dev;
5250 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5252 dev = &rte_eth_devices[port_id];
5253 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP);
5254 return eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev));
5258 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
5260 struct rte_eth_dev *dev;
5262 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5264 dev = &rte_eth_devices[port_id];
5265 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP);
5266 return eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info));
5270 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
5272 struct rte_eth_dev *dev;
5274 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5276 dev = &rte_eth_devices[port_id];
5277 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP);
5278 return eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info));
5282 rte_eth_dev_get_module_info(uint16_t port_id,
5283 struct rte_eth_dev_module_info *modinfo)
5285 struct rte_eth_dev *dev;
5287 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5289 dev = &rte_eth_devices[port_id];
5290 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_info, -ENOTSUP);
5291 return (*dev->dev_ops->get_module_info)(dev, modinfo);
5295 rte_eth_dev_get_module_eeprom(uint16_t port_id,
5296 struct rte_dev_eeprom_info *info)
5298 struct rte_eth_dev *dev;
5300 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5302 dev = &rte_eth_devices[port_id];
5303 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_eeprom, -ENOTSUP);
5304 return (*dev->dev_ops->get_module_eeprom)(dev, info);
5308 rte_eth_dev_get_dcb_info(uint16_t port_id,
5309 struct rte_eth_dcb_info *dcb_info)
5311 struct rte_eth_dev *dev;
5313 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5315 dev = &rte_eth_devices[port_id];
5316 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info));
5318 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_dcb_info, -ENOTSUP);
5319 return eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info));
5323 rte_eth_dev_l2_tunnel_eth_type_conf(uint16_t port_id,
5324 struct rte_eth_l2_tunnel_conf *l2_tunnel)
5326 struct rte_eth_dev *dev;
5328 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5329 if (l2_tunnel == NULL) {
5330 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n");
5334 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) {
5335 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
5339 dev = &rte_eth_devices[port_id];
5340 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_eth_type_conf,
5342 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_eth_type_conf)(dev,
5347 rte_eth_dev_l2_tunnel_offload_set(uint16_t port_id,
5348 struct rte_eth_l2_tunnel_conf *l2_tunnel,
5352 struct rte_eth_dev *dev;
5354 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5356 if (l2_tunnel == NULL) {
5357 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n");
5361 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) {
5362 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
5367 RTE_ETHDEV_LOG(ERR, "Mask should have a value\n");
5371 dev = &rte_eth_devices[port_id];
5372 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_offload_set,
5374 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_offload_set)(dev,
5375 l2_tunnel, mask, en));
5379 rte_eth_dev_adjust_nb_desc(uint16_t *nb_desc,
5380 const struct rte_eth_desc_lim *desc_lim)
5382 if (desc_lim->nb_align != 0)
5383 *nb_desc = RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_align);
5385 if (desc_lim->nb_max != 0)
5386 *nb_desc = RTE_MIN(*nb_desc, desc_lim->nb_max);
5388 *nb_desc = RTE_MAX(*nb_desc, desc_lim->nb_min);
5392 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id,
5393 uint16_t *nb_rx_desc,
5394 uint16_t *nb_tx_desc)
5396 struct rte_eth_dev_info dev_info;
5399 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5401 ret = rte_eth_dev_info_get(port_id, &dev_info);
5405 if (nb_rx_desc != NULL)
5406 rte_eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim);
5408 if (nb_tx_desc != NULL)
5409 rte_eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim);
5415 rte_eth_dev_hairpin_capability_get(uint16_t port_id,
5416 struct rte_eth_hairpin_cap *cap)
5418 struct rte_eth_dev *dev;
5420 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
5422 dev = &rte_eth_devices[port_id];
5423 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_cap_get, -ENOTSUP);
5424 memset(cap, 0, sizeof(*cap));
5425 return eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap));
5429 rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
5431 if (dev->data->rx_queue_state[queue_id] ==
5432 RTE_ETH_QUEUE_STATE_HAIRPIN)
5438 rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
5440 if (dev->data->tx_queue_state[queue_id] ==
5441 RTE_ETH_QUEUE_STATE_HAIRPIN)
5447 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)
5449 struct rte_eth_dev *dev;
5451 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5456 dev = &rte_eth_devices[port_id];
5458 if (*dev->dev_ops->pool_ops_supported == NULL)
5459 return 1; /* all pools are supported */
5461 return (*dev->dev_ops->pool_ops_supported)(dev, pool);
5465 * A set of values to describe the possible states of a switch domain.
5467 enum rte_eth_switch_domain_state {
5468 RTE_ETH_SWITCH_DOMAIN_UNUSED = 0,
5469 RTE_ETH_SWITCH_DOMAIN_ALLOCATED
5473 * Array of switch domains available for allocation. Array is sized to
5474 * RTE_MAX_ETHPORTS elements as there cannot be more active switch domains than
5475 * ethdev ports in a single process.
5477 static struct rte_eth_dev_switch {
5478 enum rte_eth_switch_domain_state state;
5479 } rte_eth_switch_domains[RTE_MAX_ETHPORTS];
5482 rte_eth_switch_domain_alloc(uint16_t *domain_id)
5486 *domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
5488 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
5489 if (rte_eth_switch_domains[i].state ==
5490 RTE_ETH_SWITCH_DOMAIN_UNUSED) {
5491 rte_eth_switch_domains[i].state =
5492 RTE_ETH_SWITCH_DOMAIN_ALLOCATED;
5502 rte_eth_switch_domain_free(uint16_t domain_id)
5504 if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID ||
5505 domain_id >= RTE_MAX_ETHPORTS)
5508 if (rte_eth_switch_domains[domain_id].state !=
5509 RTE_ETH_SWITCH_DOMAIN_ALLOCATED)
5512 rte_eth_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED;
5518 rte_eth_devargs_tokenise(struct rte_kvargs *arglist, const char *str_in)
5521 struct rte_kvargs_pair *pair;
5524 arglist->str = strdup(str_in);
5525 if (arglist->str == NULL)
5528 letter = arglist->str;
5531 pair = &arglist->pairs[0];
5534 case 0: /* Initial */
5537 else if (*letter == '\0')
5544 case 1: /* Parsing key */
5545 if (*letter == '=') {
5547 pair->value = letter + 1;
5549 } else if (*letter == ',' || *letter == '\0')
5554 case 2: /* Parsing value */
5557 else if (*letter == ',') {
5560 pair = &arglist->pairs[arglist->count];
5562 } else if (*letter == '\0') {
5565 pair = &arglist->pairs[arglist->count];
5570 case 3: /* Parsing list */
5573 else if (*letter == '\0')
5582 rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da)
5584 struct rte_kvargs args;
5585 struct rte_kvargs_pair *pair;
5589 memset(eth_da, 0, sizeof(*eth_da));
5591 result = rte_eth_devargs_tokenise(&args, dargs);
5595 for (i = 0; i < args.count; i++) {
5596 pair = &args.pairs[i];
5597 if (strcmp("representor", pair->key) == 0) {
5598 result = rte_eth_devargs_parse_list(pair->value,
5599 rte_eth_devargs_parse_representor_ports,
5614 handle_port_list(const char *cmd __rte_unused,
5615 const char *params __rte_unused,
5616 struct rte_tel_data *d)
5620 rte_tel_data_start_array(d, RTE_TEL_INT_VAL);
5621 RTE_ETH_FOREACH_DEV(port_id)
5622 rte_tel_data_add_array_int(d, port_id);
5627 add_port_queue_stats(struct rte_tel_data *d, uint64_t *q_stats,
5628 const char *stat_name)
5631 struct rte_tel_data *q_data = rte_tel_data_alloc();
5632 rte_tel_data_start_array(q_data, RTE_TEL_U64_VAL);
5633 for (q = 0; q < RTE_ETHDEV_QUEUE_STAT_CNTRS; q++)
5634 rte_tel_data_add_array_u64(q_data, q_stats[q]);
5635 rte_tel_data_add_dict_container(d, stat_name, q_data, 0);
5638 #define ADD_DICT_STAT(stats, s) rte_tel_data_add_dict_u64(d, #s, stats.s)
5641 handle_port_stats(const char *cmd __rte_unused,
5643 struct rte_tel_data *d)
5645 struct rte_eth_stats stats;
5648 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5651 port_id = atoi(params);
5652 if (!rte_eth_dev_is_valid_port(port_id))
5655 ret = rte_eth_stats_get(port_id, &stats);
5659 rte_tel_data_start_dict(d);
5660 ADD_DICT_STAT(stats, ipackets);
5661 ADD_DICT_STAT(stats, opackets);
5662 ADD_DICT_STAT(stats, ibytes);
5663 ADD_DICT_STAT(stats, obytes);
5664 ADD_DICT_STAT(stats, imissed);
5665 ADD_DICT_STAT(stats, ierrors);
5666 ADD_DICT_STAT(stats, oerrors);
5667 ADD_DICT_STAT(stats, rx_nombuf);
5668 add_port_queue_stats(d, stats.q_ipackets, "q_ipackets");
5669 add_port_queue_stats(d, stats.q_opackets, "q_opackets");
5670 add_port_queue_stats(d, stats.q_ibytes, "q_ibytes");
5671 add_port_queue_stats(d, stats.q_obytes, "q_obytes");
5672 add_port_queue_stats(d, stats.q_errors, "q_errors");
5678 handle_port_xstats(const char *cmd __rte_unused,
5680 struct rte_tel_data *d)
5682 struct rte_eth_xstat *eth_xstats;
5683 struct rte_eth_xstat_name *xstat_names;
5684 int port_id, num_xstats;
5688 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5691 port_id = strtoul(params, &end_param, 0);
5692 if (*end_param != '\0')
5693 RTE_ETHDEV_LOG(NOTICE,
5694 "Extra parameters passed to ethdev telemetry command, ignoring");
5695 if (!rte_eth_dev_is_valid_port(port_id))
5698 num_xstats = rte_eth_xstats_get(port_id, NULL, 0);
5702 /* use one malloc for both names and stats */
5703 eth_xstats = malloc((sizeof(struct rte_eth_xstat) +
5704 sizeof(struct rte_eth_xstat_name)) * num_xstats);
5705 if (eth_xstats == NULL)
5707 xstat_names = (void *)ð_xstats[num_xstats];
5709 ret = rte_eth_xstats_get_names(port_id, xstat_names, num_xstats);
5710 if (ret < 0 || ret > num_xstats) {
5715 ret = rte_eth_xstats_get(port_id, eth_xstats, num_xstats);
5716 if (ret < 0 || ret > num_xstats) {
5721 rte_tel_data_start_dict(d);
5722 for (i = 0; i < num_xstats; i++)
5723 rte_tel_data_add_dict_u64(d, xstat_names[i].name,
5724 eth_xstats[i].value);
5729 handle_port_link_status(const char *cmd __rte_unused,
5731 struct rte_tel_data *d)
5733 static const char *status_str = "status";
5735 struct rte_eth_link link;
5738 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5741 port_id = strtoul(params, &end_param, 0);
5742 if (*end_param != '\0')
5743 RTE_ETHDEV_LOG(NOTICE,
5744 "Extra parameters passed to ethdev telemetry command, ignoring");
5745 if (!rte_eth_dev_is_valid_port(port_id))
5748 ret = rte_eth_link_get(port_id, &link);
5752 rte_tel_data_start_dict(d);
5753 if (!link.link_status) {
5754 rte_tel_data_add_dict_string(d, status_str, "DOWN");
5757 rte_tel_data_add_dict_string(d, status_str, "UP");
5758 rte_tel_data_add_dict_u64(d, "speed", link.link_speed);
5759 rte_tel_data_add_dict_string(d, "duplex",
5760 (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
5761 "full-duplex" : "half-duplex");
5766 rte_eth_hairpin_queue_peer_update(uint16_t peer_port, uint16_t peer_queue,
5767 struct rte_hairpin_peer_info *cur_info,
5768 struct rte_hairpin_peer_info *peer_info,
5771 struct rte_eth_dev *dev;
5773 /* Current queue information is not mandatory. */
5774 if (peer_info == NULL)
5777 /* No need to check the validity again. */
5778 dev = &rte_eth_devices[peer_port];
5779 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_update,
5782 return (*dev->dev_ops->hairpin_queue_peer_update)(dev, peer_queue,
5783 cur_info, peer_info, direction);
5787 rte_eth_hairpin_queue_peer_bind(uint16_t cur_port, uint16_t cur_queue,
5788 struct rte_hairpin_peer_info *peer_info,
5791 struct rte_eth_dev *dev;
5793 if (peer_info == NULL)
5796 /* No need to check the validity again. */
5797 dev = &rte_eth_devices[cur_port];
5798 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_bind,
5801 return (*dev->dev_ops->hairpin_queue_peer_bind)(dev, cur_queue,
5802 peer_info, direction);
5806 rte_eth_hairpin_queue_peer_unbind(uint16_t cur_port, uint16_t cur_queue,
5809 struct rte_eth_dev *dev;
5811 /* No need to check the validity again. */
5812 dev = &rte_eth_devices[cur_port];
5813 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_unbind,
5816 return (*dev->dev_ops->hairpin_queue_peer_unbind)(dev, cur_queue,
5820 RTE_LOG_REGISTER(rte_eth_dev_logtype, lib.ethdev, INFO);
5822 RTE_INIT(ethdev_init_telemetry)
5824 rte_telemetry_register_cmd("/ethdev/list", handle_port_list,
5825 "Returns list of available ethdev ports. Takes no parameters");
5826 rte_telemetry_register_cmd("/ethdev/stats", handle_port_stats,
5827 "Returns the common stats for a port. Parameters: int port_id");
5828 rte_telemetry_register_cmd("/ethdev/xstats", handle_port_xstats,
5829 "Returns the extended stats for a port. Parameters: int port_id");
5830 rte_telemetry_register_cmd("/ethdev/link_status",
5831 handle_port_link_status,
5832 "Returns the link status for a port. Parameters: int port_id");