1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
16 #include <netinet/in.h>
18 #include <rte_byteorder.h>
20 #include <rte_debug.h>
21 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memcpy.h>
24 #include <rte_memzone.h>
25 #include <rte_launch.h>
27 #include <rte_per_lcore.h>
28 #include <rte_lcore.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_common.h>
31 #include <rte_mempool.h>
32 #include <rte_malloc.h>
34 #include <rte_errno.h>
35 #include <rte_spinlock.h>
36 #include <rte_string_fns.h>
37 #include <rte_kvargs.h>
38 #include <rte_class.h>
39 #include <rte_ether.h>
40 #include <rte_telemetry.h>
42 #include "rte_ethdev_trace.h"
43 #include "rte_ethdev.h"
44 #include "rte_ethdev_driver.h"
45 #include "ethdev_profile.h"
46 #include "ethdev_private.h"
48 static const char *MZ_RTE_ETH_DEV_DATA = "rte_eth_dev_data";
49 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS];
51 /* spinlock for eth device callbacks */
52 static rte_spinlock_t rte_eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER;
54 /* spinlock for add/remove rx callbacks */
55 static rte_spinlock_t rte_eth_rx_cb_lock = RTE_SPINLOCK_INITIALIZER;
57 /* spinlock for add/remove tx callbacks */
58 static rte_spinlock_t rte_eth_tx_cb_lock = RTE_SPINLOCK_INITIALIZER;
60 /* spinlock for shared data allocation */
61 static rte_spinlock_t rte_eth_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
63 /* store statistics names and its offset in stats structure */
64 struct rte_eth_xstats_name_off {
65 char name[RTE_ETH_XSTATS_NAME_SIZE];
69 /* Shared memory between primary and secondary processes. */
71 uint64_t next_owner_id;
72 rte_spinlock_t ownership_lock;
73 struct rte_eth_dev_data data[RTE_MAX_ETHPORTS];
74 } *rte_eth_dev_shared_data;
76 static const struct rte_eth_xstats_name_off rte_stats_strings[] = {
77 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)},
78 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)},
79 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)},
80 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)},
81 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)},
82 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)},
83 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)},
84 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats,
88 #define RTE_NB_STATS RTE_DIM(rte_stats_strings)
90 static const struct rte_eth_xstats_name_off rte_rxq_stats_strings[] = {
91 {"packets", offsetof(struct rte_eth_stats, q_ipackets)},
92 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)},
93 {"errors", offsetof(struct rte_eth_stats, q_errors)},
96 #define RTE_NB_RXQ_STATS RTE_DIM(rte_rxq_stats_strings)
98 static const struct rte_eth_xstats_name_off rte_txq_stats_strings[] = {
99 {"packets", offsetof(struct rte_eth_stats, q_opackets)},
100 {"bytes", offsetof(struct rte_eth_stats, q_obytes)},
102 #define RTE_NB_TXQ_STATS RTE_DIM(rte_txq_stats_strings)
104 #define RTE_RX_OFFLOAD_BIT2STR(_name) \
105 { DEV_RX_OFFLOAD_##_name, #_name }
107 #define RTE_ETH_RX_OFFLOAD_BIT2STR(_name) \
108 { RTE_ETH_RX_OFFLOAD_##_name, #_name }
110 static const struct {
113 } rte_rx_offload_names[] = {
114 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP),
115 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM),
116 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM),
117 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM),
118 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO),
119 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP),
120 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
121 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP),
122 RTE_RX_OFFLOAD_BIT2STR(HEADER_SPLIT),
123 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER),
124 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND),
125 RTE_RX_OFFLOAD_BIT2STR(JUMBO_FRAME),
126 RTE_RX_OFFLOAD_BIT2STR(SCATTER),
127 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP),
128 RTE_RX_OFFLOAD_BIT2STR(SECURITY),
129 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC),
130 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM),
131 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
132 RTE_RX_OFFLOAD_BIT2STR(RSS_HASH),
133 RTE_ETH_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT),
136 #undef RTE_RX_OFFLOAD_BIT2STR
137 #undef RTE_ETH_RX_OFFLOAD_BIT2STR
139 #define RTE_TX_OFFLOAD_BIT2STR(_name) \
140 { DEV_TX_OFFLOAD_##_name, #_name }
142 static const struct {
145 } rte_tx_offload_names[] = {
146 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT),
147 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM),
148 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM),
149 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM),
150 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM),
151 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO),
152 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO),
153 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
154 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT),
155 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO),
156 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO),
157 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO),
158 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO),
159 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT),
160 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE),
161 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS),
162 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE),
163 RTE_TX_OFFLOAD_BIT2STR(SECURITY),
164 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO),
165 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO),
166 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
167 RTE_TX_OFFLOAD_BIT2STR(SEND_ON_TIMESTAMP),
170 #undef RTE_TX_OFFLOAD_BIT2STR
173 * The user application callback description.
175 * It contains callback address to be registered by user application,
176 * the pointer to the parameters for callback, and the event type.
178 struct rte_eth_dev_callback {
179 TAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */
180 rte_eth_dev_cb_fn cb_fn; /**< Callback address */
181 void *cb_arg; /**< Parameter for callback */
182 void *ret_param; /**< Return parameter */
183 enum rte_eth_event_type event; /**< Interrupt event type */
184 uint32_t active; /**< Callback is executing */
193 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str)
196 struct rte_devargs devargs = {.args = NULL};
197 const char *bus_param_key;
198 char *bus_str = NULL;
199 char *cls_str = NULL;
202 memset(iter, 0, sizeof(*iter));
205 * The devargs string may use various syntaxes:
206 * - 0000:08:00.0,representor=[1-3]
207 * - pci:0000:06:00.0,representor=[0,5]
208 * - class=eth,mac=00:11:22:33:44:55
209 * A new syntax is in development (not yet supported):
210 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z
214 * Handle pure class filter (i.e. without any bus-level argument),
215 * from future new syntax.
216 * rte_devargs_parse() is not yet supporting the new syntax,
217 * that's why this simple case is temporarily parsed here.
219 #define iter_anybus_str "class=eth,"
220 if (strncmp(devargs_str, iter_anybus_str,
221 strlen(iter_anybus_str)) == 0) {
222 iter->cls_str = devargs_str + strlen(iter_anybus_str);
226 /* Split bus, device and parameters. */
227 ret = rte_devargs_parse(&devargs, devargs_str);
232 * Assume parameters of old syntax can match only at ethdev level.
233 * Extra parameters will be ignored, thanks to "+" prefix.
235 str_size = strlen(devargs.args) + 2;
236 cls_str = malloc(str_size);
237 if (cls_str == NULL) {
241 ret = snprintf(cls_str, str_size, "+%s", devargs.args);
242 if (ret != str_size - 1) {
246 iter->cls_str = cls_str;
247 free(devargs.args); /* allocated by rte_devargs_parse() */
250 iter->bus = devargs.bus;
251 if (iter->bus->dev_iterate == NULL) {
256 /* Convert bus args to new syntax for use with new API dev_iterate. */
257 if (strcmp(iter->bus->name, "vdev") == 0) {
258 bus_param_key = "name";
259 } else if (strcmp(iter->bus->name, "pci") == 0) {
260 bus_param_key = "addr";
265 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2;
266 bus_str = malloc(str_size);
267 if (bus_str == NULL) {
271 ret = snprintf(bus_str, str_size, "%s=%s",
272 bus_param_key, devargs.name);
273 if (ret != str_size - 1) {
277 iter->bus_str = bus_str;
280 iter->cls = rte_class_find_by_name("eth");
285 RTE_ETHDEV_LOG(ERR, "Bus %s does not support iterating.\n",
294 rte_eth_iterator_next(struct rte_dev_iterator *iter)
296 if (iter->cls == NULL) /* invalid ethdev iterator */
297 return RTE_MAX_ETHPORTS;
299 do { /* loop to try all matching rte_device */
300 /* If not pure ethdev filter and */
301 if (iter->bus != NULL &&
302 /* not in middle of rte_eth_dev iteration, */
303 iter->class_device == NULL) {
304 /* get next rte_device to try. */
305 iter->device = iter->bus->dev_iterate(
306 iter->device, iter->bus_str, iter);
307 if (iter->device == NULL)
308 break; /* no more rte_device candidate */
310 /* A device is matching bus part, need to check ethdev part. */
311 iter->class_device = iter->cls->dev_iterate(
312 iter->class_device, iter->cls_str, iter);
313 if (iter->class_device != NULL)
314 return eth_dev_to_id(iter->class_device); /* match */
315 } while (iter->bus != NULL); /* need to try next rte_device */
317 /* No more ethdev port to iterate. */
318 rte_eth_iterator_cleanup(iter);
319 return RTE_MAX_ETHPORTS;
323 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter)
325 if (iter->bus_str == NULL)
326 return; /* nothing to free in pure class filter */
327 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */
328 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */
329 memset(iter, 0, sizeof(*iter));
333 rte_eth_find_next(uint16_t port_id)
335 while (port_id < RTE_MAX_ETHPORTS &&
336 rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)
339 if (port_id >= RTE_MAX_ETHPORTS)
340 return RTE_MAX_ETHPORTS;
346 * Macro to iterate over all valid ports for internal usage.
347 * Note: RTE_ETH_FOREACH_DEV is different because filtering owned ports.
349 #define RTE_ETH_FOREACH_VALID_DEV(port_id) \
350 for (port_id = rte_eth_find_next(0); \
351 port_id < RTE_MAX_ETHPORTS; \
352 port_id = rte_eth_find_next(port_id + 1))
355 rte_eth_find_next_of(uint16_t port_id, const struct rte_device *parent)
357 port_id = rte_eth_find_next(port_id);
358 while (port_id < RTE_MAX_ETHPORTS &&
359 rte_eth_devices[port_id].device != parent)
360 port_id = rte_eth_find_next(port_id + 1);
366 rte_eth_find_next_sibling(uint16_t port_id, uint16_t ref_port_id)
368 RTE_ETH_VALID_PORTID_OR_ERR_RET(ref_port_id, RTE_MAX_ETHPORTS);
369 return rte_eth_find_next_of(port_id,
370 rte_eth_devices[ref_port_id].device);
374 rte_eth_dev_shared_data_prepare(void)
376 const unsigned flags = 0;
377 const struct rte_memzone *mz;
379 rte_spinlock_lock(&rte_eth_shared_data_lock);
381 if (rte_eth_dev_shared_data == NULL) {
382 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
383 /* Allocate port data and ownership shared memory. */
384 mz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA,
385 sizeof(*rte_eth_dev_shared_data),
386 rte_socket_id(), flags);
388 mz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA);
390 rte_panic("Cannot allocate ethdev shared data\n");
392 rte_eth_dev_shared_data = mz->addr;
393 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
394 rte_eth_dev_shared_data->next_owner_id =
395 RTE_ETH_DEV_NO_OWNER + 1;
396 rte_spinlock_init(&rte_eth_dev_shared_data->ownership_lock);
397 memset(rte_eth_dev_shared_data->data, 0,
398 sizeof(rte_eth_dev_shared_data->data));
402 rte_spinlock_unlock(&rte_eth_shared_data_lock);
406 is_allocated(const struct rte_eth_dev *ethdev)
408 return ethdev->data->name[0] != '\0';
411 static struct rte_eth_dev *
412 _rte_eth_dev_allocated(const char *name)
416 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
417 if (rte_eth_devices[i].data != NULL &&
418 strcmp(rte_eth_devices[i].data->name, name) == 0)
419 return &rte_eth_devices[i];
425 rte_eth_dev_allocated(const char *name)
427 struct rte_eth_dev *ethdev;
429 rte_eth_dev_shared_data_prepare();
431 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
433 ethdev = _rte_eth_dev_allocated(name);
435 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
441 rte_eth_dev_find_free_port(void)
445 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
446 /* Using shared name field to find a free port. */
447 if (rte_eth_dev_shared_data->data[i].name[0] == '\0') {
448 RTE_ASSERT(rte_eth_devices[i].state ==
453 return RTE_MAX_ETHPORTS;
456 static struct rte_eth_dev *
457 eth_dev_get(uint16_t port_id)
459 struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];
461 eth_dev->data = &rte_eth_dev_shared_data->data[port_id];
467 rte_eth_dev_allocate(const char *name)
470 struct rte_eth_dev *eth_dev = NULL;
473 name_len = strnlen(name, RTE_ETH_NAME_MAX_LEN);
475 RTE_ETHDEV_LOG(ERR, "Zero length Ethernet device name\n");
479 if (name_len >= RTE_ETH_NAME_MAX_LEN) {
480 RTE_ETHDEV_LOG(ERR, "Ethernet device name is too long\n");
484 rte_eth_dev_shared_data_prepare();
486 /* Synchronize port creation between primary and secondary threads. */
487 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
489 if (_rte_eth_dev_allocated(name) != NULL) {
491 "Ethernet device with name %s already allocated\n",
496 port_id = rte_eth_dev_find_free_port();
497 if (port_id == RTE_MAX_ETHPORTS) {
499 "Reached maximum number of Ethernet ports\n");
503 eth_dev = eth_dev_get(port_id);
504 strlcpy(eth_dev->data->name, name, sizeof(eth_dev->data->name));
505 eth_dev->data->port_id = port_id;
506 eth_dev->data->mtu = RTE_ETHER_MTU;
507 pthread_mutex_init(ð_dev->data->flow_ops_mutex, NULL);
510 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
516 * Attach to a port already registered by the primary process, which
517 * makes sure that the same device would have the same port id both
518 * in the primary and secondary process.
521 rte_eth_dev_attach_secondary(const char *name)
524 struct rte_eth_dev *eth_dev = NULL;
526 rte_eth_dev_shared_data_prepare();
528 /* Synchronize port attachment to primary port creation and release. */
529 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
531 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
532 if (strcmp(rte_eth_dev_shared_data->data[i].name, name) == 0)
535 if (i == RTE_MAX_ETHPORTS) {
537 "Device %s is not driven by the primary process\n",
540 eth_dev = eth_dev_get(i);
541 RTE_ASSERT(eth_dev->data->port_id == i);
544 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
549 rte_eth_dev_release_port(struct rte_eth_dev *eth_dev)
554 rte_eth_dev_shared_data_prepare();
556 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
557 rte_eth_dev_callback_process(eth_dev,
558 RTE_ETH_EVENT_DESTROY, NULL);
560 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
562 eth_dev->state = RTE_ETH_DEV_UNUSED;
563 eth_dev->device = NULL;
564 eth_dev->process_private = NULL;
565 eth_dev->intr_handle = NULL;
566 eth_dev->rx_pkt_burst = NULL;
567 eth_dev->tx_pkt_burst = NULL;
568 eth_dev->tx_pkt_prepare = NULL;
569 eth_dev->rx_queue_count = NULL;
570 eth_dev->rx_descriptor_done = NULL;
571 eth_dev->rx_descriptor_status = NULL;
572 eth_dev->tx_descriptor_status = NULL;
573 eth_dev->dev_ops = NULL;
575 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
576 rte_free(eth_dev->data->rx_queues);
577 rte_free(eth_dev->data->tx_queues);
578 rte_free(eth_dev->data->mac_addrs);
579 rte_free(eth_dev->data->hash_mac_addrs);
580 rte_free(eth_dev->data->dev_private);
581 pthread_mutex_destroy(ð_dev->data->flow_ops_mutex);
582 memset(eth_dev->data, 0, sizeof(struct rte_eth_dev_data));
585 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
591 rte_eth_dev_is_valid_port(uint16_t port_id)
593 if (port_id >= RTE_MAX_ETHPORTS ||
594 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED))
601 rte_eth_is_valid_owner_id(uint64_t owner_id)
603 if (owner_id == RTE_ETH_DEV_NO_OWNER ||
604 rte_eth_dev_shared_data->next_owner_id <= owner_id)
610 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id)
612 port_id = rte_eth_find_next(port_id);
613 while (port_id < RTE_MAX_ETHPORTS &&
614 rte_eth_devices[port_id].data->owner.id != owner_id)
615 port_id = rte_eth_find_next(port_id + 1);
621 rte_eth_dev_owner_new(uint64_t *owner_id)
623 rte_eth_dev_shared_data_prepare();
625 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
627 *owner_id = rte_eth_dev_shared_data->next_owner_id++;
629 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
634 _rte_eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id,
635 const struct rte_eth_dev_owner *new_owner)
637 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
638 struct rte_eth_dev_owner *port_owner;
640 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) {
641 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
646 if (!rte_eth_is_valid_owner_id(new_owner->id) &&
647 !rte_eth_is_valid_owner_id(old_owner_id)) {
649 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64"\n",
650 old_owner_id, new_owner->id);
654 port_owner = &rte_eth_devices[port_id].data->owner;
655 if (port_owner->id != old_owner_id) {
657 "Cannot set owner to port %u already owned by %s_%016"PRIX64"\n",
658 port_id, port_owner->name, port_owner->id);
662 /* can not truncate (same structure) */
663 strlcpy(port_owner->name, new_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN);
665 port_owner->id = new_owner->id;
667 RTE_ETHDEV_LOG(DEBUG, "Port %u owner is %s_%016"PRIx64"\n",
668 port_id, new_owner->name, new_owner->id);
674 rte_eth_dev_owner_set(const uint16_t port_id,
675 const struct rte_eth_dev_owner *owner)
679 rte_eth_dev_shared_data_prepare();
681 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
683 ret = _rte_eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner);
685 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
690 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id)
692 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner)
693 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""};
696 rte_eth_dev_shared_data_prepare();
698 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
700 ret = _rte_eth_dev_owner_set(port_id, owner_id, &new_owner);
702 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
707 rte_eth_dev_owner_delete(const uint64_t owner_id)
712 rte_eth_dev_shared_data_prepare();
714 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
716 if (rte_eth_is_valid_owner_id(owner_id)) {
717 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)
718 if (rte_eth_devices[port_id].data->owner.id == owner_id)
719 memset(&rte_eth_devices[port_id].data->owner, 0,
720 sizeof(struct rte_eth_dev_owner));
721 RTE_ETHDEV_LOG(NOTICE,
722 "All port owners owned by %016"PRIx64" identifier have removed\n",
726 "Invalid owner id=%016"PRIx64"\n",
731 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
737 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner)
740 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
742 rte_eth_dev_shared_data_prepare();
744 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
746 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) {
747 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
751 rte_memcpy(owner, ðdev->data->owner, sizeof(*owner));
754 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
759 rte_eth_dev_socket_id(uint16_t port_id)
761 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
762 return rte_eth_devices[port_id].data->numa_node;
766 rte_eth_dev_get_sec_ctx(uint16_t port_id)
768 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
769 return rte_eth_devices[port_id].security_ctx;
773 rte_eth_dev_count_avail(void)
780 RTE_ETH_FOREACH_DEV(p)
787 rte_eth_dev_count_total(void)
789 uint16_t port, count = 0;
791 RTE_ETH_FOREACH_VALID_DEV(port)
798 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name)
802 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
805 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
809 /* shouldn't check 'rte_eth_devices[i].data',
810 * because it might be overwritten by VDEV PMD */
811 tmp = rte_eth_dev_shared_data->data[port_id].name;
817 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id)
822 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
826 RTE_ETH_FOREACH_VALID_DEV(pid)
827 if (!strcmp(name, rte_eth_dev_shared_data->data[pid].name)) {
836 eth_err(uint16_t port_id, int ret)
840 if (rte_eth_dev_is_removed(port_id))
846 rte_eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
848 uint16_t old_nb_queues = dev->data->nb_rx_queues;
852 if (dev->data->rx_queues == NULL && nb_queues != 0) { /* first time configuration */
853 dev->data->rx_queues = rte_zmalloc("ethdev->rx_queues",
854 sizeof(dev->data->rx_queues[0]) * nb_queues,
855 RTE_CACHE_LINE_SIZE);
856 if (dev->data->rx_queues == NULL) {
857 dev->data->nb_rx_queues = 0;
860 } else if (dev->data->rx_queues != NULL && nb_queues != 0) { /* re-configure */
861 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
863 rxq = dev->data->rx_queues;
865 for (i = nb_queues; i < old_nb_queues; i++)
866 (*dev->dev_ops->rx_queue_release)(rxq[i]);
867 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
868 RTE_CACHE_LINE_SIZE);
871 if (nb_queues > old_nb_queues) {
872 uint16_t new_qs = nb_queues - old_nb_queues;
874 memset(rxq + old_nb_queues, 0,
875 sizeof(rxq[0]) * new_qs);
878 dev->data->rx_queues = rxq;
880 } else if (dev->data->rx_queues != NULL && nb_queues == 0) {
881 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
883 rxq = dev->data->rx_queues;
885 for (i = nb_queues; i < old_nb_queues; i++)
886 (*dev->dev_ops->rx_queue_release)(rxq[i]);
888 rte_free(dev->data->rx_queues);
889 dev->data->rx_queues = NULL;
891 dev->data->nb_rx_queues = nb_queues;
896 eth_dev_validate_rx_queue(const struct rte_eth_dev *dev, uint16_t rx_queue_id)
900 if (rx_queue_id >= dev->data->nb_rx_queues) {
901 port_id = dev->data->port_id;
903 "Invalid Rx queue_id=%u of device with port_id=%u\n",
904 rx_queue_id, port_id);
908 if (dev->data->rx_queues[rx_queue_id] == NULL) {
909 port_id = dev->data->port_id;
911 "Queue %u of device with port_id=%u has not been setup\n",
912 rx_queue_id, port_id);
920 eth_dev_validate_tx_queue(const struct rte_eth_dev *dev, uint16_t tx_queue_id)
924 if (tx_queue_id >= dev->data->nb_tx_queues) {
925 port_id = dev->data->port_id;
927 "Invalid Tx queue_id=%u of device with port_id=%u\n",
928 tx_queue_id, port_id);
932 if (dev->data->tx_queues[tx_queue_id] == NULL) {
933 port_id = dev->data->port_id;
935 "Queue %u of device with port_id=%u has not been setup\n",
936 tx_queue_id, port_id);
944 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id)
946 struct rte_eth_dev *dev;
949 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
951 dev = &rte_eth_devices[port_id];
952 if (!dev->data->dev_started) {
954 "Port %u must be started before start any queue\n",
959 ret = eth_dev_validate_rx_queue(dev, rx_queue_id);
963 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP);
965 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
967 "Can't start Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
968 rx_queue_id, port_id);
972 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
974 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
975 rx_queue_id, port_id);
979 return eth_err(port_id, dev->dev_ops->rx_queue_start(dev,
985 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id)
987 struct rte_eth_dev *dev;
990 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
992 dev = &rte_eth_devices[port_id];
994 ret = eth_dev_validate_rx_queue(dev, rx_queue_id);
998 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP);
1000 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
1001 RTE_ETHDEV_LOG(INFO,
1002 "Can't stop Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1003 rx_queue_id, port_id);
1007 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
1008 RTE_ETHDEV_LOG(INFO,
1009 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
1010 rx_queue_id, port_id);
1014 return eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id));
1019 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id)
1021 struct rte_eth_dev *dev;
1024 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1026 dev = &rte_eth_devices[port_id];
1027 if (!dev->data->dev_started) {
1029 "Port %u must be started before start any queue\n",
1034 ret = eth_dev_validate_tx_queue(dev, tx_queue_id);
1038 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP);
1040 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
1041 RTE_ETHDEV_LOG(INFO,
1042 "Can't start Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1043 tx_queue_id, port_id);
1047 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
1048 RTE_ETHDEV_LOG(INFO,
1049 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
1050 tx_queue_id, port_id);
1054 return eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id));
1058 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id)
1060 struct rte_eth_dev *dev;
1063 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1065 dev = &rte_eth_devices[port_id];
1067 ret = eth_dev_validate_tx_queue(dev, tx_queue_id);
1071 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP);
1073 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
1074 RTE_ETHDEV_LOG(INFO,
1075 "Can't stop Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1076 tx_queue_id, port_id);
1080 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
1081 RTE_ETHDEV_LOG(INFO,
1082 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
1083 tx_queue_id, port_id);
1087 return eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id));
1092 rte_eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
1094 uint16_t old_nb_queues = dev->data->nb_tx_queues;
1098 if (dev->data->tx_queues == NULL && nb_queues != 0) { /* first time configuration */
1099 dev->data->tx_queues = rte_zmalloc("ethdev->tx_queues",
1100 sizeof(dev->data->tx_queues[0]) * nb_queues,
1101 RTE_CACHE_LINE_SIZE);
1102 if (dev->data->tx_queues == NULL) {
1103 dev->data->nb_tx_queues = 0;
1106 } else if (dev->data->tx_queues != NULL && nb_queues != 0) { /* re-configure */
1107 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1109 txq = dev->data->tx_queues;
1111 for (i = nb_queues; i < old_nb_queues; i++)
1112 (*dev->dev_ops->tx_queue_release)(txq[i]);
1113 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1114 RTE_CACHE_LINE_SIZE);
1117 if (nb_queues > old_nb_queues) {
1118 uint16_t new_qs = nb_queues - old_nb_queues;
1120 memset(txq + old_nb_queues, 0,
1121 sizeof(txq[0]) * new_qs);
1124 dev->data->tx_queues = txq;
1126 } else if (dev->data->tx_queues != NULL && nb_queues == 0) {
1127 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1129 txq = dev->data->tx_queues;
1131 for (i = nb_queues; i < old_nb_queues; i++)
1132 (*dev->dev_ops->tx_queue_release)(txq[i]);
1134 rte_free(dev->data->tx_queues);
1135 dev->data->tx_queues = NULL;
1137 dev->data->nb_tx_queues = nb_queues;
1142 rte_eth_speed_bitflag(uint32_t speed, int duplex)
1145 case ETH_SPEED_NUM_10M:
1146 return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD;
1147 case ETH_SPEED_NUM_100M:
1148 return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD;
1149 case ETH_SPEED_NUM_1G:
1150 return ETH_LINK_SPEED_1G;
1151 case ETH_SPEED_NUM_2_5G:
1152 return ETH_LINK_SPEED_2_5G;
1153 case ETH_SPEED_NUM_5G:
1154 return ETH_LINK_SPEED_5G;
1155 case ETH_SPEED_NUM_10G:
1156 return ETH_LINK_SPEED_10G;
1157 case ETH_SPEED_NUM_20G:
1158 return ETH_LINK_SPEED_20G;
1159 case ETH_SPEED_NUM_25G:
1160 return ETH_LINK_SPEED_25G;
1161 case ETH_SPEED_NUM_40G:
1162 return ETH_LINK_SPEED_40G;
1163 case ETH_SPEED_NUM_50G:
1164 return ETH_LINK_SPEED_50G;
1165 case ETH_SPEED_NUM_56G:
1166 return ETH_LINK_SPEED_56G;
1167 case ETH_SPEED_NUM_100G:
1168 return ETH_LINK_SPEED_100G;
1169 case ETH_SPEED_NUM_200G:
1170 return ETH_LINK_SPEED_200G;
1177 rte_eth_dev_rx_offload_name(uint64_t offload)
1179 const char *name = "UNKNOWN";
1182 for (i = 0; i < RTE_DIM(rte_rx_offload_names); ++i) {
1183 if (offload == rte_rx_offload_names[i].offload) {
1184 name = rte_rx_offload_names[i].name;
1193 rte_eth_dev_tx_offload_name(uint64_t offload)
1195 const char *name = "UNKNOWN";
1198 for (i = 0; i < RTE_DIM(rte_tx_offload_names); ++i) {
1199 if (offload == rte_tx_offload_names[i].offload) {
1200 name = rte_tx_offload_names[i].name;
1209 check_lro_pkt_size(uint16_t port_id, uint32_t config_size,
1210 uint32_t max_rx_pkt_len, uint32_t dev_info_size)
1214 if (dev_info_size == 0) {
1215 if (config_size != max_rx_pkt_len) {
1216 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size"
1217 " %u != %u is not allowed\n",
1218 port_id, config_size, max_rx_pkt_len);
1221 } else if (config_size > dev_info_size) {
1222 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u "
1223 "> max allowed value %u\n", port_id, config_size,
1226 } else if (config_size < RTE_ETHER_MIN_LEN) {
1227 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u "
1228 "< min allowed value %u\n", port_id, config_size,
1229 (unsigned int)RTE_ETHER_MIN_LEN);
1236 * Validate offloads that are requested through rte_eth_dev_configure against
1237 * the offloads successfully set by the ethernet device.
1240 * The port identifier of the Ethernet device.
1241 * @param req_offloads
1242 * The offloads that have been requested through `rte_eth_dev_configure`.
1243 * @param set_offloads
1244 * The offloads successfully set by the ethernet device.
1245 * @param offload_type
1246 * The offload type i.e. Rx/Tx string.
1247 * @param offload_name
1248 * The function that prints the offload name.
1250 * - (0) if validation successful.
1251 * - (-EINVAL) if requested offload has been silently disabled.
1255 validate_offloads(uint16_t port_id, uint64_t req_offloads,
1256 uint64_t set_offloads, const char *offload_type,
1257 const char *(*offload_name)(uint64_t))
1259 uint64_t offloads_diff = req_offloads ^ set_offloads;
1263 while (offloads_diff != 0) {
1264 /* Check if any offload is requested but not enabled. */
1265 offload = 1ULL << __builtin_ctzll(offloads_diff);
1266 if (offload & req_offloads) {
1268 "Port %u failed to enable %s offload %s\n",
1269 port_id, offload_type, offload_name(offload));
1273 /* Check if offload couldn't be disabled. */
1274 if (offload & set_offloads) {
1275 RTE_ETHDEV_LOG(DEBUG,
1276 "Port %u %s offload %s is not requested but enabled\n",
1277 port_id, offload_type, offload_name(offload));
1280 offloads_diff &= ~offload;
1287 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,
1288 const struct rte_eth_conf *dev_conf)
1290 struct rte_eth_dev *dev;
1291 struct rte_eth_dev_info dev_info;
1292 struct rte_eth_conf orig_conf;
1296 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1298 dev = &rte_eth_devices[port_id];
1300 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP);
1302 if (dev->data->dev_started) {
1304 "Port %u must be stopped to allow configuration\n",
1309 /* Store original config, as rollback required on failure */
1310 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf));
1313 * Copy the dev_conf parameter into the dev structure.
1314 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get
1316 if (dev_conf != &dev->data->dev_conf)
1317 memcpy(&dev->data->dev_conf, dev_conf,
1318 sizeof(dev->data->dev_conf));
1320 ret = rte_eth_dev_info_get(port_id, &dev_info);
1324 /* If number of queues specified by application for both Rx and Tx is
1325 * zero, use driver preferred values. This cannot be done individually
1326 * as it is valid for either Tx or Rx (but not both) to be zero.
1327 * If driver does not provide any preferred valued, fall back on
1330 if (nb_rx_q == 0 && nb_tx_q == 0) {
1331 nb_rx_q = dev_info.default_rxportconf.nb_queues;
1333 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES;
1334 nb_tx_q = dev_info.default_txportconf.nb_queues;
1336 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES;
1339 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) {
1341 "Number of RX queues requested (%u) is greater than max supported(%d)\n",
1342 nb_rx_q, RTE_MAX_QUEUES_PER_PORT);
1347 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) {
1349 "Number of TX queues requested (%u) is greater than max supported(%d)\n",
1350 nb_tx_q, RTE_MAX_QUEUES_PER_PORT);
1356 * Check that the numbers of RX and TX queues are not greater
1357 * than the maximum number of RX and TX queues supported by the
1358 * configured device.
1360 if (nb_rx_q > dev_info.max_rx_queues) {
1361 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u\n",
1362 port_id, nb_rx_q, dev_info.max_rx_queues);
1367 if (nb_tx_q > dev_info.max_tx_queues) {
1368 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u\n",
1369 port_id, nb_tx_q, dev_info.max_tx_queues);
1374 /* Check that the device supports requested interrupts */
1375 if ((dev_conf->intr_conf.lsc == 1) &&
1376 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) {
1377 RTE_ETHDEV_LOG(ERR, "Driver %s does not support lsc\n",
1378 dev->device->driver->name);
1382 if ((dev_conf->intr_conf.rmv == 1) &&
1383 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) {
1384 RTE_ETHDEV_LOG(ERR, "Driver %s does not support rmv\n",
1385 dev->device->driver->name);
1391 * If jumbo frames are enabled, check that the maximum RX packet
1392 * length is supported by the configured device.
1394 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1395 if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen) {
1397 "Ethdev port_id=%u max_rx_pkt_len %u > max valid value %u\n",
1398 port_id, dev_conf->rxmode.max_rx_pkt_len,
1399 dev_info.max_rx_pktlen);
1402 } else if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN) {
1404 "Ethdev port_id=%u max_rx_pkt_len %u < min valid value %u\n",
1405 port_id, dev_conf->rxmode.max_rx_pkt_len,
1406 (unsigned int)RTE_ETHER_MIN_LEN);
1411 if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN ||
1412 dev_conf->rxmode.max_rx_pkt_len > RTE_ETHER_MAX_LEN)
1413 /* Use default value */
1414 dev->data->dev_conf.rxmode.max_rx_pkt_len =
1419 * If LRO is enabled, check that the maximum aggregated packet
1420 * size is supported by the configured device.
1422 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1423 if (dev_conf->rxmode.max_lro_pkt_size == 0)
1424 dev->data->dev_conf.rxmode.max_lro_pkt_size =
1425 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1426 ret = check_lro_pkt_size(port_id,
1427 dev->data->dev_conf.rxmode.max_lro_pkt_size,
1428 dev->data->dev_conf.rxmode.max_rx_pkt_len,
1429 dev_info.max_lro_pkt_size);
1434 /* Any requested offloading must be within its device capabilities */
1435 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) !=
1436 dev_conf->rxmode.offloads) {
1438 "Ethdev port_id=%u requested Rx offloads 0x%"PRIx64" doesn't match Rx offloads "
1439 "capabilities 0x%"PRIx64" in %s()\n",
1440 port_id, dev_conf->rxmode.offloads,
1441 dev_info.rx_offload_capa,
1446 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) !=
1447 dev_conf->txmode.offloads) {
1449 "Ethdev port_id=%u requested Tx offloads 0x%"PRIx64" doesn't match Tx offloads "
1450 "capabilities 0x%"PRIx64" in %s()\n",
1451 port_id, dev_conf->txmode.offloads,
1452 dev_info.tx_offload_capa,
1458 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf =
1459 rte_eth_rss_hf_refine(dev_conf->rx_adv_conf.rss_conf.rss_hf);
1461 /* Check that device supports requested rss hash functions. */
1462 if ((dev_info.flow_type_rss_offloads |
1463 dev_conf->rx_adv_conf.rss_conf.rss_hf) !=
1464 dev_info.flow_type_rss_offloads) {
1466 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
1467 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf,
1468 dev_info.flow_type_rss_offloads);
1473 /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */
1474 if (((dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) &&
1475 (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_RSS_HASH)) {
1477 "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested\n",
1479 rte_eth_dev_rx_offload_name(DEV_RX_OFFLOAD_RSS_HASH));
1485 * Setup new number of RX/TX queues and reconfigure device.
1487 diag = rte_eth_dev_rx_queue_config(dev, nb_rx_q);
1490 "Port%u rte_eth_dev_rx_queue_config = %d\n",
1496 diag = rte_eth_dev_tx_queue_config(dev, nb_tx_q);
1499 "Port%u rte_eth_dev_tx_queue_config = %d\n",
1501 rte_eth_dev_rx_queue_config(dev, 0);
1506 diag = (*dev->dev_ops->dev_configure)(dev);
1508 RTE_ETHDEV_LOG(ERR, "Port%u dev_configure = %d\n",
1510 ret = eth_err(port_id, diag);
1514 /* Initialize Rx profiling if enabled at compilation time. */
1515 diag = __rte_eth_dev_profile_init(port_id, dev);
1517 RTE_ETHDEV_LOG(ERR, "Port%u __rte_eth_dev_profile_init = %d\n",
1519 ret = eth_err(port_id, diag);
1523 /* Validate Rx offloads. */
1524 diag = validate_offloads(port_id,
1525 dev_conf->rxmode.offloads,
1526 dev->data->dev_conf.rxmode.offloads, "Rx",
1527 rte_eth_dev_rx_offload_name);
1533 /* Validate Tx offloads. */
1534 diag = validate_offloads(port_id,
1535 dev_conf->txmode.offloads,
1536 dev->data->dev_conf.txmode.offloads, "Tx",
1537 rte_eth_dev_tx_offload_name);
1543 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, 0);
1546 rte_eth_dev_rx_queue_config(dev, 0);
1547 rte_eth_dev_tx_queue_config(dev, 0);
1549 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf));
1551 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, ret);
1556 rte_eth_dev_internal_reset(struct rte_eth_dev *dev)
1558 if (dev->data->dev_started) {
1559 RTE_ETHDEV_LOG(ERR, "Port %u must be stopped to allow reset\n",
1560 dev->data->port_id);
1564 rte_eth_dev_rx_queue_config(dev, 0);
1565 rte_eth_dev_tx_queue_config(dev, 0);
1567 memset(&dev->data->dev_conf, 0, sizeof(dev->data->dev_conf));
1571 rte_eth_dev_mac_restore(struct rte_eth_dev *dev,
1572 struct rte_eth_dev_info *dev_info)
1574 struct rte_ether_addr *addr;
1579 /* replay MAC address configuration including default MAC */
1580 addr = &dev->data->mac_addrs[0];
1581 if (*dev->dev_ops->mac_addr_set != NULL)
1582 (*dev->dev_ops->mac_addr_set)(dev, addr);
1583 else if (*dev->dev_ops->mac_addr_add != NULL)
1584 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool);
1586 if (*dev->dev_ops->mac_addr_add != NULL) {
1587 for (i = 1; i < dev_info->max_mac_addrs; i++) {
1588 addr = &dev->data->mac_addrs[i];
1590 /* skip zero address */
1591 if (rte_is_zero_ether_addr(addr))
1595 pool_mask = dev->data->mac_pool_sel[i];
1598 if (pool_mask & 1ULL)
1599 (*dev->dev_ops->mac_addr_add)(dev,
1603 } while (pool_mask);
1609 rte_eth_dev_config_restore(struct rte_eth_dev *dev,
1610 struct rte_eth_dev_info *dev_info, uint16_t port_id)
1614 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR))
1615 rte_eth_dev_mac_restore(dev, dev_info);
1617 /* replay promiscuous configuration */
1619 * use callbacks directly since we don't need port_id check and
1620 * would like to bypass the same value set
1622 if (rte_eth_promiscuous_get(port_id) == 1 &&
1623 *dev->dev_ops->promiscuous_enable != NULL) {
1624 ret = eth_err(port_id,
1625 (*dev->dev_ops->promiscuous_enable)(dev));
1626 if (ret != 0 && ret != -ENOTSUP) {
1628 "Failed to enable promiscuous mode for device (port %u): %s\n",
1629 port_id, rte_strerror(-ret));
1632 } else if (rte_eth_promiscuous_get(port_id) == 0 &&
1633 *dev->dev_ops->promiscuous_disable != NULL) {
1634 ret = eth_err(port_id,
1635 (*dev->dev_ops->promiscuous_disable)(dev));
1636 if (ret != 0 && ret != -ENOTSUP) {
1638 "Failed to disable promiscuous mode for device (port %u): %s\n",
1639 port_id, rte_strerror(-ret));
1644 /* replay all multicast configuration */
1646 * use callbacks directly since we don't need port_id check and
1647 * would like to bypass the same value set
1649 if (rte_eth_allmulticast_get(port_id) == 1 &&
1650 *dev->dev_ops->allmulticast_enable != NULL) {
1651 ret = eth_err(port_id,
1652 (*dev->dev_ops->allmulticast_enable)(dev));
1653 if (ret != 0 && ret != -ENOTSUP) {
1655 "Failed to enable allmulticast mode for device (port %u): %s\n",
1656 port_id, rte_strerror(-ret));
1659 } else if (rte_eth_allmulticast_get(port_id) == 0 &&
1660 *dev->dev_ops->allmulticast_disable != NULL) {
1661 ret = eth_err(port_id,
1662 (*dev->dev_ops->allmulticast_disable)(dev));
1663 if (ret != 0 && ret != -ENOTSUP) {
1665 "Failed to disable allmulticast mode for device (port %u): %s\n",
1666 port_id, rte_strerror(-ret));
1675 rte_eth_dev_start(uint16_t port_id)
1677 struct rte_eth_dev *dev;
1678 struct rte_eth_dev_info dev_info;
1682 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1684 dev = &rte_eth_devices[port_id];
1686 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP);
1688 if (dev->data->dev_started != 0) {
1689 RTE_ETHDEV_LOG(INFO,
1690 "Device with port_id=%"PRIu16" already started\n",
1695 ret = rte_eth_dev_info_get(port_id, &dev_info);
1699 /* Lets restore MAC now if device does not support live change */
1700 if (*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR)
1701 rte_eth_dev_mac_restore(dev, &dev_info);
1703 diag = (*dev->dev_ops->dev_start)(dev);
1705 dev->data->dev_started = 1;
1707 return eth_err(port_id, diag);
1709 ret = rte_eth_dev_config_restore(dev, &dev_info, port_id);
1712 "Error during restoring configuration for device (port %u): %s\n",
1713 port_id, rte_strerror(-ret));
1714 ret_stop = rte_eth_dev_stop(port_id);
1715 if (ret_stop != 0) {
1717 "Failed to stop device (port %u): %s\n",
1718 port_id, rte_strerror(-ret_stop));
1724 if (dev->data->dev_conf.intr_conf.lsc == 0) {
1725 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
1726 (*dev->dev_ops->link_update)(dev, 0);
1729 rte_ethdev_trace_start(port_id);
1734 rte_eth_dev_stop(uint16_t port_id)
1736 struct rte_eth_dev *dev;
1739 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1740 dev = &rte_eth_devices[port_id];
1742 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_stop, -ENOTSUP);
1744 if (dev->data->dev_started == 0) {
1745 RTE_ETHDEV_LOG(INFO,
1746 "Device with port_id=%"PRIu16" already stopped\n",
1751 dev->data->dev_started = 0;
1752 ret = (*dev->dev_ops->dev_stop)(dev);
1753 rte_ethdev_trace_stop(port_id, ret);
1759 rte_eth_dev_set_link_up(uint16_t port_id)
1761 struct rte_eth_dev *dev;
1763 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1765 dev = &rte_eth_devices[port_id];
1767 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP);
1768 return eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev));
1772 rte_eth_dev_set_link_down(uint16_t port_id)
1774 struct rte_eth_dev *dev;
1776 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1778 dev = &rte_eth_devices[port_id];
1780 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP);
1781 return eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev));
1785 rte_eth_dev_close(uint16_t port_id)
1787 struct rte_eth_dev *dev;
1788 int firsterr, binerr;
1789 int *lasterr = &firsterr;
1791 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1792 dev = &rte_eth_devices[port_id];
1794 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_close, -ENOTSUP);
1795 *lasterr = (*dev->dev_ops->dev_close)(dev);
1799 rte_ethdev_trace_close(port_id);
1800 *lasterr = rte_eth_dev_release_port(dev);
1802 return eth_err(port_id, firsterr);
1806 rte_eth_dev_reset(uint16_t port_id)
1808 struct rte_eth_dev *dev;
1811 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1812 dev = &rte_eth_devices[port_id];
1814 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_reset, -ENOTSUP);
1816 ret = rte_eth_dev_stop(port_id);
1819 "Failed to stop device (port %u) before reset: %s - ignore\n",
1820 port_id, rte_strerror(-ret));
1822 ret = dev->dev_ops->dev_reset(dev);
1824 return eth_err(port_id, ret);
1828 rte_eth_dev_is_removed(uint16_t port_id)
1830 struct rte_eth_dev *dev;
1833 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
1835 dev = &rte_eth_devices[port_id];
1837 if (dev->state == RTE_ETH_DEV_REMOVED)
1840 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->is_removed, 0);
1842 ret = dev->dev_ops->is_removed(dev);
1844 /* Device is physically removed. */
1845 dev->state = RTE_ETH_DEV_REMOVED;
1851 rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg,
1852 uint16_t n_seg, uint32_t *mbp_buf_size,
1853 const struct rte_eth_dev_info *dev_info)
1855 const struct rte_eth_rxseg_capa *seg_capa = &dev_info->rx_seg_capa;
1856 struct rte_mempool *mp_first;
1857 uint32_t offset_mask;
1860 if (n_seg > seg_capa->max_nseg) {
1862 "Requested Rx segments %u exceed supported %u\n",
1863 n_seg, seg_capa->max_nseg);
1867 * Check the sizes and offsets against buffer sizes
1868 * for each segment specified in extended configuration.
1870 mp_first = rx_seg[0].mp;
1871 offset_mask = (1u << seg_capa->offset_align_log2) - 1;
1872 for (seg_idx = 0; seg_idx < n_seg; seg_idx++) {
1873 struct rte_mempool *mpl = rx_seg[seg_idx].mp;
1874 uint32_t length = rx_seg[seg_idx].length;
1875 uint32_t offset = rx_seg[seg_idx].offset;
1878 RTE_ETHDEV_LOG(ERR, "null mempool pointer\n");
1881 if (seg_idx != 0 && mp_first != mpl &&
1882 seg_capa->multi_pools == 0) {
1883 RTE_ETHDEV_LOG(ERR, "Receiving to multiple pools is not supported\n");
1887 if (seg_capa->offset_allowed == 0) {
1888 RTE_ETHDEV_LOG(ERR, "Rx segmentation with offset is not supported\n");
1891 if (offset & offset_mask) {
1892 RTE_ETHDEV_LOG(ERR, "Rx segmentation invalid offset alignment %u, %u\n",
1894 seg_capa->offset_align_log2);
1898 if (mpl->private_data_size <
1899 sizeof(struct rte_pktmbuf_pool_private)) {
1901 "%s private_data_size %u < %u\n",
1902 mpl->name, mpl->private_data_size,
1903 (unsigned int)sizeof
1904 (struct rte_pktmbuf_pool_private));
1907 offset += seg_idx != 0 ? 0 : RTE_PKTMBUF_HEADROOM;
1908 *mbp_buf_size = rte_pktmbuf_data_room_size(mpl);
1909 length = length != 0 ? length : *mbp_buf_size;
1910 if (*mbp_buf_size < length + offset) {
1912 "%s mbuf_data_room_size %u < %u (segment length=%u + segment offset=%u)\n",
1913 mpl->name, *mbp_buf_size,
1914 length + offset, length, offset);
1922 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
1923 uint16_t nb_rx_desc, unsigned int socket_id,
1924 const struct rte_eth_rxconf *rx_conf,
1925 struct rte_mempool *mp)
1928 uint32_t mbp_buf_size;
1929 struct rte_eth_dev *dev;
1930 struct rte_eth_dev_info dev_info;
1931 struct rte_eth_rxconf local_conf;
1934 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1936 dev = &rte_eth_devices[port_id];
1937 if (rx_queue_id >= dev->data->nb_rx_queues) {
1938 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
1942 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP);
1944 ret = rte_eth_dev_info_get(port_id, &dev_info);
1949 /* Single pool configuration check. */
1950 if (rx_conf != NULL && rx_conf->rx_nseg != 0) {
1952 "Ambiguous segment configuration\n");
1956 * Check the size of the mbuf data buffer, this value
1957 * must be provided in the private data of the memory pool.
1958 * First check that the memory pool(s) has a valid private data.
1960 if (mp->private_data_size <
1961 sizeof(struct rte_pktmbuf_pool_private)) {
1962 RTE_ETHDEV_LOG(ERR, "%s private_data_size %u < %u\n",
1963 mp->name, mp->private_data_size,
1965 sizeof(struct rte_pktmbuf_pool_private));
1968 mbp_buf_size = rte_pktmbuf_data_room_size(mp);
1969 if (mbp_buf_size < dev_info.min_rx_bufsize +
1970 RTE_PKTMBUF_HEADROOM) {
1972 "%s mbuf_data_room_size %u < %u (RTE_PKTMBUF_HEADROOM=%u + min_rx_bufsize(dev)=%u)\n",
1973 mp->name, mbp_buf_size,
1974 RTE_PKTMBUF_HEADROOM +
1975 dev_info.min_rx_bufsize,
1976 RTE_PKTMBUF_HEADROOM,
1977 dev_info.min_rx_bufsize);
1981 const struct rte_eth_rxseg_split *rx_seg =
1982 (const struct rte_eth_rxseg_split *)rx_conf->rx_seg;
1983 uint16_t n_seg = rx_conf->rx_nseg;
1985 /* Extended multi-segment configuration check. */
1986 if (rx_conf == NULL || rx_conf->rx_seg == NULL || rx_conf->rx_nseg == 0) {
1988 "Memory pool is null and no extended configuration provided\n");
1991 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) {
1992 ret = rte_eth_rx_queue_check_split(rx_seg, n_seg,
1998 RTE_ETHDEV_LOG(ERR, "No Rx segmentation offload configured\n");
2003 /* Use default specified by driver, if nb_rx_desc is zero */
2004 if (nb_rx_desc == 0) {
2005 nb_rx_desc = dev_info.default_rxportconf.ring_size;
2006 /* If driver default is also zero, fall back on EAL default */
2007 if (nb_rx_desc == 0)
2008 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE;
2011 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max ||
2012 nb_rx_desc < dev_info.rx_desc_lim.nb_min ||
2013 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) {
2016 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
2017 nb_rx_desc, dev_info.rx_desc_lim.nb_max,
2018 dev_info.rx_desc_lim.nb_min,
2019 dev_info.rx_desc_lim.nb_align);
2023 if (dev->data->dev_started &&
2024 !(dev_info.dev_capa &
2025 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP))
2028 if (dev->data->dev_started &&
2029 (dev->data->rx_queue_state[rx_queue_id] !=
2030 RTE_ETH_QUEUE_STATE_STOPPED))
2033 rxq = dev->data->rx_queues;
2034 if (rxq[rx_queue_id]) {
2035 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
2037 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
2038 rxq[rx_queue_id] = NULL;
2041 if (rx_conf == NULL)
2042 rx_conf = &dev_info.default_rxconf;
2044 local_conf = *rx_conf;
2047 * If an offloading has already been enabled in
2048 * rte_eth_dev_configure(), it has been enabled on all queues,
2049 * so there is no need to enable it in this queue again.
2050 * The local_conf.offloads input to underlying PMD only carries
2051 * those offloadings which are only enabled on this queue and
2052 * not enabled on all queues.
2054 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads;
2057 * New added offloadings for this queue are those not enabled in
2058 * rte_eth_dev_configure() and they must be per-queue type.
2059 * A pure per-port offloading can't be enabled on a queue while
2060 * disabled on another queue. A pure per-port offloading can't
2061 * be enabled for any queue as new added one if it hasn't been
2062 * enabled in rte_eth_dev_configure().
2064 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) !=
2065 local_conf.offloads) {
2067 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
2068 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
2069 port_id, rx_queue_id, local_conf.offloads,
2070 dev_info.rx_queue_offload_capa,
2076 * If LRO is enabled, check that the maximum aggregated packet
2077 * size is supported by the configured device.
2079 if (local_conf.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
2080 if (dev->data->dev_conf.rxmode.max_lro_pkt_size == 0)
2081 dev->data->dev_conf.rxmode.max_lro_pkt_size =
2082 dev->data->dev_conf.rxmode.max_rx_pkt_len;
2083 int ret = check_lro_pkt_size(port_id,
2084 dev->data->dev_conf.rxmode.max_lro_pkt_size,
2085 dev->data->dev_conf.rxmode.max_rx_pkt_len,
2086 dev_info.max_lro_pkt_size);
2091 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc,
2092 socket_id, &local_conf, mp);
2094 if (!dev->data->min_rx_buf_size ||
2095 dev->data->min_rx_buf_size > mbp_buf_size)
2096 dev->data->min_rx_buf_size = mbp_buf_size;
2099 rte_ethdev_trace_rxq_setup(port_id, rx_queue_id, nb_rx_desc, mp,
2101 return eth_err(port_id, ret);
2105 rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
2106 uint16_t nb_rx_desc,
2107 const struct rte_eth_hairpin_conf *conf)
2110 struct rte_eth_dev *dev;
2111 struct rte_eth_hairpin_cap cap;
2116 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2118 dev = &rte_eth_devices[port_id];
2119 if (rx_queue_id >= dev->data->nb_rx_queues) {
2120 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
2123 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
2126 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_hairpin_queue_setup,
2128 /* if nb_rx_desc is zero use max number of desc from the driver. */
2129 if (nb_rx_desc == 0)
2130 nb_rx_desc = cap.max_nb_desc;
2131 if (nb_rx_desc > cap.max_nb_desc) {
2133 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu",
2134 nb_rx_desc, cap.max_nb_desc);
2137 if (conf->peer_count > cap.max_rx_2_tx) {
2139 "Invalid value for number of peers for Rx queue(=%u), should be: <= %hu",
2140 conf->peer_count, cap.max_rx_2_tx);
2143 if (conf->peer_count == 0) {
2145 "Invalid value for number of peers for Rx queue(=%u), should be: > 0",
2149 for (i = 0, count = 0; i < dev->data->nb_rx_queues &&
2150 cap.max_nb_queues != UINT16_MAX; i++) {
2151 if (i == rx_queue_id || rte_eth_dev_is_rx_hairpin_queue(dev, i))
2154 if (count > cap.max_nb_queues) {
2155 RTE_ETHDEV_LOG(ERR, "To many Rx hairpin queues max is %d",
2159 if (dev->data->dev_started)
2161 rxq = dev->data->rx_queues;
2162 if (rxq[rx_queue_id] != NULL) {
2163 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
2165 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
2166 rxq[rx_queue_id] = NULL;
2168 ret = (*dev->dev_ops->rx_hairpin_queue_setup)(dev, rx_queue_id,
2171 dev->data->rx_queue_state[rx_queue_id] =
2172 RTE_ETH_QUEUE_STATE_HAIRPIN;
2173 return eth_err(port_id, ret);
2177 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
2178 uint16_t nb_tx_desc, unsigned int socket_id,
2179 const struct rte_eth_txconf *tx_conf)
2181 struct rte_eth_dev *dev;
2182 struct rte_eth_dev_info dev_info;
2183 struct rte_eth_txconf local_conf;
2187 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2189 dev = &rte_eth_devices[port_id];
2190 if (tx_queue_id >= dev->data->nb_tx_queues) {
2191 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
2195 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP);
2197 ret = rte_eth_dev_info_get(port_id, &dev_info);
2201 /* Use default specified by driver, if nb_tx_desc is zero */
2202 if (nb_tx_desc == 0) {
2203 nb_tx_desc = dev_info.default_txportconf.ring_size;
2204 /* If driver default is zero, fall back on EAL default */
2205 if (nb_tx_desc == 0)
2206 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE;
2208 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max ||
2209 nb_tx_desc < dev_info.tx_desc_lim.nb_min ||
2210 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) {
2212 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
2213 nb_tx_desc, dev_info.tx_desc_lim.nb_max,
2214 dev_info.tx_desc_lim.nb_min,
2215 dev_info.tx_desc_lim.nb_align);
2219 if (dev->data->dev_started &&
2220 !(dev_info.dev_capa &
2221 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP))
2224 if (dev->data->dev_started &&
2225 (dev->data->tx_queue_state[tx_queue_id] !=
2226 RTE_ETH_QUEUE_STATE_STOPPED))
2229 txq = dev->data->tx_queues;
2230 if (txq[tx_queue_id]) {
2231 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
2233 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
2234 txq[tx_queue_id] = NULL;
2237 if (tx_conf == NULL)
2238 tx_conf = &dev_info.default_txconf;
2240 local_conf = *tx_conf;
2243 * If an offloading has already been enabled in
2244 * rte_eth_dev_configure(), it has been enabled on all queues,
2245 * so there is no need to enable it in this queue again.
2246 * The local_conf.offloads input to underlying PMD only carries
2247 * those offloadings which are only enabled on this queue and
2248 * not enabled on all queues.
2250 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads;
2253 * New added offloadings for this queue are those not enabled in
2254 * rte_eth_dev_configure() and they must be per-queue type.
2255 * A pure per-port offloading can't be enabled on a queue while
2256 * disabled on another queue. A pure per-port offloading can't
2257 * be enabled for any queue as new added one if it hasn't been
2258 * enabled in rte_eth_dev_configure().
2260 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) !=
2261 local_conf.offloads) {
2263 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
2264 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
2265 port_id, tx_queue_id, local_conf.offloads,
2266 dev_info.tx_queue_offload_capa,
2271 rte_ethdev_trace_txq_setup(port_id, tx_queue_id, nb_tx_desc, tx_conf);
2272 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev,
2273 tx_queue_id, nb_tx_desc, socket_id, &local_conf));
2277 rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
2278 uint16_t nb_tx_desc,
2279 const struct rte_eth_hairpin_conf *conf)
2281 struct rte_eth_dev *dev;
2282 struct rte_eth_hairpin_cap cap;
2288 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2289 dev = &rte_eth_devices[port_id];
2290 if (tx_queue_id >= dev->data->nb_tx_queues) {
2291 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
2294 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
2297 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_hairpin_queue_setup,
2299 /* if nb_rx_desc is zero use max number of desc from the driver. */
2300 if (nb_tx_desc == 0)
2301 nb_tx_desc = cap.max_nb_desc;
2302 if (nb_tx_desc > cap.max_nb_desc) {
2304 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu",
2305 nb_tx_desc, cap.max_nb_desc);
2308 if (conf->peer_count > cap.max_tx_2_rx) {
2310 "Invalid value for number of peers for Tx queue(=%u), should be: <= %hu",
2311 conf->peer_count, cap.max_tx_2_rx);
2314 if (conf->peer_count == 0) {
2316 "Invalid value for number of peers for Tx queue(=%u), should be: > 0",
2320 for (i = 0, count = 0; i < dev->data->nb_tx_queues &&
2321 cap.max_nb_queues != UINT16_MAX; i++) {
2322 if (i == tx_queue_id || rte_eth_dev_is_tx_hairpin_queue(dev, i))
2325 if (count > cap.max_nb_queues) {
2326 RTE_ETHDEV_LOG(ERR, "To many Tx hairpin queues max is %d",
2330 if (dev->data->dev_started)
2332 txq = dev->data->tx_queues;
2333 if (txq[tx_queue_id] != NULL) {
2334 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
2336 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
2337 txq[tx_queue_id] = NULL;
2339 ret = (*dev->dev_ops->tx_hairpin_queue_setup)
2340 (dev, tx_queue_id, nb_tx_desc, conf);
2342 dev->data->tx_queue_state[tx_queue_id] =
2343 RTE_ETH_QUEUE_STATE_HAIRPIN;
2344 return eth_err(port_id, ret);
2348 rte_eth_hairpin_bind(uint16_t tx_port, uint16_t rx_port)
2350 struct rte_eth_dev *dev;
2353 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV);
2354 dev = &rte_eth_devices[tx_port];
2355 if (dev->data->dev_started == 0) {
2356 RTE_ETHDEV_LOG(ERR, "Tx port %d is not started\n", tx_port);
2360 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_bind, -ENOTSUP);
2361 ret = (*dev->dev_ops->hairpin_bind)(dev, rx_port);
2363 RTE_ETHDEV_LOG(ERR, "Failed to bind hairpin Tx %d"
2364 " to Rx %d (%d - all ports)\n",
2365 tx_port, rx_port, RTE_MAX_ETHPORTS);
2371 rte_eth_hairpin_unbind(uint16_t tx_port, uint16_t rx_port)
2373 struct rte_eth_dev *dev;
2376 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV);
2377 dev = &rte_eth_devices[tx_port];
2378 if (dev->data->dev_started == 0) {
2379 RTE_ETHDEV_LOG(ERR, "Tx port %d is already stopped\n", tx_port);
2383 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_unbind, -ENOTSUP);
2384 ret = (*dev->dev_ops->hairpin_unbind)(dev, rx_port);
2386 RTE_ETHDEV_LOG(ERR, "Failed to unbind hairpin Tx %d"
2387 " from Rx %d (%d - all ports)\n",
2388 tx_port, rx_port, RTE_MAX_ETHPORTS);
2394 rte_eth_hairpin_get_peer_ports(uint16_t port_id, uint16_t *peer_ports,
2395 size_t len, uint32_t direction)
2397 struct rte_eth_dev *dev;
2400 if (peer_ports == NULL || len == 0)
2403 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2404 dev = &rte_eth_devices[port_id];
2405 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_get_peer_ports,
2408 ret = (*dev->dev_ops->hairpin_get_peer_ports)(dev, peer_ports,
2411 RTE_ETHDEV_LOG(ERR, "Failed to get %d hairpin peer %s ports\n",
2412 port_id, direction ? "Rx" : "Tx");
2418 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent,
2419 void *userdata __rte_unused)
2421 rte_pktmbuf_free_bulk(pkts, unsent);
2425 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent,
2428 uint64_t *count = userdata;
2430 rte_pktmbuf_free_bulk(pkts, unsent);
2435 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer,
2436 buffer_tx_error_fn cbfn, void *userdata)
2438 buffer->error_callback = cbfn;
2439 buffer->error_userdata = userdata;
2444 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size)
2451 buffer->size = size;
2452 if (buffer->error_callback == NULL) {
2453 ret = rte_eth_tx_buffer_set_err_callback(
2454 buffer, rte_eth_tx_buffer_drop_callback, NULL);
2461 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt)
2463 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2466 /* Validate Input Data. Bail if not valid or not supported. */
2467 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2468 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_done_cleanup, -ENOTSUP);
2470 /* Call driver to free pending mbufs. */
2471 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id],
2473 return eth_err(port_id, ret);
2477 rte_eth_promiscuous_enable(uint16_t port_id)
2479 struct rte_eth_dev *dev;
2482 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2483 dev = &rte_eth_devices[port_id];
2485 if (dev->data->promiscuous == 1)
2488 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_enable, -ENOTSUP);
2490 diag = (*dev->dev_ops->promiscuous_enable)(dev);
2491 dev->data->promiscuous = (diag == 0) ? 1 : 0;
2493 return eth_err(port_id, diag);
2497 rte_eth_promiscuous_disable(uint16_t port_id)
2499 struct rte_eth_dev *dev;
2502 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2503 dev = &rte_eth_devices[port_id];
2505 if (dev->data->promiscuous == 0)
2508 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_disable, -ENOTSUP);
2510 dev->data->promiscuous = 0;
2511 diag = (*dev->dev_ops->promiscuous_disable)(dev);
2513 dev->data->promiscuous = 1;
2515 return eth_err(port_id, diag);
2519 rte_eth_promiscuous_get(uint16_t port_id)
2521 struct rte_eth_dev *dev;
2523 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2525 dev = &rte_eth_devices[port_id];
2526 return dev->data->promiscuous;
2530 rte_eth_allmulticast_enable(uint16_t port_id)
2532 struct rte_eth_dev *dev;
2535 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2536 dev = &rte_eth_devices[port_id];
2538 if (dev->data->all_multicast == 1)
2541 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_enable, -ENOTSUP);
2542 diag = (*dev->dev_ops->allmulticast_enable)(dev);
2543 dev->data->all_multicast = (diag == 0) ? 1 : 0;
2545 return eth_err(port_id, diag);
2549 rte_eth_allmulticast_disable(uint16_t port_id)
2551 struct rte_eth_dev *dev;
2554 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2555 dev = &rte_eth_devices[port_id];
2557 if (dev->data->all_multicast == 0)
2560 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_disable, -ENOTSUP);
2561 dev->data->all_multicast = 0;
2562 diag = (*dev->dev_ops->allmulticast_disable)(dev);
2564 dev->data->all_multicast = 1;
2566 return eth_err(port_id, diag);
2570 rte_eth_allmulticast_get(uint16_t port_id)
2572 struct rte_eth_dev *dev;
2574 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2576 dev = &rte_eth_devices[port_id];
2577 return dev->data->all_multicast;
2581 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link)
2583 struct rte_eth_dev *dev;
2585 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2586 dev = &rte_eth_devices[port_id];
2588 if (dev->data->dev_conf.intr_conf.lsc &&
2589 dev->data->dev_started)
2590 rte_eth_linkstatus_get(dev, eth_link);
2592 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
2593 (*dev->dev_ops->link_update)(dev, 1);
2594 *eth_link = dev->data->dev_link;
2601 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link)
2603 struct rte_eth_dev *dev;
2605 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2606 dev = &rte_eth_devices[port_id];
2608 if (dev->data->dev_conf.intr_conf.lsc &&
2609 dev->data->dev_started)
2610 rte_eth_linkstatus_get(dev, eth_link);
2612 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
2613 (*dev->dev_ops->link_update)(dev, 0);
2614 *eth_link = dev->data->dev_link;
2621 rte_eth_link_speed_to_str(uint32_t link_speed)
2623 switch (link_speed) {
2624 case ETH_SPEED_NUM_NONE: return "None";
2625 case ETH_SPEED_NUM_10M: return "10 Mbps";
2626 case ETH_SPEED_NUM_100M: return "100 Mbps";
2627 case ETH_SPEED_NUM_1G: return "1 Gbps";
2628 case ETH_SPEED_NUM_2_5G: return "2.5 Gbps";
2629 case ETH_SPEED_NUM_5G: return "5 Gbps";
2630 case ETH_SPEED_NUM_10G: return "10 Gbps";
2631 case ETH_SPEED_NUM_20G: return "20 Gbps";
2632 case ETH_SPEED_NUM_25G: return "25 Gbps";
2633 case ETH_SPEED_NUM_40G: return "40 Gbps";
2634 case ETH_SPEED_NUM_50G: return "50 Gbps";
2635 case ETH_SPEED_NUM_56G: return "56 Gbps";
2636 case ETH_SPEED_NUM_100G: return "100 Gbps";
2637 case ETH_SPEED_NUM_200G: return "200 Gbps";
2638 case ETH_SPEED_NUM_UNKNOWN: return "Unknown";
2639 default: return "Invalid";
2644 rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link)
2646 if (eth_link->link_status == ETH_LINK_DOWN)
2647 return snprintf(str, len, "Link down");
2649 return snprintf(str, len, "Link up at %s %s %s",
2650 rte_eth_link_speed_to_str(eth_link->link_speed),
2651 (eth_link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
2653 (eth_link->link_autoneg == ETH_LINK_AUTONEG) ?
2654 "Autoneg" : "Fixed");
2658 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
2660 struct rte_eth_dev *dev;
2662 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2664 dev = &rte_eth_devices[port_id];
2665 memset(stats, 0, sizeof(*stats));
2667 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP);
2668 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;
2669 return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats));
2673 rte_eth_stats_reset(uint16_t port_id)
2675 struct rte_eth_dev *dev;
2678 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2679 dev = &rte_eth_devices[port_id];
2681 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_reset, -ENOTSUP);
2682 ret = (*dev->dev_ops->stats_reset)(dev);
2684 return eth_err(port_id, ret);
2686 dev->data->rx_mbuf_alloc_failed = 0;
2692 get_xstats_basic_count(struct rte_eth_dev *dev)
2694 uint16_t nb_rxqs, nb_txqs;
2697 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2698 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2700 count = RTE_NB_STATS;
2701 if (dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) {
2702 count += nb_rxqs * RTE_NB_RXQ_STATS;
2703 count += nb_txqs * RTE_NB_TXQ_STATS;
2710 get_xstats_count(uint16_t port_id)
2712 struct rte_eth_dev *dev;
2715 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2716 dev = &rte_eth_devices[port_id];
2717 if (dev->dev_ops->xstats_get_names_by_id != NULL) {
2718 count = (*dev->dev_ops->xstats_get_names_by_id)(dev, NULL,
2721 return eth_err(port_id, count);
2723 if (dev->dev_ops->xstats_get_names != NULL) {
2724 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0);
2726 return eth_err(port_id, count);
2731 count += get_xstats_basic_count(dev);
2737 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name,
2740 int cnt_xstats, idx_xstat;
2742 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2745 RTE_ETHDEV_LOG(ERR, "Id pointer is NULL\n");
2750 RTE_ETHDEV_LOG(ERR, "xstat_name pointer is NULL\n");
2755 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL);
2756 if (cnt_xstats < 0) {
2757 RTE_ETHDEV_LOG(ERR, "Cannot get count of xstats\n");
2761 /* Get id-name lookup table */
2762 struct rte_eth_xstat_name xstats_names[cnt_xstats];
2764 if (cnt_xstats != rte_eth_xstats_get_names_by_id(
2765 port_id, xstats_names, cnt_xstats, NULL)) {
2766 RTE_ETHDEV_LOG(ERR, "Cannot get xstats lookup\n");
2770 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) {
2771 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) {
2780 /* retrieve basic stats names */
2782 rte_eth_basic_stats_get_names(struct rte_eth_dev *dev,
2783 struct rte_eth_xstat_name *xstats_names)
2785 int cnt_used_entries = 0;
2786 uint32_t idx, id_queue;
2789 for (idx = 0; idx < RTE_NB_STATS; idx++) {
2790 strlcpy(xstats_names[cnt_used_entries].name,
2791 rte_stats_strings[idx].name,
2792 sizeof(xstats_names[0].name));
2796 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0)
2797 return cnt_used_entries;
2799 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2800 for (id_queue = 0; id_queue < num_q; id_queue++) {
2801 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) {
2802 snprintf(xstats_names[cnt_used_entries].name,
2803 sizeof(xstats_names[0].name),
2805 id_queue, rte_rxq_stats_strings[idx].name);
2810 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2811 for (id_queue = 0; id_queue < num_q; id_queue++) {
2812 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) {
2813 snprintf(xstats_names[cnt_used_entries].name,
2814 sizeof(xstats_names[0].name),
2816 id_queue, rte_txq_stats_strings[idx].name);
2820 return cnt_used_entries;
2823 /* retrieve ethdev extended statistics names */
2825 rte_eth_xstats_get_names_by_id(uint16_t port_id,
2826 struct rte_eth_xstat_name *xstats_names, unsigned int size,
2829 struct rte_eth_xstat_name *xstats_names_copy;
2830 unsigned int no_basic_stat_requested = 1;
2831 unsigned int no_ext_stat_requested = 1;
2832 unsigned int expected_entries;
2833 unsigned int basic_count;
2834 struct rte_eth_dev *dev;
2838 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2839 dev = &rte_eth_devices[port_id];
2841 basic_count = get_xstats_basic_count(dev);
2842 ret = get_xstats_count(port_id);
2845 expected_entries = (unsigned int)ret;
2847 /* Return max number of stats if no ids given */
2850 return expected_entries;
2851 else if (xstats_names && size < expected_entries)
2852 return expected_entries;
2855 if (ids && !xstats_names)
2858 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) {
2859 uint64_t ids_copy[size];
2861 for (i = 0; i < size; i++) {
2862 if (ids[i] < basic_count) {
2863 no_basic_stat_requested = 0;
2868 * Convert ids to xstats ids that PMD knows.
2869 * ids known by user are basic + extended stats.
2871 ids_copy[i] = ids[i] - basic_count;
2874 if (no_basic_stat_requested)
2875 return (*dev->dev_ops->xstats_get_names_by_id)(dev,
2876 xstats_names, ids_copy, size);
2879 /* Retrieve all stats */
2881 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names,
2883 if (num_stats < 0 || num_stats > (int)expected_entries)
2886 return expected_entries;
2889 xstats_names_copy = calloc(expected_entries,
2890 sizeof(struct rte_eth_xstat_name));
2892 if (!xstats_names_copy) {
2893 RTE_ETHDEV_LOG(ERR, "Can't allocate memory\n");
2898 for (i = 0; i < size; i++) {
2899 if (ids[i] >= basic_count) {
2900 no_ext_stat_requested = 0;
2906 /* Fill xstats_names_copy structure */
2907 if (ids && no_ext_stat_requested) {
2908 rte_eth_basic_stats_get_names(dev, xstats_names_copy);
2910 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy,
2913 free(xstats_names_copy);
2919 for (i = 0; i < size; i++) {
2920 if (ids[i] >= expected_entries) {
2921 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
2922 free(xstats_names_copy);
2925 xstats_names[i] = xstats_names_copy[ids[i]];
2928 free(xstats_names_copy);
2933 rte_eth_xstats_get_names(uint16_t port_id,
2934 struct rte_eth_xstat_name *xstats_names,
2937 struct rte_eth_dev *dev;
2938 int cnt_used_entries;
2939 int cnt_expected_entries;
2940 int cnt_driver_entries;
2942 cnt_expected_entries = get_xstats_count(port_id);
2943 if (xstats_names == NULL || cnt_expected_entries < 0 ||
2944 (int)size < cnt_expected_entries)
2945 return cnt_expected_entries;
2947 /* port_id checked in get_xstats_count() */
2948 dev = &rte_eth_devices[port_id];
2950 cnt_used_entries = rte_eth_basic_stats_get_names(
2953 if (dev->dev_ops->xstats_get_names != NULL) {
2954 /* If there are any driver-specific xstats, append them
2957 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)(
2959 xstats_names + cnt_used_entries,
2960 size - cnt_used_entries);
2961 if (cnt_driver_entries < 0)
2962 return eth_err(port_id, cnt_driver_entries);
2963 cnt_used_entries += cnt_driver_entries;
2966 return cnt_used_entries;
2971 rte_eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats)
2973 struct rte_eth_dev *dev;
2974 struct rte_eth_stats eth_stats;
2975 unsigned int count = 0, i, q;
2976 uint64_t val, *stats_ptr;
2977 uint16_t nb_rxqs, nb_txqs;
2980 ret = rte_eth_stats_get(port_id, ð_stats);
2984 dev = &rte_eth_devices[port_id];
2986 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2987 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2990 for (i = 0; i < RTE_NB_STATS; i++) {
2991 stats_ptr = RTE_PTR_ADD(ð_stats,
2992 rte_stats_strings[i].offset);
2994 xstats[count++].value = val;
2997 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0)
3001 for (q = 0; q < nb_rxqs; q++) {
3002 for (i = 0; i < RTE_NB_RXQ_STATS; i++) {
3003 stats_ptr = RTE_PTR_ADD(ð_stats,
3004 rte_rxq_stats_strings[i].offset +
3005 q * sizeof(uint64_t));
3007 xstats[count++].value = val;
3012 for (q = 0; q < nb_txqs; q++) {
3013 for (i = 0; i < RTE_NB_TXQ_STATS; i++) {
3014 stats_ptr = RTE_PTR_ADD(ð_stats,
3015 rte_txq_stats_strings[i].offset +
3016 q * sizeof(uint64_t));
3018 xstats[count++].value = val;
3024 /* retrieve ethdev extended statistics */
3026 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids,
3027 uint64_t *values, unsigned int size)
3029 unsigned int no_basic_stat_requested = 1;
3030 unsigned int no_ext_stat_requested = 1;
3031 unsigned int num_xstats_filled;
3032 unsigned int basic_count;
3033 uint16_t expected_entries;
3034 struct rte_eth_dev *dev;
3038 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3039 ret = get_xstats_count(port_id);
3042 expected_entries = (uint16_t)ret;
3043 struct rte_eth_xstat xstats[expected_entries];
3044 dev = &rte_eth_devices[port_id];
3045 basic_count = get_xstats_basic_count(dev);
3047 /* Return max number of stats if no ids given */
3050 return expected_entries;
3051 else if (values && size < expected_entries)
3052 return expected_entries;
3058 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) {
3059 unsigned int basic_count = get_xstats_basic_count(dev);
3060 uint64_t ids_copy[size];
3062 for (i = 0; i < size; i++) {
3063 if (ids[i] < basic_count) {
3064 no_basic_stat_requested = 0;
3069 * Convert ids to xstats ids that PMD knows.
3070 * ids known by user are basic + extended stats.
3072 ids_copy[i] = ids[i] - basic_count;
3075 if (no_basic_stat_requested)
3076 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy,
3081 for (i = 0; i < size; i++) {
3082 if (ids[i] >= basic_count) {
3083 no_ext_stat_requested = 0;
3089 /* Fill the xstats structure */
3090 if (ids && no_ext_stat_requested)
3091 ret = rte_eth_basic_stats_get(port_id, xstats);
3093 ret = rte_eth_xstats_get(port_id, xstats, expected_entries);
3097 num_xstats_filled = (unsigned int)ret;
3099 /* Return all stats */
3101 for (i = 0; i < num_xstats_filled; i++)
3102 values[i] = xstats[i].value;
3103 return expected_entries;
3107 for (i = 0; i < size; i++) {
3108 if (ids[i] >= expected_entries) {
3109 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
3112 values[i] = xstats[ids[i]].value;
3118 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats,
3121 struct rte_eth_dev *dev;
3122 unsigned int count = 0, i;
3123 signed int xcount = 0;
3124 uint16_t nb_rxqs, nb_txqs;
3127 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
3129 dev = &rte_eth_devices[port_id];
3131 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
3132 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
3134 /* Return generic statistics */
3135 count = RTE_NB_STATS;
3136 if (dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS)
3137 count += (nb_rxqs * RTE_NB_RXQ_STATS) + (nb_txqs * RTE_NB_TXQ_STATS);
3139 /* implemented by the driver */
3140 if (dev->dev_ops->xstats_get != NULL) {
3141 /* Retrieve the xstats from the driver at the end of the
3144 xcount = (*dev->dev_ops->xstats_get)(dev,
3145 xstats ? xstats + count : NULL,
3146 (n > count) ? n - count : 0);
3149 return eth_err(port_id, xcount);
3152 if (n < count + xcount || xstats == NULL)
3153 return count + xcount;
3155 /* now fill the xstats structure */
3156 ret = rte_eth_basic_stats_get(port_id, xstats);
3161 for (i = 0; i < count; i++)
3163 /* add an offset to driver-specific stats */
3164 for ( ; i < count + xcount; i++)
3165 xstats[i].id += count;
3167 return count + xcount;
3170 /* reset ethdev extended statistics */
3172 rte_eth_xstats_reset(uint16_t port_id)
3174 struct rte_eth_dev *dev;
3176 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3177 dev = &rte_eth_devices[port_id];
3179 /* implemented by the driver */
3180 if (dev->dev_ops->xstats_reset != NULL)
3181 return eth_err(port_id, (*dev->dev_ops->xstats_reset)(dev));
3183 /* fallback to default */
3184 return rte_eth_stats_reset(port_id);
3188 set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id, uint8_t stat_idx,
3191 struct rte_eth_dev *dev;
3193 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3195 dev = &rte_eth_devices[port_id];
3197 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP);
3199 if (is_rx && (queue_id >= dev->data->nb_rx_queues))
3202 if (!is_rx && (queue_id >= dev->data->nb_tx_queues))
3205 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
3208 return (*dev->dev_ops->queue_stats_mapping_set)
3209 (dev, queue_id, stat_idx, is_rx);
3214 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id,
3217 return eth_err(port_id, set_queue_stats_mapping(port_id, tx_queue_id,
3218 stat_idx, STAT_QMAP_TX));
3223 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id,
3226 return eth_err(port_id, set_queue_stats_mapping(port_id, rx_queue_id,
3227 stat_idx, STAT_QMAP_RX));
3231 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size)
3233 struct rte_eth_dev *dev;
3235 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3236 dev = &rte_eth_devices[port_id];
3238 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fw_version_get, -ENOTSUP);
3239 return eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev,
3240 fw_version, fw_size));
3244 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info)
3246 struct rte_eth_dev *dev;
3247 const struct rte_eth_desc_lim lim = {
3248 .nb_max = UINT16_MAX,
3251 .nb_seg_max = UINT16_MAX,
3252 .nb_mtu_seg_max = UINT16_MAX,
3257 * Init dev_info before port_id check since caller does not have
3258 * return status and does not know if get is successful or not.
3260 memset(dev_info, 0, sizeof(struct rte_eth_dev_info));
3261 dev_info->switch_info.domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
3263 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3264 dev = &rte_eth_devices[port_id];
3266 dev_info->rx_desc_lim = lim;
3267 dev_info->tx_desc_lim = lim;
3268 dev_info->device = dev->device;
3269 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3270 dev_info->max_mtu = UINT16_MAX;
3272 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);
3273 diag = (*dev->dev_ops->dev_infos_get)(dev, dev_info);
3275 /* Cleanup already filled in device information */
3276 memset(dev_info, 0, sizeof(struct rte_eth_dev_info));
3277 return eth_err(port_id, diag);
3280 /* Maximum number of queues should be <= RTE_MAX_QUEUES_PER_PORT */
3281 dev_info->max_rx_queues = RTE_MIN(dev_info->max_rx_queues,
3282 RTE_MAX_QUEUES_PER_PORT);
3283 dev_info->max_tx_queues = RTE_MIN(dev_info->max_tx_queues,
3284 RTE_MAX_QUEUES_PER_PORT);
3286 dev_info->driver_name = dev->device->driver->name;
3287 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3288 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3290 dev_info->dev_flags = &dev->data->dev_flags;
3296 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,
3297 uint32_t *ptypes, int num)
3300 struct rte_eth_dev *dev;
3301 const uint32_t *all_ptypes;
3303 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3304 dev = &rte_eth_devices[port_id];
3305 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_supported_ptypes_get, 0);
3306 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
3311 for (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i)
3312 if (all_ptypes[i] & ptype_mask) {
3314 ptypes[j] = all_ptypes[i];
3322 rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask,
3323 uint32_t *set_ptypes, unsigned int num)
3325 const uint32_t valid_ptype_masks[] = {
3329 RTE_PTYPE_TUNNEL_MASK,
3330 RTE_PTYPE_INNER_L2_MASK,
3331 RTE_PTYPE_INNER_L3_MASK,
3332 RTE_PTYPE_INNER_L4_MASK,
3334 const uint32_t *all_ptypes;
3335 struct rte_eth_dev *dev;
3336 uint32_t unused_mask;
3340 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3341 dev = &rte_eth_devices[port_id];
3343 if (num > 0 && set_ptypes == NULL)
3346 if (*dev->dev_ops->dev_supported_ptypes_get == NULL ||
3347 *dev->dev_ops->dev_ptypes_set == NULL) {
3352 if (ptype_mask == 0) {
3353 ret = (*dev->dev_ops->dev_ptypes_set)(dev,
3358 unused_mask = ptype_mask;
3359 for (i = 0; i < RTE_DIM(valid_ptype_masks); i++) {
3360 uint32_t mask = ptype_mask & valid_ptype_masks[i];
3361 if (mask && mask != valid_ptype_masks[i]) {
3365 unused_mask &= ~valid_ptype_masks[i];
3373 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
3374 if (all_ptypes == NULL) {
3380 * Accommodate as many set_ptypes as possible. If the supplied
3381 * set_ptypes array is insufficient fill it partially.
3383 for (i = 0, j = 0; set_ptypes != NULL &&
3384 (all_ptypes[i] != RTE_PTYPE_UNKNOWN); ++i) {
3385 if (ptype_mask & all_ptypes[i]) {
3387 set_ptypes[j] = all_ptypes[i];
3395 if (set_ptypes != NULL && j < num)
3396 set_ptypes[j] = RTE_PTYPE_UNKNOWN;
3398 return (*dev->dev_ops->dev_ptypes_set)(dev, ptype_mask);
3402 set_ptypes[0] = RTE_PTYPE_UNKNOWN;
3408 rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr)
3410 struct rte_eth_dev *dev;
3412 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3413 dev = &rte_eth_devices[port_id];
3414 rte_ether_addr_copy(&dev->data->mac_addrs[0], mac_addr);
3420 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu)
3422 struct rte_eth_dev *dev;
3424 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3426 dev = &rte_eth_devices[port_id];
3427 *mtu = dev->data->mtu;
3432 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu)
3435 struct rte_eth_dev_info dev_info;
3436 struct rte_eth_dev *dev;
3438 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3439 dev = &rte_eth_devices[port_id];
3440 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP);
3443 * Check if the device supports dev_infos_get, if it does not
3444 * skip min_mtu/max_mtu validation here as this requires values
3445 * that are populated within the call to rte_eth_dev_info_get()
3446 * which relies on dev->dev_ops->dev_infos_get.
3448 if (*dev->dev_ops->dev_infos_get != NULL) {
3449 ret = rte_eth_dev_info_get(port_id, &dev_info);
3453 if (mtu < dev_info.min_mtu || mtu > dev_info.max_mtu)
3457 ret = (*dev->dev_ops->mtu_set)(dev, mtu);
3459 dev->data->mtu = mtu;
3461 return eth_err(port_id, ret);
3465 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on)
3467 struct rte_eth_dev *dev;
3470 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3471 dev = &rte_eth_devices[port_id];
3472 if (!(dev->data->dev_conf.rxmode.offloads &
3473 DEV_RX_OFFLOAD_VLAN_FILTER)) {
3474 RTE_ETHDEV_LOG(ERR, "Port %u: vlan-filtering disabled\n",
3479 if (vlan_id > 4095) {
3480 RTE_ETHDEV_LOG(ERR, "Port_id=%u invalid vlan_id=%u > 4095\n",
3484 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP);
3486 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on);
3488 struct rte_vlan_filter_conf *vfc;
3492 vfc = &dev->data->vlan_filter_conf;
3493 vidx = vlan_id / 64;
3494 vbit = vlan_id % 64;
3497 vfc->ids[vidx] |= UINT64_C(1) << vbit;
3499 vfc->ids[vidx] &= ~(UINT64_C(1) << vbit);
3502 return eth_err(port_id, ret);
3506 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id,
3509 struct rte_eth_dev *dev;
3511 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3512 dev = &rte_eth_devices[port_id];
3513 if (rx_queue_id >= dev->data->nb_rx_queues) {
3514 RTE_ETHDEV_LOG(ERR, "Invalid rx_queue_id=%u\n", rx_queue_id);
3518 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
3519 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on);
3525 rte_eth_dev_set_vlan_ether_type(uint16_t port_id,
3526 enum rte_vlan_type vlan_type,
3529 struct rte_eth_dev *dev;
3531 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3532 dev = &rte_eth_devices[port_id];
3533 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP);
3535 return eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type,
3540 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask)
3542 struct rte_eth_dev_info dev_info;
3543 struct rte_eth_dev *dev;
3547 uint64_t orig_offloads;
3548 uint64_t dev_offloads;
3549 uint64_t new_offloads;
3551 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3552 dev = &rte_eth_devices[port_id];
3554 /* save original values in case of failure */
3555 orig_offloads = dev->data->dev_conf.rxmode.offloads;
3556 dev_offloads = orig_offloads;
3558 /* check which option changed by application */
3559 cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD);
3560 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
3563 dev_offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
3565 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
3566 mask |= ETH_VLAN_STRIP_MASK;
3569 cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD);
3570 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER);
3573 dev_offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
3575 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_FILTER;
3576 mask |= ETH_VLAN_FILTER_MASK;
3579 cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD);
3580 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND);
3583 dev_offloads |= DEV_RX_OFFLOAD_VLAN_EXTEND;
3585 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_EXTEND;
3586 mask |= ETH_VLAN_EXTEND_MASK;
3589 cur = !!(offload_mask & ETH_QINQ_STRIP_OFFLOAD);
3590 org = !!(dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP);
3593 dev_offloads |= DEV_RX_OFFLOAD_QINQ_STRIP;
3595 dev_offloads &= ~DEV_RX_OFFLOAD_QINQ_STRIP;
3596 mask |= ETH_QINQ_STRIP_MASK;
3603 ret = rte_eth_dev_info_get(port_id, &dev_info);
3607 /* Rx VLAN offloading must be within its device capabilities */
3608 if ((dev_offloads & dev_info.rx_offload_capa) != dev_offloads) {
3609 new_offloads = dev_offloads & ~orig_offloads;
3611 "Ethdev port_id=%u requested new added VLAN offloads "
3612 "0x%" PRIx64 " must be within Rx offloads capabilities "
3613 "0x%" PRIx64 " in %s()\n",
3614 port_id, new_offloads, dev_info.rx_offload_capa,
3619 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP);
3620 dev->data->dev_conf.rxmode.offloads = dev_offloads;
3621 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask);
3623 /* hit an error restore original values */
3624 dev->data->dev_conf.rxmode.offloads = orig_offloads;
3627 return eth_err(port_id, ret);
3631 rte_eth_dev_get_vlan_offload(uint16_t port_id)
3633 struct rte_eth_dev *dev;
3634 uint64_t *dev_offloads;
3637 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3638 dev = &rte_eth_devices[port_id];
3639 dev_offloads = &dev->data->dev_conf.rxmode.offloads;
3641 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3642 ret |= ETH_VLAN_STRIP_OFFLOAD;
3644 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3645 ret |= ETH_VLAN_FILTER_OFFLOAD;
3647 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3648 ret |= ETH_VLAN_EXTEND_OFFLOAD;
3650 if (*dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
3651 ret |= ETH_QINQ_STRIP_OFFLOAD;
3657 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on)
3659 struct rte_eth_dev *dev;
3661 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3662 dev = &rte_eth_devices[port_id];
3663 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP);
3665 return eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on));
3669 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
3671 struct rte_eth_dev *dev;
3673 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3674 dev = &rte_eth_devices[port_id];
3675 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP);
3676 memset(fc_conf, 0, sizeof(*fc_conf));
3677 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf));
3681 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
3683 struct rte_eth_dev *dev;
3685 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3686 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) {
3687 RTE_ETHDEV_LOG(ERR, "Invalid send_xon, only 0/1 allowed\n");
3691 dev = &rte_eth_devices[port_id];
3692 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP);
3693 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf));
3697 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,
3698 struct rte_eth_pfc_conf *pfc_conf)
3700 struct rte_eth_dev *dev;
3702 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3703 if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) {
3704 RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n");
3708 dev = &rte_eth_devices[port_id];
3709 /* High water, low water validation are device specific */
3710 if (*dev->dev_ops->priority_flow_ctrl_set)
3711 return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set)
3717 rte_eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,
3725 num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE;
3726 for (i = 0; i < num; i++) {
3727 if (reta_conf[i].mask)
3735 rte_eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf,
3739 uint16_t i, idx, shift;
3745 RTE_ETHDEV_LOG(ERR, "No receive queue is available\n");
3749 for (i = 0; i < reta_size; i++) {
3750 idx = i / RTE_RETA_GROUP_SIZE;
3751 shift = i % RTE_RETA_GROUP_SIZE;
3752 if ((reta_conf[idx].mask & (1ULL << shift)) &&
3753 (reta_conf[idx].reta[shift] >= max_rxq)) {
3755 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n",
3757 reta_conf[idx].reta[shift], max_rxq);
3766 rte_eth_dev_rss_reta_update(uint16_t port_id,
3767 struct rte_eth_rss_reta_entry64 *reta_conf,
3770 struct rte_eth_dev *dev;
3773 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3774 /* Check mask bits */
3775 ret = rte_eth_check_reta_mask(reta_conf, reta_size);
3779 dev = &rte_eth_devices[port_id];
3781 /* Check entry value */
3782 ret = rte_eth_check_reta_entry(reta_conf, reta_size,
3783 dev->data->nb_rx_queues);
3787 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP);
3788 return eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf,
3793 rte_eth_dev_rss_reta_query(uint16_t port_id,
3794 struct rte_eth_rss_reta_entry64 *reta_conf,
3797 struct rte_eth_dev *dev;
3800 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3802 /* Check mask bits */
3803 ret = rte_eth_check_reta_mask(reta_conf, reta_size);
3807 dev = &rte_eth_devices[port_id];
3808 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP);
3809 return eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf,
3814 rte_eth_dev_rss_hash_update(uint16_t port_id,
3815 struct rte_eth_rss_conf *rss_conf)
3817 struct rte_eth_dev *dev;
3818 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, };
3821 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3823 ret = rte_eth_dev_info_get(port_id, &dev_info);
3827 rss_conf->rss_hf = rte_eth_rss_hf_refine(rss_conf->rss_hf);
3829 dev = &rte_eth_devices[port_id];
3830 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) !=
3831 dev_info.flow_type_rss_offloads) {
3833 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
3834 port_id, rss_conf->rss_hf,
3835 dev_info.flow_type_rss_offloads);
3838 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP);
3839 return eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev,
3844 rte_eth_dev_rss_hash_conf_get(uint16_t port_id,
3845 struct rte_eth_rss_conf *rss_conf)
3847 struct rte_eth_dev *dev;
3849 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3850 dev = &rte_eth_devices[port_id];
3851 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP);
3852 return eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev,
3857 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,
3858 struct rte_eth_udp_tunnel *udp_tunnel)
3860 struct rte_eth_dev *dev;
3862 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3863 if (udp_tunnel == NULL) {
3864 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3868 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3869 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3873 dev = &rte_eth_devices[port_id];
3874 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_add, -ENOTSUP);
3875 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev,
3880 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,
3881 struct rte_eth_udp_tunnel *udp_tunnel)
3883 struct rte_eth_dev *dev;
3885 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3886 dev = &rte_eth_devices[port_id];
3888 if (udp_tunnel == NULL) {
3889 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3893 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3894 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3898 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_del, -ENOTSUP);
3899 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev,
3904 rte_eth_led_on(uint16_t port_id)
3906 struct rte_eth_dev *dev;
3908 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3909 dev = &rte_eth_devices[port_id];
3910 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP);
3911 return eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev));
3915 rte_eth_led_off(uint16_t port_id)
3917 struct rte_eth_dev *dev;
3919 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3920 dev = &rte_eth_devices[port_id];
3921 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP);
3922 return eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev));
3926 rte_eth_fec_get_capability(uint16_t port_id,
3927 struct rte_eth_fec_capa *speed_fec_capa,
3930 struct rte_eth_dev *dev;
3933 if (speed_fec_capa == NULL && num > 0)
3936 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3937 dev = &rte_eth_devices[port_id];
3938 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get_capability, -ENOTSUP);
3939 ret = (*dev->dev_ops->fec_get_capability)(dev, speed_fec_capa, num);
3945 rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa)
3947 struct rte_eth_dev *dev;
3949 if (fec_capa == NULL)
3952 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3953 dev = &rte_eth_devices[port_id];
3954 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get, -ENOTSUP);
3955 return eth_err(port_id, (*dev->dev_ops->fec_get)(dev, fec_capa));
3959 rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa)
3961 struct rte_eth_dev *dev;
3963 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3964 dev = &rte_eth_devices[port_id];
3965 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_set, -ENOTSUP);
3966 return eth_err(port_id, (*dev->dev_ops->fec_set)(dev, fec_capa));
3970 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
3974 get_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr)
3976 struct rte_eth_dev_info dev_info;
3977 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3981 ret = rte_eth_dev_info_get(port_id, &dev_info);
3985 for (i = 0; i < dev_info.max_mac_addrs; i++)
3986 if (memcmp(addr, &dev->data->mac_addrs[i],
3987 RTE_ETHER_ADDR_LEN) == 0)
3993 static const struct rte_ether_addr null_mac_addr;
3996 rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr,
3999 struct rte_eth_dev *dev;
4004 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4005 dev = &rte_eth_devices[port_id];
4006 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP);
4008 if (rte_is_zero_ether_addr(addr)) {
4009 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
4013 if (pool >= ETH_64_POOLS) {
4014 RTE_ETHDEV_LOG(ERR, "Pool id must be 0-%d\n", ETH_64_POOLS - 1);
4018 index = get_mac_addr_index(port_id, addr);
4020 index = get_mac_addr_index(port_id, &null_mac_addr);
4022 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
4027 pool_mask = dev->data->mac_pool_sel[index];
4029 /* Check if both MAC address and pool is already there, and do nothing */
4030 if (pool_mask & (1ULL << pool))
4035 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool);
4038 /* Update address in NIC data structure */
4039 rte_ether_addr_copy(addr, &dev->data->mac_addrs[index]);
4041 /* Update pool bitmap in NIC data structure */
4042 dev->data->mac_pool_sel[index] |= (1ULL << pool);
4045 return eth_err(port_id, ret);
4049 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *addr)
4051 struct rte_eth_dev *dev;
4054 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4055 dev = &rte_eth_devices[port_id];
4056 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP);
4058 index = get_mac_addr_index(port_id, addr);
4061 "Port %u: Cannot remove default MAC address\n",
4064 } else if (index < 0)
4065 return 0; /* Do nothing if address wasn't found */
4068 (*dev->dev_ops->mac_addr_remove)(dev, index);
4070 /* Update address in NIC data structure */
4071 rte_ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]);
4073 /* reset pool bitmap */
4074 dev->data->mac_pool_sel[index] = 0;
4080 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *addr)
4082 struct rte_eth_dev *dev;
4085 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4087 if (!rte_is_valid_assigned_ether_addr(addr))
4090 dev = &rte_eth_devices[port_id];
4091 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP);
4093 ret = (*dev->dev_ops->mac_addr_set)(dev, addr);
4097 /* Update default address in NIC data structure */
4098 rte_ether_addr_copy(addr, &dev->data->mac_addrs[0]);
4105 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
4109 get_hash_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr)
4111 struct rte_eth_dev_info dev_info;
4112 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4116 ret = rte_eth_dev_info_get(port_id, &dev_info);
4120 if (!dev->data->hash_mac_addrs)
4123 for (i = 0; i < dev_info.max_hash_mac_addrs; i++)
4124 if (memcmp(addr, &dev->data->hash_mac_addrs[i],
4125 RTE_ETHER_ADDR_LEN) == 0)
4132 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr,
4137 struct rte_eth_dev *dev;
4139 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4141 dev = &rte_eth_devices[port_id];
4142 if (rte_is_zero_ether_addr(addr)) {
4143 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
4148 index = get_hash_mac_addr_index(port_id, addr);
4149 /* Check if it's already there, and do nothing */
4150 if ((index >= 0) && on)
4156 "Port %u: the MAC address was not set in UTA\n",
4161 index = get_hash_mac_addr_index(port_id, &null_mac_addr);
4163 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
4169 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP);
4170 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on);
4172 /* Update address in NIC data structure */
4174 rte_ether_addr_copy(addr,
4175 &dev->data->hash_mac_addrs[index]);
4177 rte_ether_addr_copy(&null_mac_addr,
4178 &dev->data->hash_mac_addrs[index]);
4181 return eth_err(port_id, ret);
4185 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on)
4187 struct rte_eth_dev *dev;
4189 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4191 dev = &rte_eth_devices[port_id];
4193 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP);
4194 return eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev,
4198 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,
4201 struct rte_eth_dev *dev;
4202 struct rte_eth_dev_info dev_info;
4203 struct rte_eth_link link;
4206 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4208 ret = rte_eth_dev_info_get(port_id, &dev_info);
4212 dev = &rte_eth_devices[port_id];
4213 link = dev->data->dev_link;
4215 if (queue_idx > dev_info.max_tx_queues) {
4217 "Set queue rate limit:port %u: invalid queue id=%u\n",
4218 port_id, queue_idx);
4222 if (tx_rate > link.link_speed) {
4224 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d\n",
4225 tx_rate, link.link_speed);
4229 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP);
4230 return eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev,
4231 queue_idx, tx_rate));
4235 rte_eth_mirror_rule_set(uint16_t port_id,
4236 struct rte_eth_mirror_conf *mirror_conf,
4237 uint8_t rule_id, uint8_t on)
4239 struct rte_eth_dev *dev;
4241 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4242 if (mirror_conf->rule_type == 0) {
4243 RTE_ETHDEV_LOG(ERR, "Mirror rule type can not be 0\n");
4247 if (mirror_conf->dst_pool >= ETH_64_POOLS) {
4248 RTE_ETHDEV_LOG(ERR, "Invalid dst pool, pool id must be 0-%d\n",
4253 if ((mirror_conf->rule_type & (ETH_MIRROR_VIRTUAL_POOL_UP |
4254 ETH_MIRROR_VIRTUAL_POOL_DOWN)) &&
4255 (mirror_conf->pool_mask == 0)) {
4257 "Invalid mirror pool, pool mask can not be 0\n");
4261 if ((mirror_conf->rule_type & ETH_MIRROR_VLAN) &&
4262 mirror_conf->vlan.vlan_mask == 0) {
4264 "Invalid vlan mask, vlan mask can not be 0\n");
4268 dev = &rte_eth_devices[port_id];
4269 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_set, -ENOTSUP);
4271 return eth_err(port_id, (*dev->dev_ops->mirror_rule_set)(dev,
4272 mirror_conf, rule_id, on));
4276 rte_eth_mirror_rule_reset(uint16_t port_id, uint8_t rule_id)
4278 struct rte_eth_dev *dev;
4280 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4282 dev = &rte_eth_devices[port_id];
4283 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_reset, -ENOTSUP);
4285 return eth_err(port_id, (*dev->dev_ops->mirror_rule_reset)(dev,
4289 RTE_INIT(eth_dev_init_cb_lists)
4293 for (i = 0; i < RTE_MAX_ETHPORTS; i++)
4294 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs);
4298 rte_eth_dev_callback_register(uint16_t port_id,
4299 enum rte_eth_event_type event,
4300 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
4302 struct rte_eth_dev *dev;
4303 struct rte_eth_dev_callback *user_cb;
4304 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */
4310 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
4311 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
4315 if (port_id == RTE_ETH_ALL) {
4317 last_port = RTE_MAX_ETHPORTS - 1;
4319 next_port = last_port = port_id;
4322 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4325 dev = &rte_eth_devices[next_port];
4327 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) {
4328 if (user_cb->cb_fn == cb_fn &&
4329 user_cb->cb_arg == cb_arg &&
4330 user_cb->event == event) {
4335 /* create a new callback. */
4336 if (user_cb == NULL) {
4337 user_cb = rte_zmalloc("INTR_USER_CALLBACK",
4338 sizeof(struct rte_eth_dev_callback), 0);
4339 if (user_cb != NULL) {
4340 user_cb->cb_fn = cb_fn;
4341 user_cb->cb_arg = cb_arg;
4342 user_cb->event = event;
4343 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs),
4346 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4347 rte_eth_dev_callback_unregister(port_id, event,
4353 } while (++next_port <= last_port);
4355 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4360 rte_eth_dev_callback_unregister(uint16_t port_id,
4361 enum rte_eth_event_type event,
4362 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
4365 struct rte_eth_dev *dev;
4366 struct rte_eth_dev_callback *cb, *next;
4367 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */
4373 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
4374 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
4378 if (port_id == RTE_ETH_ALL) {
4380 last_port = RTE_MAX_ETHPORTS - 1;
4382 next_port = last_port = port_id;
4385 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4388 dev = &rte_eth_devices[next_port];
4390 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL;
4393 next = TAILQ_NEXT(cb, next);
4395 if (cb->cb_fn != cb_fn || cb->event != event ||
4396 (cb_arg != (void *)-1 && cb->cb_arg != cb_arg))
4400 * if this callback is not executing right now,
4403 if (cb->active == 0) {
4404 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next);
4410 } while (++next_port <= last_port);
4412 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4417 rte_eth_dev_callback_process(struct rte_eth_dev *dev,
4418 enum rte_eth_event_type event, void *ret_param)
4420 struct rte_eth_dev_callback *cb_lst;
4421 struct rte_eth_dev_callback dev_cb;
4424 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4425 TAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) {
4426 if (cb_lst->cb_fn == NULL || cb_lst->event != event)
4430 if (ret_param != NULL)
4431 dev_cb.ret_param = ret_param;
4433 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4434 rc = dev_cb.cb_fn(dev->data->port_id, dev_cb.event,
4435 dev_cb.cb_arg, dev_cb.ret_param);
4436 rte_spinlock_lock(&rte_eth_dev_cb_lock);
4439 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
4444 rte_eth_dev_probing_finish(struct rte_eth_dev *dev)
4449 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_NEW, NULL);
4451 dev->state = RTE_ETH_DEV_ATTACHED;
4455 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data)
4458 struct rte_eth_dev *dev;
4459 struct rte_intr_handle *intr_handle;
4463 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4465 dev = &rte_eth_devices[port_id];
4467 if (!dev->intr_handle) {
4468 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4472 intr_handle = dev->intr_handle;
4473 if (!intr_handle->intr_vec) {
4474 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4478 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
4479 vec = intr_handle->intr_vec[qid];
4480 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
4481 if (rc && rc != -EEXIST) {
4483 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
4484 port_id, qid, op, epfd, vec);
4492 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id)
4494 struct rte_intr_handle *intr_handle;
4495 struct rte_eth_dev *dev;
4496 unsigned int efd_idx;
4500 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
4502 dev = &rte_eth_devices[port_id];
4504 if (queue_id >= dev->data->nb_rx_queues) {
4505 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
4509 if (!dev->intr_handle) {
4510 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4514 intr_handle = dev->intr_handle;
4515 if (!intr_handle->intr_vec) {
4516 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4520 vec = intr_handle->intr_vec[queue_id];
4521 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ?
4522 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec;
4523 fd = intr_handle->efds[efd_idx];
4529 eth_dma_mzone_name(char *name, size_t len, uint16_t port_id, uint16_t queue_id,
4530 const char *ring_name)
4532 return snprintf(name, len, "eth_p%d_q%d_%s",
4533 port_id, queue_id, ring_name);
4536 const struct rte_memzone *
4537 rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name,
4538 uint16_t queue_id, size_t size, unsigned align,
4541 char z_name[RTE_MEMZONE_NAMESIZE];
4542 const struct rte_memzone *mz;
4545 rc = eth_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,
4546 queue_id, ring_name);
4547 if (rc >= RTE_MEMZONE_NAMESIZE) {
4548 RTE_ETHDEV_LOG(ERR, "ring name too long\n");
4549 rte_errno = ENAMETOOLONG;
4553 mz = rte_memzone_lookup(z_name);
4555 if ((socket_id != SOCKET_ID_ANY && socket_id != mz->socket_id) ||
4557 ((uintptr_t)mz->addr & (align - 1)) != 0) {
4559 "memzone %s does not justify the requested attributes\n",
4567 return rte_memzone_reserve_aligned(z_name, size, socket_id,
4568 RTE_MEMZONE_IOVA_CONTIG, align);
4572 rte_eth_dma_zone_free(const struct rte_eth_dev *dev, const char *ring_name,
4575 char z_name[RTE_MEMZONE_NAMESIZE];
4576 const struct rte_memzone *mz;
4579 rc = eth_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,
4580 queue_id, ring_name);
4581 if (rc >= RTE_MEMZONE_NAMESIZE) {
4582 RTE_ETHDEV_LOG(ERR, "ring name too long\n");
4583 return -ENAMETOOLONG;
4586 mz = rte_memzone_lookup(z_name);
4588 rc = rte_memzone_free(mz);
4596 rte_eth_dev_create(struct rte_device *device, const char *name,
4597 size_t priv_data_size,
4598 ethdev_bus_specific_init ethdev_bus_specific_init,
4599 void *bus_init_params,
4600 ethdev_init_t ethdev_init, void *init_params)
4602 struct rte_eth_dev *ethdev;
4605 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL);
4607 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
4608 ethdev = rte_eth_dev_allocate(name);
4612 if (priv_data_size) {
4613 ethdev->data->dev_private = rte_zmalloc_socket(
4614 name, priv_data_size, RTE_CACHE_LINE_SIZE,
4617 if (!ethdev->data->dev_private) {
4619 "failed to allocate private data\n");
4625 ethdev = rte_eth_dev_attach_secondary(name);
4628 "secondary process attach failed, ethdev doesn't exist\n");
4633 ethdev->device = device;
4635 if (ethdev_bus_specific_init) {
4636 retval = ethdev_bus_specific_init(ethdev, bus_init_params);
4639 "ethdev bus specific initialisation failed\n");
4644 retval = ethdev_init(ethdev, init_params);
4646 RTE_ETHDEV_LOG(ERR, "ethdev initialisation failed\n");
4650 rte_eth_dev_probing_finish(ethdev);
4655 rte_eth_dev_release_port(ethdev);
4660 rte_eth_dev_destroy(struct rte_eth_dev *ethdev,
4661 ethdev_uninit_t ethdev_uninit)
4665 ethdev = rte_eth_dev_allocated(ethdev->data->name);
4669 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_uninit, -EINVAL);
4671 ret = ethdev_uninit(ethdev);
4675 return rte_eth_dev_release_port(ethdev);
4679 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id,
4680 int epfd, int op, void *data)
4683 struct rte_eth_dev *dev;
4684 struct rte_intr_handle *intr_handle;
4687 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4689 dev = &rte_eth_devices[port_id];
4690 if (queue_id >= dev->data->nb_rx_queues) {
4691 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
4695 if (!dev->intr_handle) {
4696 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4700 intr_handle = dev->intr_handle;
4701 if (!intr_handle->intr_vec) {
4702 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4706 vec = intr_handle->intr_vec[queue_id];
4707 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
4708 if (rc && rc != -EEXIST) {
4710 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
4711 port_id, queue_id, op, epfd, vec);
4719 rte_eth_dev_rx_intr_enable(uint16_t port_id,
4722 struct rte_eth_dev *dev;
4725 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4727 dev = &rte_eth_devices[port_id];
4729 ret = eth_dev_validate_rx_queue(dev, queue_id);
4733 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP);
4734 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev,
4739 rte_eth_dev_rx_intr_disable(uint16_t port_id,
4742 struct rte_eth_dev *dev;
4745 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4747 dev = &rte_eth_devices[port_id];
4749 ret = eth_dev_validate_rx_queue(dev, queue_id);
4753 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP);
4754 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev,
4760 rte_eth_dev_filter_supported(uint16_t port_id,
4761 enum rte_filter_type filter_type)
4763 struct rte_eth_dev *dev;
4765 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4767 dev = &rte_eth_devices[port_id];
4768 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);
4769 return (*dev->dev_ops->filter_ctrl)(dev, filter_type,
4770 RTE_ETH_FILTER_NOP, NULL);
4774 rte_eth_dev_filter_ctrl(uint16_t port_id, enum rte_filter_type filter_type,
4775 enum rte_filter_op filter_op, void *arg)
4777 struct rte_eth_dev *dev;
4779 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4781 dev = &rte_eth_devices[port_id];
4782 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);
4783 return eth_err(port_id, (*dev->dev_ops->filter_ctrl)(dev, filter_type,
4787 const struct rte_eth_rxtx_callback *
4788 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id,
4789 rte_rx_callback_fn fn, void *user_param)
4791 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4792 rte_errno = ENOTSUP;
4795 struct rte_eth_dev *dev;
4797 /* check input parameters */
4798 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4799 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
4803 dev = &rte_eth_devices[port_id];
4804 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
4808 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4816 cb->param = user_param;
4818 rte_spinlock_lock(&rte_eth_rx_cb_lock);
4819 /* Add the callbacks in fifo order. */
4820 struct rte_eth_rxtx_callback *tail =
4821 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
4824 /* Stores to cb->fn and cb->param should complete before
4825 * cb is visible to data plane.
4828 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id],
4829 cb, __ATOMIC_RELEASE);
4834 /* Stores to cb->fn and cb->param should complete before
4835 * cb is visible to data plane.
4837 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE);
4839 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
4844 const struct rte_eth_rxtx_callback *
4845 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id,
4846 rte_rx_callback_fn fn, void *user_param)
4848 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4849 rte_errno = ENOTSUP;
4852 /* check input parameters */
4853 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4854 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
4859 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4867 cb->param = user_param;
4869 rte_spinlock_lock(&rte_eth_rx_cb_lock);
4870 /* Add the callbacks at first position */
4871 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
4872 /* Stores to cb->fn, cb->param and cb->next should complete before
4873 * cb is visible to data plane threads.
4876 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id],
4877 cb, __ATOMIC_RELEASE);
4878 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
4883 const struct rte_eth_rxtx_callback *
4884 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id,
4885 rte_tx_callback_fn fn, void *user_param)
4887 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4888 rte_errno = ENOTSUP;
4891 struct rte_eth_dev *dev;
4893 /* check input parameters */
4894 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4895 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) {
4900 dev = &rte_eth_devices[port_id];
4901 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
4906 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4914 cb->param = user_param;
4916 rte_spinlock_lock(&rte_eth_tx_cb_lock);
4917 /* Add the callbacks in fifo order. */
4918 struct rte_eth_rxtx_callback *tail =
4919 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id];
4922 /* Stores to cb->fn and cb->param should complete before
4923 * cb is visible to data plane.
4926 &rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id],
4927 cb, __ATOMIC_RELEASE);
4932 /* Stores to cb->fn and cb->param should complete before
4933 * cb is visible to data plane.
4935 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE);
4937 rte_spinlock_unlock(&rte_eth_tx_cb_lock);
4943 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id,
4944 const struct rte_eth_rxtx_callback *user_cb)
4946 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4949 /* Check input parameters. */
4950 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
4951 if (user_cb == NULL ||
4952 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues)
4955 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4956 struct rte_eth_rxtx_callback *cb;
4957 struct rte_eth_rxtx_callback **prev_cb;
4960 rte_spinlock_lock(&rte_eth_rx_cb_lock);
4961 prev_cb = &dev->post_rx_burst_cbs[queue_id];
4962 for (; *prev_cb != NULL; prev_cb = &cb->next) {
4964 if (cb == user_cb) {
4965 /* Remove the user cb from the callback list. */
4966 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED);
4971 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
4977 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id,
4978 const struct rte_eth_rxtx_callback *user_cb)
4980 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4983 /* Check input parameters. */
4984 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
4985 if (user_cb == NULL ||
4986 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues)
4989 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4991 struct rte_eth_rxtx_callback *cb;
4992 struct rte_eth_rxtx_callback **prev_cb;
4994 rte_spinlock_lock(&rte_eth_tx_cb_lock);
4995 prev_cb = &dev->pre_tx_burst_cbs[queue_id];
4996 for (; *prev_cb != NULL; prev_cb = &cb->next) {
4998 if (cb == user_cb) {
4999 /* Remove the user cb from the callback list. */
5000 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED);
5005 rte_spinlock_unlock(&rte_eth_tx_cb_lock);
5011 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id,
5012 struct rte_eth_rxq_info *qinfo)
5014 struct rte_eth_dev *dev;
5016 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5021 dev = &rte_eth_devices[port_id];
5022 if (queue_id >= dev->data->nb_rx_queues) {
5023 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
5027 if (dev->data->rx_queues == NULL ||
5028 dev->data->rx_queues[queue_id] == NULL) {
5030 "Rx queue %"PRIu16" of device with port_id=%"
5031 PRIu16" has not been setup\n",
5036 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
5037 RTE_ETHDEV_LOG(INFO,
5038 "Can't get hairpin Rx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
5043 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP);
5045 memset(qinfo, 0, sizeof(*qinfo));
5046 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo);
5051 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id,
5052 struct rte_eth_txq_info *qinfo)
5054 struct rte_eth_dev *dev;
5056 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5061 dev = &rte_eth_devices[port_id];
5062 if (queue_id >= dev->data->nb_tx_queues) {
5063 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
5067 if (dev->data->tx_queues == NULL ||
5068 dev->data->tx_queues[queue_id] == NULL) {
5070 "Tx queue %"PRIu16" of device with port_id=%"
5071 PRIu16" has not been setup\n",
5076 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
5077 RTE_ETHDEV_LOG(INFO,
5078 "Can't get hairpin Tx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
5083 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP);
5085 memset(qinfo, 0, sizeof(*qinfo));
5086 dev->dev_ops->txq_info_get(dev, queue_id, qinfo);
5092 rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
5093 struct rte_eth_burst_mode *mode)
5095 struct rte_eth_dev *dev;
5097 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5102 dev = &rte_eth_devices[port_id];
5104 if (queue_id >= dev->data->nb_rx_queues) {
5105 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
5109 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_burst_mode_get, -ENOTSUP);
5110 memset(mode, 0, sizeof(*mode));
5111 return eth_err(port_id,
5112 dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode));
5116 rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
5117 struct rte_eth_burst_mode *mode)
5119 struct rte_eth_dev *dev;
5121 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5126 dev = &rte_eth_devices[port_id];
5128 if (queue_id >= dev->data->nb_tx_queues) {
5129 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
5133 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_burst_mode_get, -ENOTSUP);
5134 memset(mode, 0, sizeof(*mode));
5135 return eth_err(port_id,
5136 dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode));
5140 rte_eth_dev_set_mc_addr_list(uint16_t port_id,
5141 struct rte_ether_addr *mc_addr_set,
5142 uint32_t nb_mc_addr)
5144 struct rte_eth_dev *dev;
5146 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5148 dev = &rte_eth_devices[port_id];
5149 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP);
5150 return eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev,
5151 mc_addr_set, nb_mc_addr));
5155 rte_eth_timesync_enable(uint16_t port_id)
5157 struct rte_eth_dev *dev;
5159 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5160 dev = &rte_eth_devices[port_id];
5162 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP);
5163 return eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev));
5167 rte_eth_timesync_disable(uint16_t port_id)
5169 struct rte_eth_dev *dev;
5171 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5172 dev = &rte_eth_devices[port_id];
5174 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP);
5175 return eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev));
5179 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp,
5182 struct rte_eth_dev *dev;
5184 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5185 dev = &rte_eth_devices[port_id];
5187 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP);
5188 return eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp)
5189 (dev, timestamp, flags));
5193 rte_eth_timesync_read_tx_timestamp(uint16_t port_id,
5194 struct timespec *timestamp)
5196 struct rte_eth_dev *dev;
5198 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5199 dev = &rte_eth_devices[port_id];
5201 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP);
5202 return eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp)
5207 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta)
5209 struct rte_eth_dev *dev;
5211 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5212 dev = &rte_eth_devices[port_id];
5214 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_adjust_time, -ENOTSUP);
5215 return eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev,
5220 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp)
5222 struct rte_eth_dev *dev;
5224 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5225 dev = &rte_eth_devices[port_id];
5227 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_time, -ENOTSUP);
5228 return eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev,
5233 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp)
5235 struct rte_eth_dev *dev;
5237 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5238 dev = &rte_eth_devices[port_id];
5240 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_write_time, -ENOTSUP);
5241 return eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev,
5246 rte_eth_read_clock(uint16_t port_id, uint64_t *clock)
5248 struct rte_eth_dev *dev;
5250 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5251 dev = &rte_eth_devices[port_id];
5253 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->read_clock, -ENOTSUP);
5254 return eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock));
5258 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)
5260 struct rte_eth_dev *dev;
5262 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5264 dev = &rte_eth_devices[port_id];
5265 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP);
5266 return eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info));
5270 rte_eth_dev_get_eeprom_length(uint16_t port_id)
5272 struct rte_eth_dev *dev;
5274 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5276 dev = &rte_eth_devices[port_id];
5277 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP);
5278 return eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev));
5282 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
5284 struct rte_eth_dev *dev;
5286 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5288 dev = &rte_eth_devices[port_id];
5289 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP);
5290 return eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info));
5294 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
5296 struct rte_eth_dev *dev;
5298 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5300 dev = &rte_eth_devices[port_id];
5301 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP);
5302 return eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info));
5306 rte_eth_dev_get_module_info(uint16_t port_id,
5307 struct rte_eth_dev_module_info *modinfo)
5309 struct rte_eth_dev *dev;
5311 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5313 dev = &rte_eth_devices[port_id];
5314 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_info, -ENOTSUP);
5315 return (*dev->dev_ops->get_module_info)(dev, modinfo);
5319 rte_eth_dev_get_module_eeprom(uint16_t port_id,
5320 struct rte_dev_eeprom_info *info)
5322 struct rte_eth_dev *dev;
5324 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5326 dev = &rte_eth_devices[port_id];
5327 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_eeprom, -ENOTSUP);
5328 return (*dev->dev_ops->get_module_eeprom)(dev, info);
5332 rte_eth_dev_get_dcb_info(uint16_t port_id,
5333 struct rte_eth_dcb_info *dcb_info)
5335 struct rte_eth_dev *dev;
5337 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5339 dev = &rte_eth_devices[port_id];
5340 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info));
5342 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_dcb_info, -ENOTSUP);
5343 return eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info));
5347 rte_eth_dev_l2_tunnel_eth_type_conf(uint16_t port_id,
5348 struct rte_eth_l2_tunnel_conf *l2_tunnel)
5350 struct rte_eth_dev *dev;
5352 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5353 if (l2_tunnel == NULL) {
5354 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n");
5358 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) {
5359 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
5363 dev = &rte_eth_devices[port_id];
5364 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_eth_type_conf,
5366 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_eth_type_conf)(dev,
5371 rte_eth_dev_l2_tunnel_offload_set(uint16_t port_id,
5372 struct rte_eth_l2_tunnel_conf *l2_tunnel,
5376 struct rte_eth_dev *dev;
5378 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5380 if (l2_tunnel == NULL) {
5381 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n");
5385 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) {
5386 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
5391 RTE_ETHDEV_LOG(ERR, "Mask should have a value\n");
5395 dev = &rte_eth_devices[port_id];
5396 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_offload_set,
5398 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_offload_set)(dev,
5399 l2_tunnel, mask, en));
5403 rte_eth_dev_adjust_nb_desc(uint16_t *nb_desc,
5404 const struct rte_eth_desc_lim *desc_lim)
5406 if (desc_lim->nb_align != 0)
5407 *nb_desc = RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_align);
5409 if (desc_lim->nb_max != 0)
5410 *nb_desc = RTE_MIN(*nb_desc, desc_lim->nb_max);
5412 *nb_desc = RTE_MAX(*nb_desc, desc_lim->nb_min);
5416 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id,
5417 uint16_t *nb_rx_desc,
5418 uint16_t *nb_tx_desc)
5420 struct rte_eth_dev_info dev_info;
5423 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5425 ret = rte_eth_dev_info_get(port_id, &dev_info);
5429 if (nb_rx_desc != NULL)
5430 rte_eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim);
5432 if (nb_tx_desc != NULL)
5433 rte_eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim);
5439 rte_eth_dev_hairpin_capability_get(uint16_t port_id,
5440 struct rte_eth_hairpin_cap *cap)
5442 struct rte_eth_dev *dev;
5444 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
5446 dev = &rte_eth_devices[port_id];
5447 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_cap_get, -ENOTSUP);
5448 memset(cap, 0, sizeof(*cap));
5449 return eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap));
5453 rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
5455 if (dev->data->rx_queue_state[queue_id] ==
5456 RTE_ETH_QUEUE_STATE_HAIRPIN)
5462 rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
5464 if (dev->data->tx_queue_state[queue_id] ==
5465 RTE_ETH_QUEUE_STATE_HAIRPIN)
5471 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)
5473 struct rte_eth_dev *dev;
5475 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5480 dev = &rte_eth_devices[port_id];
5482 if (*dev->dev_ops->pool_ops_supported == NULL)
5483 return 1; /* all pools are supported */
5485 return (*dev->dev_ops->pool_ops_supported)(dev, pool);
5489 * A set of values to describe the possible states of a switch domain.
5491 enum rte_eth_switch_domain_state {
5492 RTE_ETH_SWITCH_DOMAIN_UNUSED = 0,
5493 RTE_ETH_SWITCH_DOMAIN_ALLOCATED
5497 * Array of switch domains available for allocation. Array is sized to
5498 * RTE_MAX_ETHPORTS elements as there cannot be more active switch domains than
5499 * ethdev ports in a single process.
5501 static struct rte_eth_dev_switch {
5502 enum rte_eth_switch_domain_state state;
5503 } rte_eth_switch_domains[RTE_MAX_ETHPORTS];
5506 rte_eth_switch_domain_alloc(uint16_t *domain_id)
5510 *domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
5512 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
5513 if (rte_eth_switch_domains[i].state ==
5514 RTE_ETH_SWITCH_DOMAIN_UNUSED) {
5515 rte_eth_switch_domains[i].state =
5516 RTE_ETH_SWITCH_DOMAIN_ALLOCATED;
5526 rte_eth_switch_domain_free(uint16_t domain_id)
5528 if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID ||
5529 domain_id >= RTE_MAX_ETHPORTS)
5532 if (rte_eth_switch_domains[domain_id].state !=
5533 RTE_ETH_SWITCH_DOMAIN_ALLOCATED)
5536 rte_eth_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED;
5542 rte_eth_devargs_tokenise(struct rte_kvargs *arglist, const char *str_in)
5545 struct rte_kvargs_pair *pair;
5548 arglist->str = strdup(str_in);
5549 if (arglist->str == NULL)
5552 letter = arglist->str;
5555 pair = &arglist->pairs[0];
5558 case 0: /* Initial */
5561 else if (*letter == '\0')
5568 case 1: /* Parsing key */
5569 if (*letter == '=') {
5571 pair->value = letter + 1;
5573 } else if (*letter == ',' || *letter == '\0')
5578 case 2: /* Parsing value */
5581 else if (*letter == ',') {
5584 pair = &arglist->pairs[arglist->count];
5586 } else if (*letter == '\0') {
5589 pair = &arglist->pairs[arglist->count];
5594 case 3: /* Parsing list */
5597 else if (*letter == '\0')
5606 rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da)
5608 struct rte_kvargs args;
5609 struct rte_kvargs_pair *pair;
5613 memset(eth_da, 0, sizeof(*eth_da));
5615 result = rte_eth_devargs_tokenise(&args, dargs);
5619 for (i = 0; i < args.count; i++) {
5620 pair = &args.pairs[i];
5621 if (strcmp("representor", pair->key) == 0) {
5622 result = rte_eth_devargs_parse_list(pair->value,
5623 rte_eth_devargs_parse_representor_ports,
5638 handle_port_list(const char *cmd __rte_unused,
5639 const char *params __rte_unused,
5640 struct rte_tel_data *d)
5644 rte_tel_data_start_array(d, RTE_TEL_INT_VAL);
5645 RTE_ETH_FOREACH_DEV(port_id)
5646 rte_tel_data_add_array_int(d, port_id);
5651 add_port_queue_stats(struct rte_tel_data *d, uint64_t *q_stats,
5652 const char *stat_name)
5655 struct rte_tel_data *q_data = rte_tel_data_alloc();
5656 rte_tel_data_start_array(q_data, RTE_TEL_U64_VAL);
5657 for (q = 0; q < RTE_ETHDEV_QUEUE_STAT_CNTRS; q++)
5658 rte_tel_data_add_array_u64(q_data, q_stats[q]);
5659 rte_tel_data_add_dict_container(d, stat_name, q_data, 0);
5662 #define ADD_DICT_STAT(stats, s) rte_tel_data_add_dict_u64(d, #s, stats.s)
5665 handle_port_stats(const char *cmd __rte_unused,
5667 struct rte_tel_data *d)
5669 struct rte_eth_stats stats;
5672 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5675 port_id = atoi(params);
5676 if (!rte_eth_dev_is_valid_port(port_id))
5679 ret = rte_eth_stats_get(port_id, &stats);
5683 rte_tel_data_start_dict(d);
5684 ADD_DICT_STAT(stats, ipackets);
5685 ADD_DICT_STAT(stats, opackets);
5686 ADD_DICT_STAT(stats, ibytes);
5687 ADD_DICT_STAT(stats, obytes);
5688 ADD_DICT_STAT(stats, imissed);
5689 ADD_DICT_STAT(stats, ierrors);
5690 ADD_DICT_STAT(stats, oerrors);
5691 ADD_DICT_STAT(stats, rx_nombuf);
5692 add_port_queue_stats(d, stats.q_ipackets, "q_ipackets");
5693 add_port_queue_stats(d, stats.q_opackets, "q_opackets");
5694 add_port_queue_stats(d, stats.q_ibytes, "q_ibytes");
5695 add_port_queue_stats(d, stats.q_obytes, "q_obytes");
5696 add_port_queue_stats(d, stats.q_errors, "q_errors");
5702 handle_port_xstats(const char *cmd __rte_unused,
5704 struct rte_tel_data *d)
5706 struct rte_eth_xstat *eth_xstats;
5707 struct rte_eth_xstat_name *xstat_names;
5708 int port_id, num_xstats;
5712 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5715 port_id = strtoul(params, &end_param, 0);
5716 if (*end_param != '\0')
5717 RTE_ETHDEV_LOG(NOTICE,
5718 "Extra parameters passed to ethdev telemetry command, ignoring");
5719 if (!rte_eth_dev_is_valid_port(port_id))
5722 num_xstats = rte_eth_xstats_get(port_id, NULL, 0);
5726 /* use one malloc for both names and stats */
5727 eth_xstats = malloc((sizeof(struct rte_eth_xstat) +
5728 sizeof(struct rte_eth_xstat_name)) * num_xstats);
5729 if (eth_xstats == NULL)
5731 xstat_names = (void *)ð_xstats[num_xstats];
5733 ret = rte_eth_xstats_get_names(port_id, xstat_names, num_xstats);
5734 if (ret < 0 || ret > num_xstats) {
5739 ret = rte_eth_xstats_get(port_id, eth_xstats, num_xstats);
5740 if (ret < 0 || ret > num_xstats) {
5745 rte_tel_data_start_dict(d);
5746 for (i = 0; i < num_xstats; i++)
5747 rte_tel_data_add_dict_u64(d, xstat_names[i].name,
5748 eth_xstats[i].value);
5753 handle_port_link_status(const char *cmd __rte_unused,
5755 struct rte_tel_data *d)
5757 static const char *status_str = "status";
5759 struct rte_eth_link link;
5762 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5765 port_id = strtoul(params, &end_param, 0);
5766 if (*end_param != '\0')
5767 RTE_ETHDEV_LOG(NOTICE,
5768 "Extra parameters passed to ethdev telemetry command, ignoring");
5769 if (!rte_eth_dev_is_valid_port(port_id))
5772 ret = rte_eth_link_get(port_id, &link);
5776 rte_tel_data_start_dict(d);
5777 if (!link.link_status) {
5778 rte_tel_data_add_dict_string(d, status_str, "DOWN");
5781 rte_tel_data_add_dict_string(d, status_str, "UP");
5782 rte_tel_data_add_dict_u64(d, "speed", link.link_speed);
5783 rte_tel_data_add_dict_string(d, "duplex",
5784 (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
5785 "full-duplex" : "half-duplex");
5790 rte_eth_hairpin_queue_peer_update(uint16_t peer_port, uint16_t peer_queue,
5791 struct rte_hairpin_peer_info *cur_info,
5792 struct rte_hairpin_peer_info *peer_info,
5795 struct rte_eth_dev *dev;
5797 /* Current queue information is not mandatory. */
5798 if (peer_info == NULL)
5801 /* No need to check the validity again. */
5802 dev = &rte_eth_devices[peer_port];
5803 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_update,
5806 return (*dev->dev_ops->hairpin_queue_peer_update)(dev, peer_queue,
5807 cur_info, peer_info, direction);
5811 rte_eth_hairpin_queue_peer_bind(uint16_t cur_port, uint16_t cur_queue,
5812 struct rte_hairpin_peer_info *peer_info,
5815 struct rte_eth_dev *dev;
5817 if (peer_info == NULL)
5820 /* No need to check the validity again. */
5821 dev = &rte_eth_devices[cur_port];
5822 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_bind,
5825 return (*dev->dev_ops->hairpin_queue_peer_bind)(dev, cur_queue,
5826 peer_info, direction);
5830 rte_eth_hairpin_queue_peer_unbind(uint16_t cur_port, uint16_t cur_queue,
5833 struct rte_eth_dev *dev;
5835 /* No need to check the validity again. */
5836 dev = &rte_eth_devices[cur_port];
5837 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_unbind,
5840 return (*dev->dev_ops->hairpin_queue_peer_unbind)(dev, cur_queue,
5844 RTE_LOG_REGISTER(rte_eth_dev_logtype, lib.ethdev, INFO);
5846 RTE_INIT(ethdev_init_telemetry)
5848 rte_telemetry_register_cmd("/ethdev/list", handle_port_list,
5849 "Returns list of available ethdev ports. Takes no parameters");
5850 rte_telemetry_register_cmd("/ethdev/stats", handle_port_stats,
5851 "Returns the common stats for a port. Parameters: int port_id");
5852 rte_telemetry_register_cmd("/ethdev/xstats", handle_port_xstats,
5853 "Returns the extended stats for a port. Parameters: int port_id");
5854 rte_telemetry_register_cmd("/ethdev/link_status",
5855 handle_port_link_status,
5856 "Returns the link status for a port. Parameters: int port_id");