1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
16 #include <netinet/in.h>
18 #include <rte_byteorder.h>
20 #include <rte_debug.h>
21 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memcpy.h>
24 #include <rte_memzone.h>
25 #include <rte_launch.h>
27 #include <rte_per_lcore.h>
28 #include <rte_lcore.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_common.h>
31 #include <rte_mempool.h>
32 #include <rte_malloc.h>
34 #include <rte_errno.h>
35 #include <rte_spinlock.h>
36 #include <rte_string_fns.h>
37 #include <rte_kvargs.h>
38 #include <rte_class.h>
39 #include <rte_ether.h>
40 #include <rte_telemetry.h>
42 #include "rte_ethdev_trace.h"
43 #include "rte_ethdev.h"
44 #include "rte_ethdev_driver.h"
45 #include "ethdev_profile.h"
46 #include "ethdev_private.h"
48 static const char *MZ_RTE_ETH_DEV_DATA = "rte_eth_dev_data";
49 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS];
51 /* spinlock for eth device callbacks */
52 static rte_spinlock_t eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER;
54 /* spinlock for add/remove rx callbacks */
55 static rte_spinlock_t eth_dev_rx_cb_lock = RTE_SPINLOCK_INITIALIZER;
57 /* spinlock for add/remove tx callbacks */
58 static rte_spinlock_t eth_dev_tx_cb_lock = RTE_SPINLOCK_INITIALIZER;
60 /* spinlock for shared data allocation */
61 static rte_spinlock_t eth_dev_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
63 /* store statistics names and its offset in stats structure */
64 struct rte_eth_xstats_name_off {
65 char name[RTE_ETH_XSTATS_NAME_SIZE];
69 /* Shared memory between primary and secondary processes. */
71 uint64_t next_owner_id;
72 rte_spinlock_t ownership_lock;
73 struct rte_eth_dev_data data[RTE_MAX_ETHPORTS];
74 } *eth_dev_shared_data;
76 static const struct rte_eth_xstats_name_off eth_dev_stats_strings[] = {
77 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)},
78 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)},
79 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)},
80 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)},
81 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)},
82 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)},
83 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)},
84 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats,
88 #define RTE_NB_STATS RTE_DIM(eth_dev_stats_strings)
90 static const struct rte_eth_xstats_name_off eth_dev_rxq_stats_strings[] = {
91 {"packets", offsetof(struct rte_eth_stats, q_ipackets)},
92 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)},
93 {"errors", offsetof(struct rte_eth_stats, q_errors)},
96 #define RTE_NB_RXQ_STATS RTE_DIM(eth_dev_rxq_stats_strings)
98 static const struct rte_eth_xstats_name_off eth_dev_txq_stats_strings[] = {
99 {"packets", offsetof(struct rte_eth_stats, q_opackets)},
100 {"bytes", offsetof(struct rte_eth_stats, q_obytes)},
102 #define RTE_NB_TXQ_STATS RTE_DIM(eth_dev_txq_stats_strings)
104 #define RTE_RX_OFFLOAD_BIT2STR(_name) \
105 { DEV_RX_OFFLOAD_##_name, #_name }
107 #define RTE_ETH_RX_OFFLOAD_BIT2STR(_name) \
108 { RTE_ETH_RX_OFFLOAD_##_name, #_name }
110 static const struct {
113 } eth_dev_rx_offload_names[] = {
114 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP),
115 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM),
116 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM),
117 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM),
118 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO),
119 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP),
120 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
121 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP),
122 RTE_RX_OFFLOAD_BIT2STR(HEADER_SPLIT),
123 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER),
124 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND),
125 RTE_RX_OFFLOAD_BIT2STR(JUMBO_FRAME),
126 RTE_RX_OFFLOAD_BIT2STR(SCATTER),
127 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP),
128 RTE_RX_OFFLOAD_BIT2STR(SECURITY),
129 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC),
130 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM),
131 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
132 RTE_RX_OFFLOAD_BIT2STR(RSS_HASH),
133 RTE_ETH_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT),
136 #undef RTE_RX_OFFLOAD_BIT2STR
137 #undef RTE_ETH_RX_OFFLOAD_BIT2STR
139 #define RTE_TX_OFFLOAD_BIT2STR(_name) \
140 { DEV_TX_OFFLOAD_##_name, #_name }
142 static const struct {
145 } eth_dev_tx_offload_names[] = {
146 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT),
147 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM),
148 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM),
149 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM),
150 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM),
151 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO),
152 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO),
153 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
154 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT),
155 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO),
156 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO),
157 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO),
158 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO),
159 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT),
160 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE),
161 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS),
162 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE),
163 RTE_TX_OFFLOAD_BIT2STR(SECURITY),
164 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO),
165 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO),
166 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
167 RTE_TX_OFFLOAD_BIT2STR(SEND_ON_TIMESTAMP),
170 #undef RTE_TX_OFFLOAD_BIT2STR
173 * The user application callback description.
175 * It contains callback address to be registered by user application,
176 * the pointer to the parameters for callback, and the event type.
178 struct rte_eth_dev_callback {
179 TAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */
180 rte_eth_dev_cb_fn cb_fn; /**< Callback address */
181 void *cb_arg; /**< Parameter for callback */
182 void *ret_param; /**< Return parameter */
183 enum rte_eth_event_type event; /**< Interrupt event type */
184 uint32_t active; /**< Callback is executing */
193 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str)
196 struct rte_devargs devargs = {.args = NULL};
197 const char *bus_param_key;
198 char *bus_str = NULL;
199 char *cls_str = NULL;
202 memset(iter, 0, sizeof(*iter));
205 * The devargs string may use various syntaxes:
206 * - 0000:08:00.0,representor=[1-3]
207 * - pci:0000:06:00.0,representor=[0,5]
208 * - class=eth,mac=00:11:22:33:44:55
209 * A new syntax is in development (not yet supported):
210 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z
214 * Handle pure class filter (i.e. without any bus-level argument),
215 * from future new syntax.
216 * rte_devargs_parse() is not yet supporting the new syntax,
217 * that's why this simple case is temporarily parsed here.
219 #define iter_anybus_str "class=eth,"
220 if (strncmp(devargs_str, iter_anybus_str,
221 strlen(iter_anybus_str)) == 0) {
222 iter->cls_str = devargs_str + strlen(iter_anybus_str);
226 /* Split bus, device and parameters. */
227 ret = rte_devargs_parse(&devargs, devargs_str);
232 * Assume parameters of old syntax can match only at ethdev level.
233 * Extra parameters will be ignored, thanks to "+" prefix.
235 str_size = strlen(devargs.args) + 2;
236 cls_str = malloc(str_size);
237 if (cls_str == NULL) {
241 ret = snprintf(cls_str, str_size, "+%s", devargs.args);
242 if (ret != str_size - 1) {
246 iter->cls_str = cls_str;
247 free(devargs.args); /* allocated by rte_devargs_parse() */
250 iter->bus = devargs.bus;
251 if (iter->bus->dev_iterate == NULL) {
256 /* Convert bus args to new syntax for use with new API dev_iterate. */
257 if (strcmp(iter->bus->name, "vdev") == 0) {
258 bus_param_key = "name";
259 } else if (strcmp(iter->bus->name, "pci") == 0) {
260 bus_param_key = "addr";
265 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2;
266 bus_str = malloc(str_size);
267 if (bus_str == NULL) {
271 ret = snprintf(bus_str, str_size, "%s=%s",
272 bus_param_key, devargs.name);
273 if (ret != str_size - 1) {
277 iter->bus_str = bus_str;
280 iter->cls = rte_class_find_by_name("eth");
285 RTE_ETHDEV_LOG(ERR, "Bus %s does not support iterating.\n",
294 rte_eth_iterator_next(struct rte_dev_iterator *iter)
296 if (iter->cls == NULL) /* invalid ethdev iterator */
297 return RTE_MAX_ETHPORTS;
299 do { /* loop to try all matching rte_device */
300 /* If not pure ethdev filter and */
301 if (iter->bus != NULL &&
302 /* not in middle of rte_eth_dev iteration, */
303 iter->class_device == NULL) {
304 /* get next rte_device to try. */
305 iter->device = iter->bus->dev_iterate(
306 iter->device, iter->bus_str, iter);
307 if (iter->device == NULL)
308 break; /* no more rte_device candidate */
310 /* A device is matching bus part, need to check ethdev part. */
311 iter->class_device = iter->cls->dev_iterate(
312 iter->class_device, iter->cls_str, iter);
313 if (iter->class_device != NULL)
314 return eth_dev_to_id(iter->class_device); /* match */
315 } while (iter->bus != NULL); /* need to try next rte_device */
317 /* No more ethdev port to iterate. */
318 rte_eth_iterator_cleanup(iter);
319 return RTE_MAX_ETHPORTS;
323 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter)
325 if (iter->bus_str == NULL)
326 return; /* nothing to free in pure class filter */
327 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */
328 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */
329 memset(iter, 0, sizeof(*iter));
333 rte_eth_find_next(uint16_t port_id)
335 while (port_id < RTE_MAX_ETHPORTS &&
336 rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)
339 if (port_id >= RTE_MAX_ETHPORTS)
340 return RTE_MAX_ETHPORTS;
346 * Macro to iterate over all valid ports for internal usage.
347 * Note: RTE_ETH_FOREACH_DEV is different because filtering owned ports.
349 #define RTE_ETH_FOREACH_VALID_DEV(port_id) \
350 for (port_id = rte_eth_find_next(0); \
351 port_id < RTE_MAX_ETHPORTS; \
352 port_id = rte_eth_find_next(port_id + 1))
355 rte_eth_find_next_of(uint16_t port_id, const struct rte_device *parent)
357 port_id = rte_eth_find_next(port_id);
358 while (port_id < RTE_MAX_ETHPORTS &&
359 rte_eth_devices[port_id].device != parent)
360 port_id = rte_eth_find_next(port_id + 1);
366 rte_eth_find_next_sibling(uint16_t port_id, uint16_t ref_port_id)
368 RTE_ETH_VALID_PORTID_OR_ERR_RET(ref_port_id, RTE_MAX_ETHPORTS);
369 return rte_eth_find_next_of(port_id,
370 rte_eth_devices[ref_port_id].device);
374 eth_dev_shared_data_prepare(void)
376 const unsigned flags = 0;
377 const struct rte_memzone *mz;
379 rte_spinlock_lock(ð_dev_shared_data_lock);
381 if (eth_dev_shared_data == NULL) {
382 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
383 /* Allocate port data and ownership shared memory. */
384 mz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA,
385 sizeof(*eth_dev_shared_data),
386 rte_socket_id(), flags);
388 mz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA);
390 rte_panic("Cannot allocate ethdev shared data\n");
392 eth_dev_shared_data = mz->addr;
393 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
394 eth_dev_shared_data->next_owner_id =
395 RTE_ETH_DEV_NO_OWNER + 1;
396 rte_spinlock_init(ð_dev_shared_data->ownership_lock);
397 memset(eth_dev_shared_data->data, 0,
398 sizeof(eth_dev_shared_data->data));
402 rte_spinlock_unlock(ð_dev_shared_data_lock);
406 eth_dev_is_allocated(const struct rte_eth_dev *ethdev)
408 return ethdev->data->name[0] != '\0';
411 static struct rte_eth_dev *
412 eth_dev_allocated(const char *name)
416 RTE_BUILD_BUG_ON(RTE_MAX_ETHPORTS >= UINT16_MAX);
418 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
419 if (rte_eth_devices[i].data != NULL &&
420 strcmp(rte_eth_devices[i].data->name, name) == 0)
421 return &rte_eth_devices[i];
427 rte_eth_dev_allocated(const char *name)
429 struct rte_eth_dev *ethdev;
431 eth_dev_shared_data_prepare();
433 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
435 ethdev = eth_dev_allocated(name);
437 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
443 eth_dev_find_free_port(void)
447 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
448 /* Using shared name field to find a free port. */
449 if (eth_dev_shared_data->data[i].name[0] == '\0') {
450 RTE_ASSERT(rte_eth_devices[i].state ==
455 return RTE_MAX_ETHPORTS;
458 static struct rte_eth_dev *
459 eth_dev_get(uint16_t port_id)
461 struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];
463 eth_dev->data = ð_dev_shared_data->data[port_id];
469 rte_eth_dev_allocate(const char *name)
472 struct rte_eth_dev *eth_dev = NULL;
475 name_len = strnlen(name, RTE_ETH_NAME_MAX_LEN);
477 RTE_ETHDEV_LOG(ERR, "Zero length Ethernet device name\n");
481 if (name_len >= RTE_ETH_NAME_MAX_LEN) {
482 RTE_ETHDEV_LOG(ERR, "Ethernet device name is too long\n");
486 eth_dev_shared_data_prepare();
488 /* Synchronize port creation between primary and secondary threads. */
489 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
491 if (eth_dev_allocated(name) != NULL) {
493 "Ethernet device with name %s already allocated\n",
498 port_id = eth_dev_find_free_port();
499 if (port_id == RTE_MAX_ETHPORTS) {
501 "Reached maximum number of Ethernet ports\n");
505 eth_dev = eth_dev_get(port_id);
506 strlcpy(eth_dev->data->name, name, sizeof(eth_dev->data->name));
507 eth_dev->data->port_id = port_id;
508 eth_dev->data->mtu = RTE_ETHER_MTU;
509 pthread_mutex_init(ð_dev->data->flow_ops_mutex, NULL);
512 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
518 * Attach to a port already registered by the primary process, which
519 * makes sure that the same device would have the same port id both
520 * in the primary and secondary process.
523 rte_eth_dev_attach_secondary(const char *name)
526 struct rte_eth_dev *eth_dev = NULL;
528 eth_dev_shared_data_prepare();
530 /* Synchronize port attachment to primary port creation and release. */
531 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
533 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
534 if (strcmp(eth_dev_shared_data->data[i].name, name) == 0)
537 if (i == RTE_MAX_ETHPORTS) {
539 "Device %s is not driven by the primary process\n",
542 eth_dev = eth_dev_get(i);
543 RTE_ASSERT(eth_dev->data->port_id == i);
546 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
551 rte_eth_dev_release_port(struct rte_eth_dev *eth_dev)
556 eth_dev_shared_data_prepare();
558 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
559 rte_eth_dev_callback_process(eth_dev,
560 RTE_ETH_EVENT_DESTROY, NULL);
562 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
564 eth_dev->state = RTE_ETH_DEV_UNUSED;
565 eth_dev->device = NULL;
566 eth_dev->process_private = NULL;
567 eth_dev->intr_handle = NULL;
568 eth_dev->rx_pkt_burst = NULL;
569 eth_dev->tx_pkt_burst = NULL;
570 eth_dev->tx_pkt_prepare = NULL;
571 eth_dev->rx_queue_count = NULL;
572 eth_dev->rx_descriptor_done = NULL;
573 eth_dev->rx_descriptor_status = NULL;
574 eth_dev->tx_descriptor_status = NULL;
575 eth_dev->dev_ops = NULL;
577 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
578 rte_free(eth_dev->data->rx_queues);
579 rte_free(eth_dev->data->tx_queues);
580 rte_free(eth_dev->data->mac_addrs);
581 rte_free(eth_dev->data->hash_mac_addrs);
582 rte_free(eth_dev->data->dev_private);
583 pthread_mutex_destroy(ð_dev->data->flow_ops_mutex);
584 memset(eth_dev->data, 0, sizeof(struct rte_eth_dev_data));
587 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
593 rte_eth_dev_is_valid_port(uint16_t port_id)
595 if (port_id >= RTE_MAX_ETHPORTS ||
596 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED))
603 eth_is_valid_owner_id(uint64_t owner_id)
605 if (owner_id == RTE_ETH_DEV_NO_OWNER ||
606 eth_dev_shared_data->next_owner_id <= owner_id)
612 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id)
614 port_id = rte_eth_find_next(port_id);
615 while (port_id < RTE_MAX_ETHPORTS &&
616 rte_eth_devices[port_id].data->owner.id != owner_id)
617 port_id = rte_eth_find_next(port_id + 1);
623 rte_eth_dev_owner_new(uint64_t *owner_id)
625 eth_dev_shared_data_prepare();
627 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
629 *owner_id = eth_dev_shared_data->next_owner_id++;
631 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
636 eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id,
637 const struct rte_eth_dev_owner *new_owner)
639 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
640 struct rte_eth_dev_owner *port_owner;
642 if (port_id >= RTE_MAX_ETHPORTS || !eth_dev_is_allocated(ethdev)) {
643 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
648 if (!eth_is_valid_owner_id(new_owner->id) &&
649 !eth_is_valid_owner_id(old_owner_id)) {
651 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64"\n",
652 old_owner_id, new_owner->id);
656 port_owner = &rte_eth_devices[port_id].data->owner;
657 if (port_owner->id != old_owner_id) {
659 "Cannot set owner to port %u already owned by %s_%016"PRIX64"\n",
660 port_id, port_owner->name, port_owner->id);
664 /* can not truncate (same structure) */
665 strlcpy(port_owner->name, new_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN);
667 port_owner->id = new_owner->id;
669 RTE_ETHDEV_LOG(DEBUG, "Port %u owner is %s_%016"PRIx64"\n",
670 port_id, new_owner->name, new_owner->id);
676 rte_eth_dev_owner_set(const uint16_t port_id,
677 const struct rte_eth_dev_owner *owner)
681 eth_dev_shared_data_prepare();
683 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
685 ret = eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner);
687 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
692 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id)
694 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner)
695 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""};
698 eth_dev_shared_data_prepare();
700 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
702 ret = eth_dev_owner_set(port_id, owner_id, &new_owner);
704 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
709 rte_eth_dev_owner_delete(const uint64_t owner_id)
714 eth_dev_shared_data_prepare();
716 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
718 if (eth_is_valid_owner_id(owner_id)) {
719 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)
720 if (rte_eth_devices[port_id].data->owner.id == owner_id)
721 memset(&rte_eth_devices[port_id].data->owner, 0,
722 sizeof(struct rte_eth_dev_owner));
723 RTE_ETHDEV_LOG(NOTICE,
724 "All port owners owned by %016"PRIx64" identifier have removed\n",
728 "Invalid owner id=%016"PRIx64"\n",
733 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
739 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner)
742 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
744 eth_dev_shared_data_prepare();
746 rte_spinlock_lock(ð_dev_shared_data->ownership_lock);
748 if (port_id >= RTE_MAX_ETHPORTS || !eth_dev_is_allocated(ethdev)) {
749 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
753 rte_memcpy(owner, ðdev->data->owner, sizeof(*owner));
756 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock);
761 rte_eth_dev_socket_id(uint16_t port_id)
763 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
764 return rte_eth_devices[port_id].data->numa_node;
768 rte_eth_dev_get_sec_ctx(uint16_t port_id)
770 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
771 return rte_eth_devices[port_id].security_ctx;
775 rte_eth_dev_count_avail(void)
782 RTE_ETH_FOREACH_DEV(p)
789 rte_eth_dev_count_total(void)
791 uint16_t port, count = 0;
793 RTE_ETH_FOREACH_VALID_DEV(port)
800 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name)
804 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
807 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
811 /* shouldn't check 'rte_eth_devices[i].data',
812 * because it might be overwritten by VDEV PMD */
813 tmp = eth_dev_shared_data->data[port_id].name;
819 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id)
824 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
828 RTE_ETH_FOREACH_VALID_DEV(pid)
829 if (!strcmp(name, eth_dev_shared_data->data[pid].name)) {
838 eth_err(uint16_t port_id, int ret)
842 if (rte_eth_dev_is_removed(port_id))
848 eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
850 uint16_t old_nb_queues = dev->data->nb_rx_queues;
854 if (dev->data->rx_queues == NULL && nb_queues != 0) { /* first time configuration */
855 dev->data->rx_queues = rte_zmalloc("ethdev->rx_queues",
856 sizeof(dev->data->rx_queues[0]) * nb_queues,
857 RTE_CACHE_LINE_SIZE);
858 if (dev->data->rx_queues == NULL) {
859 dev->data->nb_rx_queues = 0;
862 } else if (dev->data->rx_queues != NULL && nb_queues != 0) { /* re-configure */
863 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
865 rxq = dev->data->rx_queues;
867 for (i = nb_queues; i < old_nb_queues; i++)
868 (*dev->dev_ops->rx_queue_release)(rxq[i]);
869 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
870 RTE_CACHE_LINE_SIZE);
873 if (nb_queues > old_nb_queues) {
874 uint16_t new_qs = nb_queues - old_nb_queues;
876 memset(rxq + old_nb_queues, 0,
877 sizeof(rxq[0]) * new_qs);
880 dev->data->rx_queues = rxq;
882 } else if (dev->data->rx_queues != NULL && nb_queues == 0) {
883 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
885 rxq = dev->data->rx_queues;
887 for (i = nb_queues; i < old_nb_queues; i++)
888 (*dev->dev_ops->rx_queue_release)(rxq[i]);
890 rte_free(dev->data->rx_queues);
891 dev->data->rx_queues = NULL;
893 dev->data->nb_rx_queues = nb_queues;
898 eth_dev_validate_rx_queue(const struct rte_eth_dev *dev, uint16_t rx_queue_id)
902 if (rx_queue_id >= dev->data->nb_rx_queues) {
903 port_id = dev->data->port_id;
905 "Invalid Rx queue_id=%u of device with port_id=%u\n",
906 rx_queue_id, port_id);
910 if (dev->data->rx_queues[rx_queue_id] == NULL) {
911 port_id = dev->data->port_id;
913 "Queue %u of device with port_id=%u has not been setup\n",
914 rx_queue_id, port_id);
922 eth_dev_validate_tx_queue(const struct rte_eth_dev *dev, uint16_t tx_queue_id)
926 if (tx_queue_id >= dev->data->nb_tx_queues) {
927 port_id = dev->data->port_id;
929 "Invalid Tx queue_id=%u of device with port_id=%u\n",
930 tx_queue_id, port_id);
934 if (dev->data->tx_queues[tx_queue_id] == NULL) {
935 port_id = dev->data->port_id;
937 "Queue %u of device with port_id=%u has not been setup\n",
938 tx_queue_id, port_id);
946 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id)
948 struct rte_eth_dev *dev;
951 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
953 dev = &rte_eth_devices[port_id];
954 if (!dev->data->dev_started) {
956 "Port %u must be started before start any queue\n",
961 ret = eth_dev_validate_rx_queue(dev, rx_queue_id);
965 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP);
967 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
969 "Can't start Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
970 rx_queue_id, port_id);
974 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
976 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
977 rx_queue_id, port_id);
981 return eth_err(port_id, dev->dev_ops->rx_queue_start(dev,
987 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id)
989 struct rte_eth_dev *dev;
992 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
994 dev = &rte_eth_devices[port_id];
996 ret = eth_dev_validate_rx_queue(dev, rx_queue_id);
1000 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP);
1002 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
1003 RTE_ETHDEV_LOG(INFO,
1004 "Can't stop Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1005 rx_queue_id, port_id);
1009 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
1010 RTE_ETHDEV_LOG(INFO,
1011 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
1012 rx_queue_id, port_id);
1016 return eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id));
1021 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id)
1023 struct rte_eth_dev *dev;
1026 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1028 dev = &rte_eth_devices[port_id];
1029 if (!dev->data->dev_started) {
1031 "Port %u must be started before start any queue\n",
1036 ret = eth_dev_validate_tx_queue(dev, tx_queue_id);
1040 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP);
1042 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
1043 RTE_ETHDEV_LOG(INFO,
1044 "Can't start Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1045 tx_queue_id, port_id);
1049 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
1050 RTE_ETHDEV_LOG(INFO,
1051 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
1052 tx_queue_id, port_id);
1056 return eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id));
1060 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id)
1062 struct rte_eth_dev *dev;
1065 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1067 dev = &rte_eth_devices[port_id];
1069 ret = eth_dev_validate_tx_queue(dev, tx_queue_id);
1073 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP);
1075 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
1076 RTE_ETHDEV_LOG(INFO,
1077 "Can't stop Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
1078 tx_queue_id, port_id);
1082 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
1083 RTE_ETHDEV_LOG(INFO,
1084 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
1085 tx_queue_id, port_id);
1089 return eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id));
1094 eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
1096 uint16_t old_nb_queues = dev->data->nb_tx_queues;
1100 if (dev->data->tx_queues == NULL && nb_queues != 0) { /* first time configuration */
1101 dev->data->tx_queues = rte_zmalloc("ethdev->tx_queues",
1102 sizeof(dev->data->tx_queues[0]) * nb_queues,
1103 RTE_CACHE_LINE_SIZE);
1104 if (dev->data->tx_queues == NULL) {
1105 dev->data->nb_tx_queues = 0;
1108 } else if (dev->data->tx_queues != NULL && nb_queues != 0) { /* re-configure */
1109 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1111 txq = dev->data->tx_queues;
1113 for (i = nb_queues; i < old_nb_queues; i++)
1114 (*dev->dev_ops->tx_queue_release)(txq[i]);
1115 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1116 RTE_CACHE_LINE_SIZE);
1119 if (nb_queues > old_nb_queues) {
1120 uint16_t new_qs = nb_queues - old_nb_queues;
1122 memset(txq + old_nb_queues, 0,
1123 sizeof(txq[0]) * new_qs);
1126 dev->data->tx_queues = txq;
1128 } else if (dev->data->tx_queues != NULL && nb_queues == 0) {
1129 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1131 txq = dev->data->tx_queues;
1133 for (i = nb_queues; i < old_nb_queues; i++)
1134 (*dev->dev_ops->tx_queue_release)(txq[i]);
1136 rte_free(dev->data->tx_queues);
1137 dev->data->tx_queues = NULL;
1139 dev->data->nb_tx_queues = nb_queues;
1144 rte_eth_speed_bitflag(uint32_t speed, int duplex)
1147 case ETH_SPEED_NUM_10M:
1148 return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD;
1149 case ETH_SPEED_NUM_100M:
1150 return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD;
1151 case ETH_SPEED_NUM_1G:
1152 return ETH_LINK_SPEED_1G;
1153 case ETH_SPEED_NUM_2_5G:
1154 return ETH_LINK_SPEED_2_5G;
1155 case ETH_SPEED_NUM_5G:
1156 return ETH_LINK_SPEED_5G;
1157 case ETH_SPEED_NUM_10G:
1158 return ETH_LINK_SPEED_10G;
1159 case ETH_SPEED_NUM_20G:
1160 return ETH_LINK_SPEED_20G;
1161 case ETH_SPEED_NUM_25G:
1162 return ETH_LINK_SPEED_25G;
1163 case ETH_SPEED_NUM_40G:
1164 return ETH_LINK_SPEED_40G;
1165 case ETH_SPEED_NUM_50G:
1166 return ETH_LINK_SPEED_50G;
1167 case ETH_SPEED_NUM_56G:
1168 return ETH_LINK_SPEED_56G;
1169 case ETH_SPEED_NUM_100G:
1170 return ETH_LINK_SPEED_100G;
1171 case ETH_SPEED_NUM_200G:
1172 return ETH_LINK_SPEED_200G;
1179 rte_eth_dev_rx_offload_name(uint64_t offload)
1181 const char *name = "UNKNOWN";
1184 for (i = 0; i < RTE_DIM(eth_dev_rx_offload_names); ++i) {
1185 if (offload == eth_dev_rx_offload_names[i].offload) {
1186 name = eth_dev_rx_offload_names[i].name;
1195 rte_eth_dev_tx_offload_name(uint64_t offload)
1197 const char *name = "UNKNOWN";
1200 for (i = 0; i < RTE_DIM(eth_dev_tx_offload_names); ++i) {
1201 if (offload == eth_dev_tx_offload_names[i].offload) {
1202 name = eth_dev_tx_offload_names[i].name;
1211 eth_dev_check_lro_pkt_size(uint16_t port_id, uint32_t config_size,
1212 uint32_t max_rx_pkt_len, uint32_t dev_info_size)
1216 if (dev_info_size == 0) {
1217 if (config_size != max_rx_pkt_len) {
1218 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size"
1219 " %u != %u is not allowed\n",
1220 port_id, config_size, max_rx_pkt_len);
1223 } else if (config_size > dev_info_size) {
1224 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u "
1225 "> max allowed value %u\n", port_id, config_size,
1228 } else if (config_size < RTE_ETHER_MIN_LEN) {
1229 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u "
1230 "< min allowed value %u\n", port_id, config_size,
1231 (unsigned int)RTE_ETHER_MIN_LEN);
1238 * Validate offloads that are requested through rte_eth_dev_configure against
1239 * the offloads successfully set by the ethernet device.
1242 * The port identifier of the Ethernet device.
1243 * @param req_offloads
1244 * The offloads that have been requested through `rte_eth_dev_configure`.
1245 * @param set_offloads
1246 * The offloads successfully set by the ethernet device.
1247 * @param offload_type
1248 * The offload type i.e. Rx/Tx string.
1249 * @param offload_name
1250 * The function that prints the offload name.
1252 * - (0) if validation successful.
1253 * - (-EINVAL) if requested offload has been silently disabled.
1257 eth_dev_validate_offloads(uint16_t port_id, uint64_t req_offloads,
1258 uint64_t set_offloads, const char *offload_type,
1259 const char *(*offload_name)(uint64_t))
1261 uint64_t offloads_diff = req_offloads ^ set_offloads;
1265 while (offloads_diff != 0) {
1266 /* Check if any offload is requested but not enabled. */
1267 offload = 1ULL << __builtin_ctzll(offloads_diff);
1268 if (offload & req_offloads) {
1270 "Port %u failed to enable %s offload %s\n",
1271 port_id, offload_type, offload_name(offload));
1275 /* Check if offload couldn't be disabled. */
1276 if (offload & set_offloads) {
1277 RTE_ETHDEV_LOG(DEBUG,
1278 "Port %u %s offload %s is not requested but enabled\n",
1279 port_id, offload_type, offload_name(offload));
1282 offloads_diff &= ~offload;
1289 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,
1290 const struct rte_eth_conf *dev_conf)
1292 struct rte_eth_dev *dev;
1293 struct rte_eth_dev_info dev_info;
1294 struct rte_eth_conf orig_conf;
1298 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1300 dev = &rte_eth_devices[port_id];
1302 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP);
1304 if (dev->data->dev_started) {
1306 "Port %u must be stopped to allow configuration\n",
1311 /* Store original config, as rollback required on failure */
1312 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf));
1315 * Copy the dev_conf parameter into the dev structure.
1316 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get
1318 if (dev_conf != &dev->data->dev_conf)
1319 memcpy(&dev->data->dev_conf, dev_conf,
1320 sizeof(dev->data->dev_conf));
1322 ret = rte_eth_dev_info_get(port_id, &dev_info);
1326 /* If number of queues specified by application for both Rx and Tx is
1327 * zero, use driver preferred values. This cannot be done individually
1328 * as it is valid for either Tx or Rx (but not both) to be zero.
1329 * If driver does not provide any preferred valued, fall back on
1332 if (nb_rx_q == 0 && nb_tx_q == 0) {
1333 nb_rx_q = dev_info.default_rxportconf.nb_queues;
1335 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES;
1336 nb_tx_q = dev_info.default_txportconf.nb_queues;
1338 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES;
1341 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) {
1343 "Number of RX queues requested (%u) is greater than max supported(%d)\n",
1344 nb_rx_q, RTE_MAX_QUEUES_PER_PORT);
1349 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) {
1351 "Number of TX queues requested (%u) is greater than max supported(%d)\n",
1352 nb_tx_q, RTE_MAX_QUEUES_PER_PORT);
1358 * Check that the numbers of RX and TX queues are not greater
1359 * than the maximum number of RX and TX queues supported by the
1360 * configured device.
1362 if (nb_rx_q > dev_info.max_rx_queues) {
1363 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u\n",
1364 port_id, nb_rx_q, dev_info.max_rx_queues);
1369 if (nb_tx_q > dev_info.max_tx_queues) {
1370 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u\n",
1371 port_id, nb_tx_q, dev_info.max_tx_queues);
1376 /* Check that the device supports requested interrupts */
1377 if ((dev_conf->intr_conf.lsc == 1) &&
1378 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) {
1379 RTE_ETHDEV_LOG(ERR, "Driver %s does not support lsc\n",
1380 dev->device->driver->name);
1384 if ((dev_conf->intr_conf.rmv == 1) &&
1385 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) {
1386 RTE_ETHDEV_LOG(ERR, "Driver %s does not support rmv\n",
1387 dev->device->driver->name);
1393 * If jumbo frames are enabled, check that the maximum RX packet
1394 * length is supported by the configured device.
1396 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1397 if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen) {
1399 "Ethdev port_id=%u max_rx_pkt_len %u > max valid value %u\n",
1400 port_id, dev_conf->rxmode.max_rx_pkt_len,
1401 dev_info.max_rx_pktlen);
1404 } else if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN) {
1406 "Ethdev port_id=%u max_rx_pkt_len %u < min valid value %u\n",
1407 port_id, dev_conf->rxmode.max_rx_pkt_len,
1408 (unsigned int)RTE_ETHER_MIN_LEN);
1413 if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN ||
1414 dev_conf->rxmode.max_rx_pkt_len > RTE_ETHER_MAX_LEN)
1415 /* Use default value */
1416 dev->data->dev_conf.rxmode.max_rx_pkt_len =
1421 * If LRO is enabled, check that the maximum aggregated packet
1422 * size is supported by the configured device.
1424 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1425 if (dev_conf->rxmode.max_lro_pkt_size == 0)
1426 dev->data->dev_conf.rxmode.max_lro_pkt_size =
1427 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1428 ret = eth_dev_check_lro_pkt_size(port_id,
1429 dev->data->dev_conf.rxmode.max_lro_pkt_size,
1430 dev->data->dev_conf.rxmode.max_rx_pkt_len,
1431 dev_info.max_lro_pkt_size);
1436 /* Any requested offloading must be within its device capabilities */
1437 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) !=
1438 dev_conf->rxmode.offloads) {
1440 "Ethdev port_id=%u requested Rx offloads 0x%"PRIx64" doesn't match Rx offloads "
1441 "capabilities 0x%"PRIx64" in %s()\n",
1442 port_id, dev_conf->rxmode.offloads,
1443 dev_info.rx_offload_capa,
1448 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) !=
1449 dev_conf->txmode.offloads) {
1451 "Ethdev port_id=%u requested Tx offloads 0x%"PRIx64" doesn't match Tx offloads "
1452 "capabilities 0x%"PRIx64" in %s()\n",
1453 port_id, dev_conf->txmode.offloads,
1454 dev_info.tx_offload_capa,
1460 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf =
1461 rte_eth_rss_hf_refine(dev_conf->rx_adv_conf.rss_conf.rss_hf);
1463 /* Check that device supports requested rss hash functions. */
1464 if ((dev_info.flow_type_rss_offloads |
1465 dev_conf->rx_adv_conf.rss_conf.rss_hf) !=
1466 dev_info.flow_type_rss_offloads) {
1468 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
1469 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf,
1470 dev_info.flow_type_rss_offloads);
1475 /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */
1476 if (((dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) &&
1477 (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_RSS_HASH)) {
1479 "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested\n",
1481 rte_eth_dev_rx_offload_name(DEV_RX_OFFLOAD_RSS_HASH));
1487 * Setup new number of RX/TX queues and reconfigure device.
1489 diag = eth_dev_rx_queue_config(dev, nb_rx_q);
1492 "Port%u eth_dev_rx_queue_config = %d\n",
1498 diag = eth_dev_tx_queue_config(dev, nb_tx_q);
1501 "Port%u eth_dev_tx_queue_config = %d\n",
1503 eth_dev_rx_queue_config(dev, 0);
1508 diag = (*dev->dev_ops->dev_configure)(dev);
1510 RTE_ETHDEV_LOG(ERR, "Port%u dev_configure = %d\n",
1512 ret = eth_err(port_id, diag);
1516 /* Initialize Rx profiling if enabled at compilation time. */
1517 diag = __rte_eth_dev_profile_init(port_id, dev);
1519 RTE_ETHDEV_LOG(ERR, "Port%u __rte_eth_dev_profile_init = %d\n",
1521 ret = eth_err(port_id, diag);
1525 /* Validate Rx offloads. */
1526 diag = eth_dev_validate_offloads(port_id,
1527 dev_conf->rxmode.offloads,
1528 dev->data->dev_conf.rxmode.offloads, "Rx",
1529 rte_eth_dev_rx_offload_name);
1535 /* Validate Tx offloads. */
1536 diag = eth_dev_validate_offloads(port_id,
1537 dev_conf->txmode.offloads,
1538 dev->data->dev_conf.txmode.offloads, "Tx",
1539 rte_eth_dev_tx_offload_name);
1545 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, 0);
1548 eth_dev_rx_queue_config(dev, 0);
1549 eth_dev_tx_queue_config(dev, 0);
1551 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf));
1553 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, ret);
1558 rte_eth_dev_internal_reset(struct rte_eth_dev *dev)
1560 if (dev->data->dev_started) {
1561 RTE_ETHDEV_LOG(ERR, "Port %u must be stopped to allow reset\n",
1562 dev->data->port_id);
1566 eth_dev_rx_queue_config(dev, 0);
1567 eth_dev_tx_queue_config(dev, 0);
1569 memset(&dev->data->dev_conf, 0, sizeof(dev->data->dev_conf));
1573 eth_dev_mac_restore(struct rte_eth_dev *dev,
1574 struct rte_eth_dev_info *dev_info)
1576 struct rte_ether_addr *addr;
1581 /* replay MAC address configuration including default MAC */
1582 addr = &dev->data->mac_addrs[0];
1583 if (*dev->dev_ops->mac_addr_set != NULL)
1584 (*dev->dev_ops->mac_addr_set)(dev, addr);
1585 else if (*dev->dev_ops->mac_addr_add != NULL)
1586 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool);
1588 if (*dev->dev_ops->mac_addr_add != NULL) {
1589 for (i = 1; i < dev_info->max_mac_addrs; i++) {
1590 addr = &dev->data->mac_addrs[i];
1592 /* skip zero address */
1593 if (rte_is_zero_ether_addr(addr))
1597 pool_mask = dev->data->mac_pool_sel[i];
1600 if (pool_mask & 1ULL)
1601 (*dev->dev_ops->mac_addr_add)(dev,
1605 } while (pool_mask);
1611 eth_dev_config_restore(struct rte_eth_dev *dev,
1612 struct rte_eth_dev_info *dev_info, uint16_t port_id)
1616 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR))
1617 eth_dev_mac_restore(dev, dev_info);
1619 /* replay promiscuous configuration */
1621 * use callbacks directly since we don't need port_id check and
1622 * would like to bypass the same value set
1624 if (rte_eth_promiscuous_get(port_id) == 1 &&
1625 *dev->dev_ops->promiscuous_enable != NULL) {
1626 ret = eth_err(port_id,
1627 (*dev->dev_ops->promiscuous_enable)(dev));
1628 if (ret != 0 && ret != -ENOTSUP) {
1630 "Failed to enable promiscuous mode for device (port %u): %s\n",
1631 port_id, rte_strerror(-ret));
1634 } else if (rte_eth_promiscuous_get(port_id) == 0 &&
1635 *dev->dev_ops->promiscuous_disable != NULL) {
1636 ret = eth_err(port_id,
1637 (*dev->dev_ops->promiscuous_disable)(dev));
1638 if (ret != 0 && ret != -ENOTSUP) {
1640 "Failed to disable promiscuous mode for device (port %u): %s\n",
1641 port_id, rte_strerror(-ret));
1646 /* replay all multicast configuration */
1648 * use callbacks directly since we don't need port_id check and
1649 * would like to bypass the same value set
1651 if (rte_eth_allmulticast_get(port_id) == 1 &&
1652 *dev->dev_ops->allmulticast_enable != NULL) {
1653 ret = eth_err(port_id,
1654 (*dev->dev_ops->allmulticast_enable)(dev));
1655 if (ret != 0 && ret != -ENOTSUP) {
1657 "Failed to enable allmulticast mode for device (port %u): %s\n",
1658 port_id, rte_strerror(-ret));
1661 } else if (rte_eth_allmulticast_get(port_id) == 0 &&
1662 *dev->dev_ops->allmulticast_disable != NULL) {
1663 ret = eth_err(port_id,
1664 (*dev->dev_ops->allmulticast_disable)(dev));
1665 if (ret != 0 && ret != -ENOTSUP) {
1667 "Failed to disable allmulticast mode for device (port %u): %s\n",
1668 port_id, rte_strerror(-ret));
1677 rte_eth_dev_start(uint16_t port_id)
1679 struct rte_eth_dev *dev;
1680 struct rte_eth_dev_info dev_info;
1684 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1686 dev = &rte_eth_devices[port_id];
1688 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP);
1690 if (dev->data->dev_started != 0) {
1691 RTE_ETHDEV_LOG(INFO,
1692 "Device with port_id=%"PRIu16" already started\n",
1697 ret = rte_eth_dev_info_get(port_id, &dev_info);
1701 /* Lets restore MAC now if device does not support live change */
1702 if (*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR)
1703 eth_dev_mac_restore(dev, &dev_info);
1705 diag = (*dev->dev_ops->dev_start)(dev);
1707 dev->data->dev_started = 1;
1709 return eth_err(port_id, diag);
1711 ret = eth_dev_config_restore(dev, &dev_info, port_id);
1714 "Error during restoring configuration for device (port %u): %s\n",
1715 port_id, rte_strerror(-ret));
1716 ret_stop = rte_eth_dev_stop(port_id);
1717 if (ret_stop != 0) {
1719 "Failed to stop device (port %u): %s\n",
1720 port_id, rte_strerror(-ret_stop));
1726 if (dev->data->dev_conf.intr_conf.lsc == 0) {
1727 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
1728 (*dev->dev_ops->link_update)(dev, 0);
1731 rte_ethdev_trace_start(port_id);
1736 rte_eth_dev_stop(uint16_t port_id)
1738 struct rte_eth_dev *dev;
1741 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1742 dev = &rte_eth_devices[port_id];
1744 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_stop, -ENOTSUP);
1746 if (dev->data->dev_started == 0) {
1747 RTE_ETHDEV_LOG(INFO,
1748 "Device with port_id=%"PRIu16" already stopped\n",
1753 dev->data->dev_started = 0;
1754 ret = (*dev->dev_ops->dev_stop)(dev);
1755 rte_ethdev_trace_stop(port_id, ret);
1761 rte_eth_dev_set_link_up(uint16_t port_id)
1763 struct rte_eth_dev *dev;
1765 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1767 dev = &rte_eth_devices[port_id];
1769 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP);
1770 return eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev));
1774 rte_eth_dev_set_link_down(uint16_t port_id)
1776 struct rte_eth_dev *dev;
1778 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1780 dev = &rte_eth_devices[port_id];
1782 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP);
1783 return eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev));
1787 rte_eth_dev_close(uint16_t port_id)
1789 struct rte_eth_dev *dev;
1790 int firsterr, binerr;
1791 int *lasterr = &firsterr;
1793 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1794 dev = &rte_eth_devices[port_id];
1796 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_close, -ENOTSUP);
1797 *lasterr = (*dev->dev_ops->dev_close)(dev);
1801 rte_ethdev_trace_close(port_id);
1802 *lasterr = rte_eth_dev_release_port(dev);
1804 return eth_err(port_id, firsterr);
1808 rte_eth_dev_reset(uint16_t port_id)
1810 struct rte_eth_dev *dev;
1813 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1814 dev = &rte_eth_devices[port_id];
1816 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_reset, -ENOTSUP);
1818 ret = rte_eth_dev_stop(port_id);
1821 "Failed to stop device (port %u) before reset: %s - ignore\n",
1822 port_id, rte_strerror(-ret));
1824 ret = dev->dev_ops->dev_reset(dev);
1826 return eth_err(port_id, ret);
1830 rte_eth_dev_is_removed(uint16_t port_id)
1832 struct rte_eth_dev *dev;
1835 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
1837 dev = &rte_eth_devices[port_id];
1839 if (dev->state == RTE_ETH_DEV_REMOVED)
1842 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->is_removed, 0);
1844 ret = dev->dev_ops->is_removed(dev);
1846 /* Device is physically removed. */
1847 dev->state = RTE_ETH_DEV_REMOVED;
1853 rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg,
1854 uint16_t n_seg, uint32_t *mbp_buf_size,
1855 const struct rte_eth_dev_info *dev_info)
1857 const struct rte_eth_rxseg_capa *seg_capa = &dev_info->rx_seg_capa;
1858 struct rte_mempool *mp_first;
1859 uint32_t offset_mask;
1862 if (n_seg > seg_capa->max_nseg) {
1864 "Requested Rx segments %u exceed supported %u\n",
1865 n_seg, seg_capa->max_nseg);
1869 * Check the sizes and offsets against buffer sizes
1870 * for each segment specified in extended configuration.
1872 mp_first = rx_seg[0].mp;
1873 offset_mask = (1u << seg_capa->offset_align_log2) - 1;
1874 for (seg_idx = 0; seg_idx < n_seg; seg_idx++) {
1875 struct rte_mempool *mpl = rx_seg[seg_idx].mp;
1876 uint32_t length = rx_seg[seg_idx].length;
1877 uint32_t offset = rx_seg[seg_idx].offset;
1880 RTE_ETHDEV_LOG(ERR, "null mempool pointer\n");
1883 if (seg_idx != 0 && mp_first != mpl &&
1884 seg_capa->multi_pools == 0) {
1885 RTE_ETHDEV_LOG(ERR, "Receiving to multiple pools is not supported\n");
1889 if (seg_capa->offset_allowed == 0) {
1890 RTE_ETHDEV_LOG(ERR, "Rx segmentation with offset is not supported\n");
1893 if (offset & offset_mask) {
1894 RTE_ETHDEV_LOG(ERR, "Rx segmentation invalid offset alignment %u, %u\n",
1896 seg_capa->offset_align_log2);
1900 if (mpl->private_data_size <
1901 sizeof(struct rte_pktmbuf_pool_private)) {
1903 "%s private_data_size %u < %u\n",
1904 mpl->name, mpl->private_data_size,
1905 (unsigned int)sizeof
1906 (struct rte_pktmbuf_pool_private));
1909 offset += seg_idx != 0 ? 0 : RTE_PKTMBUF_HEADROOM;
1910 *mbp_buf_size = rte_pktmbuf_data_room_size(mpl);
1911 length = length != 0 ? length : *mbp_buf_size;
1912 if (*mbp_buf_size < length + offset) {
1914 "%s mbuf_data_room_size %u < %u (segment length=%u + segment offset=%u)\n",
1915 mpl->name, *mbp_buf_size,
1916 length + offset, length, offset);
1924 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
1925 uint16_t nb_rx_desc, unsigned int socket_id,
1926 const struct rte_eth_rxconf *rx_conf,
1927 struct rte_mempool *mp)
1930 uint32_t mbp_buf_size;
1931 struct rte_eth_dev *dev;
1932 struct rte_eth_dev_info dev_info;
1933 struct rte_eth_rxconf local_conf;
1936 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1938 dev = &rte_eth_devices[port_id];
1939 if (rx_queue_id >= dev->data->nb_rx_queues) {
1940 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
1944 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP);
1946 ret = rte_eth_dev_info_get(port_id, &dev_info);
1951 /* Single pool configuration check. */
1952 if (rx_conf != NULL && rx_conf->rx_nseg != 0) {
1954 "Ambiguous segment configuration\n");
1958 * Check the size of the mbuf data buffer, this value
1959 * must be provided in the private data of the memory pool.
1960 * First check that the memory pool(s) has a valid private data.
1962 if (mp->private_data_size <
1963 sizeof(struct rte_pktmbuf_pool_private)) {
1964 RTE_ETHDEV_LOG(ERR, "%s private_data_size %u < %u\n",
1965 mp->name, mp->private_data_size,
1967 sizeof(struct rte_pktmbuf_pool_private));
1970 mbp_buf_size = rte_pktmbuf_data_room_size(mp);
1971 if (mbp_buf_size < dev_info.min_rx_bufsize +
1972 RTE_PKTMBUF_HEADROOM) {
1974 "%s mbuf_data_room_size %u < %u (RTE_PKTMBUF_HEADROOM=%u + min_rx_bufsize(dev)=%u)\n",
1975 mp->name, mbp_buf_size,
1976 RTE_PKTMBUF_HEADROOM +
1977 dev_info.min_rx_bufsize,
1978 RTE_PKTMBUF_HEADROOM,
1979 dev_info.min_rx_bufsize);
1983 const struct rte_eth_rxseg_split *rx_seg;
1986 /* Extended multi-segment configuration check. */
1987 if (rx_conf == NULL || rx_conf->rx_seg == NULL || rx_conf->rx_nseg == 0) {
1989 "Memory pool is null and no extended configuration provided\n");
1993 rx_seg = (const struct rte_eth_rxseg_split *)rx_conf->rx_seg;
1994 n_seg = rx_conf->rx_nseg;
1996 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) {
1997 ret = rte_eth_rx_queue_check_split(rx_seg, n_seg,
2003 RTE_ETHDEV_LOG(ERR, "No Rx segmentation offload configured\n");
2008 /* Use default specified by driver, if nb_rx_desc is zero */
2009 if (nb_rx_desc == 0) {
2010 nb_rx_desc = dev_info.default_rxportconf.ring_size;
2011 /* If driver default is also zero, fall back on EAL default */
2012 if (nb_rx_desc == 0)
2013 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE;
2016 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max ||
2017 nb_rx_desc < dev_info.rx_desc_lim.nb_min ||
2018 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) {
2021 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
2022 nb_rx_desc, dev_info.rx_desc_lim.nb_max,
2023 dev_info.rx_desc_lim.nb_min,
2024 dev_info.rx_desc_lim.nb_align);
2028 if (dev->data->dev_started &&
2029 !(dev_info.dev_capa &
2030 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP))
2033 if (dev->data->dev_started &&
2034 (dev->data->rx_queue_state[rx_queue_id] !=
2035 RTE_ETH_QUEUE_STATE_STOPPED))
2038 rxq = dev->data->rx_queues;
2039 if (rxq[rx_queue_id]) {
2040 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
2042 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
2043 rxq[rx_queue_id] = NULL;
2046 if (rx_conf == NULL)
2047 rx_conf = &dev_info.default_rxconf;
2049 local_conf = *rx_conf;
2052 * If an offloading has already been enabled in
2053 * rte_eth_dev_configure(), it has been enabled on all queues,
2054 * so there is no need to enable it in this queue again.
2055 * The local_conf.offloads input to underlying PMD only carries
2056 * those offloadings which are only enabled on this queue and
2057 * not enabled on all queues.
2059 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads;
2062 * New added offloadings for this queue are those not enabled in
2063 * rte_eth_dev_configure() and they must be per-queue type.
2064 * A pure per-port offloading can't be enabled on a queue while
2065 * disabled on another queue. A pure per-port offloading can't
2066 * be enabled for any queue as new added one if it hasn't been
2067 * enabled in rte_eth_dev_configure().
2069 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) !=
2070 local_conf.offloads) {
2072 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
2073 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
2074 port_id, rx_queue_id, local_conf.offloads,
2075 dev_info.rx_queue_offload_capa,
2081 * If LRO is enabled, check that the maximum aggregated packet
2082 * size is supported by the configured device.
2084 if (local_conf.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
2085 if (dev->data->dev_conf.rxmode.max_lro_pkt_size == 0)
2086 dev->data->dev_conf.rxmode.max_lro_pkt_size =
2087 dev->data->dev_conf.rxmode.max_rx_pkt_len;
2088 int ret = eth_dev_check_lro_pkt_size(port_id,
2089 dev->data->dev_conf.rxmode.max_lro_pkt_size,
2090 dev->data->dev_conf.rxmode.max_rx_pkt_len,
2091 dev_info.max_lro_pkt_size);
2096 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc,
2097 socket_id, &local_conf, mp);
2099 if (!dev->data->min_rx_buf_size ||
2100 dev->data->min_rx_buf_size > mbp_buf_size)
2101 dev->data->min_rx_buf_size = mbp_buf_size;
2104 rte_ethdev_trace_rxq_setup(port_id, rx_queue_id, nb_rx_desc, mp,
2106 return eth_err(port_id, ret);
2110 rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
2111 uint16_t nb_rx_desc,
2112 const struct rte_eth_hairpin_conf *conf)
2115 struct rte_eth_dev *dev;
2116 struct rte_eth_hairpin_cap cap;
2121 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2123 dev = &rte_eth_devices[port_id];
2124 if (rx_queue_id >= dev->data->nb_rx_queues) {
2125 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
2128 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
2131 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_hairpin_queue_setup,
2133 /* if nb_rx_desc is zero use max number of desc from the driver. */
2134 if (nb_rx_desc == 0)
2135 nb_rx_desc = cap.max_nb_desc;
2136 if (nb_rx_desc > cap.max_nb_desc) {
2138 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu",
2139 nb_rx_desc, cap.max_nb_desc);
2142 if (conf->peer_count > cap.max_rx_2_tx) {
2144 "Invalid value for number of peers for Rx queue(=%u), should be: <= %hu",
2145 conf->peer_count, cap.max_rx_2_tx);
2148 if (conf->peer_count == 0) {
2150 "Invalid value for number of peers for Rx queue(=%u), should be: > 0",
2154 for (i = 0, count = 0; i < dev->data->nb_rx_queues &&
2155 cap.max_nb_queues != UINT16_MAX; i++) {
2156 if (i == rx_queue_id || rte_eth_dev_is_rx_hairpin_queue(dev, i))
2159 if (count > cap.max_nb_queues) {
2160 RTE_ETHDEV_LOG(ERR, "To many Rx hairpin queues max is %d",
2164 if (dev->data->dev_started)
2166 rxq = dev->data->rx_queues;
2167 if (rxq[rx_queue_id] != NULL) {
2168 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
2170 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
2171 rxq[rx_queue_id] = NULL;
2173 ret = (*dev->dev_ops->rx_hairpin_queue_setup)(dev, rx_queue_id,
2176 dev->data->rx_queue_state[rx_queue_id] =
2177 RTE_ETH_QUEUE_STATE_HAIRPIN;
2178 return eth_err(port_id, ret);
2182 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
2183 uint16_t nb_tx_desc, unsigned int socket_id,
2184 const struct rte_eth_txconf *tx_conf)
2186 struct rte_eth_dev *dev;
2187 struct rte_eth_dev_info dev_info;
2188 struct rte_eth_txconf local_conf;
2192 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2194 dev = &rte_eth_devices[port_id];
2195 if (tx_queue_id >= dev->data->nb_tx_queues) {
2196 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
2200 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP);
2202 ret = rte_eth_dev_info_get(port_id, &dev_info);
2206 /* Use default specified by driver, if nb_tx_desc is zero */
2207 if (nb_tx_desc == 0) {
2208 nb_tx_desc = dev_info.default_txportconf.ring_size;
2209 /* If driver default is zero, fall back on EAL default */
2210 if (nb_tx_desc == 0)
2211 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE;
2213 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max ||
2214 nb_tx_desc < dev_info.tx_desc_lim.nb_min ||
2215 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) {
2217 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
2218 nb_tx_desc, dev_info.tx_desc_lim.nb_max,
2219 dev_info.tx_desc_lim.nb_min,
2220 dev_info.tx_desc_lim.nb_align);
2224 if (dev->data->dev_started &&
2225 !(dev_info.dev_capa &
2226 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP))
2229 if (dev->data->dev_started &&
2230 (dev->data->tx_queue_state[tx_queue_id] !=
2231 RTE_ETH_QUEUE_STATE_STOPPED))
2234 txq = dev->data->tx_queues;
2235 if (txq[tx_queue_id]) {
2236 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
2238 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
2239 txq[tx_queue_id] = NULL;
2242 if (tx_conf == NULL)
2243 tx_conf = &dev_info.default_txconf;
2245 local_conf = *tx_conf;
2248 * If an offloading has already been enabled in
2249 * rte_eth_dev_configure(), it has been enabled on all queues,
2250 * so there is no need to enable it in this queue again.
2251 * The local_conf.offloads input to underlying PMD only carries
2252 * those offloadings which are only enabled on this queue and
2253 * not enabled on all queues.
2255 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads;
2258 * New added offloadings for this queue are those not enabled in
2259 * rte_eth_dev_configure() and they must be per-queue type.
2260 * A pure per-port offloading can't be enabled on a queue while
2261 * disabled on another queue. A pure per-port offloading can't
2262 * be enabled for any queue as new added one if it hasn't been
2263 * enabled in rte_eth_dev_configure().
2265 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) !=
2266 local_conf.offloads) {
2268 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
2269 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
2270 port_id, tx_queue_id, local_conf.offloads,
2271 dev_info.tx_queue_offload_capa,
2276 rte_ethdev_trace_txq_setup(port_id, tx_queue_id, nb_tx_desc, tx_conf);
2277 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev,
2278 tx_queue_id, nb_tx_desc, socket_id, &local_conf));
2282 rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
2283 uint16_t nb_tx_desc,
2284 const struct rte_eth_hairpin_conf *conf)
2286 struct rte_eth_dev *dev;
2287 struct rte_eth_hairpin_cap cap;
2293 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2294 dev = &rte_eth_devices[port_id];
2295 if (tx_queue_id >= dev->data->nb_tx_queues) {
2296 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
2299 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
2302 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_hairpin_queue_setup,
2304 /* if nb_rx_desc is zero use max number of desc from the driver. */
2305 if (nb_tx_desc == 0)
2306 nb_tx_desc = cap.max_nb_desc;
2307 if (nb_tx_desc > cap.max_nb_desc) {
2309 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu",
2310 nb_tx_desc, cap.max_nb_desc);
2313 if (conf->peer_count > cap.max_tx_2_rx) {
2315 "Invalid value for number of peers for Tx queue(=%u), should be: <= %hu",
2316 conf->peer_count, cap.max_tx_2_rx);
2319 if (conf->peer_count == 0) {
2321 "Invalid value for number of peers for Tx queue(=%u), should be: > 0",
2325 for (i = 0, count = 0; i < dev->data->nb_tx_queues &&
2326 cap.max_nb_queues != UINT16_MAX; i++) {
2327 if (i == tx_queue_id || rte_eth_dev_is_tx_hairpin_queue(dev, i))
2330 if (count > cap.max_nb_queues) {
2331 RTE_ETHDEV_LOG(ERR, "To many Tx hairpin queues max is %d",
2335 if (dev->data->dev_started)
2337 txq = dev->data->tx_queues;
2338 if (txq[tx_queue_id] != NULL) {
2339 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
2341 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
2342 txq[tx_queue_id] = NULL;
2344 ret = (*dev->dev_ops->tx_hairpin_queue_setup)
2345 (dev, tx_queue_id, nb_tx_desc, conf);
2347 dev->data->tx_queue_state[tx_queue_id] =
2348 RTE_ETH_QUEUE_STATE_HAIRPIN;
2349 return eth_err(port_id, ret);
2353 rte_eth_hairpin_bind(uint16_t tx_port, uint16_t rx_port)
2355 struct rte_eth_dev *dev;
2358 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV);
2359 dev = &rte_eth_devices[tx_port];
2360 if (dev->data->dev_started == 0) {
2361 RTE_ETHDEV_LOG(ERR, "Tx port %d is not started\n", tx_port);
2365 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_bind, -ENOTSUP);
2366 ret = (*dev->dev_ops->hairpin_bind)(dev, rx_port);
2368 RTE_ETHDEV_LOG(ERR, "Failed to bind hairpin Tx %d"
2369 " to Rx %d (%d - all ports)\n",
2370 tx_port, rx_port, RTE_MAX_ETHPORTS);
2376 rte_eth_hairpin_unbind(uint16_t tx_port, uint16_t rx_port)
2378 struct rte_eth_dev *dev;
2381 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV);
2382 dev = &rte_eth_devices[tx_port];
2383 if (dev->data->dev_started == 0) {
2384 RTE_ETHDEV_LOG(ERR, "Tx port %d is already stopped\n", tx_port);
2388 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_unbind, -ENOTSUP);
2389 ret = (*dev->dev_ops->hairpin_unbind)(dev, rx_port);
2391 RTE_ETHDEV_LOG(ERR, "Failed to unbind hairpin Tx %d"
2392 " from Rx %d (%d - all ports)\n",
2393 tx_port, rx_port, RTE_MAX_ETHPORTS);
2399 rte_eth_hairpin_get_peer_ports(uint16_t port_id, uint16_t *peer_ports,
2400 size_t len, uint32_t direction)
2402 struct rte_eth_dev *dev;
2405 if (peer_ports == NULL || len == 0)
2408 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2409 dev = &rte_eth_devices[port_id];
2410 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_get_peer_ports,
2413 ret = (*dev->dev_ops->hairpin_get_peer_ports)(dev, peer_ports,
2416 RTE_ETHDEV_LOG(ERR, "Failed to get %d hairpin peer %s ports\n",
2417 port_id, direction ? "Rx" : "Tx");
2423 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent,
2424 void *userdata __rte_unused)
2426 rte_pktmbuf_free_bulk(pkts, unsent);
2430 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent,
2433 uint64_t *count = userdata;
2435 rte_pktmbuf_free_bulk(pkts, unsent);
2440 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer,
2441 buffer_tx_error_fn cbfn, void *userdata)
2443 buffer->error_callback = cbfn;
2444 buffer->error_userdata = userdata;
2449 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size)
2456 buffer->size = size;
2457 if (buffer->error_callback == NULL) {
2458 ret = rte_eth_tx_buffer_set_err_callback(
2459 buffer, rte_eth_tx_buffer_drop_callback, NULL);
2466 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt)
2468 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2471 /* Validate Input Data. Bail if not valid or not supported. */
2472 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2473 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_done_cleanup, -ENOTSUP);
2475 /* Call driver to free pending mbufs. */
2476 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id],
2478 return eth_err(port_id, ret);
2482 rte_eth_promiscuous_enable(uint16_t port_id)
2484 struct rte_eth_dev *dev;
2487 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2488 dev = &rte_eth_devices[port_id];
2490 if (dev->data->promiscuous == 1)
2493 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_enable, -ENOTSUP);
2495 diag = (*dev->dev_ops->promiscuous_enable)(dev);
2496 dev->data->promiscuous = (diag == 0) ? 1 : 0;
2498 return eth_err(port_id, diag);
2502 rte_eth_promiscuous_disable(uint16_t port_id)
2504 struct rte_eth_dev *dev;
2507 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2508 dev = &rte_eth_devices[port_id];
2510 if (dev->data->promiscuous == 0)
2513 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_disable, -ENOTSUP);
2515 dev->data->promiscuous = 0;
2516 diag = (*dev->dev_ops->promiscuous_disable)(dev);
2518 dev->data->promiscuous = 1;
2520 return eth_err(port_id, diag);
2524 rte_eth_promiscuous_get(uint16_t port_id)
2526 struct rte_eth_dev *dev;
2528 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2530 dev = &rte_eth_devices[port_id];
2531 return dev->data->promiscuous;
2535 rte_eth_allmulticast_enable(uint16_t port_id)
2537 struct rte_eth_dev *dev;
2540 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2541 dev = &rte_eth_devices[port_id];
2543 if (dev->data->all_multicast == 1)
2546 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_enable, -ENOTSUP);
2547 diag = (*dev->dev_ops->allmulticast_enable)(dev);
2548 dev->data->all_multicast = (diag == 0) ? 1 : 0;
2550 return eth_err(port_id, diag);
2554 rte_eth_allmulticast_disable(uint16_t port_id)
2556 struct rte_eth_dev *dev;
2559 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2560 dev = &rte_eth_devices[port_id];
2562 if (dev->data->all_multicast == 0)
2565 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_disable, -ENOTSUP);
2566 dev->data->all_multicast = 0;
2567 diag = (*dev->dev_ops->allmulticast_disable)(dev);
2569 dev->data->all_multicast = 1;
2571 return eth_err(port_id, diag);
2575 rte_eth_allmulticast_get(uint16_t port_id)
2577 struct rte_eth_dev *dev;
2579 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2581 dev = &rte_eth_devices[port_id];
2582 return dev->data->all_multicast;
2586 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link)
2588 struct rte_eth_dev *dev;
2590 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2591 dev = &rte_eth_devices[port_id];
2593 if (dev->data->dev_conf.intr_conf.lsc &&
2594 dev->data->dev_started)
2595 rte_eth_linkstatus_get(dev, eth_link);
2597 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
2598 (*dev->dev_ops->link_update)(dev, 1);
2599 *eth_link = dev->data->dev_link;
2606 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link)
2608 struct rte_eth_dev *dev;
2610 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2611 dev = &rte_eth_devices[port_id];
2613 if (dev->data->dev_conf.intr_conf.lsc &&
2614 dev->data->dev_started)
2615 rte_eth_linkstatus_get(dev, eth_link);
2617 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
2618 (*dev->dev_ops->link_update)(dev, 0);
2619 *eth_link = dev->data->dev_link;
2626 rte_eth_link_speed_to_str(uint32_t link_speed)
2628 switch (link_speed) {
2629 case ETH_SPEED_NUM_NONE: return "None";
2630 case ETH_SPEED_NUM_10M: return "10 Mbps";
2631 case ETH_SPEED_NUM_100M: return "100 Mbps";
2632 case ETH_SPEED_NUM_1G: return "1 Gbps";
2633 case ETH_SPEED_NUM_2_5G: return "2.5 Gbps";
2634 case ETH_SPEED_NUM_5G: return "5 Gbps";
2635 case ETH_SPEED_NUM_10G: return "10 Gbps";
2636 case ETH_SPEED_NUM_20G: return "20 Gbps";
2637 case ETH_SPEED_NUM_25G: return "25 Gbps";
2638 case ETH_SPEED_NUM_40G: return "40 Gbps";
2639 case ETH_SPEED_NUM_50G: return "50 Gbps";
2640 case ETH_SPEED_NUM_56G: return "56 Gbps";
2641 case ETH_SPEED_NUM_100G: return "100 Gbps";
2642 case ETH_SPEED_NUM_200G: return "200 Gbps";
2643 case ETH_SPEED_NUM_UNKNOWN: return "Unknown";
2644 default: return "Invalid";
2649 rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link)
2651 if (eth_link->link_status == ETH_LINK_DOWN)
2652 return snprintf(str, len, "Link down");
2654 return snprintf(str, len, "Link up at %s %s %s",
2655 rte_eth_link_speed_to_str(eth_link->link_speed),
2656 (eth_link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
2658 (eth_link->link_autoneg == ETH_LINK_AUTONEG) ?
2659 "Autoneg" : "Fixed");
2663 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
2665 struct rte_eth_dev *dev;
2667 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2669 dev = &rte_eth_devices[port_id];
2670 memset(stats, 0, sizeof(*stats));
2672 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP);
2673 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;
2674 return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats));
2678 rte_eth_stats_reset(uint16_t port_id)
2680 struct rte_eth_dev *dev;
2683 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2684 dev = &rte_eth_devices[port_id];
2686 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_reset, -ENOTSUP);
2687 ret = (*dev->dev_ops->stats_reset)(dev);
2689 return eth_err(port_id, ret);
2691 dev->data->rx_mbuf_alloc_failed = 0;
2697 eth_dev_get_xstats_basic_count(struct rte_eth_dev *dev)
2699 uint16_t nb_rxqs, nb_txqs;
2702 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2703 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2705 count = RTE_NB_STATS;
2706 if (dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) {
2707 count += nb_rxqs * RTE_NB_RXQ_STATS;
2708 count += nb_txqs * RTE_NB_TXQ_STATS;
2715 eth_dev_get_xstats_count(uint16_t port_id)
2717 struct rte_eth_dev *dev;
2720 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2721 dev = &rte_eth_devices[port_id];
2722 if (dev->dev_ops->xstats_get_names_by_id != NULL) {
2723 count = (*dev->dev_ops->xstats_get_names_by_id)(dev, NULL,
2726 return eth_err(port_id, count);
2728 if (dev->dev_ops->xstats_get_names != NULL) {
2729 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0);
2731 return eth_err(port_id, count);
2736 count += eth_dev_get_xstats_basic_count(dev);
2742 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name,
2745 int cnt_xstats, idx_xstat;
2747 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2750 RTE_ETHDEV_LOG(ERR, "Id pointer is NULL\n");
2755 RTE_ETHDEV_LOG(ERR, "xstat_name pointer is NULL\n");
2760 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL);
2761 if (cnt_xstats < 0) {
2762 RTE_ETHDEV_LOG(ERR, "Cannot get count of xstats\n");
2766 /* Get id-name lookup table */
2767 struct rte_eth_xstat_name xstats_names[cnt_xstats];
2769 if (cnt_xstats != rte_eth_xstats_get_names_by_id(
2770 port_id, xstats_names, cnt_xstats, NULL)) {
2771 RTE_ETHDEV_LOG(ERR, "Cannot get xstats lookup\n");
2775 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) {
2776 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) {
2785 /* retrieve basic stats names */
2787 eth_basic_stats_get_names(struct rte_eth_dev *dev,
2788 struct rte_eth_xstat_name *xstats_names)
2790 int cnt_used_entries = 0;
2791 uint32_t idx, id_queue;
2794 for (idx = 0; idx < RTE_NB_STATS; idx++) {
2795 strlcpy(xstats_names[cnt_used_entries].name,
2796 eth_dev_stats_strings[idx].name,
2797 sizeof(xstats_names[0].name));
2801 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0)
2802 return cnt_used_entries;
2804 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2805 for (id_queue = 0; id_queue < num_q; id_queue++) {
2806 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) {
2807 snprintf(xstats_names[cnt_used_entries].name,
2808 sizeof(xstats_names[0].name),
2810 id_queue, eth_dev_rxq_stats_strings[idx].name);
2815 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2816 for (id_queue = 0; id_queue < num_q; id_queue++) {
2817 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) {
2818 snprintf(xstats_names[cnt_used_entries].name,
2819 sizeof(xstats_names[0].name),
2821 id_queue, eth_dev_txq_stats_strings[idx].name);
2825 return cnt_used_entries;
2828 /* retrieve ethdev extended statistics names */
2830 rte_eth_xstats_get_names_by_id(uint16_t port_id,
2831 struct rte_eth_xstat_name *xstats_names, unsigned int size,
2834 struct rte_eth_xstat_name *xstats_names_copy;
2835 unsigned int no_basic_stat_requested = 1;
2836 unsigned int no_ext_stat_requested = 1;
2837 unsigned int expected_entries;
2838 unsigned int basic_count;
2839 struct rte_eth_dev *dev;
2843 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2844 dev = &rte_eth_devices[port_id];
2846 basic_count = eth_dev_get_xstats_basic_count(dev);
2847 ret = eth_dev_get_xstats_count(port_id);
2850 expected_entries = (unsigned int)ret;
2852 /* Return max number of stats if no ids given */
2855 return expected_entries;
2856 else if (xstats_names && size < expected_entries)
2857 return expected_entries;
2860 if (ids && !xstats_names)
2863 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) {
2864 uint64_t ids_copy[size];
2866 for (i = 0; i < size; i++) {
2867 if (ids[i] < basic_count) {
2868 no_basic_stat_requested = 0;
2873 * Convert ids to xstats ids that PMD knows.
2874 * ids known by user are basic + extended stats.
2876 ids_copy[i] = ids[i] - basic_count;
2879 if (no_basic_stat_requested)
2880 return (*dev->dev_ops->xstats_get_names_by_id)(dev,
2881 xstats_names, ids_copy, size);
2884 /* Retrieve all stats */
2886 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names,
2888 if (num_stats < 0 || num_stats > (int)expected_entries)
2891 return expected_entries;
2894 xstats_names_copy = calloc(expected_entries,
2895 sizeof(struct rte_eth_xstat_name));
2897 if (!xstats_names_copy) {
2898 RTE_ETHDEV_LOG(ERR, "Can't allocate memory\n");
2903 for (i = 0; i < size; i++) {
2904 if (ids[i] >= basic_count) {
2905 no_ext_stat_requested = 0;
2911 /* Fill xstats_names_copy structure */
2912 if (ids && no_ext_stat_requested) {
2913 eth_basic_stats_get_names(dev, xstats_names_copy);
2915 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy,
2918 free(xstats_names_copy);
2924 for (i = 0; i < size; i++) {
2925 if (ids[i] >= expected_entries) {
2926 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
2927 free(xstats_names_copy);
2930 xstats_names[i] = xstats_names_copy[ids[i]];
2933 free(xstats_names_copy);
2938 rte_eth_xstats_get_names(uint16_t port_id,
2939 struct rte_eth_xstat_name *xstats_names,
2942 struct rte_eth_dev *dev;
2943 int cnt_used_entries;
2944 int cnt_expected_entries;
2945 int cnt_driver_entries;
2947 cnt_expected_entries = eth_dev_get_xstats_count(port_id);
2948 if (xstats_names == NULL || cnt_expected_entries < 0 ||
2949 (int)size < cnt_expected_entries)
2950 return cnt_expected_entries;
2952 /* port_id checked in eth_dev_get_xstats_count() */
2953 dev = &rte_eth_devices[port_id];
2955 cnt_used_entries = eth_basic_stats_get_names(dev, xstats_names);
2957 if (dev->dev_ops->xstats_get_names != NULL) {
2958 /* If there are any driver-specific xstats, append them
2961 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)(
2963 xstats_names + cnt_used_entries,
2964 size - cnt_used_entries);
2965 if (cnt_driver_entries < 0)
2966 return eth_err(port_id, cnt_driver_entries);
2967 cnt_used_entries += cnt_driver_entries;
2970 return cnt_used_entries;
2975 eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats)
2977 struct rte_eth_dev *dev;
2978 struct rte_eth_stats eth_stats;
2979 unsigned int count = 0, i, q;
2980 uint64_t val, *stats_ptr;
2981 uint16_t nb_rxqs, nb_txqs;
2984 ret = rte_eth_stats_get(port_id, ð_stats);
2988 dev = &rte_eth_devices[port_id];
2990 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2991 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2994 for (i = 0; i < RTE_NB_STATS; i++) {
2995 stats_ptr = RTE_PTR_ADD(ð_stats,
2996 eth_dev_stats_strings[i].offset);
2998 xstats[count++].value = val;
3001 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0)
3005 for (q = 0; q < nb_rxqs; q++) {
3006 for (i = 0; i < RTE_NB_RXQ_STATS; i++) {
3007 stats_ptr = RTE_PTR_ADD(ð_stats,
3008 eth_dev_rxq_stats_strings[i].offset +
3009 q * sizeof(uint64_t));
3011 xstats[count++].value = val;
3016 for (q = 0; q < nb_txqs; q++) {
3017 for (i = 0; i < RTE_NB_TXQ_STATS; i++) {
3018 stats_ptr = RTE_PTR_ADD(ð_stats,
3019 eth_dev_txq_stats_strings[i].offset +
3020 q * sizeof(uint64_t));
3022 xstats[count++].value = val;
3028 /* retrieve ethdev extended statistics */
3030 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids,
3031 uint64_t *values, unsigned int size)
3033 unsigned int no_basic_stat_requested = 1;
3034 unsigned int no_ext_stat_requested = 1;
3035 unsigned int num_xstats_filled;
3036 unsigned int basic_count;
3037 uint16_t expected_entries;
3038 struct rte_eth_dev *dev;
3042 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3043 ret = eth_dev_get_xstats_count(port_id);
3046 expected_entries = (uint16_t)ret;
3047 struct rte_eth_xstat xstats[expected_entries];
3048 dev = &rte_eth_devices[port_id];
3049 basic_count = eth_dev_get_xstats_basic_count(dev);
3051 /* Return max number of stats if no ids given */
3054 return expected_entries;
3055 else if (values && size < expected_entries)
3056 return expected_entries;
3062 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) {
3063 unsigned int basic_count = eth_dev_get_xstats_basic_count(dev);
3064 uint64_t ids_copy[size];
3066 for (i = 0; i < size; i++) {
3067 if (ids[i] < basic_count) {
3068 no_basic_stat_requested = 0;
3073 * Convert ids to xstats ids that PMD knows.
3074 * ids known by user are basic + extended stats.
3076 ids_copy[i] = ids[i] - basic_count;
3079 if (no_basic_stat_requested)
3080 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy,
3085 for (i = 0; i < size; i++) {
3086 if (ids[i] >= basic_count) {
3087 no_ext_stat_requested = 0;
3093 /* Fill the xstats structure */
3094 if (ids && no_ext_stat_requested)
3095 ret = eth_basic_stats_get(port_id, xstats);
3097 ret = rte_eth_xstats_get(port_id, xstats, expected_entries);
3101 num_xstats_filled = (unsigned int)ret;
3103 /* Return all stats */
3105 for (i = 0; i < num_xstats_filled; i++)
3106 values[i] = xstats[i].value;
3107 return expected_entries;
3111 for (i = 0; i < size; i++) {
3112 if (ids[i] >= expected_entries) {
3113 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
3116 values[i] = xstats[ids[i]].value;
3122 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats,
3125 struct rte_eth_dev *dev;
3126 unsigned int count = 0, i;
3127 signed int xcount = 0;
3128 uint16_t nb_rxqs, nb_txqs;
3131 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3133 dev = &rte_eth_devices[port_id];
3135 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
3136 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
3138 /* Return generic statistics */
3139 count = RTE_NB_STATS;
3140 if (dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS)
3141 count += (nb_rxqs * RTE_NB_RXQ_STATS) + (nb_txqs * RTE_NB_TXQ_STATS);
3143 /* implemented by the driver */
3144 if (dev->dev_ops->xstats_get != NULL) {
3145 /* Retrieve the xstats from the driver at the end of the
3148 xcount = (*dev->dev_ops->xstats_get)(dev,
3149 xstats ? xstats + count : NULL,
3150 (n > count) ? n - count : 0);
3153 return eth_err(port_id, xcount);
3156 if (n < count + xcount || xstats == NULL)
3157 return count + xcount;
3159 /* now fill the xstats structure */
3160 ret = eth_basic_stats_get(port_id, xstats);
3165 for (i = 0; i < count; i++)
3167 /* add an offset to driver-specific stats */
3168 for ( ; i < count + xcount; i++)
3169 xstats[i].id += count;
3171 return count + xcount;
3174 /* reset ethdev extended statistics */
3176 rte_eth_xstats_reset(uint16_t port_id)
3178 struct rte_eth_dev *dev;
3180 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3181 dev = &rte_eth_devices[port_id];
3183 /* implemented by the driver */
3184 if (dev->dev_ops->xstats_reset != NULL)
3185 return eth_err(port_id, (*dev->dev_ops->xstats_reset)(dev));
3187 /* fallback to default */
3188 return rte_eth_stats_reset(port_id);
3192 eth_dev_set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id,
3193 uint8_t stat_idx, uint8_t is_rx)
3195 struct rte_eth_dev *dev;
3197 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3199 dev = &rte_eth_devices[port_id];
3201 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP);
3203 if (is_rx && (queue_id >= dev->data->nb_rx_queues))
3206 if (!is_rx && (queue_id >= dev->data->nb_tx_queues))
3209 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
3212 return (*dev->dev_ops->queue_stats_mapping_set)
3213 (dev, queue_id, stat_idx, is_rx);
3218 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id,
3221 return eth_err(port_id, eth_dev_set_queue_stats_mapping(port_id,
3223 stat_idx, STAT_QMAP_TX));
3228 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id,
3231 return eth_err(port_id, eth_dev_set_queue_stats_mapping(port_id,
3233 stat_idx, STAT_QMAP_RX));
3237 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size)
3239 struct rte_eth_dev *dev;
3241 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3242 dev = &rte_eth_devices[port_id];
3244 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fw_version_get, -ENOTSUP);
3245 return eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev,
3246 fw_version, fw_size));
3250 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info)
3252 struct rte_eth_dev *dev;
3253 const struct rte_eth_desc_lim lim = {
3254 .nb_max = UINT16_MAX,
3257 .nb_seg_max = UINT16_MAX,
3258 .nb_mtu_seg_max = UINT16_MAX,
3263 * Init dev_info before port_id check since caller does not have
3264 * return status and does not know if get is successful or not.
3266 memset(dev_info, 0, sizeof(struct rte_eth_dev_info));
3267 dev_info->switch_info.domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
3269 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3270 dev = &rte_eth_devices[port_id];
3272 dev_info->rx_desc_lim = lim;
3273 dev_info->tx_desc_lim = lim;
3274 dev_info->device = dev->device;
3275 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3276 dev_info->max_mtu = UINT16_MAX;
3278 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);
3279 diag = (*dev->dev_ops->dev_infos_get)(dev, dev_info);
3281 /* Cleanup already filled in device information */
3282 memset(dev_info, 0, sizeof(struct rte_eth_dev_info));
3283 return eth_err(port_id, diag);
3286 /* Maximum number of queues should be <= RTE_MAX_QUEUES_PER_PORT */
3287 dev_info->max_rx_queues = RTE_MIN(dev_info->max_rx_queues,
3288 RTE_MAX_QUEUES_PER_PORT);
3289 dev_info->max_tx_queues = RTE_MIN(dev_info->max_tx_queues,
3290 RTE_MAX_QUEUES_PER_PORT);
3292 dev_info->driver_name = dev->device->driver->name;
3293 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3294 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3296 dev_info->dev_flags = &dev->data->dev_flags;
3302 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,
3303 uint32_t *ptypes, int num)
3306 struct rte_eth_dev *dev;
3307 const uint32_t *all_ptypes;
3309 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3310 dev = &rte_eth_devices[port_id];
3311 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_supported_ptypes_get, 0);
3312 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
3317 for (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i)
3318 if (all_ptypes[i] & ptype_mask) {
3320 ptypes[j] = all_ptypes[i];
3328 rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask,
3329 uint32_t *set_ptypes, unsigned int num)
3331 const uint32_t valid_ptype_masks[] = {
3335 RTE_PTYPE_TUNNEL_MASK,
3336 RTE_PTYPE_INNER_L2_MASK,
3337 RTE_PTYPE_INNER_L3_MASK,
3338 RTE_PTYPE_INNER_L4_MASK,
3340 const uint32_t *all_ptypes;
3341 struct rte_eth_dev *dev;
3342 uint32_t unused_mask;
3346 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3347 dev = &rte_eth_devices[port_id];
3349 if (num > 0 && set_ptypes == NULL)
3352 if (*dev->dev_ops->dev_supported_ptypes_get == NULL ||
3353 *dev->dev_ops->dev_ptypes_set == NULL) {
3358 if (ptype_mask == 0) {
3359 ret = (*dev->dev_ops->dev_ptypes_set)(dev,
3364 unused_mask = ptype_mask;
3365 for (i = 0; i < RTE_DIM(valid_ptype_masks); i++) {
3366 uint32_t mask = ptype_mask & valid_ptype_masks[i];
3367 if (mask && mask != valid_ptype_masks[i]) {
3371 unused_mask &= ~valid_ptype_masks[i];
3379 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
3380 if (all_ptypes == NULL) {
3386 * Accommodate as many set_ptypes as possible. If the supplied
3387 * set_ptypes array is insufficient fill it partially.
3389 for (i = 0, j = 0; set_ptypes != NULL &&
3390 (all_ptypes[i] != RTE_PTYPE_UNKNOWN); ++i) {
3391 if (ptype_mask & all_ptypes[i]) {
3393 set_ptypes[j] = all_ptypes[i];
3401 if (set_ptypes != NULL && j < num)
3402 set_ptypes[j] = RTE_PTYPE_UNKNOWN;
3404 return (*dev->dev_ops->dev_ptypes_set)(dev, ptype_mask);
3408 set_ptypes[0] = RTE_PTYPE_UNKNOWN;
3414 rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr)
3416 struct rte_eth_dev *dev;
3418 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3419 dev = &rte_eth_devices[port_id];
3420 rte_ether_addr_copy(&dev->data->mac_addrs[0], mac_addr);
3426 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu)
3428 struct rte_eth_dev *dev;
3430 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3432 dev = &rte_eth_devices[port_id];
3433 *mtu = dev->data->mtu;
3438 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu)
3441 struct rte_eth_dev_info dev_info;
3442 struct rte_eth_dev *dev;
3444 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3445 dev = &rte_eth_devices[port_id];
3446 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP);
3449 * Check if the device supports dev_infos_get, if it does not
3450 * skip min_mtu/max_mtu validation here as this requires values
3451 * that are populated within the call to rte_eth_dev_info_get()
3452 * which relies on dev->dev_ops->dev_infos_get.
3454 if (*dev->dev_ops->dev_infos_get != NULL) {
3455 ret = rte_eth_dev_info_get(port_id, &dev_info);
3459 if (mtu < dev_info.min_mtu || mtu > dev_info.max_mtu)
3463 ret = (*dev->dev_ops->mtu_set)(dev, mtu);
3465 dev->data->mtu = mtu;
3467 return eth_err(port_id, ret);
3471 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on)
3473 struct rte_eth_dev *dev;
3476 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3477 dev = &rte_eth_devices[port_id];
3478 if (!(dev->data->dev_conf.rxmode.offloads &
3479 DEV_RX_OFFLOAD_VLAN_FILTER)) {
3480 RTE_ETHDEV_LOG(ERR, "Port %u: vlan-filtering disabled\n",
3485 if (vlan_id > 4095) {
3486 RTE_ETHDEV_LOG(ERR, "Port_id=%u invalid vlan_id=%u > 4095\n",
3490 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP);
3492 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on);
3494 struct rte_vlan_filter_conf *vfc;
3498 vfc = &dev->data->vlan_filter_conf;
3499 vidx = vlan_id / 64;
3500 vbit = vlan_id % 64;
3503 vfc->ids[vidx] |= UINT64_C(1) << vbit;
3505 vfc->ids[vidx] &= ~(UINT64_C(1) << vbit);
3508 return eth_err(port_id, ret);
3512 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id,
3515 struct rte_eth_dev *dev;
3517 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3518 dev = &rte_eth_devices[port_id];
3519 if (rx_queue_id >= dev->data->nb_rx_queues) {
3520 RTE_ETHDEV_LOG(ERR, "Invalid rx_queue_id=%u\n", rx_queue_id);
3524 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
3525 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on);
3531 rte_eth_dev_set_vlan_ether_type(uint16_t port_id,
3532 enum rte_vlan_type vlan_type,
3535 struct rte_eth_dev *dev;
3537 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3538 dev = &rte_eth_devices[port_id];
3539 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP);
3541 return eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type,
3546 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask)
3548 struct rte_eth_dev_info dev_info;
3549 struct rte_eth_dev *dev;
3553 uint64_t orig_offloads;
3554 uint64_t dev_offloads;
3555 uint64_t new_offloads;
3557 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3558 dev = &rte_eth_devices[port_id];
3560 /* save original values in case of failure */
3561 orig_offloads = dev->data->dev_conf.rxmode.offloads;
3562 dev_offloads = orig_offloads;
3564 /* check which option changed by application */
3565 cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD);
3566 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
3569 dev_offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
3571 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
3572 mask |= ETH_VLAN_STRIP_MASK;
3575 cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD);
3576 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER);
3579 dev_offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
3581 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_FILTER;
3582 mask |= ETH_VLAN_FILTER_MASK;
3585 cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD);
3586 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND);
3589 dev_offloads |= DEV_RX_OFFLOAD_VLAN_EXTEND;
3591 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_EXTEND;
3592 mask |= ETH_VLAN_EXTEND_MASK;
3595 cur = !!(offload_mask & ETH_QINQ_STRIP_OFFLOAD);
3596 org = !!(dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP);
3599 dev_offloads |= DEV_RX_OFFLOAD_QINQ_STRIP;
3601 dev_offloads &= ~DEV_RX_OFFLOAD_QINQ_STRIP;
3602 mask |= ETH_QINQ_STRIP_MASK;
3609 ret = rte_eth_dev_info_get(port_id, &dev_info);
3613 /* Rx VLAN offloading must be within its device capabilities */
3614 if ((dev_offloads & dev_info.rx_offload_capa) != dev_offloads) {
3615 new_offloads = dev_offloads & ~orig_offloads;
3617 "Ethdev port_id=%u requested new added VLAN offloads "
3618 "0x%" PRIx64 " must be within Rx offloads capabilities "
3619 "0x%" PRIx64 " in %s()\n",
3620 port_id, new_offloads, dev_info.rx_offload_capa,
3625 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP);
3626 dev->data->dev_conf.rxmode.offloads = dev_offloads;
3627 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask);
3629 /* hit an error restore original values */
3630 dev->data->dev_conf.rxmode.offloads = orig_offloads;
3633 return eth_err(port_id, ret);
3637 rte_eth_dev_get_vlan_offload(uint16_t port_id)
3639 struct rte_eth_dev *dev;
3640 uint64_t *dev_offloads;
3643 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3644 dev = &rte_eth_devices[port_id];
3645 dev_offloads = &dev->data->dev_conf.rxmode.offloads;
3647 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3648 ret |= ETH_VLAN_STRIP_OFFLOAD;
3650 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3651 ret |= ETH_VLAN_FILTER_OFFLOAD;
3653 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3654 ret |= ETH_VLAN_EXTEND_OFFLOAD;
3656 if (*dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
3657 ret |= ETH_QINQ_STRIP_OFFLOAD;
3663 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on)
3665 struct rte_eth_dev *dev;
3667 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3668 dev = &rte_eth_devices[port_id];
3669 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP);
3671 return eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on));
3675 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
3677 struct rte_eth_dev *dev;
3679 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3680 dev = &rte_eth_devices[port_id];
3681 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP);
3682 memset(fc_conf, 0, sizeof(*fc_conf));
3683 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf));
3687 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
3689 struct rte_eth_dev *dev;
3691 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3692 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) {
3693 RTE_ETHDEV_LOG(ERR, "Invalid send_xon, only 0/1 allowed\n");
3697 dev = &rte_eth_devices[port_id];
3698 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP);
3699 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf));
3703 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,
3704 struct rte_eth_pfc_conf *pfc_conf)
3706 struct rte_eth_dev *dev;
3708 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3709 if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) {
3710 RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n");
3714 dev = &rte_eth_devices[port_id];
3715 /* High water, low water validation are device specific */
3716 if (*dev->dev_ops->priority_flow_ctrl_set)
3717 return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set)
3723 eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,
3731 num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE;
3732 for (i = 0; i < num; i++) {
3733 if (reta_conf[i].mask)
3741 eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf,
3745 uint16_t i, idx, shift;
3751 RTE_ETHDEV_LOG(ERR, "No receive queue is available\n");
3755 for (i = 0; i < reta_size; i++) {
3756 idx = i / RTE_RETA_GROUP_SIZE;
3757 shift = i % RTE_RETA_GROUP_SIZE;
3758 if ((reta_conf[idx].mask & (1ULL << shift)) &&
3759 (reta_conf[idx].reta[shift] >= max_rxq)) {
3761 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n",
3763 reta_conf[idx].reta[shift], max_rxq);
3772 rte_eth_dev_rss_reta_update(uint16_t port_id,
3773 struct rte_eth_rss_reta_entry64 *reta_conf,
3776 struct rte_eth_dev *dev;
3779 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3780 /* Check mask bits */
3781 ret = eth_check_reta_mask(reta_conf, reta_size);
3785 dev = &rte_eth_devices[port_id];
3787 /* Check entry value */
3788 ret = eth_check_reta_entry(reta_conf, reta_size,
3789 dev->data->nb_rx_queues);
3793 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP);
3794 return eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf,
3799 rte_eth_dev_rss_reta_query(uint16_t port_id,
3800 struct rte_eth_rss_reta_entry64 *reta_conf,
3803 struct rte_eth_dev *dev;
3806 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3808 /* Check mask bits */
3809 ret = eth_check_reta_mask(reta_conf, reta_size);
3813 dev = &rte_eth_devices[port_id];
3814 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP);
3815 return eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf,
3820 rte_eth_dev_rss_hash_update(uint16_t port_id,
3821 struct rte_eth_rss_conf *rss_conf)
3823 struct rte_eth_dev *dev;
3824 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, };
3827 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3829 ret = rte_eth_dev_info_get(port_id, &dev_info);
3833 rss_conf->rss_hf = rte_eth_rss_hf_refine(rss_conf->rss_hf);
3835 dev = &rte_eth_devices[port_id];
3836 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) !=
3837 dev_info.flow_type_rss_offloads) {
3839 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
3840 port_id, rss_conf->rss_hf,
3841 dev_info.flow_type_rss_offloads);
3844 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP);
3845 return eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev,
3850 rte_eth_dev_rss_hash_conf_get(uint16_t port_id,
3851 struct rte_eth_rss_conf *rss_conf)
3853 struct rte_eth_dev *dev;
3855 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3856 dev = &rte_eth_devices[port_id];
3857 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP);
3858 return eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev,
3863 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,
3864 struct rte_eth_udp_tunnel *udp_tunnel)
3866 struct rte_eth_dev *dev;
3868 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3869 if (udp_tunnel == NULL) {
3870 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3874 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3875 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3879 dev = &rte_eth_devices[port_id];
3880 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_add, -ENOTSUP);
3881 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev,
3886 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,
3887 struct rte_eth_udp_tunnel *udp_tunnel)
3889 struct rte_eth_dev *dev;
3891 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3892 dev = &rte_eth_devices[port_id];
3894 if (udp_tunnel == NULL) {
3895 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3899 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3900 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3904 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_del, -ENOTSUP);
3905 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev,
3910 rte_eth_led_on(uint16_t port_id)
3912 struct rte_eth_dev *dev;
3914 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3915 dev = &rte_eth_devices[port_id];
3916 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP);
3917 return eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev));
3921 rte_eth_led_off(uint16_t port_id)
3923 struct rte_eth_dev *dev;
3925 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3926 dev = &rte_eth_devices[port_id];
3927 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP);
3928 return eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev));
3932 rte_eth_fec_get_capability(uint16_t port_id,
3933 struct rte_eth_fec_capa *speed_fec_capa,
3936 struct rte_eth_dev *dev;
3939 if (speed_fec_capa == NULL && num > 0)
3942 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3943 dev = &rte_eth_devices[port_id];
3944 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get_capability, -ENOTSUP);
3945 ret = (*dev->dev_ops->fec_get_capability)(dev, speed_fec_capa, num);
3951 rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa)
3953 struct rte_eth_dev *dev;
3955 if (fec_capa == NULL)
3958 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3959 dev = &rte_eth_devices[port_id];
3960 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get, -ENOTSUP);
3961 return eth_err(port_id, (*dev->dev_ops->fec_get)(dev, fec_capa));
3965 rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa)
3967 struct rte_eth_dev *dev;
3969 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3970 dev = &rte_eth_devices[port_id];
3971 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_set, -ENOTSUP);
3972 return eth_err(port_id, (*dev->dev_ops->fec_set)(dev, fec_capa));
3976 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
3980 eth_dev_get_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr)
3982 struct rte_eth_dev_info dev_info;
3983 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3987 ret = rte_eth_dev_info_get(port_id, &dev_info);
3991 for (i = 0; i < dev_info.max_mac_addrs; i++)
3992 if (memcmp(addr, &dev->data->mac_addrs[i],
3993 RTE_ETHER_ADDR_LEN) == 0)
3999 static const struct rte_ether_addr null_mac_addr;
4002 rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr,
4005 struct rte_eth_dev *dev;
4010 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4011 dev = &rte_eth_devices[port_id];
4012 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP);
4014 if (rte_is_zero_ether_addr(addr)) {
4015 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
4019 if (pool >= ETH_64_POOLS) {
4020 RTE_ETHDEV_LOG(ERR, "Pool id must be 0-%d\n", ETH_64_POOLS - 1);
4024 index = eth_dev_get_mac_addr_index(port_id, addr);
4026 index = eth_dev_get_mac_addr_index(port_id, &null_mac_addr);
4028 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
4033 pool_mask = dev->data->mac_pool_sel[index];
4035 /* Check if both MAC address and pool is already there, and do nothing */
4036 if (pool_mask & (1ULL << pool))
4041 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool);
4044 /* Update address in NIC data structure */
4045 rte_ether_addr_copy(addr, &dev->data->mac_addrs[index]);
4047 /* Update pool bitmap in NIC data structure */
4048 dev->data->mac_pool_sel[index] |= (1ULL << pool);
4051 return eth_err(port_id, ret);
4055 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *addr)
4057 struct rte_eth_dev *dev;
4060 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4061 dev = &rte_eth_devices[port_id];
4062 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP);
4064 index = eth_dev_get_mac_addr_index(port_id, addr);
4067 "Port %u: Cannot remove default MAC address\n",
4070 } else if (index < 0)
4071 return 0; /* Do nothing if address wasn't found */
4074 (*dev->dev_ops->mac_addr_remove)(dev, index);
4076 /* Update address in NIC data structure */
4077 rte_ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]);
4079 /* reset pool bitmap */
4080 dev->data->mac_pool_sel[index] = 0;
4086 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *addr)
4088 struct rte_eth_dev *dev;
4091 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4093 if (!rte_is_valid_assigned_ether_addr(addr))
4096 dev = &rte_eth_devices[port_id];
4097 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP);
4099 ret = (*dev->dev_ops->mac_addr_set)(dev, addr);
4103 /* Update default address in NIC data structure */
4104 rte_ether_addr_copy(addr, &dev->data->mac_addrs[0]);
4111 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
4115 eth_dev_get_hash_mac_addr_index(uint16_t port_id,
4116 const struct rte_ether_addr *addr)
4118 struct rte_eth_dev_info dev_info;
4119 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4123 ret = rte_eth_dev_info_get(port_id, &dev_info);
4127 if (!dev->data->hash_mac_addrs)
4130 for (i = 0; i < dev_info.max_hash_mac_addrs; i++)
4131 if (memcmp(addr, &dev->data->hash_mac_addrs[i],
4132 RTE_ETHER_ADDR_LEN) == 0)
4139 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr,
4144 struct rte_eth_dev *dev;
4146 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4148 dev = &rte_eth_devices[port_id];
4149 if (rte_is_zero_ether_addr(addr)) {
4150 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
4155 index = eth_dev_get_hash_mac_addr_index(port_id, addr);
4156 /* Check if it's already there, and do nothing */
4157 if ((index >= 0) && on)
4163 "Port %u: the MAC address was not set in UTA\n",
4168 index = eth_dev_get_hash_mac_addr_index(port_id, &null_mac_addr);
4170 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
4176 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP);
4177 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on);
4179 /* Update address in NIC data structure */
4181 rte_ether_addr_copy(addr,
4182 &dev->data->hash_mac_addrs[index]);
4184 rte_ether_addr_copy(&null_mac_addr,
4185 &dev->data->hash_mac_addrs[index]);
4188 return eth_err(port_id, ret);
4192 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on)
4194 struct rte_eth_dev *dev;
4196 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4198 dev = &rte_eth_devices[port_id];
4200 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP);
4201 return eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev,
4205 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,
4208 struct rte_eth_dev *dev;
4209 struct rte_eth_dev_info dev_info;
4210 struct rte_eth_link link;
4213 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4215 ret = rte_eth_dev_info_get(port_id, &dev_info);
4219 dev = &rte_eth_devices[port_id];
4220 link = dev->data->dev_link;
4222 if (queue_idx > dev_info.max_tx_queues) {
4224 "Set queue rate limit:port %u: invalid queue id=%u\n",
4225 port_id, queue_idx);
4229 if (tx_rate > link.link_speed) {
4231 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d\n",
4232 tx_rate, link.link_speed);
4236 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP);
4237 return eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev,
4238 queue_idx, tx_rate));
4242 rte_eth_mirror_rule_set(uint16_t port_id,
4243 struct rte_eth_mirror_conf *mirror_conf,
4244 uint8_t rule_id, uint8_t on)
4246 struct rte_eth_dev *dev;
4248 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4249 if (mirror_conf->rule_type == 0) {
4250 RTE_ETHDEV_LOG(ERR, "Mirror rule type can not be 0\n");
4254 if (mirror_conf->dst_pool >= ETH_64_POOLS) {
4255 RTE_ETHDEV_LOG(ERR, "Invalid dst pool, pool id must be 0-%d\n",
4260 if ((mirror_conf->rule_type & (ETH_MIRROR_VIRTUAL_POOL_UP |
4261 ETH_MIRROR_VIRTUAL_POOL_DOWN)) &&
4262 (mirror_conf->pool_mask == 0)) {
4264 "Invalid mirror pool, pool mask can not be 0\n");
4268 if ((mirror_conf->rule_type & ETH_MIRROR_VLAN) &&
4269 mirror_conf->vlan.vlan_mask == 0) {
4271 "Invalid vlan mask, vlan mask can not be 0\n");
4275 dev = &rte_eth_devices[port_id];
4276 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_set, -ENOTSUP);
4278 return eth_err(port_id, (*dev->dev_ops->mirror_rule_set)(dev,
4279 mirror_conf, rule_id, on));
4283 rte_eth_mirror_rule_reset(uint16_t port_id, uint8_t rule_id)
4285 struct rte_eth_dev *dev;
4287 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4289 dev = &rte_eth_devices[port_id];
4290 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_reset, -ENOTSUP);
4292 return eth_err(port_id, (*dev->dev_ops->mirror_rule_reset)(dev,
4296 RTE_INIT(eth_dev_init_cb_lists)
4300 for (i = 0; i < RTE_MAX_ETHPORTS; i++)
4301 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs);
4305 rte_eth_dev_callback_register(uint16_t port_id,
4306 enum rte_eth_event_type event,
4307 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
4309 struct rte_eth_dev *dev;
4310 struct rte_eth_dev_callback *user_cb;
4317 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
4318 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
4322 if (port_id == RTE_ETH_ALL) {
4324 last_port = RTE_MAX_ETHPORTS - 1;
4326 next_port = last_port = port_id;
4329 rte_spinlock_lock(ð_dev_cb_lock);
4332 dev = &rte_eth_devices[next_port];
4334 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) {
4335 if (user_cb->cb_fn == cb_fn &&
4336 user_cb->cb_arg == cb_arg &&
4337 user_cb->event == event) {
4342 /* create a new callback. */
4343 if (user_cb == NULL) {
4344 user_cb = rte_zmalloc("INTR_USER_CALLBACK",
4345 sizeof(struct rte_eth_dev_callback), 0);
4346 if (user_cb != NULL) {
4347 user_cb->cb_fn = cb_fn;
4348 user_cb->cb_arg = cb_arg;
4349 user_cb->event = event;
4350 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs),
4353 rte_spinlock_unlock(ð_dev_cb_lock);
4354 rte_eth_dev_callback_unregister(port_id, event,
4360 } while (++next_port <= last_port);
4362 rte_spinlock_unlock(ð_dev_cb_lock);
4367 rte_eth_dev_callback_unregister(uint16_t port_id,
4368 enum rte_eth_event_type event,
4369 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
4372 struct rte_eth_dev *dev;
4373 struct rte_eth_dev_callback *cb, *next;
4380 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
4381 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
4385 if (port_id == RTE_ETH_ALL) {
4387 last_port = RTE_MAX_ETHPORTS - 1;
4389 next_port = last_port = port_id;
4392 rte_spinlock_lock(ð_dev_cb_lock);
4395 dev = &rte_eth_devices[next_port];
4397 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL;
4400 next = TAILQ_NEXT(cb, next);
4402 if (cb->cb_fn != cb_fn || cb->event != event ||
4403 (cb_arg != (void *)-1 && cb->cb_arg != cb_arg))
4407 * if this callback is not executing right now,
4410 if (cb->active == 0) {
4411 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next);
4417 } while (++next_port <= last_port);
4419 rte_spinlock_unlock(ð_dev_cb_lock);
4424 rte_eth_dev_callback_process(struct rte_eth_dev *dev,
4425 enum rte_eth_event_type event, void *ret_param)
4427 struct rte_eth_dev_callback *cb_lst;
4428 struct rte_eth_dev_callback dev_cb;
4431 rte_spinlock_lock(ð_dev_cb_lock);
4432 TAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) {
4433 if (cb_lst->cb_fn == NULL || cb_lst->event != event)
4437 if (ret_param != NULL)
4438 dev_cb.ret_param = ret_param;
4440 rte_spinlock_unlock(ð_dev_cb_lock);
4441 rc = dev_cb.cb_fn(dev->data->port_id, dev_cb.event,
4442 dev_cb.cb_arg, dev_cb.ret_param);
4443 rte_spinlock_lock(ð_dev_cb_lock);
4446 rte_spinlock_unlock(ð_dev_cb_lock);
4451 rte_eth_dev_probing_finish(struct rte_eth_dev *dev)
4456 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_NEW, NULL);
4458 dev->state = RTE_ETH_DEV_ATTACHED;
4462 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data)
4465 struct rte_eth_dev *dev;
4466 struct rte_intr_handle *intr_handle;
4470 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4472 dev = &rte_eth_devices[port_id];
4474 if (!dev->intr_handle) {
4475 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4479 intr_handle = dev->intr_handle;
4480 if (!intr_handle->intr_vec) {
4481 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4485 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
4486 vec = intr_handle->intr_vec[qid];
4487 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
4488 if (rc && rc != -EEXIST) {
4490 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
4491 port_id, qid, op, epfd, vec);
4499 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id)
4501 struct rte_intr_handle *intr_handle;
4502 struct rte_eth_dev *dev;
4503 unsigned int efd_idx;
4507 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
4509 dev = &rte_eth_devices[port_id];
4511 if (queue_id >= dev->data->nb_rx_queues) {
4512 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
4516 if (!dev->intr_handle) {
4517 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4521 intr_handle = dev->intr_handle;
4522 if (!intr_handle->intr_vec) {
4523 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4527 vec = intr_handle->intr_vec[queue_id];
4528 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ?
4529 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec;
4530 fd = intr_handle->efds[efd_idx];
4536 eth_dev_dma_mzone_name(char *name, size_t len, uint16_t port_id, uint16_t queue_id,
4537 const char *ring_name)
4539 return snprintf(name, len, "eth_p%d_q%d_%s",
4540 port_id, queue_id, ring_name);
4543 const struct rte_memzone *
4544 rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name,
4545 uint16_t queue_id, size_t size, unsigned align,
4548 char z_name[RTE_MEMZONE_NAMESIZE];
4549 const struct rte_memzone *mz;
4552 rc = eth_dev_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,
4553 queue_id, ring_name);
4554 if (rc >= RTE_MEMZONE_NAMESIZE) {
4555 RTE_ETHDEV_LOG(ERR, "ring name too long\n");
4556 rte_errno = ENAMETOOLONG;
4560 mz = rte_memzone_lookup(z_name);
4562 if ((socket_id != SOCKET_ID_ANY && socket_id != mz->socket_id) ||
4564 ((uintptr_t)mz->addr & (align - 1)) != 0) {
4566 "memzone %s does not justify the requested attributes\n",
4574 return rte_memzone_reserve_aligned(z_name, size, socket_id,
4575 RTE_MEMZONE_IOVA_CONTIG, align);
4579 rte_eth_dma_zone_free(const struct rte_eth_dev *dev, const char *ring_name,
4582 char z_name[RTE_MEMZONE_NAMESIZE];
4583 const struct rte_memzone *mz;
4586 rc = eth_dev_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,
4587 queue_id, ring_name);
4588 if (rc >= RTE_MEMZONE_NAMESIZE) {
4589 RTE_ETHDEV_LOG(ERR, "ring name too long\n");
4590 return -ENAMETOOLONG;
4593 mz = rte_memzone_lookup(z_name);
4595 rc = rte_memzone_free(mz);
4603 rte_eth_dev_create(struct rte_device *device, const char *name,
4604 size_t priv_data_size,
4605 ethdev_bus_specific_init ethdev_bus_specific_init,
4606 void *bus_init_params,
4607 ethdev_init_t ethdev_init, void *init_params)
4609 struct rte_eth_dev *ethdev;
4612 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL);
4614 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
4615 ethdev = rte_eth_dev_allocate(name);
4619 if (priv_data_size) {
4620 ethdev->data->dev_private = rte_zmalloc_socket(
4621 name, priv_data_size, RTE_CACHE_LINE_SIZE,
4624 if (!ethdev->data->dev_private) {
4626 "failed to allocate private data\n");
4632 ethdev = rte_eth_dev_attach_secondary(name);
4635 "secondary process attach failed, ethdev doesn't exist\n");
4640 ethdev->device = device;
4642 if (ethdev_bus_specific_init) {
4643 retval = ethdev_bus_specific_init(ethdev, bus_init_params);
4646 "ethdev bus specific initialisation failed\n");
4651 retval = ethdev_init(ethdev, init_params);
4653 RTE_ETHDEV_LOG(ERR, "ethdev initialisation failed\n");
4657 rte_eth_dev_probing_finish(ethdev);
4662 rte_eth_dev_release_port(ethdev);
4667 rte_eth_dev_destroy(struct rte_eth_dev *ethdev,
4668 ethdev_uninit_t ethdev_uninit)
4672 ethdev = rte_eth_dev_allocated(ethdev->data->name);
4676 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_uninit, -EINVAL);
4678 ret = ethdev_uninit(ethdev);
4682 return rte_eth_dev_release_port(ethdev);
4686 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id,
4687 int epfd, int op, void *data)
4690 struct rte_eth_dev *dev;
4691 struct rte_intr_handle *intr_handle;
4694 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4696 dev = &rte_eth_devices[port_id];
4697 if (queue_id >= dev->data->nb_rx_queues) {
4698 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
4702 if (!dev->intr_handle) {
4703 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
4707 intr_handle = dev->intr_handle;
4708 if (!intr_handle->intr_vec) {
4709 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
4713 vec = intr_handle->intr_vec[queue_id];
4714 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
4715 if (rc && rc != -EEXIST) {
4717 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
4718 port_id, queue_id, op, epfd, vec);
4726 rte_eth_dev_rx_intr_enable(uint16_t port_id,
4729 struct rte_eth_dev *dev;
4732 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4734 dev = &rte_eth_devices[port_id];
4736 ret = eth_dev_validate_rx_queue(dev, queue_id);
4740 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP);
4741 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev,
4746 rte_eth_dev_rx_intr_disable(uint16_t port_id,
4749 struct rte_eth_dev *dev;
4752 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4754 dev = &rte_eth_devices[port_id];
4756 ret = eth_dev_validate_rx_queue(dev, queue_id);
4760 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP);
4761 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev,
4766 const struct rte_eth_rxtx_callback *
4767 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id,
4768 rte_rx_callback_fn fn, void *user_param)
4770 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4771 rte_errno = ENOTSUP;
4774 struct rte_eth_dev *dev;
4776 /* check input parameters */
4777 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4778 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
4782 dev = &rte_eth_devices[port_id];
4783 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
4787 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4795 cb->param = user_param;
4797 rte_spinlock_lock(ð_dev_rx_cb_lock);
4798 /* Add the callbacks in fifo order. */
4799 struct rte_eth_rxtx_callback *tail =
4800 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
4803 /* Stores to cb->fn and cb->param should complete before
4804 * cb is visible to data plane.
4807 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id],
4808 cb, __ATOMIC_RELEASE);
4813 /* Stores to cb->fn and cb->param should complete before
4814 * cb is visible to data plane.
4816 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE);
4818 rte_spinlock_unlock(ð_dev_rx_cb_lock);
4823 const struct rte_eth_rxtx_callback *
4824 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id,
4825 rte_rx_callback_fn fn, void *user_param)
4827 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4828 rte_errno = ENOTSUP;
4831 /* check input parameters */
4832 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4833 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
4838 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4846 cb->param = user_param;
4848 rte_spinlock_lock(ð_dev_rx_cb_lock);
4849 /* Add the callbacks at first position */
4850 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
4851 /* Stores to cb->fn, cb->param and cb->next should complete before
4852 * cb is visible to data plane threads.
4855 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id],
4856 cb, __ATOMIC_RELEASE);
4857 rte_spinlock_unlock(ð_dev_rx_cb_lock);
4862 const struct rte_eth_rxtx_callback *
4863 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id,
4864 rte_tx_callback_fn fn, void *user_param)
4866 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4867 rte_errno = ENOTSUP;
4870 struct rte_eth_dev *dev;
4872 /* check input parameters */
4873 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
4874 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) {
4879 dev = &rte_eth_devices[port_id];
4880 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
4885 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
4893 cb->param = user_param;
4895 rte_spinlock_lock(ð_dev_tx_cb_lock);
4896 /* Add the callbacks in fifo order. */
4897 struct rte_eth_rxtx_callback *tail =
4898 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id];
4901 /* Stores to cb->fn and cb->param should complete before
4902 * cb is visible to data plane.
4905 &rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id],
4906 cb, __ATOMIC_RELEASE);
4911 /* Stores to cb->fn and cb->param should complete before
4912 * cb is visible to data plane.
4914 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE);
4916 rte_spinlock_unlock(ð_dev_tx_cb_lock);
4922 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id,
4923 const struct rte_eth_rxtx_callback *user_cb)
4925 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4928 /* Check input parameters. */
4929 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4930 if (user_cb == NULL ||
4931 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues)
4934 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4935 struct rte_eth_rxtx_callback *cb;
4936 struct rte_eth_rxtx_callback **prev_cb;
4939 rte_spinlock_lock(ð_dev_rx_cb_lock);
4940 prev_cb = &dev->post_rx_burst_cbs[queue_id];
4941 for (; *prev_cb != NULL; prev_cb = &cb->next) {
4943 if (cb == user_cb) {
4944 /* Remove the user cb from the callback list. */
4945 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED);
4950 rte_spinlock_unlock(ð_dev_rx_cb_lock);
4956 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id,
4957 const struct rte_eth_rxtx_callback *user_cb)
4959 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
4962 /* Check input parameters. */
4963 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4964 if (user_cb == NULL ||
4965 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues)
4968 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4970 struct rte_eth_rxtx_callback *cb;
4971 struct rte_eth_rxtx_callback **prev_cb;
4973 rte_spinlock_lock(ð_dev_tx_cb_lock);
4974 prev_cb = &dev->pre_tx_burst_cbs[queue_id];
4975 for (; *prev_cb != NULL; prev_cb = &cb->next) {
4977 if (cb == user_cb) {
4978 /* Remove the user cb from the callback list. */
4979 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED);
4984 rte_spinlock_unlock(ð_dev_tx_cb_lock);
4990 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id,
4991 struct rte_eth_rxq_info *qinfo)
4993 struct rte_eth_dev *dev;
4995 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5000 dev = &rte_eth_devices[port_id];
5001 if (queue_id >= dev->data->nb_rx_queues) {
5002 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
5006 if (dev->data->rx_queues == NULL ||
5007 dev->data->rx_queues[queue_id] == NULL) {
5009 "Rx queue %"PRIu16" of device with port_id=%"
5010 PRIu16" has not been setup\n",
5015 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
5016 RTE_ETHDEV_LOG(INFO,
5017 "Can't get hairpin Rx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
5022 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP);
5024 memset(qinfo, 0, sizeof(*qinfo));
5025 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo);
5030 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id,
5031 struct rte_eth_txq_info *qinfo)
5033 struct rte_eth_dev *dev;
5035 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5040 dev = &rte_eth_devices[port_id];
5041 if (queue_id >= dev->data->nb_tx_queues) {
5042 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
5046 if (dev->data->tx_queues == NULL ||
5047 dev->data->tx_queues[queue_id] == NULL) {
5049 "Tx queue %"PRIu16" of device with port_id=%"
5050 PRIu16" has not been setup\n",
5055 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
5056 RTE_ETHDEV_LOG(INFO,
5057 "Can't get hairpin Tx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
5062 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP);
5064 memset(qinfo, 0, sizeof(*qinfo));
5065 dev->dev_ops->txq_info_get(dev, queue_id, qinfo);
5071 rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
5072 struct rte_eth_burst_mode *mode)
5074 struct rte_eth_dev *dev;
5076 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5081 dev = &rte_eth_devices[port_id];
5083 if (queue_id >= dev->data->nb_rx_queues) {
5084 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
5088 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_burst_mode_get, -ENOTSUP);
5089 memset(mode, 0, sizeof(*mode));
5090 return eth_err(port_id,
5091 dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode));
5095 rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
5096 struct rte_eth_burst_mode *mode)
5098 struct rte_eth_dev *dev;
5100 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5105 dev = &rte_eth_devices[port_id];
5107 if (queue_id >= dev->data->nb_tx_queues) {
5108 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
5112 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_burst_mode_get, -ENOTSUP);
5113 memset(mode, 0, sizeof(*mode));
5114 return eth_err(port_id,
5115 dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode));
5119 rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id,
5120 struct rte_power_monitor_cond *pmc)
5122 struct rte_eth_dev *dev;
5124 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5126 dev = &rte_eth_devices[port_id];
5128 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_monitor_addr, -ENOTSUP);
5130 if (queue_id >= dev->data->nb_rx_queues) {
5131 RTE_ETHDEV_LOG(ERR, "Invalid Rx queue_id=%u\n", queue_id);
5136 RTE_ETHDEV_LOG(ERR, "Invalid power monitor condition=%p\n",
5141 return eth_err(port_id,
5142 dev->dev_ops->get_monitor_addr(dev->data->rx_queues[queue_id],
5147 rte_eth_dev_set_mc_addr_list(uint16_t port_id,
5148 struct rte_ether_addr *mc_addr_set,
5149 uint32_t nb_mc_addr)
5151 struct rte_eth_dev *dev;
5153 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5155 dev = &rte_eth_devices[port_id];
5156 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP);
5157 return eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev,
5158 mc_addr_set, nb_mc_addr));
5162 rte_eth_timesync_enable(uint16_t port_id)
5164 struct rte_eth_dev *dev;
5166 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5167 dev = &rte_eth_devices[port_id];
5169 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP);
5170 return eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev));
5174 rte_eth_timesync_disable(uint16_t port_id)
5176 struct rte_eth_dev *dev;
5178 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5179 dev = &rte_eth_devices[port_id];
5181 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP);
5182 return eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev));
5186 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp,
5189 struct rte_eth_dev *dev;
5191 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5192 dev = &rte_eth_devices[port_id];
5194 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP);
5195 return eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp)
5196 (dev, timestamp, flags));
5200 rte_eth_timesync_read_tx_timestamp(uint16_t port_id,
5201 struct timespec *timestamp)
5203 struct rte_eth_dev *dev;
5205 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5206 dev = &rte_eth_devices[port_id];
5208 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP);
5209 return eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp)
5214 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta)
5216 struct rte_eth_dev *dev;
5218 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5219 dev = &rte_eth_devices[port_id];
5221 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_adjust_time, -ENOTSUP);
5222 return eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev,
5227 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp)
5229 struct rte_eth_dev *dev;
5231 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5232 dev = &rte_eth_devices[port_id];
5234 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_time, -ENOTSUP);
5235 return eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev,
5240 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp)
5242 struct rte_eth_dev *dev;
5244 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5245 dev = &rte_eth_devices[port_id];
5247 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_write_time, -ENOTSUP);
5248 return eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev,
5253 rte_eth_read_clock(uint16_t port_id, uint64_t *clock)
5255 struct rte_eth_dev *dev;
5257 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5258 dev = &rte_eth_devices[port_id];
5260 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->read_clock, -ENOTSUP);
5261 return eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock));
5265 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)
5267 struct rte_eth_dev *dev;
5269 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5271 dev = &rte_eth_devices[port_id];
5272 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP);
5273 return eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info));
5277 rte_eth_dev_get_eeprom_length(uint16_t port_id)
5279 struct rte_eth_dev *dev;
5281 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5283 dev = &rte_eth_devices[port_id];
5284 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP);
5285 return eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev));
5289 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
5291 struct rte_eth_dev *dev;
5293 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5295 dev = &rte_eth_devices[port_id];
5296 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP);
5297 return eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info));
5301 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
5303 struct rte_eth_dev *dev;
5305 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5307 dev = &rte_eth_devices[port_id];
5308 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP);
5309 return eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info));
5313 rte_eth_dev_get_module_info(uint16_t port_id,
5314 struct rte_eth_dev_module_info *modinfo)
5316 struct rte_eth_dev *dev;
5318 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5320 dev = &rte_eth_devices[port_id];
5321 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_info, -ENOTSUP);
5322 return (*dev->dev_ops->get_module_info)(dev, modinfo);
5326 rte_eth_dev_get_module_eeprom(uint16_t port_id,
5327 struct rte_dev_eeprom_info *info)
5329 struct rte_eth_dev *dev;
5331 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5333 dev = &rte_eth_devices[port_id];
5334 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_eeprom, -ENOTSUP);
5335 return (*dev->dev_ops->get_module_eeprom)(dev, info);
5339 rte_eth_dev_get_dcb_info(uint16_t port_id,
5340 struct rte_eth_dcb_info *dcb_info)
5342 struct rte_eth_dev *dev;
5344 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5346 dev = &rte_eth_devices[port_id];
5347 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info));
5349 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_dcb_info, -ENOTSUP);
5350 return eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info));
5354 eth_dev_adjust_nb_desc(uint16_t *nb_desc,
5355 const struct rte_eth_desc_lim *desc_lim)
5357 if (desc_lim->nb_align != 0)
5358 *nb_desc = RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_align);
5360 if (desc_lim->nb_max != 0)
5361 *nb_desc = RTE_MIN(*nb_desc, desc_lim->nb_max);
5363 *nb_desc = RTE_MAX(*nb_desc, desc_lim->nb_min);
5367 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id,
5368 uint16_t *nb_rx_desc,
5369 uint16_t *nb_tx_desc)
5371 struct rte_eth_dev_info dev_info;
5374 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5376 ret = rte_eth_dev_info_get(port_id, &dev_info);
5380 if (nb_rx_desc != NULL)
5381 eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim);
5383 if (nb_tx_desc != NULL)
5384 eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim);
5390 rte_eth_dev_hairpin_capability_get(uint16_t port_id,
5391 struct rte_eth_hairpin_cap *cap)
5393 struct rte_eth_dev *dev;
5395 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5397 dev = &rte_eth_devices[port_id];
5398 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_cap_get, -ENOTSUP);
5399 memset(cap, 0, sizeof(*cap));
5400 return eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap));
5404 rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
5406 if (dev->data->rx_queue_state[queue_id] ==
5407 RTE_ETH_QUEUE_STATE_HAIRPIN)
5413 rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
5415 if (dev->data->tx_queue_state[queue_id] ==
5416 RTE_ETH_QUEUE_STATE_HAIRPIN)
5422 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)
5424 struct rte_eth_dev *dev;
5426 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5431 dev = &rte_eth_devices[port_id];
5433 if (*dev->dev_ops->pool_ops_supported == NULL)
5434 return 1; /* all pools are supported */
5436 return (*dev->dev_ops->pool_ops_supported)(dev, pool);
5440 * A set of values to describe the possible states of a switch domain.
5442 enum rte_eth_switch_domain_state {
5443 RTE_ETH_SWITCH_DOMAIN_UNUSED = 0,
5444 RTE_ETH_SWITCH_DOMAIN_ALLOCATED
5448 * Array of switch domains available for allocation. Array is sized to
5449 * RTE_MAX_ETHPORTS elements as there cannot be more active switch domains than
5450 * ethdev ports in a single process.
5452 static struct rte_eth_dev_switch {
5453 enum rte_eth_switch_domain_state state;
5454 } eth_dev_switch_domains[RTE_MAX_ETHPORTS];
5457 rte_eth_switch_domain_alloc(uint16_t *domain_id)
5461 *domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
5463 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
5464 if (eth_dev_switch_domains[i].state ==
5465 RTE_ETH_SWITCH_DOMAIN_UNUSED) {
5466 eth_dev_switch_domains[i].state =
5467 RTE_ETH_SWITCH_DOMAIN_ALLOCATED;
5477 rte_eth_switch_domain_free(uint16_t domain_id)
5479 if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID ||
5480 domain_id >= RTE_MAX_ETHPORTS)
5483 if (eth_dev_switch_domains[domain_id].state !=
5484 RTE_ETH_SWITCH_DOMAIN_ALLOCATED)
5487 eth_dev_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED;
5493 eth_dev_devargs_tokenise(struct rte_kvargs *arglist, const char *str_in)
5496 struct rte_kvargs_pair *pair;
5499 arglist->str = strdup(str_in);
5500 if (arglist->str == NULL)
5503 letter = arglist->str;
5506 pair = &arglist->pairs[0];
5509 case 0: /* Initial */
5512 else if (*letter == '\0')
5519 case 1: /* Parsing key */
5520 if (*letter == '=') {
5522 pair->value = letter + 1;
5524 } else if (*letter == ',' || *letter == '\0')
5529 case 2: /* Parsing value */
5532 else if (*letter == ',') {
5535 pair = &arglist->pairs[arglist->count];
5537 } else if (*letter == '\0') {
5540 pair = &arglist->pairs[arglist->count];
5545 case 3: /* Parsing list */
5548 else if (*letter == '\0')
5557 rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da)
5559 struct rte_kvargs args;
5560 struct rte_kvargs_pair *pair;
5564 memset(eth_da, 0, sizeof(*eth_da));
5566 result = eth_dev_devargs_tokenise(&args, dargs);
5570 for (i = 0; i < args.count; i++) {
5571 pair = &args.pairs[i];
5572 if (strcmp("representor", pair->key) == 0) {
5573 result = rte_eth_devargs_parse_list(pair->value,
5574 rte_eth_devargs_parse_representor_ports,
5589 eth_dev_handle_port_list(const char *cmd __rte_unused,
5590 const char *params __rte_unused,
5591 struct rte_tel_data *d)
5595 rte_tel_data_start_array(d, RTE_TEL_INT_VAL);
5596 RTE_ETH_FOREACH_DEV(port_id)
5597 rte_tel_data_add_array_int(d, port_id);
5602 eth_dev_add_port_queue_stats(struct rte_tel_data *d, uint64_t *q_stats,
5603 const char *stat_name)
5606 struct rte_tel_data *q_data = rte_tel_data_alloc();
5607 rte_tel_data_start_array(q_data, RTE_TEL_U64_VAL);
5608 for (q = 0; q < RTE_ETHDEV_QUEUE_STAT_CNTRS; q++)
5609 rte_tel_data_add_array_u64(q_data, q_stats[q]);
5610 rte_tel_data_add_dict_container(d, stat_name, q_data, 0);
5613 #define ADD_DICT_STAT(stats, s) rte_tel_data_add_dict_u64(d, #s, stats.s)
5616 eth_dev_handle_port_stats(const char *cmd __rte_unused,
5618 struct rte_tel_data *d)
5620 struct rte_eth_stats stats;
5623 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5626 port_id = atoi(params);
5627 if (!rte_eth_dev_is_valid_port(port_id))
5630 ret = rte_eth_stats_get(port_id, &stats);
5634 rte_tel_data_start_dict(d);
5635 ADD_DICT_STAT(stats, ipackets);
5636 ADD_DICT_STAT(stats, opackets);
5637 ADD_DICT_STAT(stats, ibytes);
5638 ADD_DICT_STAT(stats, obytes);
5639 ADD_DICT_STAT(stats, imissed);
5640 ADD_DICT_STAT(stats, ierrors);
5641 ADD_DICT_STAT(stats, oerrors);
5642 ADD_DICT_STAT(stats, rx_nombuf);
5643 eth_dev_add_port_queue_stats(d, stats.q_ipackets, "q_ipackets");
5644 eth_dev_add_port_queue_stats(d, stats.q_opackets, "q_opackets");
5645 eth_dev_add_port_queue_stats(d, stats.q_ibytes, "q_ibytes");
5646 eth_dev_add_port_queue_stats(d, stats.q_obytes, "q_obytes");
5647 eth_dev_add_port_queue_stats(d, stats.q_errors, "q_errors");
5653 eth_dev_handle_port_xstats(const char *cmd __rte_unused,
5655 struct rte_tel_data *d)
5657 struct rte_eth_xstat *eth_xstats;
5658 struct rte_eth_xstat_name *xstat_names;
5659 int port_id, num_xstats;
5663 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5666 port_id = strtoul(params, &end_param, 0);
5667 if (*end_param != '\0')
5668 RTE_ETHDEV_LOG(NOTICE,
5669 "Extra parameters passed to ethdev telemetry command, ignoring");
5670 if (!rte_eth_dev_is_valid_port(port_id))
5673 num_xstats = rte_eth_xstats_get(port_id, NULL, 0);
5677 /* use one malloc for both names and stats */
5678 eth_xstats = malloc((sizeof(struct rte_eth_xstat) +
5679 sizeof(struct rte_eth_xstat_name)) * num_xstats);
5680 if (eth_xstats == NULL)
5682 xstat_names = (void *)ð_xstats[num_xstats];
5684 ret = rte_eth_xstats_get_names(port_id, xstat_names, num_xstats);
5685 if (ret < 0 || ret > num_xstats) {
5690 ret = rte_eth_xstats_get(port_id, eth_xstats, num_xstats);
5691 if (ret < 0 || ret > num_xstats) {
5696 rte_tel_data_start_dict(d);
5697 for (i = 0; i < num_xstats; i++)
5698 rte_tel_data_add_dict_u64(d, xstat_names[i].name,
5699 eth_xstats[i].value);
5704 eth_dev_handle_port_link_status(const char *cmd __rte_unused,
5706 struct rte_tel_data *d)
5708 static const char *status_str = "status";
5710 struct rte_eth_link link;
5713 if (params == NULL || strlen(params) == 0 || !isdigit(*params))
5716 port_id = strtoul(params, &end_param, 0);
5717 if (*end_param != '\0')
5718 RTE_ETHDEV_LOG(NOTICE,
5719 "Extra parameters passed to ethdev telemetry command, ignoring");
5720 if (!rte_eth_dev_is_valid_port(port_id))
5723 ret = rte_eth_link_get(port_id, &link);
5727 rte_tel_data_start_dict(d);
5728 if (!link.link_status) {
5729 rte_tel_data_add_dict_string(d, status_str, "DOWN");
5732 rte_tel_data_add_dict_string(d, status_str, "UP");
5733 rte_tel_data_add_dict_u64(d, "speed", link.link_speed);
5734 rte_tel_data_add_dict_string(d, "duplex",
5735 (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
5736 "full-duplex" : "half-duplex");
5741 rte_eth_hairpin_queue_peer_update(uint16_t peer_port, uint16_t peer_queue,
5742 struct rte_hairpin_peer_info *cur_info,
5743 struct rte_hairpin_peer_info *peer_info,
5746 struct rte_eth_dev *dev;
5748 /* Current queue information is not mandatory. */
5749 if (peer_info == NULL)
5752 /* No need to check the validity again. */
5753 dev = &rte_eth_devices[peer_port];
5754 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_update,
5757 return (*dev->dev_ops->hairpin_queue_peer_update)(dev, peer_queue,
5758 cur_info, peer_info, direction);
5762 rte_eth_hairpin_queue_peer_bind(uint16_t cur_port, uint16_t cur_queue,
5763 struct rte_hairpin_peer_info *peer_info,
5766 struct rte_eth_dev *dev;
5768 if (peer_info == NULL)
5771 /* No need to check the validity again. */
5772 dev = &rte_eth_devices[cur_port];
5773 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_bind,
5776 return (*dev->dev_ops->hairpin_queue_peer_bind)(dev, cur_queue,
5777 peer_info, direction);
5781 rte_eth_hairpin_queue_peer_unbind(uint16_t cur_port, uint16_t cur_queue,
5784 struct rte_eth_dev *dev;
5786 /* No need to check the validity again. */
5787 dev = &rte_eth_devices[cur_port];
5788 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_unbind,
5791 return (*dev->dev_ops->hairpin_queue_peer_unbind)(dev, cur_queue,
5795 RTE_LOG_REGISTER(rte_eth_dev_logtype, lib.ethdev, INFO);
5797 RTE_INIT(ethdev_init_telemetry)
5799 rte_telemetry_register_cmd("/ethdev/list", eth_dev_handle_port_list,
5800 "Returns list of available ethdev ports. Takes no parameters");
5801 rte_telemetry_register_cmd("/ethdev/stats", eth_dev_handle_port_stats,
5802 "Returns the common stats for a port. Parameters: int port_id");
5803 rte_telemetry_register_cmd("/ethdev/xstats", eth_dev_handle_port_xstats,
5804 "Returns the extended stats for a port. Parameters: int port_id");
5805 rte_telemetry_register_cmd("/ethdev/link_status",
5806 eth_dev_handle_port_link_status,
5807 "Returns the link status for a port. Parameters: int port_id");