lib/librte_pmd_e1000/e1000/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  */
  41
  42 #include "e1000_api.h"
  43
  44 static s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  45 static s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  46 static s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  47 static void e1000_release_phy_82575(struct e1000_hw *hw);
  48 static s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  49 static void e1000_release_nvm_82575(struct e1000_hw *hw);
  50 static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  51 static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  52 static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  53                                          u16 *duplex);
  54 static s32  e1000_init_hw_82575(struct e1000_hw *hw);
  55 static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  56 static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  57                                            u16 *data);
  58 static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  59 static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  60 static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  61                                     u32 offset, u16 *data);
  62 static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  63                                      u32 offset, u16 data);
  64 static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  65                                           bool active);
  66 static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  67                                           bool active);
  68 static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  69                                           bool active);
  70 static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  71 static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  72 static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  73 static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  74                                             u32 offset, u16 data);
  75 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  76 static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  77 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  78                                                  u16 *speed, u16 *duplex);
  79 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  80 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  81 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  82 static s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  83 static s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  84 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  85 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  86 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  87 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  88 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  89 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  90 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  91 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  92 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  93                                                 u16 offset);
  94 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
  95                                                 u16 offset);
  96 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
  97 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
  98
  99 static const u16 e1000_82580_rxpbs_table[] =
 100         { 36, 72, 144, 1, 2, 4, 8, 16,
 101           35, 70, 140 };
 102 #define E1000_82580_RXPBS_TABLE_SIZE \
 103         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
 104
 105
 106 /**
 107  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 108  *  @hw: pointer to the HW structure
 109  *
 110  *  Called to determine if the I2C pins are being used for I2C or as an
 111  *  external MDIO interface since the two options are mutually exclusive.
 112  **/
 113 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 114 {
 115         u32 reg = 0;
 116         bool ext_mdio = FALSE;
 117
 118         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 119
 120         switch (hw->mac.type) {
 121         case e1000_82575:
 122         case e1000_82576:
 123                 reg = E1000_READ_REG(hw, E1000_MDIC);
 124                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 125                 break;
 126         case e1000_82580:
 127         case e1000_i350:
 128                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 129                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 130                 break;
 131         default:
 132                 break;
 133         }
 134         return ext_mdio;
 135 }
 136
 137 /**
 138  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 139  *  @hw: pointer to the HW structure
 140  **/
 141 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 142 {
 143         struct e1000_phy_info *phy = &hw->phy;
 144         s32 ret_val = E1000_SUCCESS;
 145         u32 ctrl_ext;
 146
 147         DEBUGFUNC("e1000_init_phy_params_82575");
 148
 149         if (hw->phy.media_type != e1000_media_type_copper) {
 150                 phy->type = e1000_phy_none;
 151                 goto out;
 152         }
 153
 154         phy->ops.power_up   = e1000_power_up_phy_copper;
 155         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 156
 157         phy->autoneg_mask           = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 158         phy->reset_delay_us         = 100;
 159
 160         phy->ops.acquire            = e1000_acquire_phy_82575;
 161         phy->ops.check_reset_block  = e1000_check_reset_block_generic;
 162         phy->ops.commit             = e1000_phy_sw_reset_generic;
 163         phy->ops.get_cfg_done       = e1000_get_cfg_done_82575;
 164         phy->ops.release            = e1000_release_phy_82575;
 165
 166         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 167
 168         if (e1000_sgmii_active_82575(hw)) {
 169                 phy->ops.reset      = e1000_phy_hw_reset_sgmii_82575;
 170                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 171         } else {
 172                 phy->ops.reset      = e1000_phy_hw_reset_generic;
 173                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 174         }
 175
 176         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 177         e1000_reset_mdicnfg_82580(hw);
 178
 179         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 180                 phy->ops.read_reg   = e1000_read_phy_reg_sgmii_82575;
 181                 phy->ops.write_reg  = e1000_write_phy_reg_sgmii_82575;
 182         } else if (hw->mac.type >= e1000_82580) {
 183                 phy->ops.read_reg   = e1000_read_phy_reg_82580;
 184                 phy->ops.write_reg  = e1000_write_phy_reg_82580;
 185         } else {
 186                 phy->ops.read_reg   = e1000_read_phy_reg_igp;
 187                 phy->ops.write_reg  = e1000_write_phy_reg_igp;
 188         }
 189
 190         /* Set phy->phy_addr and phy->id. */
 191         ret_val = e1000_get_phy_id_82575(hw);
 192
 193         /* Verify phy id and set remaining function pointers */
 194         switch (phy->id) {
 195         case I347AT4_E_PHY_ID:
 196         case M88E1112_E_PHY_ID:
 197         case M88E1340M_E_PHY_ID:
 198         case M88E1111_I_PHY_ID:
 199                 phy->type                   = e1000_phy_m88;
 200                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 201                 phy->ops.get_info           = e1000_get_phy_info_m88;
 202                 if (phy->id == I347AT4_E_PHY_ID ||
 203                     phy->id == M88E1112_E_PHY_ID ||
 204                     phy->id == M88E1340M_E_PHY_ID)
 205                         phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 206                 else
 207                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 208                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 209                 break;
 210         case IGP03E1000_E_PHY_ID:
 211         case IGP04E1000_E_PHY_ID:
 212                 phy->type                   = e1000_phy_igp_3;
 213                 phy->ops.check_polarity     = e1000_check_polarity_igp;
 214                 phy->ops.get_info           = e1000_get_phy_info_igp;
 215                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 216                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 217                 phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82575;
 218                 phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
 219                 break;
 220         case I82580_I_PHY_ID:
 221         case I350_I_PHY_ID:
 222                 phy->type                   = e1000_phy_82580;
 223                 phy->ops.check_polarity     = e1000_check_polarity_82577;
 224                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
 225                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 226                 phy->ops.get_info           = e1000_get_phy_info_82577;
 227                 phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82580;
 228                 phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_82580;
 229                 break;
 230         default:
 231                 ret_val = -E1000_ERR_PHY;
 232                 goto out;
 233         }
 234
 235 out:
 236         return ret_val;
 237 }
 238
 239 /**
 240  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 241  *  @hw: pointer to the HW structure
 242  **/
 243 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 244 {
 245         struct e1000_nvm_info *nvm = &hw->nvm;
 246         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 247         u16 size;
 248
 249         DEBUGFUNC("e1000_init_nvm_params_82575");
 250
 251         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 252                      E1000_EECD_SIZE_EX_SHIFT);
 253         /*
 254          * Added to a constant, "size" becomes the left-shift value
 255          * for setting word_size.
 256          */
 257         size += NVM_WORD_SIZE_BASE_SHIFT;
 258
 259         nvm->word_size = 1 << size;
 260         nvm->opcode_bits        = 8;
 261         nvm->delay_usec         = 1;
 262         switch (nvm->override) {
 263         case e1000_nvm_override_spi_large:
 264                 nvm->page_size    = 32;
 265                 nvm->address_bits = 16;
 266                 break;
 267         case e1000_nvm_override_spi_small:
 268                 nvm->page_size    = 8;
 269                 nvm->address_bits = 8;
 270                 break;
 271         default:
 272                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 273                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 274                 break;
 275         }
 276
 277         nvm->type = e1000_nvm_eeprom_spi;
 278
 279         if (nvm->word_size == (1 << 15))
 280                 nvm->page_size = 128;
 281
 282         /* Function Pointers */
 283         nvm->ops.acquire    = e1000_acquire_nvm_82575;
 284         nvm->ops.release    = e1000_release_nvm_82575;
 285         if (nvm->word_size < (1 << 15))
 286                 nvm->ops.read    = e1000_read_nvm_eerd;
 287         else
 288                 nvm->ops.read    = e1000_read_nvm_spi;
 289
 290         nvm->ops.write              = e1000_write_nvm_spi;
 291         nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
 292         nvm->ops.update             = e1000_update_nvm_checksum_generic;
 293         nvm->ops.valid_led_default  = e1000_valid_led_default_82575;
 294
 295         /* override genric family function pointers for specific descendants */
 296         switch (hw->mac.type) {
 297         case e1000_82580:
 298                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 299                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 300                 break;
 301         case e1000_i350:
 302                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 303                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 304                 break;
 305         default:
 306                 break;
 307         }
 308
 309         return E1000_SUCCESS;
 310 }
 311
 312 /**
 313  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 314  *  @hw: pointer to the HW structure
 315  **/
 316 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 317 {
 318         struct e1000_mac_info *mac = &hw->mac;
 319         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 320         u32 ctrl_ext = 0;
 321
 322         DEBUGFUNC("e1000_init_mac_params_82575");
 323
 324         /* Set media type */
 325         /*
 326          * The 82575 uses bits 22:23 for link mode. The mode can be changed
 327          * based on the EEPROM. We cannot rely upon device ID. There
 328          * is no distinguishable difference between fiber and internal
 329          * SerDes mode on the 82575. There can be an external PHY attached
 330          * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
 331          */
 332         hw->phy.media_type = e1000_media_type_copper;
 333         dev_spec->sgmii_active = FALSE;
 334
 335         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 336         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
 337         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 338                 dev_spec->sgmii_active = TRUE;
 339                 break;
 340         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 341         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 342                 hw->phy.media_type = e1000_media_type_internal_serdes;
 343                 break;
 344         default:
 345                 break;
 346         }
 347
 348         /* Set mta register count */
 349         mac->mta_reg_count = 128;
 350         /* Set uta register count */
 351         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 352         /* Set rar entry count */
 353         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 354         if (mac->type == e1000_82576)
 355                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 356         if (mac->type == e1000_82580)
 357                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 358         if (mac->type == e1000_i350) {
 359                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 360                 /* Enable EEE default settings for i350 */
 361                 dev_spec->eee_disable = FALSE;
 362         }
 363
 364         /* Set if part includes ASF firmware */
 365         mac->asf_firmware_present = TRUE;
 366         /* FWSM register */
 367         mac->has_fwsm = TRUE;
 368         /* ARC supported; valid only if manageability features are enabled. */
 369         mac->arc_subsystem_valid =
 370                 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 371                         ? TRUE : FALSE;
 372
 373         /* Function pointers */
 374
 375         /* bus type/speed/width */
 376         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 377         /* reset */
 378         if (mac->type >= e1000_82580)
 379                 mac->ops.reset_hw = e1000_reset_hw_82580;
 380         else
 381         mac->ops.reset_hw = e1000_reset_hw_82575;
 382         /* hw initialization */
 383         mac->ops.init_hw = e1000_init_hw_82575;
 384         /* link setup */
 385         mac->ops.setup_link = e1000_setup_link_generic;
 386         /* physical interface link setup */
 387         mac->ops.setup_physical_interface =
 388                 (hw->phy.media_type == e1000_media_type_copper)
 389                         ? e1000_setup_copper_link_82575
 390                         : e1000_setup_serdes_link_82575;
 391         /* physical interface shutdown */
 392         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 393         /* physical interface power up */
 394         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 395         /* check for link */
 396         mac->ops.check_for_link = e1000_check_for_link_82575;
 397         /* receive address register setting */
 398         mac->ops.rar_set = e1000_rar_set_generic;
 399         /* read mac address */
 400         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 401         /* configure collision distance */
 402         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 403         /* multicast address update */
 404         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 405         /* writing VFTA */
 406         mac->ops.write_vfta = e1000_write_vfta_generic;
 407         /* clearing VFTA */
 408         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 409         /* ID LED init */
 410         mac->ops.id_led_init = e1000_id_led_init_generic;
 411         /* blink LED */
 412         mac->ops.blink_led = e1000_blink_led_generic;
 413         /* setup LED */
 414         mac->ops.setup_led = e1000_setup_led_generic;
 415         /* cleanup LED */
 416         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 417         /* turn on/off LED */
 418         mac->ops.led_on = e1000_led_on_generic;
 419         mac->ops.led_off = e1000_led_off_generic;
 420         /* clear hardware counters */
 421         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 422         /* link info */
 423         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 424
 425         /* set lan id for port to determine which phy lock to use */
 426         hw->mac.ops.set_lan_id(hw);
 427
 428         return E1000_SUCCESS;
 429 }
 430
 431 /**
 432  *  e1000_init_function_pointers_82575 - Init func ptrs.
 433  *  @hw: pointer to the HW structure
 434  *
 435  *  Called to initialize all function pointers and parameters.
 436  **/
 437 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 438 {
 439         DEBUGFUNC("e1000_init_function_pointers_82575");
 440
 441         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 442         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 443         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 444         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 445 }
 446
 447 /**
 448  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 449  *  @hw: pointer to the HW structure
 450  *
 451  *  Acquire access rights to the correct PHY.
 452  **/
 453 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 454 {
 455         u16 mask = E1000_SWFW_PHY0_SM;
 456
 457         DEBUGFUNC("e1000_acquire_phy_82575");
 458
 459         if (hw->bus.func == E1000_FUNC_1)
 460                 mask = E1000_SWFW_PHY1_SM;
 461         else if (hw->bus.func == E1000_FUNC_2)
 462                 mask = E1000_SWFW_PHY2_SM;
 463         else if (hw->bus.func == E1000_FUNC_3)
 464                 mask = E1000_SWFW_PHY3_SM;
 465
 466         return e1000_acquire_swfw_sync_82575(hw, mask);
 467 }
 468
 469 /**
 470  *  e1000_release_phy_82575 - Release rights to access PHY
 471  *  @hw: pointer to the HW structure
 472  *
 473  *  A wrapper to release access rights to the correct PHY.
 474  **/
 475 static void e1000_release_phy_82575(struct e1000_hw *hw)
 476 {
 477         u16 mask = E1000_SWFW_PHY0_SM;
 478
 479         DEBUGFUNC("e1000_release_phy_82575");
 480
 481         if (hw->bus.func == E1000_FUNC_1)
 482                 mask = E1000_SWFW_PHY1_SM;
 483         else if (hw->bus.func == E1000_FUNC_2)
 484                 mask = E1000_SWFW_PHY2_SM;
 485         else if (hw->bus.func == E1000_FUNC_3)
 486                 mask = E1000_SWFW_PHY3_SM;
 487
 488         e1000_release_swfw_sync_82575(hw, mask);
 489 }
 490
 491 /**
 492  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 493  *  @hw: pointer to the HW structure
 494  *  @offset: register offset to be read
 495  *  @data: pointer to the read data
 496  *
 497  *  Reads the PHY register at offset using the serial gigabit media independent
 498  *  interface and stores the retrieved information in data.
 499  **/
 500 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 501                                           u16 *data)
 502 {
 503         s32 ret_val = -E1000_ERR_PARAM;
 504
 505         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 506
 507         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 508                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 509                 goto out;
 510         }
 511
 512         ret_val = hw->phy.ops.acquire(hw);
 513         if (ret_val)
 514                 goto out;
 515
 516         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 517
 518         hw->phy.ops.release(hw);
 519
 520 out:
 521         return ret_val;
 522 }
 523
 524 /**
 525  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 526  *  @hw: pointer to the HW structure
 527  *  @offset: register offset to write to
 528  *  @data: data to write at register offset
 529  *
 530  *  Writes the data to PHY register at the offset using the serial gigabit
 531  *  media independent interface.
 532  **/
 533 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 534                                            u16 data)
 535 {
 536         s32 ret_val = -E1000_ERR_PARAM;
 537
 538         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 539
 540         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 541                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 542                 goto out;
 543         }
 544
 545         ret_val = hw->phy.ops.acquire(hw);
 546         if (ret_val)
 547                 goto out;
 548
 549         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 550
 551         hw->phy.ops.release(hw);
 552
 553 out:
 554         return ret_val;
 555 }
 556
 557 /**
 558  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 559  *  @hw: pointer to the HW structure
 560  *
 561  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 562  *  sgmi interface.
 563  **/
 564 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 565 {
 566         struct e1000_phy_info *phy = &hw->phy;
 567         s32  ret_val = E1000_SUCCESS;
 568         u16 phy_id;
 569         u32 ctrl_ext;
 570         u32 mdic;
 571
 572         DEBUGFUNC("e1000_get_phy_id_82575");
 573
 574         /*
 575          * For SGMII PHYs, we try the list of possible addresses until
 576          * we find one that works.  For non-SGMII PHYs
 577          * (e.g. integrated copper PHYs), an address of 1 should
 578          * work.  The result of this function should mean phy->phy_addr
 579          * and phy->id are set correctly.
 580          */
 581         if (!e1000_sgmii_active_82575(hw)) {
 582                 phy->addr = 1;
 583                 ret_val = e1000_get_phy_id(hw);
 584                 goto out;
 585         }
 586
 587         if (e1000_sgmii_uses_mdio_82575(hw)) {
 588                 switch (hw->mac.type) {
 589                 case e1000_82575:
 590                 case e1000_82576:
 591                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 592                         mdic &= E1000_MDIC_PHY_MASK;
 593                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 594                         break;
 595                 case e1000_82580:
 596                 case e1000_i350:
 597                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 598                         mdic &= E1000_MDICNFG_PHY_MASK;
 599                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 600                         break;
 601                 default:
 602                         ret_val = -E1000_ERR_PHY;
 603                         goto out;
 604                         break;
 605                 }
 606                 ret_val = e1000_get_phy_id(hw);
 607                 goto out;
 608         }
 609
 610         /* Power on sgmii phy if it is disabled */
 611         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 612         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 613                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 614         E1000_WRITE_FLUSH(hw);
 615         msec_delay(300);
 616
 617         /*
 618          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 619          * Therefore, we need to test 1-7
 620          */
 621         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 622                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 623                 if (ret_val == E1000_SUCCESS) {
 624                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 625                                   phy_id,
 626                                   phy->addr);
 627                         /*
 628                          * At the time of this writing, The M88 part is
 629                          * the only supported SGMII PHY product.
 630                          */
 631                         if (phy_id == M88_VENDOR)
 632                                 break;
 633                 } else {
 634                         DEBUGOUT1("PHY address %u was unreadable\n",
 635                                   phy->addr);
 636                 }
 637         }
 638
 639         /* A valid PHY type couldn't be found. */
 640         if (phy->addr == 8) {
 641                 phy->addr = 0;
 642                 ret_val = -E1000_ERR_PHY;
 643         } else {
 644                 ret_val = e1000_get_phy_id(hw);
 645         }
 646
 647         /* restore previous sfp cage power state */
 648         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 649
 650 out:
 651         return ret_val;
 652 }
 653
 654 /**
 655  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 656  *  @hw: pointer to the HW structure
 657  *
 658  *  Resets the PHY using the serial gigabit media independent interface.
 659  **/
 660 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 661 {
 662         s32 ret_val = E1000_SUCCESS;
 663
 664         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 665
 666         /*
 667          * This isn't a TRUE "hard" reset, but is the only reset
 668          * available to us at this time.
 669          */
 670
 671         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 672
 673         if (!(hw->phy.ops.write_reg))
 674                 goto out;
 675
 676         /*
 677          * SFP documentation requires the following to configure the SPF module
 678          * to work on SGMII.  No further documentation is given.
 679          */
 680         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 681         if (ret_val)
 682                 goto out;
 683
 684         ret_val = hw->phy.ops.commit(hw);
 685
 686 out:
 687         return ret_val;
 688 }
 689
 690 /**
 691  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 692  *  @hw: pointer to the HW structure
 693  *  @active: TRUE to enable LPLU, FALSE to disable
 694  *
 695  *  Sets the LPLU D0 state according to the active flag.  When
 696  *  activating LPLU this function also disables smart speed
 697  *  and vice versa.  LPLU will not be activated unless the
 698  *  device autonegotiation advertisement meets standards of
 699  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 700  *  This is a function pointer entry point only called by
 701  *  PHY setup routines.
 702  **/
 703 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 704 {
 705         struct e1000_phy_info *phy = &hw->phy;
 706         s32 ret_val = E1000_SUCCESS;
 707         u16 data;
 708
 709         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 710
 711         if (!(hw->phy.ops.read_reg))
 712                 goto out;
 713
 714         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 715         if (ret_val)
 716                 goto out;
 717
 718         if (active) {
 719                 data |= IGP02E1000_PM_D0_LPLU;
 720                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 721                                              data);
 722                 if (ret_val)
 723                         goto out;
 724
 725                 /* When LPLU is enabled, we should disable SmartSpeed */
 726                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 727                                             &data);
 728                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 729                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 730                                              data);
 731                 if (ret_val)
 732                         goto out;
 733         } else {
 734                 data &= ~IGP02E1000_PM_D0_LPLU;
 735                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 736                                              data);
 737                 /*
 738                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 739                  * during Dx states where the power conservation is most
 740                  * important.  During driver activity we should enable
 741                  * SmartSpeed, so performance is maintained.
 742                  */
 743                 if (phy->smart_speed == e1000_smart_speed_on) {
 744                         ret_val = phy->ops.read_reg(hw,
 745                                                     IGP01E1000_PHY_PORT_CONFIG,
 746                                                     &data);
 747                         if (ret_val)
 748                                 goto out;
 749
 750                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 751                         ret_val = phy->ops.write_reg(hw,
 752                                                      IGP01E1000_PHY_PORT_CONFIG,
 753                                                      data);
 754                         if (ret_val)
 755                                 goto out;
 756                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 757                         ret_val = phy->ops.read_reg(hw,
 758                                                     IGP01E1000_PHY_PORT_CONFIG,
 759                                                     &data);
 760                         if (ret_val)
 761                                 goto out;
 762
 763                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 764                         ret_val = phy->ops.write_reg(hw,
 765                                                      IGP01E1000_PHY_PORT_CONFIG,
 766                                                      data);
 767                         if (ret_val)
 768                                 goto out;
 769                 }
 770         }
 771
 772 out:
 773         return ret_val;
 774 }
 775
 776 /**
 777  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 778  *  @hw: pointer to the HW structure
 779  *  @active: TRUE to enable LPLU, FALSE to disable
 780  *
 781  *  Sets the LPLU D0 state according to the active flag.  When
 782  *  activating LPLU this function also disables smart speed
 783  *  and vice versa.  LPLU will not be activated unless the
 784  *  device autonegotiation advertisement meets standards of
 785  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 786  *  This is a function pointer entry point only called by
 787  *  PHY setup routines.
 788  **/
 789 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 790 {
 791         struct e1000_phy_info *phy = &hw->phy;
 792         s32 ret_val = E1000_SUCCESS;
 793         u16 data;
 794
 795         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 796
 797         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 798
 799         if (active) {
 800                 data |= E1000_82580_PM_D0_LPLU;
 801
 802                 /* When LPLU is enabled, we should disable SmartSpeed */
 803                 data &= ~E1000_82580_PM_SPD;
 804         } else {
 805                 data &= ~E1000_82580_PM_D0_LPLU;
 806
 807                 /*
 808                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 809                  * during Dx states where the power conservation is most
 810                  * important.  During driver activity we should enable
 811                  * SmartSpeed, so performance is maintained.
 812                  */
 813                 if (phy->smart_speed == e1000_smart_speed_on) {
 814                         data |= E1000_82580_PM_SPD;
 815                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 816                         data &= ~E1000_82580_PM_SPD;
 817                 }
 818         }
 819
 820         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 821         return ret_val;
 822 }
 823
 824 /**
 825  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 826  *  @hw: pointer to the HW structure
 827  *  @active: boolean used to enable/disable lplu
 828  *
 829  *  Success returns 0, Failure returns 1
 830  *
 831  *  The low power link up (lplu) state is set to the power management level D3
 832  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
 833  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 834  *  is used during Dx states where the power conservation is most important.
 835  *  During driver activity, SmartSpeed should be enabled so performance is
 836  *  maintained.
 837  **/
 838 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 839 {
 840         struct e1000_phy_info *phy = &hw->phy;
 841         s32 ret_val = E1000_SUCCESS;
 842         u16 data;
 843
 844         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 845
 846         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 847
 848         if (!active) {
 849                 data &= ~E1000_82580_PM_D3_LPLU;
 850                 /*
 851                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 852                  * during Dx states where the power conservation is most
 853                  * important.  During driver activity we should enable
 854                  * SmartSpeed, so performance is maintained.
 855                  */
 856                 if (phy->smart_speed == e1000_smart_speed_on) {
 857                         data |= E1000_82580_PM_SPD;
 858                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 859                         data &= ~E1000_82580_PM_SPD;
 860                 }
 861         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 862                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 863                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 864                 data |= E1000_82580_PM_D3_LPLU;
 865                 /* When LPLU is enabled, we should disable SmartSpeed */
 866                 data &= ~E1000_82580_PM_SPD;
 867         }
 868
 869         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 870         return ret_val;
 871 }
 872
 873 /**
 874  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 875  *  @hw: pointer to the HW structure
 876  *
 877  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 878  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 879  *  Return successful if access grant bit set, else clear the request for
 880  *  EEPROM access and return -E1000_ERR_NVM (-1).
 881  **/
 882 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 883 {
 884         s32 ret_val;
 885
 886         DEBUGFUNC("e1000_acquire_nvm_82575");
 887
 888         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 889         if (ret_val)
 890                 goto out;
 891
 892         /*
 893          * Check if there is some access
 894          * error this access may hook on
 895          */
 896         if (hw->mac.type == e1000_i350) {
 897                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 898                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 899                     E1000_EECD_TIMEOUT)) {
 900                         /* Clear all access error flags */
 901                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 902                                         E1000_EECD_ERROR_CLR);
 903                         DEBUGOUT("Nvm bit banging access error"
 904                                 " detected and cleared.\n");
 905                 }
 906         }
 907         if (hw->mac.type == e1000_82580) {
 908                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 909                 if (eecd & E1000_EECD_BLOCKED) {
 910                         /* Clear access error flag */
 911                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 912                                         E1000_EECD_BLOCKED);
 913                         DEBUGOUT("Nvm bit banging access"
 914                                 " error detected and cleared.\n");
 915                 }
 916         }
 917
 918         ret_val = e1000_acquire_nvm_generic(hw);
 919         if (ret_val)
 920                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 921
 922 out:
 923         return ret_val;
 924 }
 925
 926 /**
 927  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
 928  *  @hw: pointer to the HW structure
 929  *
 930  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
 931  *  then release the semaphores acquired.
 932  **/
 933 static void e1000_release_nvm_82575(struct e1000_hw *hw)
 934 {
 935         DEBUGFUNC("e1000_release_nvm_82575");
 936
 937         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 938 }
 939
 940 /**
 941  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
 942  *  @hw: pointer to the HW structure
 943  *  @mask: specifies which semaphore to acquire
 944  *
 945  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 946  *  will also specify which port we're acquiring the lock for.
 947  **/
 948 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 949 {
 950         u32 swfw_sync;
 951         u32 swmask = mask;
 952         u32 fwmask = mask << 16;
 953         s32 ret_val = E1000_SUCCESS;
 954         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
 955
 956         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
 957
 958         while (i < timeout) {
 959                 if (e1000_get_hw_semaphore_generic(hw)) {
 960                         ret_val = -E1000_ERR_SWFW_SYNC;
 961                         goto out;
 962                 }
 963
 964                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 965                 if (!(swfw_sync & (fwmask | swmask)))
 966                         break;
 967
 968                 /*
 969                  * Firmware currently using resource (fwmask)
 970                  * or other software thread using resource (swmask)
 971                  */
 972                 e1000_put_hw_semaphore_generic(hw);
 973                 msec_delay_irq(5);
 974                 i++;
 975         }
 976
 977         if (i == timeout) {
 978                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
 979                 ret_val = -E1000_ERR_SWFW_SYNC;
 980                 goto out;
 981         }
 982
 983         swfw_sync |= swmask;
 984         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 985
 986         e1000_put_hw_semaphore_generic(hw);
 987
 988 out:
 989         return ret_val;
 990 }
 991
 992 /**
 993  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
 994  *  @hw: pointer to the HW structure
 995  *  @mask: specifies which semaphore to acquire
 996  *
 997  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 998  *  will also specify which port we're releasing the lock for.
 999  **/
1000 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1001 {
1002         u32 swfw_sync;
1003
1004         DEBUGFUNC("e1000_release_swfw_sync_82575");
1005
1006         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
1007         /* Empty */
1008
1009         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1010         swfw_sync &= ~mask;
1011         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1012
1013         e1000_put_hw_semaphore_generic(hw);
1014 }
1015
1016 /**
1017  *  e1000_get_cfg_done_82575 - Read config done bit
1018  *  @hw: pointer to the HW structure
1019  *
1020  *  Read the management control register for the config done bit for
1021  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1022  *  to read the config done bit, so an error is *ONLY* logged and returns
1023  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1024  *  would not be able to be reset or change link.
1025  **/
1026 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1027 {
1028         s32 timeout = PHY_CFG_TIMEOUT;
1029         s32 ret_val = E1000_SUCCESS;
1030         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1031
1032         DEBUGFUNC("e1000_get_cfg_done_82575");
1033
1034         if (hw->bus.func == E1000_FUNC_1)
1035                 mask = E1000_NVM_CFG_DONE_PORT_1;
1036         else if (hw->bus.func == E1000_FUNC_2)
1037                 mask = E1000_NVM_CFG_DONE_PORT_2;
1038         else if (hw->bus.func == E1000_FUNC_3)
1039                 mask = E1000_NVM_CFG_DONE_PORT_3;
1040         while (timeout) {
1041                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1042                         break;
1043                 msec_delay(1);
1044                 timeout--;
1045         }
1046         if (!timeout)
1047                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1048
1049         /* If EEPROM is not marked present, init the PHY manually */
1050         if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
1051             (hw->phy.type == e1000_phy_igp_3))
1052                 e1000_phy_init_script_igp3(hw);
1053
1054         return ret_val;
1055 }
1056
1057 /**
1058  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1059  *  @hw: pointer to the HW structure
1060  *  @speed: stores the current speed
1061  *  @duplex: stores the current duplex
1062  *
1063  *  This is a wrapper function, if using the serial gigabit media independent
1064  *  interface, use PCS to retrieve the link speed and duplex information.
1065  *  Otherwise, use the generic function to get the link speed and duplex info.
1066  **/
1067 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1068                                         u16 *duplex)
1069 {
1070         s32 ret_val;
1071
1072         DEBUGFUNC("e1000_get_link_up_info_82575");
1073
1074         if (hw->phy.media_type != e1000_media_type_copper)
1075                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1076                                                                duplex);
1077         else
1078                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1079                                                                     duplex);
1080
1081         return ret_val;
1082 }
1083
1084 /**
1085  *  e1000_check_for_link_82575 - Check for link
1086  *  @hw: pointer to the HW structure
1087  *
1088  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1089  *  use the generic interface for determining link.
1090  **/
1091 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1092 {
1093         s32 ret_val;
1094         u16 speed, duplex;
1095
1096         DEBUGFUNC("e1000_check_for_link_82575");
1097
1098         if (hw->phy.media_type != e1000_media_type_copper) {
1099                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1100                                                                &duplex);
1101                 /*
1102                  * Use this flag to determine if link needs to be checked or
1103                  * not.  If we have link clear the flag so that we do not
1104                  * continue to check for link.
1105                  */
1106                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1107         } else {
1108                 ret_val = e1000_check_for_copper_link_generic(hw);
1109         }
1110
1111         return ret_val;
1112 }
1113
1114 /**
1115  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1116  *  @hw: pointer to the HW structure
1117  **/
1118 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1119 {
1120         u32 reg;
1121
1122         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1123
1124         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1125             !e1000_sgmii_active_82575(hw))
1126                 return;
1127
1128         /* Enable PCS to turn on link */
1129         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1130         reg |= E1000_PCS_CFG_PCS_EN;
1131         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1132
1133         /* Power up the laser */
1134         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1135         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1136         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1137
1138         /* flush the write to verify completion */
1139         E1000_WRITE_FLUSH(hw);
1140         msec_delay(1);
1141 }
1142
1143 /**
1144  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1145  *  @hw: pointer to the HW structure
1146  *  @speed: stores the current speed
1147  *  @duplex: stores the current duplex
1148  *
1149  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1150  *  duplex, then store the values in the pointers provided.
1151  **/
1152 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1153                                                 u16 *speed, u16 *duplex)
1154 {
1155         struct e1000_mac_info *mac = &hw->mac;
1156         u32 pcs;
1157
1158         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1159
1160         /* Set up defaults for the return values of this function */
1161         mac->serdes_has_link = FALSE;
1162         *speed = 0;
1163         *duplex = 0;
1164
1165         /*
1166          * Read the PCS Status register for link state. For non-copper mode,
1167          * the status register is not accurate. The PCS status register is
1168          * used instead.
1169          */
1170         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1171
1172         /*
1173          * The link up bit determines when link is up on autoneg. The sync ok
1174          * gets set once both sides sync up and agree upon link. Stable link
1175          * can be determined by checking for both link up and link sync ok
1176          */
1177         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1178                 mac->serdes_has_link = TRUE;
1179
1180                 /* Detect and store PCS speed */
1181                 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1182                         *speed = SPEED_1000;
1183                 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1184                         *speed = SPEED_100;
1185                 } else {
1186                         *speed = SPEED_10;
1187                 }
1188
1189                 /* Detect and store PCS duplex */
1190                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1191                         *duplex = FULL_DUPLEX;
1192                 } else {
1193                         *duplex = HALF_DUPLEX;
1194                 }
1195         }
1196
1197         return E1000_SUCCESS;
1198 }
1199
1200 /**
1201  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1202  *  @hw: pointer to the HW structure
1203  *
1204  *  In the case of serdes shut down sfp and PCS on driver unload
1205  *  when management pass thru is not enabled.
1206  **/
1207 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1208 {
1209         u32 reg;
1210
1211         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1212
1213         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1214             !e1000_sgmii_active_82575(hw))
1215                 return;
1216
1217         if (!e1000_enable_mng_pass_thru(hw)) {
1218                 /* Disable PCS to turn off link */
1219                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1220                 reg &= ~E1000_PCS_CFG_PCS_EN;
1221                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1222
1223                 /* shutdown the laser */
1224                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1225                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1226                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1227
1228                 /* flush the write to verify completion */
1229                 E1000_WRITE_FLUSH(hw);
1230                 msec_delay(1);
1231         }
1232
1233         return;
1234 }
1235
1236 /**
1237  *  e1000_reset_hw_82575 - Reset hardware
1238  *  @hw: pointer to the HW structure
1239  *
1240  *  This resets the hardware into a known state.
1241  **/
1242 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1243 {
1244         u32 ctrl;
1245         s32 ret_val;
1246
1247         DEBUGFUNC("e1000_reset_hw_82575");
1248
1249         /*
1250          * Prevent the PCI-E bus from sticking if there is no TLP connection
1251          * on the last TLP read/write transaction when MAC is reset.
1252          */
1253         ret_val = e1000_disable_pcie_master_generic(hw);
1254         if (ret_val) {
1255                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1256         }
1257
1258         /* set the completion timeout for interface */
1259         ret_val = e1000_set_pcie_completion_timeout(hw);
1260         if (ret_val) {
1261                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1262         }
1263
1264         DEBUGOUT("Masking off all interrupts\n");
1265         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1266
1267         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1268         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1269         E1000_WRITE_FLUSH(hw);
1270
1271         msec_delay(10);
1272
1273         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1274
1275         DEBUGOUT("Issuing a global reset to MAC\n");
1276         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1277
1278         ret_val = e1000_get_auto_rd_done_generic(hw);
1279         if (ret_val) {
1280                 /*
1281                  * When auto config read does not complete, do not
1282                  * return with an error. This can happen in situations
1283                  * where there is no eeprom and prevents getting link.
1284                  */
1285                 DEBUGOUT("Auto Read Done did not complete\n");
1286         }
1287
1288         /* If EEPROM is not present, run manual init scripts */
1289         if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1290                 e1000_reset_init_script_82575(hw);
1291
1292         /* Clear any pending interrupt events. */
1293         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1294         E1000_READ_REG(hw, E1000_ICR);
1295
1296         /* Install any alternate MAC address into RAR0 */
1297         ret_val = e1000_check_alt_mac_addr_generic(hw);
1298
1299         return ret_val;
1300 }
1301
1302 /**
1303  *  e1000_init_hw_82575 - Initialize hardware
1304  *  @hw: pointer to the HW structure
1305  *
1306  *  This inits the hardware readying it for operation.
1307  **/
1308 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1309 {
1310         struct e1000_mac_info *mac = &hw->mac;
1311         s32 ret_val;
1312         u16 i, rar_count = mac->rar_entry_count;
1313
1314         DEBUGFUNC("e1000_init_hw_82575");
1315
1316         /* Initialize identification LED */
1317         ret_val = mac->ops.id_led_init(hw);
1318         if (ret_val) {
1319                 DEBUGOUT("Error initializing identification LED\n");
1320                 /* This is not fatal and we should not stop init due to this */
1321         }
1322
1323         /* Disabling VLAN filtering */
1324         DEBUGOUT("Initializing the IEEE VLAN\n");
1325         mac->ops.clear_vfta(hw);
1326
1327         /* Setup the receive address */
1328         e1000_init_rx_addrs_generic(hw, rar_count);
1329
1330         /* Zero out the Multicast HASH table */
1331         DEBUGOUT("Zeroing the MTA\n");
1332         for (i = 0; i < mac->mta_reg_count; i++)
1333                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1334
1335         /* Zero out the Unicast HASH table */
1336         DEBUGOUT("Zeroing the UTA\n");
1337         for (i = 0; i < mac->uta_reg_count; i++)
1338                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1339
1340         /* Setup link and flow control */
1341         ret_val = mac->ops.setup_link(hw);
1342
1343         /*
1344          * Clear all of the statistics registers (clear on read).  It is
1345          * important that we do this after we have tried to establish link
1346          * because the symbol error count will increment wildly if there
1347          * is no link.
1348          */
1349         e1000_clear_hw_cntrs_82575(hw);
1350
1351         return ret_val;
1352 }
1353
1354 /**
1355  *  e1000_setup_copper_link_82575 - Configure copper link settings
1356  *  @hw: pointer to the HW structure
1357  *
1358  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1359  *  for link, once link is established calls to configure collision distance
1360  *  and flow control are called.
1361  **/
1362 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1363 {
1364         u32 ctrl;
1365         s32  ret_val;
1366
1367         DEBUGFUNC("e1000_setup_copper_link_82575");
1368
1369         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1370         ctrl |= E1000_CTRL_SLU;
1371         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1372         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1373
1374         ret_val = e1000_setup_serdes_link_82575(hw);
1375         if (ret_val)
1376                 goto out;
1377
1378         if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1379                 /* allow time for SFP cage time to power up phy */
1380                 msec_delay(300);
1381
1382                 ret_val = hw->phy.ops.reset(hw);
1383                 if (ret_val) {
1384                         DEBUGOUT("Error resetting the PHY.\n");
1385                         goto out;
1386                 }
1387         }
1388         switch (hw->phy.type) {
1389         case e1000_phy_m88:
1390                 if (hw->phy.id == I347AT4_E_PHY_ID ||
1391                     hw->phy.id == M88E1112_E_PHY_ID ||
1392                     hw->phy.id == M88E1340M_E_PHY_ID)
1393                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1394                 else
1395                         ret_val = e1000_copper_link_setup_m88(hw);
1396                 break;
1397         case e1000_phy_igp_3:
1398                 ret_val = e1000_copper_link_setup_igp(hw);
1399                 break;
1400         case e1000_phy_82580:
1401                 ret_val = e1000_copper_link_setup_82577(hw);
1402                 break;
1403         default:
1404                 ret_val = -E1000_ERR_PHY;
1405                 break;
1406         }
1407
1408         if (ret_val)
1409                 goto out;
1410
1411         ret_val = e1000_setup_copper_link_generic(hw);
1412 out:
1413         return ret_val;
1414 }
1415
1416 /**
1417  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1418  *  @hw: pointer to the HW structure
1419  *
1420  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1421  *  used on copper connections where the serialized gigabit media independent
1422  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1423  *  for auto-negotiation or forces speed/duplex.
1424  **/
1425 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1426 {
1427         u32 ctrl_ext, ctrl_reg, reg;
1428         bool pcs_autoneg;
1429
1430         DEBUGFUNC("e1000_setup_serdes_link_82575");
1431
1432         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1433             !e1000_sgmii_active_82575(hw))
1434                 return E1000_SUCCESS;
1435
1436         /*
1437          * On the 82575, SerDes loopback mode persists until it is
1438          * explicitly turned off or a power cycle is performed.  A read to
1439          * the register does not indicate its status.  Therefore, we ensure
1440          * loopback mode is disabled during initialization.
1441          */
1442         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1443
1444         /* power on the sfp cage if present */
1445         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1446         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1447         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1448
1449         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1450         ctrl_reg |= E1000_CTRL_SLU;
1451
1452         /* set both sw defined pins on 82575/82576*/
1453         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1454                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1455
1456         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1457
1458         /* default pcs_autoneg to the same setting as mac autoneg */
1459         pcs_autoneg = hw->mac.autoneg;
1460
1461         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1462         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1463                 /* sgmii mode lets the phy handle forcing speed/duplex */
1464                 pcs_autoneg = TRUE;
1465                 /* autoneg time out should be disabled for SGMII mode */
1466                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1467                 break;
1468         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1469                 /* disable PCS autoneg and support parallel detect only */
1470                 pcs_autoneg = FALSE;
1471                 /* fall through to default case */
1472         default:
1473                 /*
1474                  * non-SGMII modes only supports a speed of 1000/Full for the
1475                  * link so it is best to just force the MAC and let the pcs
1476                  * link either autoneg or be forced to 1000/Full
1477                  */
1478                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1479                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1480
1481                 /* set speed of 1000/Full if speed/duplex is forced */
1482                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1483                 break;
1484         }
1485
1486         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1487
1488         /*
1489          * New SerDes mode allows for forcing speed or autonegotiating speed
1490          * at 1gb. Autoneg should be default set by most drivers. This is the
1491          * mode that will be compatible with older link partners and switches.
1492          * However, both are supported by the hardware and some drivers/tools.
1493          */
1494         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1495                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1496
1497         /*
1498          * We force flow control to prevent the CTRL register values from being
1499          * overwritten by the autonegotiated flow control values
1500          */
1501         reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1502
1503         if (pcs_autoneg) {
1504                 /* Set PCS register for autoneg */
1505                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1506                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1507                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1508         } else {
1509                 /* Set PCS register for forced link */
1510                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1511                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1512         }
1513
1514         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1515
1516         if (!e1000_sgmii_active_82575(hw))
1517                 e1000_force_mac_fc_generic(hw);
1518
1519         return E1000_SUCCESS;
1520 }
1521
1522 /**
1523  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1524  *  @hw: pointer to the HW structure
1525  *  @data: pointer to the NVM (EEPROM)
1526  *
1527  *  Read the EEPROM for the current default LED configuration.  If the
1528  *  LED configuration is not valid, set to a valid LED configuration.
1529  **/
1530 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1531 {
1532         s32 ret_val;
1533
1534         DEBUGFUNC("e1000_valid_led_default_82575");
1535
1536         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1537         if (ret_val) {
1538                 DEBUGOUT("NVM Read Error\n");
1539                 goto out;
1540         }
1541
1542         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1543                 switch(hw->phy.media_type) {
1544                 case e1000_media_type_internal_serdes:
1545                         *data = ID_LED_DEFAULT_82575_SERDES;
1546                         break;
1547                 case e1000_media_type_copper:
1548                 default:
1549                         *data = ID_LED_DEFAULT;
1550                         break;
1551                 }
1552         }
1553 out:
1554         return ret_val;
1555 }
1556
1557 /**
1558  *  e1000_sgmii_active_82575 - Return sgmii state
1559  *  @hw: pointer to the HW structure
1560  *
1561  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1562  *  which can be enabled for use in the embedded applications.  Simply
1563  *  return the current state of the sgmii interface.
1564  **/
1565 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1566 {
1567         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1568         return dev_spec->sgmii_active;
1569 }
1570
1571 /**
1572  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1573  *  @hw: pointer to the HW structure
1574  *
1575  *  Inits recommended HW defaults after a reset when there is no EEPROM
1576  *  detected. This is only for the 82575.
1577  **/
1578 static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1579 {
1580         DEBUGFUNC("e1000_reset_init_script_82575");
1581
1582         if (hw->mac.type == e1000_82575) {
1583                 DEBUGOUT("Running reset init script for 82575\n");
1584                 /* SerDes configuration via SERDESCTRL */
1585                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1586                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1587                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1588                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1589
1590                 /* CCM configuration via CCMCTL register */
1591                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1592                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1593
1594                 /* PCIe lanes configuration */
1595                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1596                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1597                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1598                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1599
1600                 /* PCIe PLL Configuration */
1601                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1602                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1603                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1604         }
1605
1606         return E1000_SUCCESS;
1607 }
1608
1609 /**
1610  *  e1000_read_mac_addr_82575 - Read device MAC address
1611  *  @hw: pointer to the HW structure
1612  **/
1613 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1614 {
1615         s32 ret_val = E1000_SUCCESS;
1616
1617         DEBUGFUNC("e1000_read_mac_addr_82575");
1618
1619         /*
1620          * If there's an alternate MAC address place it in RAR0
1621          * so that it will override the Si installed default perm
1622          * address.
1623          */
1624         ret_val = e1000_check_alt_mac_addr_generic(hw);
1625         if (ret_val)
1626                 goto out;
1627
1628         ret_val = e1000_read_mac_addr_generic(hw);
1629
1630 out:
1631         return ret_val;
1632 }
1633
1634 /**
1635  *  e1000_config_collision_dist_82575 - Configure collision distance
1636  *  @hw: pointer to the HW structure
1637  *
1638  *  Configures the collision distance to the default value and is used
1639  *  during link setup.
1640  **/
1641 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1642 {
1643         u32 tctl_ext;
1644
1645         DEBUGFUNC("e1000_config_collision_dist_82575");
1646
1647         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1648
1649         tctl_ext &= ~E1000_TCTL_EXT_COLD;
1650         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1651
1652         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1653         E1000_WRITE_FLUSH(hw);
1654 }
1655
1656 /**
1657  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1658  * @hw: pointer to the HW structure
1659  *
1660  * In the case of a PHY power down to save power, or to turn off link during a
1661  * driver unload, or wake on lan is not enabled, remove the link.
1662  **/
1663 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1664 {
1665         struct e1000_phy_info *phy = &hw->phy;
1666
1667         if (!(phy->ops.check_reset_block))
1668                 return;
1669
1670         /* If the management interface is not enabled, then power down */
1671         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1672                 e1000_power_down_phy_copper(hw);
1673
1674         return;
1675 }
1676
1677 /**
1678  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1679  *  @hw: pointer to the HW structure
1680  *
1681  *  Clears the hardware counters by reading the counter registers.
1682  **/
1683 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1684 {
1685         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1686
1687         e1000_clear_hw_cntrs_base_generic(hw);
1688
1689         E1000_READ_REG(hw, E1000_PRC64);
1690         E1000_READ_REG(hw, E1000_PRC127);
1691         E1000_READ_REG(hw, E1000_PRC255);
1692         E1000_READ_REG(hw, E1000_PRC511);
1693         E1000_READ_REG(hw, E1000_PRC1023);
1694         E1000_READ_REG(hw, E1000_PRC1522);
1695         E1000_READ_REG(hw, E1000_PTC64);
1696         E1000_READ_REG(hw, E1000_PTC127);
1697         E1000_READ_REG(hw, E1000_PTC255);
1698         E1000_READ_REG(hw, E1000_PTC511);
1699         E1000_READ_REG(hw, E1000_PTC1023);
1700         E1000_READ_REG(hw, E1000_PTC1522);
1701
1702         E1000_READ_REG(hw, E1000_ALGNERRC);
1703         E1000_READ_REG(hw, E1000_RXERRC);
1704         E1000_READ_REG(hw, E1000_TNCRS);
1705         E1000_READ_REG(hw, E1000_CEXTERR);
1706         E1000_READ_REG(hw, E1000_TSCTC);
1707         E1000_READ_REG(hw, E1000_TSCTFC);
1708
1709         E1000_READ_REG(hw, E1000_MGTPRC);
1710         E1000_READ_REG(hw, E1000_MGTPDC);
1711         E1000_READ_REG(hw, E1000_MGTPTC);
1712
1713         E1000_READ_REG(hw, E1000_IAC);
1714         E1000_READ_REG(hw, E1000_ICRXOC);
1715
1716         E1000_READ_REG(hw, E1000_ICRXPTC);
1717         E1000_READ_REG(hw, E1000_ICRXATC);
1718         E1000_READ_REG(hw, E1000_ICTXPTC);
1719         E1000_READ_REG(hw, E1000_ICTXATC);
1720         E1000_READ_REG(hw, E1000_ICTXQEC);
1721         E1000_READ_REG(hw, E1000_ICTXQMTC);
1722         E1000_READ_REG(hw, E1000_ICRXDMTC);
1723
1724         E1000_READ_REG(hw, E1000_CBTMPC);
1725         E1000_READ_REG(hw, E1000_HTDPMC);
1726         E1000_READ_REG(hw, E1000_CBRMPC);
1727         E1000_READ_REG(hw, E1000_RPTHC);
1728         E1000_READ_REG(hw, E1000_HGPTC);
1729         E1000_READ_REG(hw, E1000_HTCBDPC);
1730         E1000_READ_REG(hw, E1000_HGORCL);
1731         E1000_READ_REG(hw, E1000_HGORCH);
1732         E1000_READ_REG(hw, E1000_HGOTCL);
1733         E1000_READ_REG(hw, E1000_HGOTCH);
1734         E1000_READ_REG(hw, E1000_LENERRS);
1735
1736         /* This register should not be read in copper configurations */
1737         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1738             e1000_sgmii_active_82575(hw))
1739                 E1000_READ_REG(hw, E1000_SCVPC);
1740 }
1741
1742 /**
1743  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
1744  *  @hw: pointer to the HW structure
1745  *
1746  *  After rx enable if managability is enabled then there is likely some
1747  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
1748  *  function clears the fifos and flushes any packets that came in as rx was
1749  *  being enabled.
1750  **/
1751 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1752 {
1753         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1754         int i, ms_wait;
1755
1756         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1757         if (hw->mac.type != e1000_82575 ||
1758             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1759                 return;
1760
1761         /* Disable all Rx queues */
1762         for (i = 0; i < 4; i++) {
1763                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1764                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1765                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1766         }
1767         /* Poll all queues to verify they have shut down */
1768         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1769                 msec_delay(1);
1770                 rx_enabled = 0;
1771                 for (i = 0; i < 4; i++)
1772                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
1773                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1774                         break;
1775         }
1776
1777         if (ms_wait == 10)
1778                 DEBUGOUT("Queue disable timed out after 10ms\n");
1779
1780         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1781          * incoming packets are rejected.  Set enable and wait 2ms so that
1782          * any packet that was coming in as RCTL.EN was set is flushed
1783          */
1784         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1785         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1786
1787         rlpml = E1000_READ_REG(hw, E1000_RLPML);
1788         E1000_WRITE_REG(hw, E1000_RLPML, 0);
1789
1790         rctl = E1000_READ_REG(hw, E1000_RCTL);
1791         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1792         temp_rctl |= E1000_RCTL_LPE;
1793
1794         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1795         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1796         E1000_WRITE_FLUSH(hw);
1797         msec_delay(2);
1798
1799         /* Enable Rx queues that were previously enabled and restore our
1800          * previous state
1801          */
1802         for (i = 0; i < 4; i++)
1803                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1804         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1805         E1000_WRITE_FLUSH(hw);
1806
1807         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
1808         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1809
1810         /* Flush receive errors generated by workaround */
1811         E1000_READ_REG(hw, E1000_ROC);
1812         E1000_READ_REG(hw, E1000_RNBC);
1813         E1000_READ_REG(hw, E1000_MPC);
1814 }
1815
1816 /**
1817  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
1818  *  @hw: pointer to the HW structure
1819  *
1820  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1821  *  however the hardware default for these parts is 500us to 1ms which is less
1822  *  than the 10ms recommended by the pci-e spec.  To address this we need to
1823  *  increase the value to either 10ms to 200ms for capability version 1 config,
1824  *  or 16ms to 55ms for version 2.
1825  **/
1826 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1827 {
1828         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1829         s32 ret_val = E1000_SUCCESS;
1830         u16 pcie_devctl2;
1831
1832         /* only take action if timeout value is defaulted to 0 */
1833         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1834                 goto out;
1835
1836         /*
1837          * if capababilities version is type 1 we can write the
1838          * timeout of 10ms to 200ms through the GCR register
1839          */
1840         if (!(gcr & E1000_GCR_CAP_VER2)) {
1841                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1842                 goto out;
1843         }
1844
1845         /*
1846          * for version 2 capabilities we need to write the config space
1847          * directly in order to set the completion timeout value for
1848          * 16ms to 55ms
1849          */
1850         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1851                                           &pcie_devctl2);
1852         if (ret_val)
1853                 goto out;
1854
1855         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1856
1857         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1858                                            &pcie_devctl2);
1859 out:
1860         /* disable completion timeout resend */
1861         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1862
1863         E1000_WRITE_REG(hw, E1000_GCR, gcr);
1864         return ret_val;
1865 }
1866
1867 /**
1868  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1869  *  @hw: pointer to the hardware struct
1870  *  @enable: state to enter, either enabled or disabled
1871  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
1872  *
1873  *  enables/disables L2 switch anti-spoofing functionality.
1874  **/
1875 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1876 {
1877         u32 dtxswc;
1878
1879         switch (hw->mac.type) {
1880         case e1000_82576:
1881                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1882                 if (enable) {
1883                         dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1884                                    E1000_DTXSWC_VLAN_SPOOF_MASK);
1885                         /* The PF can spoof - it has to in order to
1886                          * support emulation mode NICs */
1887                         dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1888                 } else {
1889                         dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1890                                     E1000_DTXSWC_VLAN_SPOOF_MASK);
1891                 }
1892                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1893                 break;
1894         case e1000_i350:
1895                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
1896                 if (enable) {
1897                         dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1898                                    E1000_DTXSWC_VLAN_SPOOF_MASK);
1899                         /* The PF can spoof - it has to in order to
1900                          * support emulation mode NICs
1901                          */
1902                         dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1903                 } else {
1904                         dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1905                                     E1000_DTXSWC_VLAN_SPOOF_MASK);
1906                 }
1907                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
1908         default:
1909                 break;
1910         }
1911 }
1912
1913 /**
1914  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
1915  *  @hw: pointer to the hardware struct
1916  *  @enable: state to enter, either enabled or disabled
1917  *
1918  *  enables/disables L2 switch loopback functionality.
1919  **/
1920 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1921 {
1922         u32 dtxswc;
1923
1924         switch (hw->mac.type) {
1925         case e1000_82576:
1926                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1927                 if (enable)
1928                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1929                 else
1930                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1931                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1932                 break;
1933         case e1000_i350:
1934                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
1935                 if (enable)
1936                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1937                 else
1938                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1939                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
1940                 break;
1941         default:
1942                 /* Currently no other hardware supports loopback */
1943                 break;
1944         }
1945
1946
1947 }
1948
1949 /**
1950  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
1951  *  @hw: pointer to the hardware struct
1952  *  @enable: state to enter, either enabled or disabled
1953  *
1954  *  enables/disables replication of packets across multiple pools.
1955  **/
1956 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1957 {
1958         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1959
1960         if (enable)
1961                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1962         else
1963                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1964
1965         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1966 }
1967
1968 /**
1969  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
1970  *  @hw: pointer to the HW structure
1971  *  @offset: register offset to be read
1972  *  @data: pointer to the read data
1973  *
1974  *  Reads the MDI control register in the PHY at offset and stores the
1975  *  information read to data.
1976  **/
1977 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1978 {
1979         s32 ret_val;
1980
1981         DEBUGFUNC("e1000_read_phy_reg_82580");
1982
1983         ret_val = hw->phy.ops.acquire(hw);
1984         if (ret_val)
1985                 goto out;
1986
1987         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
1988
1989         hw->phy.ops.release(hw);
1990
1991 out:
1992         return ret_val;
1993 }
1994
1995 /**
1996  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
1997  *  @hw: pointer to the HW structure
1998  *  @offset: register offset to write to
1999  *  @data: data to write to register at offset
2000  *
2001  *  Writes data to MDI control register in the PHY at offset.
2002  **/
2003 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2004 {
2005         s32 ret_val;
2006
2007         DEBUGFUNC("e1000_write_phy_reg_82580");
2008
2009         ret_val = hw->phy.ops.acquire(hw);
2010         if (ret_val)
2011                 goto out;
2012
2013         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2014
2015         hw->phy.ops.release(hw);
2016
2017 out:
2018         return ret_val;
2019 }
2020
2021 /**
2022  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2023  *  @hw: pointer to the HW structure
2024  *
2025  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2026  *  the values found in the EEPROM.  This addresses an issue in which these
2027  *  bits are not restored from EEPROM after reset.
2028  **/
2029 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2030 {
2031         s32 ret_val = E1000_SUCCESS;
2032         u32 mdicnfg;
2033         u16 nvm_data = 0;
2034
2035         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2036
2037         if (hw->mac.type != e1000_82580)
2038                 goto out;
2039         if (!e1000_sgmii_active_82575(hw))
2040                 goto out;
2041
2042         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2043                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2044                                    &nvm_data);
2045         if (ret_val) {
2046                 DEBUGOUT("NVM Read Error\n");
2047                 goto out;
2048         }
2049
2050         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2051         if (nvm_data & NVM_WORD24_EXT_MDIO)
2052                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2053         if (nvm_data & NVM_WORD24_COM_MDIO)
2054                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2055         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2056 out:
2057         return ret_val;
2058 }
2059
2060 /**
2061  *  e1000_reset_hw_82580 - Reset hardware
2062  *  @hw: pointer to the HW structure
2063  *
2064  *  This resets function or entire device (all ports, etc.)
2065  *  to a known state.
2066  **/
2067 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2068 {
2069         s32 ret_val = E1000_SUCCESS;
2070         /* BH SW mailbox bit in SW_FW_SYNC */
2071         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2072         u32 ctrl;
2073         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2074
2075         DEBUGFUNC("e1000_reset_hw_82580");
2076
2077         hw->dev_spec._82575.global_device_reset = FALSE;
2078
2079         /* Get current control state. */
2080         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2081
2082         /*
2083          * Prevent the PCI-E bus from sticking if there is no TLP connection
2084          * on the last TLP read/write transaction when MAC is reset.
2085          */
2086         ret_val = e1000_disable_pcie_master_generic(hw);
2087         if (ret_val)
2088                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2089
2090         DEBUGOUT("Masking off all interrupts\n");
2091         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2092         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2093         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2094         E1000_WRITE_FLUSH(hw);
2095
2096         msec_delay(10);
2097
2098         /* Determine whether or not a global dev reset is requested */
2099         if (global_device_reset &&
2100                 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
2101                         global_device_reset = FALSE;
2102
2103         if (global_device_reset &&
2104                 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2105                 ctrl |= E1000_CTRL_DEV_RST;
2106         else
2107                 ctrl |= E1000_CTRL_RST;
2108
2109         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2110
2111         /* Add delay to insure DEV_RST has time to complete */
2112         if (global_device_reset)
2113                 msec_delay(5);
2114
2115         ret_val = e1000_get_auto_rd_done_generic(hw);
2116         if (ret_val) {
2117                 /*
2118                  * When auto config read does not complete, do not
2119                  * return with an error. This can happen in situations
2120                  * where there is no eeprom and prevents getting link.
2121                  */
2122                 DEBUGOUT("Auto Read Done did not complete\n");
2123         }
2124
2125         /* If EEPROM is not present, run manual init scripts */
2126         if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
2127                 e1000_reset_init_script_82575(hw);
2128
2129         /* clear global device reset status bit */
2130         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2131
2132         /* Clear any pending interrupt events. */
2133         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2134         E1000_READ_REG(hw, E1000_ICR);
2135
2136         ret_val = e1000_reset_mdicnfg_82580(hw);
2137         if (ret_val)
2138                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2139
2140         /* Install any alternate MAC address into RAR0 */
2141         ret_val = e1000_check_alt_mac_addr_generic(hw);
2142
2143         /* Release semaphore */
2144         if (global_device_reset)
2145                 e1000_release_swfw_sync_82575(hw, swmbsw_mask);
2146
2147         return ret_val;
2148 }
2149
2150 /**
2151  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2152  *  @data: data received by reading RXPBS register
2153  *
2154  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2155  *  This function converts the retrieved value into the correct table value
2156  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2157  *  0x0 36  72 144   1   2   4   8  16
2158  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2159  */
2160 u16 e1000_rxpbs_adjust_82580(u32 data)
2161 {
2162         u16 ret_val = 0;
2163
2164         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2165                 ret_val = e1000_82580_rxpbs_table[data];
2166
2167         return ret_val;
2168 }
2169
2170 /**
2171  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2172  *  checksum
2173  *  @hw: pointer to the HW structure
2174  *  @offset: offset in words of the checksum protected region
2175  *
2176  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2177  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2178  **/
2179 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2180 {
2181         s32 ret_val = E1000_SUCCESS;
2182         u16 checksum = 0;
2183         u16 i, nvm_data;
2184
2185         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2186
2187         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2188                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2189                 if (ret_val) {
2190                         DEBUGOUT("NVM Read Error\n");
2191                         goto out;
2192                 }
2193                 checksum += nvm_data;
2194         }
2195
2196         if (checksum != (u16) NVM_SUM) {
2197                 DEBUGOUT("NVM Checksum Invalid\n");
2198                 ret_val = -E1000_ERR_NVM;
2199                 goto out;
2200         }
2201
2202 out:
2203         return ret_val;
2204 }
2205
2206 /**
2207  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2208  *  checksum
2209  *  @hw: pointer to the HW structure
2210  *  @offset: offset in words of the checksum protected region
2211  *
2212  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2213  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2214  *  value to the EEPROM.
2215  **/
2216 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2217 {
2218         s32 ret_val;
2219         u16 checksum = 0;
2220         u16 i, nvm_data;
2221
2222         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2223
2224         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2225                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2226                 if (ret_val) {
2227                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2228                         goto out;
2229                 }
2230                 checksum += nvm_data;
2231         }
2232         checksum = (u16) NVM_SUM - checksum;
2233         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2234                                 &checksum);
2235         if (ret_val)
2236                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2237
2238 out:
2239         return ret_val;
2240 }
2241
2242 /**
2243  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2244  *  @hw: pointer to the HW structure
2245  *
2246  *  Calculates the EEPROM section checksum by reading/adding each word of
2247  *  the EEPROM and then verifies that the sum of the EEPROM is
2248  *  equal to 0xBABA.
2249  **/
2250 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2251 {
2252         s32 ret_val = E1000_SUCCESS;
2253         u16 eeprom_regions_count = 1;
2254         u16 j, nvm_data;
2255         u16 nvm_offset;
2256
2257         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2258
2259         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2260         if (ret_val) {
2261                 DEBUGOUT("NVM Read Error\n");
2262                 goto out;
2263         }
2264
2265         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2266                 /* if chekcsums compatibility bit is set validate checksums
2267                  * for all 4 ports. */
2268                 eeprom_regions_count = 4;
2269         }
2270
2271         for (j = 0; j < eeprom_regions_count; j++) {
2272                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2273                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2274                                                                 nvm_offset);
2275                 if (ret_val != E1000_SUCCESS)
2276                         goto out;
2277         }
2278
2279 out:
2280         return ret_val;
2281 }
2282
2283 /**
2284  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2285  *  @hw: pointer to the HW structure
2286  *
2287  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2288  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2289  *  checksum and writes the value to the EEPROM.
2290  **/
2291 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2292 {
2293         s32 ret_val;
2294         u16 j, nvm_data;
2295         u16 nvm_offset;
2296
2297         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2298
2299         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2300         if (ret_val) {
2301                 DEBUGOUT("NVM Read Error while updating checksum"
2302                         " compatibility bit.\n");
2303                 goto out;
2304         }
2305
2306         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2307                 /* set compatibility bit to validate checksums appropriately */
2308                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2309                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2310                                         &nvm_data);
2311                 if (ret_val) {
2312                         DEBUGOUT("NVM Write Error while updating checksum"
2313                                 " compatibility bit.\n");
2314                         goto out;
2315                 }
2316         }
2317
2318         for (j = 0; j < 4; j++) {
2319                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2320                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2321                 if (ret_val) {
2322                         goto out;
2323                 }
2324         }
2325
2326 out:
2327         return ret_val;
2328 }
2329
2330 /**
2331  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2332  *  @hw: pointer to the HW structure
2333  *
2334  *  Calculates the EEPROM section checksum by reading/adding each word of
2335  *  the EEPROM and then verifies that the sum of the EEPROM is
2336  *  equal to 0xBABA.
2337  **/
2338 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2339 {
2340         s32 ret_val = E1000_SUCCESS;
2341         u16 j;
2342         u16 nvm_offset;
2343
2344         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2345
2346         for (j = 0; j < 4; j++) {
2347                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2348                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2349                                                                 nvm_offset);
2350                 if (ret_val != E1000_SUCCESS)
2351                         goto out;
2352         }
2353
2354 out:
2355         return ret_val;
2356 }
2357
2358 /**
2359  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2360  *  @hw: pointer to the HW structure
2361  *
2362  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2363  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2364  *  checksum and writes the value to the EEPROM.
2365  **/
2366 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2367 {
2368         s32 ret_val = E1000_SUCCESS;
2369         u16 j;
2370         u16 nvm_offset;
2371
2372         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2373
2374         for (j = 0; j < 4; j++) {
2375                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2376                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2377                 if (ret_val != E1000_SUCCESS)
2378                         goto out;
2379         }
2380
2381 out:
2382         return ret_val;
2383 }
2384
2385 /**
2386  *  e1000_set_eee_i350 - Enable/disable EEE support
2387  *  @hw: pointer to the HW structure
2388  *
2389  *  Enable/disable EEE based on setting in dev_spec structure.
2390  *
2391  **/
2392 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2393 {
2394         s32 ret_val = E1000_SUCCESS;
2395         u32 ipcnfg, eeer, ctrl_ext;
2396
2397         DEBUGFUNC("e1000_set_eee_i350");
2398
2399         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2400         if ((hw->mac.type != e1000_i350) ||
2401             (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2402                 goto out;
2403         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2404         eeer = E1000_READ_REG(hw, E1000_EEER);
2405
2406         /* enable or disable per user setting */
2407         if (!(hw->dev_spec._82575.eee_disable)) {
2408                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2409                            E1000_IPCNFG_EEE_100M_AN);
2410                 eeer |= (E1000_EEER_TX_LPI_EN |
2411                          E1000_EEER_RX_LPI_EN |
2412                          E1000_EEER_LPI_FC);
2413
2414         } else {
2415                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2416                             E1000_IPCNFG_EEE_100M_AN);
2417                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2418                           E1000_EEER_RX_LPI_EN |
2419                           E1000_EEER_LPI_FC);
2420         }
2421         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2422         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2423                         E1000_READ_REG(hw, E1000_IPCNFG);
2424                         E1000_READ_REG(hw, E1000_EEER);
2425 out:
2426
2427         return ret_val;
2428 }