lib/librte_pmd_e1000/e1000/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  56                                          u16 *duplex);
  57 STATIC s32  e1000_init_hw_82575(struct e1000_hw *hw);
  58 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  60                                            u16 *data);
  61 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  62 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  63 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  64                                      u32 offset, u16 *data);
  65 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  66                                       u32 offset, u16 data);
  67 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  68                                           bool active);
  69 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  72                                           bool active);
  73 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  74 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  78 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  79                                             u32 offset, u16 data);
  80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  81 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  82 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  83                                                  u16 *speed, u16 *duplex);
  84 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  86 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  87 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  98                                                  u16 offset);
  99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                    u16 offset);
 101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 105
 106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 117
 118 static const u16 e1000_82580_rxpbs_table[] = {
 119         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 120 #define E1000_82580_RXPBS_TABLE_SIZE \
 121         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
 122
 123
 124 /**
 125  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 126  *  @hw: pointer to the HW structure
 127  *
 128  *  Called to determine if the I2C pins are being used for I2C or as an
 129  *  external MDIO interface since the two options are mutually exclusive.
 130  **/
 131 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 132 {
 133         u32 reg = 0;
 134         bool ext_mdio = false;
 135
 136         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 137
 138         switch (hw->mac.type) {
 139         case e1000_82575:
 140         case e1000_82576:
 141                 reg = E1000_READ_REG(hw, E1000_MDIC);
 142                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 143                 break;
 144         case e1000_82580:
 145         case e1000_i350:
 146         case e1000_i210:
 147         case e1000_i211:
 148                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 149                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 150                 break;
 151         default:
 152                 break;
 153         }
 154         return ext_mdio;
 155 }
 156
 157 /**
 158  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 159  *  @hw: pointer to the HW structure
 160  **/
 161 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 162 {
 163         struct e1000_phy_info *phy = &hw->phy;
 164         s32 ret_val = E1000_SUCCESS;
 165         u32 ctrl_ext;
 166
 167         DEBUGFUNC("e1000_init_phy_params_82575");
 168
 169         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 170         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 171
 172         if (hw->phy.media_type != e1000_media_type_copper) {
 173                 phy->type = e1000_phy_none;
 174                 goto out;
 175         }
 176
 177         phy->ops.power_up   = e1000_power_up_phy_copper;
 178         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 179
 180         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 181         phy->reset_delay_us     = 100;
 182
 183         phy->ops.acquire        = e1000_acquire_phy_82575;
 184         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 185         phy->ops.commit         = e1000_phy_sw_reset_generic;
 186         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 187         phy->ops.release        = e1000_release_phy_82575;
 188
 189         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 190
 191         if (e1000_sgmii_active_82575(hw)) {
 192                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 193                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 194         } else {
 195                 phy->ops.reset = e1000_phy_hw_reset_generic;
 196                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 197         }
 198
 199         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 200         e1000_reset_mdicnfg_82580(hw);
 201
 202         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 203                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 204                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 205         } else {
 206                 switch (hw->mac.type) {
 207                 case e1000_82580:
 208                 case e1000_i350:
 209                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 210                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 211                         break;
 212                 case e1000_i210:
 213                 case e1000_i211:
 214                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 215                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 216                         break;
 217                 default:
 218                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 219                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 220                 }
 221         }
 222
 223         /* Set phy->phy_addr and phy->id. */
 224         ret_val = e1000_get_phy_id_82575(hw);
 225
 226         /* Verify phy id and set remaining function pointers */
 227         switch (phy->id) {
 228         case I347AT4_E_PHY_ID:
 229         case M88E1112_E_PHY_ID:
 230         case M88E1340M_E_PHY_ID:
 231         case M88E1111_I_PHY_ID:
 232                 phy->type               = e1000_phy_m88;
 233                 phy->ops.check_polarity = e1000_check_polarity_m88;
 234                 phy->ops.get_info       = e1000_get_phy_info_m88;
 235                 if (phy->id == I347AT4_E_PHY_ID ||
 236                     phy->id == M88E1112_E_PHY_ID ||
 237                     phy->id == M88E1340M_E_PHY_ID)
 238                         phy->ops.get_cable_length =
 239                                          e1000_get_cable_length_m88_gen2;
 240                 else
 241                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 242                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 243                 break;
 244         case IGP03E1000_E_PHY_ID:
 245         case IGP04E1000_E_PHY_ID:
 246                 phy->type = e1000_phy_igp_3;
 247                 phy->ops.check_polarity = e1000_check_polarity_igp;
 248                 phy->ops.get_info = e1000_get_phy_info_igp;
 249                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 250                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 251                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 252                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 253                 break;
 254         case I82580_I_PHY_ID:
 255         case I350_I_PHY_ID:
 256                 phy->type = e1000_phy_82580;
 257                 phy->ops.check_polarity = e1000_check_polarity_82577;
 258                 phy->ops.force_speed_duplex =
 259                                          e1000_phy_force_speed_duplex_82577;
 260                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 261                 phy->ops.get_info = e1000_get_phy_info_82577;
 262                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 263                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 264                 break;
 265         case I210_I_PHY_ID:
 266                 phy->type               = e1000_phy_i210;
 267                 phy->ops.check_polarity = e1000_check_polarity_m88;
 268                 phy->ops.get_info       = e1000_get_phy_info_m88;
 269                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 270                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 271                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 272                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 273                 break;
 274         default:
 275                 ret_val = -E1000_ERR_PHY;
 276                 goto out;
 277         }
 278
 279 out:
 280         return ret_val;
 281 }
 282
 283 /**
 284  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 285  *  @hw: pointer to the HW structure
 286  **/
 287 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 288 {
 289         struct e1000_nvm_info *nvm = &hw->nvm;
 290         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 291         u16 size;
 292
 293         DEBUGFUNC("e1000_init_nvm_params_82575");
 294
 295         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 296                      E1000_EECD_SIZE_EX_SHIFT);
 297         /*
 298          * Added to a constant, "size" becomes the left-shift value
 299          * for setting word_size.
 300          */
 301         size += NVM_WORD_SIZE_BASE_SHIFT;
 302
 303         /* Just in case size is out of range, cap it to the largest
 304          * EEPROM size supported
 305          */
 306         if (size > 15)
 307                 size = 15;
 308
 309         nvm->word_size = 1 << size;
 310         if (hw->mac.type < e1000_i210) {
 311                 nvm->opcode_bits = 8;
 312                 nvm->delay_usec = 1;
 313
 314                 switch (nvm->override) {
 315                 case e1000_nvm_override_spi_large:
 316                         nvm->page_size = 32;
 317                         nvm->address_bits = 16;
 318                         break;
 319                 case e1000_nvm_override_spi_small:
 320                         nvm->page_size = 8;
 321                         nvm->address_bits = 8;
 322                         break;
 323                 default:
 324                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 325                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 326                                             16 : 8;
 327                         break;
 328                 }
 329                 if (nvm->word_size == (1 << 15))
 330                         nvm->page_size = 128;
 331
 332                 nvm->type = e1000_nvm_eeprom_spi;
 333         } else {
 334                 nvm->type = e1000_nvm_flash_hw;
 335         }
 336         /* Function Pointers */
 337         nvm->ops.acquire = e1000_acquire_nvm_82575;
 338         nvm->ops.release = e1000_release_nvm_82575;
 339         if (nvm->word_size < (1 << 15))
 340                 nvm->ops.read = e1000_read_nvm_eerd;
 341         else
 342                 nvm->ops.read = e1000_read_nvm_spi;
 343
 344         nvm->ops.write = e1000_write_nvm_spi;
 345         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 346         nvm->ops.update = e1000_update_nvm_checksum_generic;
 347         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 348
 349         /* override generic family function pointers for specific descendants */
 350         switch (hw->mac.type) {
 351         case e1000_82580:
 352                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 353                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 354                 break;
 355         case e1000_i350:
 356                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 357                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 358                 break;
 359         default:
 360                 break;
 361         }
 362
 363         return E1000_SUCCESS;
 364 }
 365
 366 /**
 367  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 368  *  @hw: pointer to the HW structure
 369  **/
 370 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 371 {
 372         struct e1000_mac_info *mac = &hw->mac;
 373         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 374
 375         DEBUGFUNC("e1000_init_mac_params_82575");
 376
 377         /* Derives media type */
 378         e1000_get_media_type_82575(hw);
 379         /* Set mta register count */
 380         mac->mta_reg_count = 128;
 381         /* Set uta register count */
 382         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 383         /* Set rar entry count */
 384         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 385         if (mac->type == e1000_82576)
 386                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 387         if (mac->type == e1000_82580)
 388                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 389         if (mac->type == e1000_i350) {
 390                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 391                 /* Enable EEE default settings for i350 */
 392                 dev_spec->eee_disable = false;
 393         }
 394
 395         /* Set if part includes ASF firmware */
 396         mac->asf_firmware_present = true;
 397         /* FWSM register */
 398         mac->has_fwsm = true;
 399         /* ARC supported; valid only if manageability features are enabled. */
 400         mac->arc_subsystem_valid =
 401                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 402
 403         /* Function pointers */
 404
 405         /* bus type/speed/width */
 406         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 407         /* reset */
 408         if (mac->type >= e1000_82580)
 409                 mac->ops.reset_hw = e1000_reset_hw_82580;
 410         else
 411         mac->ops.reset_hw = e1000_reset_hw_82575;
 412         /* hw initialization */
 413         mac->ops.init_hw = e1000_init_hw_82575;
 414         /* link setup */
 415         mac->ops.setup_link = e1000_setup_link_generic;
 416         /* physical interface link setup */
 417         mac->ops.setup_physical_interface =
 418                 (hw->phy.media_type == e1000_media_type_copper)
 419                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 420         /* physical interface shutdown */
 421         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 422         /* physical interface power up */
 423         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 424         /* check for link */
 425         mac->ops.check_for_link = e1000_check_for_link_82575;
 426         /* read mac address */
 427         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 428         /* configure collision distance */
 429         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 430         /* multicast address update */
 431         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 432         if (mac->type == e1000_i350) {
 433                 /* writing VFTA */
 434                 mac->ops.write_vfta = e1000_write_vfta_i350;
 435                 /* clearing VFTA */
 436                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 437         } else {
 438                 /* writing VFTA */
 439                 mac->ops.write_vfta = e1000_write_vfta_generic;
 440                 /* clearing VFTA */
 441                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 442         }
 443         if (hw->mac.type >= e1000_82580)
 444                 mac->ops.validate_mdi_setting =
 445                                 e1000_validate_mdi_setting_crossover_generic;
 446         /* ID LED init */
 447         mac->ops.id_led_init = e1000_id_led_init_generic;
 448         /* blink LED */
 449         mac->ops.blink_led = e1000_blink_led_generic;
 450         /* setup LED */
 451         mac->ops.setup_led = e1000_setup_led_generic;
 452         /* cleanup LED */
 453         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 454         /* turn on/off LED */
 455         mac->ops.led_on = e1000_led_on_generic;
 456         mac->ops.led_off = e1000_led_off_generic;
 457         /* clear hardware counters */
 458         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 459         /* link info */
 460         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 461         /* acquire SW_FW sync */
 462         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 463         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 464         if (mac->type >= e1000_i210) {
 465                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 466                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 467         }
 468
 469         /* set lan id for port to determine which phy lock to use */
 470         hw->mac.ops.set_lan_id(hw);
 471
 472         return E1000_SUCCESS;
 473 }
 474
 475 /**
 476  *  e1000_init_function_pointers_82575 - Init func ptrs.
 477  *  @hw: pointer to the HW structure
 478  *
 479  *  Called to initialize all function pointers and parameters.
 480  **/
 481 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 482 {
 483         DEBUGFUNC("e1000_init_function_pointers_82575");
 484
 485         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 486         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 487         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 488         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 489 }
 490
 491 /**
 492  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Acquire access rights to the correct PHY.
 496  **/
 497 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 498 {
 499         u16 mask = E1000_SWFW_PHY0_SM;
 500
 501         DEBUGFUNC("e1000_acquire_phy_82575");
 502
 503         if (hw->bus.func == E1000_FUNC_1)
 504                 mask = E1000_SWFW_PHY1_SM;
 505         else if (hw->bus.func == E1000_FUNC_2)
 506                 mask = E1000_SWFW_PHY2_SM;
 507         else if (hw->bus.func == E1000_FUNC_3)
 508                 mask = E1000_SWFW_PHY3_SM;
 509
 510         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 511 }
 512
 513 /**
 514  *  e1000_release_phy_82575 - Release rights to access PHY
 515  *  @hw: pointer to the HW structure
 516  *
 517  *  A wrapper to release access rights to the correct PHY.
 518  **/
 519 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 520 {
 521         u16 mask = E1000_SWFW_PHY0_SM;
 522
 523         DEBUGFUNC("e1000_release_phy_82575");
 524
 525         if (hw->bus.func == E1000_FUNC_1)
 526                 mask = E1000_SWFW_PHY1_SM;
 527         else if (hw->bus.func == E1000_FUNC_2)
 528                 mask = E1000_SWFW_PHY2_SM;
 529         else if (hw->bus.func == E1000_FUNC_3)
 530                 mask = E1000_SWFW_PHY3_SM;
 531
 532         hw->mac.ops.release_swfw_sync(hw, mask);
 533 }
 534
 535 /**
 536  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 537  *  @hw: pointer to the HW structure
 538  *  @offset: register offset to be read
 539  *  @data: pointer to the read data
 540  *
 541  *  Reads the PHY register at offset using the serial gigabit media independent
 542  *  interface and stores the retrieved information in data.
 543  **/
 544 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 545                                           u16 *data)
 546 {
 547         s32 ret_val = -E1000_ERR_PARAM;
 548
 549         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 550
 551         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 552                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 553                 goto out;
 554         }
 555
 556         ret_val = hw->phy.ops.acquire(hw);
 557         if (ret_val)
 558                 goto out;
 559
 560         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 561
 562         hw->phy.ops.release(hw);
 563
 564 out:
 565         return ret_val;
 566 }
 567
 568 /**
 569  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 570  *  @hw: pointer to the HW structure
 571  *  @offset: register offset to write to
 572  *  @data: data to write at register offset
 573  *
 574  *  Writes the data to PHY register at the offset using the serial gigabit
 575  *  media independent interface.
 576  **/
 577 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 578                                            u16 data)
 579 {
 580         s32 ret_val = -E1000_ERR_PARAM;
 581
 582         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 583
 584         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 585                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 586                 goto out;
 587         }
 588
 589         ret_val = hw->phy.ops.acquire(hw);
 590         if (ret_val)
 591                 goto out;
 592
 593         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 594
 595         hw->phy.ops.release(hw);
 596
 597 out:
 598         return ret_val;
 599 }
 600
 601 /**
 602  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 603  *  @hw: pointer to the HW structure
 604  *
 605  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 606  *  sgmi interface.
 607  **/
 608 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 609 {
 610         struct e1000_phy_info *phy = &hw->phy;
 611         s32  ret_val = E1000_SUCCESS;
 612         u16 phy_id;
 613         u32 ctrl_ext;
 614         u32 mdic;
 615
 616         DEBUGFUNC("e1000_get_phy_id_82575");
 617
 618         /*
 619          * For SGMII PHYs, we try the list of possible addresses until
 620          * we find one that works.  For non-SGMII PHYs
 621          * (e.g. integrated copper PHYs), an address of 1 should
 622          * work.  The result of this function should mean phy->phy_addr
 623          * and phy->id are set correctly.
 624          */
 625         if (!e1000_sgmii_active_82575(hw)) {
 626                 phy->addr = 1;
 627                 ret_val = e1000_get_phy_id(hw);
 628                 goto out;
 629         }
 630
 631         if (e1000_sgmii_uses_mdio_82575(hw)) {
 632                 switch (hw->mac.type) {
 633                 case e1000_82575:
 634                 case e1000_82576:
 635                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 636                         mdic &= E1000_MDIC_PHY_MASK;
 637                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 638                         break;
 639                 case e1000_82580:
 640                 case e1000_i350:
 641                 case e1000_i210:
 642                 case e1000_i211:
 643                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 644                         mdic &= E1000_MDICNFG_PHY_MASK;
 645                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 646                         break;
 647                 default:
 648                         ret_val = -E1000_ERR_PHY;
 649                         goto out;
 650                         break;
 651                 }
 652                 ret_val = e1000_get_phy_id(hw);
 653                 goto out;
 654         }
 655
 656         /* Power on sgmii phy if it is disabled */
 657         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 658         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 659                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 660         E1000_WRITE_FLUSH(hw);
 661         msec_delay(300);
 662
 663         /*
 664          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 665          * Therefore, we need to test 1-7
 666          */
 667         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 668                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 669                 if (ret_val == E1000_SUCCESS) {
 670                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 671                                   phy_id, phy->addr);
 672                         /*
 673                          * At the time of this writing, The M88 part is
 674                          * the only supported SGMII PHY product.
 675                          */
 676                         if (phy_id == M88_VENDOR)
 677                                 break;
 678                 } else {
 679                         DEBUGOUT1("PHY address %u was unreadable\n",
 680                                   phy->addr);
 681                 }
 682         }
 683
 684         /* A valid PHY type couldn't be found. */
 685         if (phy->addr == 8) {
 686                 phy->addr = 0;
 687                 ret_val = -E1000_ERR_PHY;
 688         } else {
 689                 ret_val = e1000_get_phy_id(hw);
 690         }
 691
 692         /* restore previous sfp cage power state */
 693         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 694
 695 out:
 696         return ret_val;
 697 }
 698
 699 /**
 700  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 701  *  @hw: pointer to the HW structure
 702  *
 703  *  Resets the PHY using the serial gigabit media independent interface.
 704  **/
 705 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 706 {
 707         s32 ret_val = E1000_SUCCESS;
 708
 709         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 710
 711         /*
 712          * This isn't a true "hard" reset, but is the only reset
 713          * available to us at this time.
 714          */
 715
 716         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 717
 718         if (!(hw->phy.ops.write_reg))
 719                 goto out;
 720
 721         /*
 722          * SFP documentation requires the following to configure the SPF module
 723          * to work on SGMII.  No further documentation is given.
 724          */
 725         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 726         if (ret_val)
 727                 goto out;
 728
 729         ret_val = hw->phy.ops.commit(hw);
 730
 731 out:
 732         return ret_val;
 733 }
 734
 735 /**
 736  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 737  *  @hw: pointer to the HW structure
 738  *  @active: true to enable LPLU, false to disable
 739  *
 740  *  Sets the LPLU D0 state according to the active flag.  When
 741  *  activating LPLU this function also disables smart speed
 742  *  and vice versa.  LPLU will not be activated unless the
 743  *  device autonegotiation advertisement meets standards of
 744  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 745  *  This is a function pointer entry point only called by
 746  *  PHY setup routines.
 747  **/
 748 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 749 {
 750         struct e1000_phy_info *phy = &hw->phy;
 751         s32 ret_val = E1000_SUCCESS;
 752         u16 data;
 753
 754         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 755
 756         if (!(hw->phy.ops.read_reg))
 757                 goto out;
 758
 759         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 760         if (ret_val)
 761                 goto out;
 762
 763         if (active) {
 764                 data |= IGP02E1000_PM_D0_LPLU;
 765                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 766                                              data);
 767                 if (ret_val)
 768                         goto out;
 769
 770                 /* When LPLU is enabled, we should disable SmartSpeed */
 771                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 772                                             &data);
 773                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 774                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 775                                              data);
 776                 if (ret_val)
 777                         goto out;
 778         } else {
 779                 data &= ~IGP02E1000_PM_D0_LPLU;
 780                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 781                                              data);
 782                 /*
 783                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 784                  * during Dx states where the power conservation is most
 785                  * important.  During driver activity we should enable
 786                  * SmartSpeed, so performance is maintained.
 787                  */
 788                 if (phy->smart_speed == e1000_smart_speed_on) {
 789                         ret_val = phy->ops.read_reg(hw,
 790                                                     IGP01E1000_PHY_PORT_CONFIG,
 791                                                     &data);
 792                         if (ret_val)
 793                                 goto out;
 794
 795                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 796                         ret_val = phy->ops.write_reg(hw,
 797                                                      IGP01E1000_PHY_PORT_CONFIG,
 798                                                      data);
 799                         if (ret_val)
 800                                 goto out;
 801                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 802                         ret_val = phy->ops.read_reg(hw,
 803                                                     IGP01E1000_PHY_PORT_CONFIG,
 804                                                     &data);
 805                         if (ret_val)
 806                                 goto out;
 807
 808                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 809                         ret_val = phy->ops.write_reg(hw,
 810                                                      IGP01E1000_PHY_PORT_CONFIG,
 811                                                      data);
 812                         if (ret_val)
 813                                 goto out;
 814                 }
 815         }
 816
 817 out:
 818         return ret_val;
 819 }
 820
 821 /**
 822  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 823  *  @hw: pointer to the HW structure
 824  *  @active: true to enable LPLU, false to disable
 825  *
 826  *  Sets the LPLU D0 state according to the active flag.  When
 827  *  activating LPLU this function also disables smart speed
 828  *  and vice versa.  LPLU will not be activated unless the
 829  *  device autonegotiation advertisement meets standards of
 830  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 831  *  This is a function pointer entry point only called by
 832  *  PHY setup routines.
 833  **/
 834 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 835 {
 836         struct e1000_phy_info *phy = &hw->phy;
 837         s32 ret_val = E1000_SUCCESS;
 838         u32 data;
 839
 840         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 841
 842         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 843
 844         if (active) {
 845                 data |= E1000_82580_PM_D0_LPLU;
 846
 847                 /* When LPLU is enabled, we should disable SmartSpeed */
 848                 data &= ~E1000_82580_PM_SPD;
 849         } else {
 850                 data &= ~E1000_82580_PM_D0_LPLU;
 851
 852                 /*
 853                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 854                  * during Dx states where the power conservation is most
 855                  * important.  During driver activity we should enable
 856                  * SmartSpeed, so performance is maintained.
 857                  */
 858                 if (phy->smart_speed == e1000_smart_speed_on)
 859                         data |= E1000_82580_PM_SPD;
 860                 else if (phy->smart_speed == e1000_smart_speed_off)
 861                         data &= ~E1000_82580_PM_SPD;
 862         }
 863
 864         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 865         return ret_val;
 866 }
 867
 868 /**
 869  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 870  *  @hw: pointer to the HW structure
 871  *  @active: boolean used to enable/disable lplu
 872  *
 873  *  Success returns 0, Failure returns 1
 874  *
 875  *  The low power link up (lplu) state is set to the power management level D3
 876  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 877  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 878  *  is used during Dx states where the power conservation is most important.
 879  *  During driver activity, SmartSpeed should be enabled so performance is
 880  *  maintained.
 881  **/
 882 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 883 {
 884         struct e1000_phy_info *phy = &hw->phy;
 885         s32 ret_val = E1000_SUCCESS;
 886         u32 data;
 887
 888         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 889
 890         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 891
 892         if (!active) {
 893                 data &= ~E1000_82580_PM_D3_LPLU;
 894                 /*
 895                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 896                  * during Dx states where the power conservation is most
 897                  * important.  During driver activity we should enable
 898                  * SmartSpeed, so performance is maintained.
 899                  */
 900                 if (phy->smart_speed == e1000_smart_speed_on)
 901                         data |= E1000_82580_PM_SPD;
 902                 else if (phy->smart_speed == e1000_smart_speed_off)
 903                         data &= ~E1000_82580_PM_SPD;
 904         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 905                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 906                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 907                 data |= E1000_82580_PM_D3_LPLU;
 908                 /* When LPLU is enabled, we should disable SmartSpeed */
 909                 data &= ~E1000_82580_PM_SPD;
 910         }
 911
 912         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 913         return ret_val;
 914 }
 915
 916 /**
 917  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 918  *  @hw: pointer to the HW structure
 919  *
 920  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 921  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 922  *  Return successful if access grant bit set, else clear the request for
 923  *  EEPROM access and return -E1000_ERR_NVM (-1).
 924  **/
 925 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 926 {
 927         s32 ret_val;
 928
 929         DEBUGFUNC("e1000_acquire_nvm_82575");
 930
 931         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 932         if (ret_val)
 933                 goto out;
 934
 935         /*
 936          * Check if there is some access
 937          * error this access may hook on
 938          */
 939         if (hw->mac.type == e1000_i350) {
 940                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 941                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 942                     E1000_EECD_TIMEOUT)) {
 943                         /* Clear all access error flags */
 944                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 945                                         E1000_EECD_ERROR_CLR);
 946                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 947                 }
 948         }
 949         if (hw->mac.type == e1000_82580) {
 950                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 951                 if (eecd & E1000_EECD_BLOCKED) {
 952                         /* Clear access error flag */
 953                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 954                                         E1000_EECD_BLOCKED);
 955                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 956                 }
 957         }
 958
 959
 960         ret_val = e1000_acquire_nvm_generic(hw);
 961         if (ret_val)
 962                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 963
 964 out:
 965         return ret_val;
 966 }
 967
 968 /**
 969  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
 970  *  @hw: pointer to the HW structure
 971  *
 972  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
 973  *  then release the semaphores acquired.
 974  **/
 975 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
 976 {
 977         DEBUGFUNC("e1000_release_nvm_82575");
 978
 979         e1000_release_nvm_generic(hw);
 980
 981         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 982 }
 983
 984 /**
 985  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
 986  *  @hw: pointer to the HW structure
 987  *  @mask: specifies which semaphore to acquire
 988  *
 989  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 990  *  will also specify which port we're acquiring the lock for.
 991  **/
 992 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 993 {
 994         u32 swfw_sync;
 995         u32 swmask = mask;
 996         u32 fwmask = mask << 16;
 997         s32 ret_val = E1000_SUCCESS;
 998         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
 999
1000         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1001
1002         while (i < timeout) {
1003                 if (e1000_get_hw_semaphore_generic(hw)) {
1004                         ret_val = -E1000_ERR_SWFW_SYNC;
1005                         goto out;
1006                 }
1007
1008                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1009                 if (!(swfw_sync & (fwmask | swmask)))
1010                         break;
1011
1012                 /*
1013                  * Firmware currently using resource (fwmask)
1014                  * or other software thread using resource (swmask)
1015                  */
1016                 e1000_put_hw_semaphore_generic(hw);
1017                 msec_delay_irq(5);
1018                 i++;
1019         }
1020
1021         if (i == timeout) {
1022                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1023                 ret_val = -E1000_ERR_SWFW_SYNC;
1024                 goto out;
1025         }
1026
1027         swfw_sync |= swmask;
1028         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1029
1030         e1000_put_hw_semaphore_generic(hw);
1031
1032 out:
1033         return ret_val;
1034 }
1035
1036 /**
1037  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1038  *  @hw: pointer to the HW structure
1039  *  @mask: specifies which semaphore to acquire
1040  *
1041  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1042  *  will also specify which port we're releasing the lock for.
1043  **/
1044 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1045 {
1046         u32 swfw_sync;
1047
1048         DEBUGFUNC("e1000_release_swfw_sync_82575");
1049
1050         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1051                 ; /* Empty */
1052
1053         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1054         swfw_sync &= ~mask;
1055         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1056
1057         e1000_put_hw_semaphore_generic(hw);
1058 }
1059
1060 /**
1061  *  e1000_get_cfg_done_82575 - Read config done bit
1062  *  @hw: pointer to the HW structure
1063  *
1064  *  Read the management control register for the config done bit for
1065  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1066  *  to read the config done bit, so an error is *ONLY* logged and returns
1067  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1068  *  would not be able to be reset or change link.
1069  **/
1070 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1071 {
1072         s32 timeout = PHY_CFG_TIMEOUT;
1073         s32 ret_val = E1000_SUCCESS;
1074         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1075
1076         DEBUGFUNC("e1000_get_cfg_done_82575");
1077
1078         if (hw->bus.func == E1000_FUNC_1)
1079                 mask = E1000_NVM_CFG_DONE_PORT_1;
1080         else if (hw->bus.func == E1000_FUNC_2)
1081                 mask = E1000_NVM_CFG_DONE_PORT_2;
1082         else if (hw->bus.func == E1000_FUNC_3)
1083                 mask = E1000_NVM_CFG_DONE_PORT_3;
1084         while (timeout) {
1085                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1086                         break;
1087                 msec_delay(1);
1088                 timeout--;
1089         }
1090         if (!timeout)
1091                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1092
1093         /* If EEPROM is not marked present, init the PHY manually */
1094         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1095             (hw->phy.type == e1000_phy_igp_3))
1096                 e1000_phy_init_script_igp3(hw);
1097
1098         return ret_val;
1099 }
1100
1101 /**
1102  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1103  *  @hw: pointer to the HW structure
1104  *  @speed: stores the current speed
1105  *  @duplex: stores the current duplex
1106  *
1107  *  This is a wrapper function, if using the serial gigabit media independent
1108  *  interface, use PCS to retrieve the link speed and duplex information.
1109  *  Otherwise, use the generic function to get the link speed and duplex info.
1110  **/
1111 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1112                                         u16 *duplex)
1113 {
1114         s32 ret_val;
1115
1116         DEBUGFUNC("e1000_get_link_up_info_82575");
1117
1118         if (hw->phy.media_type != e1000_media_type_copper)
1119                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1120                                                                duplex);
1121         else
1122                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1123                                                                     duplex);
1124
1125         return ret_val;
1126 }
1127
1128 /**
1129  *  e1000_check_for_link_82575 - Check for link
1130  *  @hw: pointer to the HW structure
1131  *
1132  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1133  *  use the generic interface for determining link.
1134  **/
1135 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1136 {
1137         s32 ret_val;
1138         u16 speed, duplex;
1139
1140         DEBUGFUNC("e1000_check_for_link_82575");
1141
1142         if (hw->phy.media_type != e1000_media_type_copper) {
1143                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1144                                                                &duplex);
1145                 /*
1146                  * Use this flag to determine if link needs to be checked or
1147                  * not.  If we have link clear the flag so that we do not
1148                  * continue to check for link.
1149                  */
1150                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1151
1152                 /*
1153                  * Configure Flow Control now that Auto-Neg has completed.
1154                  * First, we need to restore the desired flow control
1155                  * settings because we may have had to re-autoneg with a
1156                  * different link partner.
1157                  */
1158                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1159                 if (ret_val)
1160                         DEBUGOUT("Error configuring flow control\n");
1161         } else {
1162                 ret_val = e1000_check_for_copper_link_generic(hw);
1163         }
1164
1165         return ret_val;
1166 }
1167
1168 /**
1169  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1170  *  @hw: pointer to the HW structure
1171  **/
1172 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1173 {
1174         u32 reg;
1175
1176         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1177
1178         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1179             !e1000_sgmii_active_82575(hw))
1180                 return;
1181
1182         /* Enable PCS to turn on link */
1183         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1184         reg |= E1000_PCS_CFG_PCS_EN;
1185         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1186
1187         /* Power up the laser */
1188         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1189         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1190         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1191
1192         /* flush the write to verify completion */
1193         E1000_WRITE_FLUSH(hw);
1194         msec_delay(1);
1195 }
1196
1197 /**
1198  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1199  *  @hw: pointer to the HW structure
1200  *  @speed: stores the current speed
1201  *  @duplex: stores the current duplex
1202  *
1203  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1204  *  duplex, then store the values in the pointers provided.
1205  **/
1206 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1207                                                 u16 *speed, u16 *duplex)
1208 {
1209         struct e1000_mac_info *mac = &hw->mac;
1210         u32 pcs;
1211
1212         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1213
1214         /*
1215          * Read the PCS Status register for link state. For non-copper mode,
1216          * the status register is not accurate. The PCS status register is
1217          * used instead.
1218          */
1219         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1220
1221         /*
1222          * The link up bit determines when link is up on autoneg.
1223          */
1224         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1225                 mac->serdes_has_link = true;
1226
1227                 /* Detect and store PCS speed */
1228                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1229                         *speed = SPEED_1000;
1230                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1231                         *speed = SPEED_100;
1232                 else
1233                         *speed = SPEED_10;
1234
1235                 /* Detect and store PCS duplex */
1236                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1237                         *duplex = FULL_DUPLEX;
1238                 else
1239                         *duplex = HALF_DUPLEX;
1240
1241         } else {
1242                 mac->serdes_has_link = false;
1243                 *speed = 0;
1244                 *duplex = 0;
1245         }
1246
1247         return E1000_SUCCESS;
1248 }
1249
1250 /**
1251  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1252  *  @hw: pointer to the HW structure
1253  *
1254  *  In the case of serdes shut down sfp and PCS on driver unload
1255  *  when management pass thru is not enabled.
1256  **/
1257 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1258 {
1259         u32 reg;
1260
1261         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1262
1263         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1264             !e1000_sgmii_active_82575(hw))
1265                 return;
1266
1267         if (!e1000_enable_mng_pass_thru(hw)) {
1268                 /* Disable PCS to turn off link */
1269                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1270                 reg &= ~E1000_PCS_CFG_PCS_EN;
1271                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1272
1273                 /* shutdown the laser */
1274                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1275                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1276                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1277
1278                 /* flush the write to verify completion */
1279                 E1000_WRITE_FLUSH(hw);
1280                 msec_delay(1);
1281         }
1282
1283         return;
1284 }
1285
1286 /**
1287  *  e1000_reset_hw_82575 - Reset hardware
1288  *  @hw: pointer to the HW structure
1289  *
1290  *  This resets the hardware into a known state.
1291  **/
1292 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1293 {
1294         u32 ctrl;
1295         s32 ret_val;
1296
1297         DEBUGFUNC("e1000_reset_hw_82575");
1298
1299         /*
1300          * Prevent the PCI-E bus from sticking if there is no TLP connection
1301          * on the last TLP read/write transaction when MAC is reset.
1302          */
1303         ret_val = e1000_disable_pcie_master_generic(hw);
1304         if (ret_val)
1305                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1306
1307         /* set the completion timeout for interface */
1308         ret_val = e1000_set_pcie_completion_timeout(hw);
1309         if (ret_val)
1310                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1311
1312         DEBUGOUT("Masking off all interrupts\n");
1313         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1314
1315         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1316         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1317         E1000_WRITE_FLUSH(hw);
1318
1319         msec_delay(10);
1320
1321         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1322
1323         DEBUGOUT("Issuing a global reset to MAC\n");
1324         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1325
1326         ret_val = e1000_get_auto_rd_done_generic(hw);
1327         if (ret_val) {
1328                 /*
1329                  * When auto config read does not complete, do not
1330                  * return with an error. This can happen in situations
1331                  * where there is no eeprom and prevents getting link.
1332                  */
1333                 DEBUGOUT("Auto Read Done did not complete\n");
1334         }
1335
1336         /* If EEPROM is not present, run manual init scripts */
1337         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1338                 e1000_reset_init_script_82575(hw);
1339
1340         /* Clear any pending interrupt events. */
1341         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1342         E1000_READ_REG(hw, E1000_ICR);
1343
1344         /* Install any alternate MAC address into RAR0 */
1345         ret_val = e1000_check_alt_mac_addr_generic(hw);
1346
1347         return ret_val;
1348 }
1349
1350 /**
1351  *  e1000_init_hw_82575 - Initialize hardware
1352  *  @hw: pointer to the HW structure
1353  *
1354  *  This inits the hardware readying it for operation.
1355  **/
1356 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1357 {
1358         struct e1000_mac_info *mac = &hw->mac;
1359         s32 ret_val;
1360         u16 i, rar_count = mac->rar_entry_count;
1361
1362         DEBUGFUNC("e1000_init_hw_82575");
1363
1364         /* Initialize identification LED */
1365         ret_val = mac->ops.id_led_init(hw);
1366         if (ret_val) {
1367                 DEBUGOUT("Error initializing identification LED\n");
1368                 /* This is not fatal and we should not stop init due to this */
1369         }
1370
1371         /* Disabling VLAN filtering */
1372         DEBUGOUT("Initializing the IEEE VLAN\n");
1373         mac->ops.clear_vfta(hw);
1374
1375         /* Setup the receive address */
1376         e1000_init_rx_addrs_generic(hw, rar_count);
1377
1378         /* Zero out the Multicast HASH table */
1379         DEBUGOUT("Zeroing the MTA\n");
1380         for (i = 0; i < mac->mta_reg_count; i++)
1381                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1382
1383         /* Zero out the Unicast HASH table */
1384         DEBUGOUT("Zeroing the UTA\n");
1385         for (i = 0; i < mac->uta_reg_count; i++)
1386                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1387
1388         /* Setup link and flow control */
1389         ret_val = mac->ops.setup_link(hw);
1390
1391         /* Set the default MTU size */
1392         hw->dev_spec._82575.mtu = 1500;
1393
1394         /*
1395          * Clear all of the statistics registers (clear on read).  It is
1396          * important that we do this after we have tried to establish link
1397          * because the symbol error count will increment wildly if there
1398          * is no link.
1399          */
1400         e1000_clear_hw_cntrs_82575(hw);
1401
1402         return ret_val;
1403 }
1404
1405 /**
1406  *  e1000_setup_copper_link_82575 - Configure copper link settings
1407  *  @hw: pointer to the HW structure
1408  *
1409  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1410  *  for link, once link is established calls to configure collision distance
1411  *  and flow control are called.
1412  **/
1413 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1414 {
1415         u32 ctrl;
1416         s32 ret_val;
1417         u32 phpm_reg;
1418
1419         DEBUGFUNC("e1000_setup_copper_link_82575");
1420
1421         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1422         ctrl |= E1000_CTRL_SLU;
1423         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1424         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1425
1426         /* Clear Go Link Disconnect bit */
1427         if (hw->mac.type >= e1000_82580) {
1428                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1429                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1430                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1431         }
1432
1433         ret_val = e1000_setup_serdes_link_82575(hw);
1434         if (ret_val)
1435                 goto out;
1436
1437         if (e1000_sgmii_active_82575(hw)) {
1438                 /* allow time for SFP cage time to power up phy */
1439                 msec_delay(300);
1440
1441                 ret_val = hw->phy.ops.reset(hw);
1442                 if (ret_val) {
1443                         DEBUGOUT("Error resetting the PHY.\n");
1444                         goto out;
1445                 }
1446         }
1447         switch (hw->phy.type) {
1448         case e1000_phy_i210:
1449         case e1000_phy_m88:
1450                 if (hw->phy.id == I347AT4_E_PHY_ID ||
1451                     hw->phy.id == M88E1112_E_PHY_ID ||
1452                     hw->phy.id == M88E1340M_E_PHY_ID)
1453                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1454                 else
1455                         ret_val = e1000_copper_link_setup_m88(hw);
1456                 break;
1457         case e1000_phy_igp_3:
1458                 ret_val = e1000_copper_link_setup_igp(hw);
1459                 break;
1460         case e1000_phy_82580:
1461                 ret_val = e1000_copper_link_setup_82577(hw);
1462                 break;
1463         default:
1464                 ret_val = -E1000_ERR_PHY;
1465                 break;
1466         }
1467
1468         if (ret_val)
1469                 goto out;
1470
1471         ret_val = e1000_setup_copper_link_generic(hw);
1472 out:
1473         return ret_val;
1474 }
1475
1476 /**
1477  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1478  *  @hw: pointer to the HW structure
1479  *
1480  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1481  *  used on copper connections where the serialized gigabit media independent
1482  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1483  *  for auto-negotiation or forces speed/duplex.
1484  **/
1485 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1486 {
1487         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1488         bool pcs_autoneg;
1489         s32 ret_val = E1000_SUCCESS;
1490         u16 data;
1491
1492         DEBUGFUNC("e1000_setup_serdes_link_82575");
1493
1494         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1495             !e1000_sgmii_active_82575(hw))
1496                 return ret_val;
1497
1498         /*
1499          * On the 82575, SerDes loopback mode persists until it is
1500          * explicitly turned off or a power cycle is performed.  A read to
1501          * the register does not indicate its status.  Therefore, we ensure
1502          * loopback mode is disabled during initialization.
1503          */
1504         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1505
1506         /* power on the sfp cage if present */
1507         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1508         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1509         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1510
1511         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1512         ctrl_reg |= E1000_CTRL_SLU;
1513
1514         /* set both sw defined pins on 82575/82576*/
1515         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1516                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1517
1518         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1519
1520         /* default pcs_autoneg to the same setting as mac autoneg */
1521         pcs_autoneg = hw->mac.autoneg;
1522
1523         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1524         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1525                 /* sgmii mode lets the phy handle forcing speed/duplex */
1526                 pcs_autoneg = true;
1527                 /* autoneg time out should be disabled for SGMII mode */
1528                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1529                 break;
1530         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1531                 /* disable PCS autoneg and support parallel detect only */
1532                 pcs_autoneg = false;
1533                 /* fall through to default case */
1534         default:
1535                 if (hw->mac.type == e1000_82575 ||
1536                     hw->mac.type == e1000_82576) {
1537                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1538                         if (ret_val) {
1539                                 DEBUGOUT("NVM Read Error\n");
1540                                 return ret_val;
1541                         }
1542
1543                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1544                                 pcs_autoneg = false;
1545                 }
1546
1547                 /*
1548                  * non-SGMII modes only supports a speed of 1000/Full for the
1549                  * link so it is best to just force the MAC and let the pcs
1550                  * link either autoneg or be forced to 1000/Full
1551                  */
1552                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1553                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1554
1555                 /* set speed of 1000/Full if speed/duplex is forced */
1556                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1557                 break;
1558         }
1559
1560         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1561
1562         /*
1563          * New SerDes mode allows for forcing speed or autonegotiating speed
1564          * at 1gb. Autoneg should be default set by most drivers. This is the
1565          * mode that will be compatible with older link partners and switches.
1566          * However, both are supported by the hardware and some drivers/tools.
1567          */
1568         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1569                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1570
1571         if (pcs_autoneg) {
1572                 /* Set PCS register for autoneg */
1573                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1574                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1575
1576                 /* Disable force flow control for autoneg */
1577                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1578
1579                 /* Configure flow control advertisement for autoneg */
1580                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1581                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1582
1583                 switch (hw->fc.requested_mode) {
1584                 case e1000_fc_full:
1585                 case e1000_fc_rx_pause:
1586                         anadv_reg |= E1000_TXCW_ASM_DIR;
1587                         anadv_reg |= E1000_TXCW_PAUSE;
1588                         break;
1589                 case e1000_fc_tx_pause:
1590                         anadv_reg |= E1000_TXCW_ASM_DIR;
1591                         break;
1592                 default:
1593                         break;
1594                 }
1595
1596                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1597
1598                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1599         } else {
1600                 /* Set PCS register for forced link */
1601                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1602
1603                 /* Force flow control for forced link */
1604                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1605
1606                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1607         }
1608
1609         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1610
1611         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1612                 e1000_force_mac_fc_generic(hw);
1613
1614         return ret_val;
1615 }
1616
1617 /**
1618  *  e1000_get_media_type_82575 - derives current media type.
1619  *  @hw: pointer to the HW structure
1620  *
1621  *  The media type is chosen reflecting few settings.
1622  *  The following are taken into account:
1623  *  - link mode set in the current port Init Control Word #3
1624  *  - current link mode settings in CSR register
1625  *  - MDIO vs. I2C PHY control interface chosen
1626  *  - SFP module media type
1627  **/
1628 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1629 {
1630         u32 lan_id = 0;
1631         s32 ret_val = E1000_ERR_CONFIG;
1632         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1633         u32 ctrl_ext = 0;
1634         u32 current_link_mode = 0;
1635         u16 init_ctrl_wd_3 = 0;
1636         u8 init_ctrl_wd_3_offset = 0;
1637         u8 init_ctrl_wd_3_bit_offset = 0;
1638
1639         /* Set internal phy as default */
1640         dev_spec->sgmii_active = false;
1641         dev_spec->module_plugged = false;
1642
1643         /*
1644          * Check if NVM access method is attached already.
1645          * If it is then Init Control Word #3 is considered
1646          * otherwise runtime CSR register content is taken.
1647          */
1648
1649         /* Get CSR setting */
1650         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1651
1652         /* Get link mode setting */
1653         if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
1654                 /* Take link mode from EEPROM */
1655
1656                 /*
1657                  * Get LAN port ID to derive its
1658                  * adequate Init Control Word #3
1659                  */
1660                 lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
1661                       E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
1662                 /*
1663                  * Derive Init Control Word #3 offset
1664                  * and mask to pick up link mode setting.
1665                  */
1666                 if (hw->mac.type < e1000_82580) {
1667                         init_ctrl_wd_3_offset = lan_id ?
1668                            NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
1669                         init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
1670                 } else {
1671                         init_ctrl_wd_3_offset =
1672                                             NVM_82580_LAN_FUNC_OFFSET(lan_id) +
1673                                             NVM_INIT_CONTROL3_PORT_A;
1674                         init_ctrl_wd_3_bit_offset =
1675                                               NVM_WORD24_82580_LNK_MODE_OFFSET;
1676                 }
1677                 /* Read Init Control Word #3*/
1678                 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
1679
1680                 /*
1681                  * Align link mode bits to
1682                  * their CTRL_EXT location.
1683                  */
1684                 current_link_mode = init_ctrl_wd_3;
1685                 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1686                                        init_ctrl_wd_3_bit_offset);
1687                 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
1688
1689                 /*
1690                  * Switch to CSR for all but internal PHY.
1691                  */
1692                 if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII)
1693                         /* Take link mode from CSR */
1694                         current_link_mode = ctrl_ext &
1695                                             E1000_CTRL_EXT_LINK_MODE_MASK;
1696         } else {
1697                 /* Take link mode from CSR */
1698                 current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1699         }
1700
1701         switch (current_link_mode) {
1702
1703         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1704                 hw->phy.media_type = e1000_media_type_internal_serdes;
1705                 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
1706                 break;
1707         case E1000_CTRL_EXT_LINK_MODE_GMII:
1708                 hw->phy.media_type = e1000_media_type_copper;
1709                 current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
1710                 break;
1711         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1712         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1713                 /* Get phy control interface type set (MDIO vs. I2C)*/
1714                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1715                         hw->phy.media_type = e1000_media_type_copper;
1716                         dev_spec->sgmii_active = true;
1717                         current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
1718                 } else {
1719                         ret_val = e1000_set_sfp_media_type_82575(hw);
1720                         if (ret_val != E1000_SUCCESS)
1721                                 goto out;
1722                         if (hw->phy.media_type ==
1723                                 e1000_media_type_internal_serdes) {
1724                                 /* Keep Link Mode as SGMII for 100BaseFX */
1725                                 if (!dev_spec->eth_flags.e100_base_fx) {
1726                                         current_link_mode =
1727                                          E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1728                                 }
1729                         } else if (hw->phy.media_type ==
1730                                 e1000_media_type_copper) {
1731                                 current_link_mode =
1732                                                E1000_CTRL_EXT_LINK_MODE_SGMII;
1733                         }
1734                 }
1735                 break;
1736         default:
1737                 DEBUGOUT("Link mode mask doesn't fit bit field size\n");
1738                 goto out;
1739         }
1740         /*
1741          * Do not change current link mode setting
1742          * if media type is fibre or has not been
1743          * recognized.
1744          */
1745         if ((hw->phy.media_type != e1000_media_type_unknown) &&
1746             (hw->phy.media_type != e1000_media_type_fiber)) {
1747                 /* Update link mode */
1748                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1749                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
1750                                 current_link_mode);
1751         }
1752
1753         ret_val = E1000_SUCCESS;
1754 out:
1755         /*
1756          * If media type was not identified then return media type
1757          * defined by the CTRL_EXT settings.
1758          */
1759         if (hw->phy.media_type == e1000_media_type_unknown) {
1760                 if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
1761                         hw->phy.media_type = e1000_media_type_copper;
1762                 else
1763                         hw->phy.media_type = e1000_media_type_internal_serdes;
1764         }
1765
1766         return ret_val;
1767 }
1768
1769 /**
1770  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1771  *  @hw: pointer to the HW structure
1772  *
1773  *  The media type is chosen based on SFP module.
1774  *  compatibility flags retrieved from SFP ID EEPROM.
1775  **/
1776 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1777 {
1778         s32 ret_val = E1000_ERR_CONFIG;
1779         u32 ctrl_ext = 0;
1780         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1781         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1782         u8 tranceiver_type = 0;
1783         s32 timeout = 3;
1784
1785         /* Turn I2C interface ON and power on sfp cage */
1786         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1787         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1788         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1789
1790         E1000_WRITE_FLUSH(hw);
1791
1792         /* Read SFP module data */
1793         while (timeout) {
1794                 ret_val = e1000_read_sfp_data_byte(hw,
1795                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1796                         &tranceiver_type);
1797                 if (ret_val == E1000_SUCCESS)
1798                         break;
1799                 msec_delay(100);
1800                 timeout--;
1801         }
1802         if (ret_val != E1000_SUCCESS)
1803                 goto out;
1804         ret_val = e1000_read_sfp_data_byte(hw,
1805                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1806                         (u8 *)eth_flags);
1807         if (ret_val != E1000_SUCCESS)
1808                 goto out;
1809         /*
1810          * Check if there is some SFP
1811          * module plugged and powered
1812          */
1813         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1814             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1815                 dev_spec->module_plugged = true;
1816                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1817                         hw->phy.media_type = e1000_media_type_internal_serdes;
1818                 } else if (eth_flags->e100_base_fx) {
1819                         dev_spec->sgmii_active = true;
1820                         hw->phy.media_type = e1000_media_type_internal_serdes;
1821                 } else if (eth_flags->e1000_base_t) {
1822                         dev_spec->sgmii_active = true;
1823                         hw->phy.media_type = e1000_media_type_copper;
1824                 } else {
1825                                 hw->phy.media_type = e1000_media_type_unknown;
1826                                 DEBUGOUT("PHY module has not been recognized\n");
1827                                 goto out;
1828                 }
1829         } else {
1830                 hw->phy.media_type = e1000_media_type_unknown;
1831         }
1832         ret_val = E1000_SUCCESS;
1833 out:
1834         /* Restore I2C interface setting */
1835         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1836         return ret_val;
1837 }
1838
1839 /**
1840  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1841  *  @hw: pointer to the HW structure
1842  *  @data: pointer to the NVM (EEPROM)
1843  *
1844  *  Read the EEPROM for the current default LED configuration.  If the
1845  *  LED configuration is not valid, set to a valid LED configuration.
1846  **/
1847 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1848 {
1849         s32 ret_val;
1850
1851         DEBUGFUNC("e1000_valid_led_default_82575");
1852
1853         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1854         if (ret_val) {
1855                 DEBUGOUT("NVM Read Error\n");
1856                 goto out;
1857         }
1858
1859         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1860                 switch (hw->phy.media_type) {
1861                 case e1000_media_type_internal_serdes:
1862                         *data = ID_LED_DEFAULT_82575_SERDES;
1863                         break;
1864                 case e1000_media_type_copper:
1865                 default:
1866                         *data = ID_LED_DEFAULT;
1867                         break;
1868                 }
1869         }
1870 out:
1871         return ret_val;
1872 }
1873
1874 /**
1875  *  e1000_sgmii_active_82575 - Return sgmii state
1876  *  @hw: pointer to the HW structure
1877  *
1878  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1879  *  which can be enabled for use in the embedded applications.  Simply
1880  *  return the current state of the sgmii interface.
1881  **/
1882 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1883 {
1884         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1885         return dev_spec->sgmii_active;
1886 }
1887
1888 /**
1889  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1890  *  @hw: pointer to the HW structure
1891  *
1892  *  Inits recommended HW defaults after a reset when there is no EEPROM
1893  *  detected. This is only for the 82575.
1894  **/
1895 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1896 {
1897         DEBUGFUNC("e1000_reset_init_script_82575");
1898
1899         if (hw->mac.type == e1000_82575) {
1900                 DEBUGOUT("Running reset init script for 82575\n");
1901                 /* SerDes configuration via SERDESCTRL */
1902                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1903                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1904                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1905                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1906
1907                 /* CCM configuration via CCMCTL register */
1908                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1909                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1910
1911                 /* PCIe lanes configuration */
1912                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1913                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1914                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1915                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1916
1917                 /* PCIe PLL Configuration */
1918                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1919                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1920                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1921         }
1922
1923         return E1000_SUCCESS;
1924 }
1925
1926 /**
1927  *  e1000_read_mac_addr_82575 - Read device MAC address
1928  *  @hw: pointer to the HW structure
1929  **/
1930 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1931 {
1932         s32 ret_val = E1000_SUCCESS;
1933
1934         DEBUGFUNC("e1000_read_mac_addr_82575");
1935
1936         /*
1937          * If there's an alternate MAC address place it in RAR0
1938          * so that it will override the Si installed default perm
1939          * address.
1940          */
1941         ret_val = e1000_check_alt_mac_addr_generic(hw);
1942         if (ret_val)
1943                 goto out;
1944
1945         ret_val = e1000_read_mac_addr_generic(hw);
1946
1947 out:
1948         return ret_val;
1949 }
1950
1951 /**
1952  *  e1000_config_collision_dist_82575 - Configure collision distance
1953  *  @hw: pointer to the HW structure
1954  *
1955  *  Configures the collision distance to the default value and is used
1956  *  during link setup.
1957  **/
1958 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1959 {
1960         u32 tctl_ext;
1961
1962         DEBUGFUNC("e1000_config_collision_dist_82575");
1963
1964         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1965
1966         tctl_ext &= ~E1000_TCTL_EXT_COLD;
1967         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1968
1969         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1970         E1000_WRITE_FLUSH(hw);
1971 }
1972
1973 /**
1974  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1975  * @hw: pointer to the HW structure
1976  *
1977  * In the case of a PHY power down to save power, or to turn off link during a
1978  * driver unload, or wake on lan is not enabled, remove the link.
1979  **/
1980 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1981 {
1982         struct e1000_phy_info *phy = &hw->phy;
1983
1984         if (!(phy->ops.check_reset_block))
1985                 return;
1986
1987         /* If the management interface is not enabled, then power down */
1988         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1989                 e1000_power_down_phy_copper(hw);
1990
1991         return;
1992 }
1993
1994 /**
1995  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1996  *  @hw: pointer to the HW structure
1997  *
1998  *  Clears the hardware counters by reading the counter registers.
1999  **/
2000 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2001 {
2002         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2003
2004         e1000_clear_hw_cntrs_base_generic(hw);
2005
2006         E1000_READ_REG(hw, E1000_PRC64);
2007         E1000_READ_REG(hw, E1000_PRC127);
2008         E1000_READ_REG(hw, E1000_PRC255);
2009         E1000_READ_REG(hw, E1000_PRC511);
2010         E1000_READ_REG(hw, E1000_PRC1023);
2011         E1000_READ_REG(hw, E1000_PRC1522);
2012         E1000_READ_REG(hw, E1000_PTC64);
2013         E1000_READ_REG(hw, E1000_PTC127);
2014         E1000_READ_REG(hw, E1000_PTC255);
2015         E1000_READ_REG(hw, E1000_PTC511);
2016         E1000_READ_REG(hw, E1000_PTC1023);
2017         E1000_READ_REG(hw, E1000_PTC1522);
2018
2019         E1000_READ_REG(hw, E1000_ALGNERRC);
2020         E1000_READ_REG(hw, E1000_RXERRC);
2021         E1000_READ_REG(hw, E1000_TNCRS);
2022         E1000_READ_REG(hw, E1000_CEXTERR);
2023         E1000_READ_REG(hw, E1000_TSCTC);
2024         E1000_READ_REG(hw, E1000_TSCTFC);
2025
2026         E1000_READ_REG(hw, E1000_MGTPRC);
2027         E1000_READ_REG(hw, E1000_MGTPDC);
2028         E1000_READ_REG(hw, E1000_MGTPTC);
2029
2030         E1000_READ_REG(hw, E1000_IAC);
2031         E1000_READ_REG(hw, E1000_ICRXOC);
2032
2033         E1000_READ_REG(hw, E1000_ICRXPTC);
2034         E1000_READ_REG(hw, E1000_ICRXATC);
2035         E1000_READ_REG(hw, E1000_ICTXPTC);
2036         E1000_READ_REG(hw, E1000_ICTXATC);
2037         E1000_READ_REG(hw, E1000_ICTXQEC);
2038         E1000_READ_REG(hw, E1000_ICTXQMTC);
2039         E1000_READ_REG(hw, E1000_ICRXDMTC);
2040
2041         E1000_READ_REG(hw, E1000_CBTMPC);
2042         E1000_READ_REG(hw, E1000_HTDPMC);
2043         E1000_READ_REG(hw, E1000_CBRMPC);
2044         E1000_READ_REG(hw, E1000_RPTHC);
2045         E1000_READ_REG(hw, E1000_HGPTC);
2046         E1000_READ_REG(hw, E1000_HTCBDPC);
2047         E1000_READ_REG(hw, E1000_HGORCL);
2048         E1000_READ_REG(hw, E1000_HGORCH);
2049         E1000_READ_REG(hw, E1000_HGOTCL);
2050         E1000_READ_REG(hw, E1000_HGOTCH);
2051         E1000_READ_REG(hw, E1000_LENERRS);
2052
2053         /* This register should not be read in copper configurations */
2054         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2055             e1000_sgmii_active_82575(hw))
2056                 E1000_READ_REG(hw, E1000_SCVPC);
2057 }
2058
2059 /**
2060  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2061  *  @hw: pointer to the HW structure
2062  *
2063  *  After rx enable if managability is enabled then there is likely some
2064  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2065  *  function clears the fifos and flushes any packets that came in as rx was
2066  *  being enabled.
2067  **/
2068 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2069 {
2070         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2071         int i, ms_wait;
2072
2073         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2074         if (hw->mac.type != e1000_82575 ||
2075             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2076                 return;
2077
2078         /* Disable all Rx queues */
2079         for (i = 0; i < 4; i++) {
2080                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2081                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2082                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2083         }
2084         /* Poll all queues to verify they have shut down */
2085         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2086                 msec_delay(1);
2087                 rx_enabled = 0;
2088                 for (i = 0; i < 4; i++)
2089                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2090                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2091                         break;
2092         }
2093
2094         if (ms_wait == 10)
2095                 DEBUGOUT("Queue disable timed out after 10ms\n");
2096
2097         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2098          * incoming packets are rejected.  Set enable and wait 2ms so that
2099          * any packet that was coming in as RCTL.EN was set is flushed
2100          */
2101         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2102         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2103
2104         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2105         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2106
2107         rctl = E1000_READ_REG(hw, E1000_RCTL);
2108         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2109         temp_rctl |= E1000_RCTL_LPE;
2110
2111         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2112         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2113         E1000_WRITE_FLUSH(hw);
2114         msec_delay(2);
2115
2116         /* Enable Rx queues that were previously enabled and restore our
2117          * previous state
2118          */
2119         for (i = 0; i < 4; i++)
2120                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2121         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2122         E1000_WRITE_FLUSH(hw);
2123
2124         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2125         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2126
2127         /* Flush receive errors generated by workaround */
2128         E1000_READ_REG(hw, E1000_ROC);
2129         E1000_READ_REG(hw, E1000_RNBC);
2130         E1000_READ_REG(hw, E1000_MPC);
2131 }
2132
2133 /**
2134  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2135  *  @hw: pointer to the HW structure
2136  *
2137  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2138  *  however the hardware default for these parts is 500us to 1ms which is less
2139  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2140  *  increase the value to either 10ms to 200ms for capability version 1 config,
2141  *  or 16ms to 55ms for version 2.
2142  **/
2143 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2144 {
2145         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2146         s32 ret_val = E1000_SUCCESS;
2147         u16 pcie_devctl2;
2148
2149         /* only take action if timeout value is defaulted to 0 */
2150         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2151                 goto out;
2152
2153         /*
2154          * if capababilities version is type 1 we can write the
2155          * timeout of 10ms to 200ms through the GCR register
2156          */
2157         if (!(gcr & E1000_GCR_CAP_VER2)) {
2158                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2159                 goto out;
2160         }
2161
2162         /*
2163          * for version 2 capabilities we need to write the config space
2164          * directly in order to set the completion timeout value for
2165          * 16ms to 55ms
2166          */
2167         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2168                                           &pcie_devctl2);
2169         if (ret_val)
2170                 goto out;
2171
2172         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2173
2174         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2175                                            &pcie_devctl2);
2176 out:
2177         /* disable completion timeout resend */
2178         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2179
2180         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2181         return ret_val;
2182 }
2183
2184 /**
2185  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2186  *  @hw: pointer to the hardware struct
2187  *  @enable: state to enter, either enabled or disabled
2188  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2189  *
2190  *  enables/disables L2 switch anti-spoofing functionality.
2191  **/
2192 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2193 {
2194         u32 dtxswc;
2195
2196         switch (hw->mac.type) {
2197         case e1000_82576:
2198                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2199                 if (enable) {
2200                         dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2201                                    E1000_DTXSWC_VLAN_SPOOF_MASK);
2202                         /* The PF can spoof - it has to in order to
2203                          * support emulation mode NICs */
2204                         dtxswc ^= (1 << pf | 1 << (pf +
2205                                    E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2206                 } else {
2207                         dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2208                                     E1000_DTXSWC_VLAN_SPOOF_MASK);
2209                 }
2210                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2211                 break;
2212         case e1000_i350:
2213                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2214                 if (enable) {
2215                         dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2216                                    E1000_DTXSWC_VLAN_SPOOF_MASK);
2217                         /* The PF can spoof - it has to in order to
2218                          * support emulation mode NICs
2219                          */
2220                         dtxswc ^= (1 << pf | 1 << (pf +
2221                                    E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2222                 } else {
2223                         dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2224                                     E1000_DTXSWC_VLAN_SPOOF_MASK);
2225                 }
2226                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2227         default:
2228                 break;
2229         }
2230 }
2231
2232 /**
2233  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2234  *  @hw: pointer to the hardware struct
2235  *  @enable: state to enter, either enabled or disabled
2236  *
2237  *  enables/disables L2 switch loopback functionality.
2238  **/
2239 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2240 {
2241         u32 dtxswc;
2242
2243         switch (hw->mac.type) {
2244         case e1000_82576:
2245                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2246                 if (enable)
2247                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2248                 else
2249                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2250                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2251                 break;
2252         case e1000_i350:
2253                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2254                 if (enable)
2255                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2256                 else
2257                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2258                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2259                 break;
2260         default:
2261                 /* Currently no other hardware supports loopback */
2262                 break;
2263         }
2264
2265
2266 }
2267
2268 /**
2269  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2270  *  @hw: pointer to the hardware struct
2271  *  @enable: state to enter, either enabled or disabled
2272  *
2273  *  enables/disables replication of packets across multiple pools.
2274  **/
2275 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2276 {
2277         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2278
2279         if (enable)
2280                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2281         else
2282                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2283
2284         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2285 }
2286
2287 /**
2288  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2289  *  @hw: pointer to the HW structure
2290  *  @offset: register offset to be read
2291  *  @data: pointer to the read data
2292  *
2293  *  Reads the MDI control register in the PHY at offset and stores the
2294  *  information read to data.
2295  **/
2296 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2297 {
2298         s32 ret_val;
2299
2300         DEBUGFUNC("e1000_read_phy_reg_82580");
2301
2302         ret_val = hw->phy.ops.acquire(hw);
2303         if (ret_val)
2304                 goto out;
2305
2306         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2307
2308         hw->phy.ops.release(hw);
2309
2310 out:
2311         return ret_val;
2312 }
2313
2314 /**
2315  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2316  *  @hw: pointer to the HW structure
2317  *  @offset: register offset to write to
2318  *  @data: data to write to register at offset
2319  *
2320  *  Writes data to MDI control register in the PHY at offset.
2321  **/
2322 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2323 {
2324         s32 ret_val;
2325
2326         DEBUGFUNC("e1000_write_phy_reg_82580");
2327
2328         ret_val = hw->phy.ops.acquire(hw);
2329         if (ret_val)
2330                 goto out;
2331
2332         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2333
2334         hw->phy.ops.release(hw);
2335
2336 out:
2337         return ret_val;
2338 }
2339
2340 /**
2341  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2342  *  @hw: pointer to the HW structure
2343  *
2344  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2345  *  the values found in the EEPROM.  This addresses an issue in which these
2346  *  bits are not restored from EEPROM after reset.
2347  **/
2348 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2349 {
2350         s32 ret_val = E1000_SUCCESS;
2351         u32 mdicnfg;
2352         u16 nvm_data = 0;
2353
2354         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2355
2356         if (hw->mac.type != e1000_82580)
2357                 goto out;
2358         if (!e1000_sgmii_active_82575(hw))
2359                 goto out;
2360
2361         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2362                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2363                                    &nvm_data);
2364         if (ret_val) {
2365                 DEBUGOUT("NVM Read Error\n");
2366                 goto out;
2367         }
2368
2369         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2370         if (nvm_data & NVM_WORD24_EXT_MDIO)
2371                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2372         if (nvm_data & NVM_WORD24_COM_MDIO)
2373                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2374         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2375 out:
2376         return ret_val;
2377 }
2378
2379 /**
2380  *  e1000_reset_hw_82580 - Reset hardware
2381  *  @hw: pointer to the HW structure
2382  *
2383  *  This resets function or entire device (all ports, etc.)
2384  *  to a known state.
2385  **/
2386 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2387 {
2388         s32 ret_val = E1000_SUCCESS;
2389         /* BH SW mailbox bit in SW_FW_SYNC */
2390         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2391         u32 ctrl;
2392         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2393
2394         DEBUGFUNC("e1000_reset_hw_82580");
2395
2396         hw->dev_spec._82575.global_device_reset = false;
2397
2398         /* Get current control state. */
2399         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2400
2401         /*
2402          * Prevent the PCI-E bus from sticking if there is no TLP connection
2403          * on the last TLP read/write transaction when MAC is reset.
2404          */
2405         ret_val = e1000_disable_pcie_master_generic(hw);
2406         if (ret_val)
2407                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2408
2409         DEBUGOUT("Masking off all interrupts\n");
2410         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2411         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2412         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2413         E1000_WRITE_FLUSH(hw);
2414
2415         msec_delay(10);
2416
2417         /* Determine whether or not a global dev reset is requested */
2418         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2419             swmbsw_mask))
2420                         global_device_reset = false;
2421
2422         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2423             E1000_STAT_DEV_RST_SET))
2424                 ctrl |= E1000_CTRL_DEV_RST;
2425         else
2426                 ctrl |= E1000_CTRL_RST;
2427
2428         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2429         E1000_WRITE_FLUSH(hw);
2430
2431         /* Add delay to insure DEV_RST has time to complete */
2432         if (global_device_reset)
2433                 msec_delay(5);
2434
2435         ret_val = e1000_get_auto_rd_done_generic(hw);
2436         if (ret_val) {
2437                 /*
2438                  * When auto config read does not complete, do not
2439                  * return with an error. This can happen in situations
2440                  * where there is no eeprom and prevents getting link.
2441                  */
2442                 DEBUGOUT("Auto Read Done did not complete\n");
2443         }
2444
2445         /* If EEPROM is not present, run manual init scripts */
2446         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2447                 e1000_reset_init_script_82575(hw);
2448
2449         /* clear global device reset status bit */
2450         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2451
2452         /* Clear any pending interrupt events. */
2453         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2454         E1000_READ_REG(hw, E1000_ICR);
2455
2456         ret_val = e1000_reset_mdicnfg_82580(hw);
2457         if (ret_val)
2458                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2459
2460         /* Install any alternate MAC address into RAR0 */
2461         ret_val = e1000_check_alt_mac_addr_generic(hw);
2462
2463         /* Release semaphore */
2464         if (global_device_reset)
2465                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2466
2467         return ret_val;
2468 }
2469
2470 /**
2471  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2472  *  @data: data received by reading RXPBS register
2473  *
2474  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2475  *  This function converts the retrieved value into the correct table value
2476  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2477  *  0x0 36  72 144   1   2   4   8  16
2478  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2479  */
2480 u16 e1000_rxpbs_adjust_82580(u32 data)
2481 {
2482         u16 ret_val = 0;
2483
2484         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2485                 ret_val = e1000_82580_rxpbs_table[data];
2486
2487         return ret_val;
2488 }
2489
2490 /**
2491  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2492  *  checksum
2493  *  @hw: pointer to the HW structure
2494  *  @offset: offset in words of the checksum protected region
2495  *
2496  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2497  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2498  **/
2499 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2500 {
2501         s32 ret_val = E1000_SUCCESS;
2502         u16 checksum = 0;
2503         u16 i, nvm_data;
2504
2505         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2506
2507         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2508                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2509                 if (ret_val) {
2510                         DEBUGOUT("NVM Read Error\n");
2511                         goto out;
2512                 }
2513                 checksum += nvm_data;
2514         }
2515
2516         if (checksum != (u16) NVM_SUM) {
2517                 DEBUGOUT("NVM Checksum Invalid\n");
2518                 ret_val = -E1000_ERR_NVM;
2519                 goto out;
2520         }
2521
2522 out:
2523         return ret_val;
2524 }
2525
2526 /**
2527  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2528  *  checksum
2529  *  @hw: pointer to the HW structure
2530  *  @offset: offset in words of the checksum protected region
2531  *
2532  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2533  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2534  *  value to the EEPROM.
2535  **/
2536 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2537 {
2538         s32 ret_val;
2539         u16 checksum = 0;
2540         u16 i, nvm_data;
2541
2542         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2543
2544         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2545                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2546                 if (ret_val) {
2547                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2548                         goto out;
2549                 }
2550                 checksum += nvm_data;
2551         }
2552         checksum = (u16) NVM_SUM - checksum;
2553         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2554                                     &checksum);
2555         if (ret_val)
2556                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2557
2558 out:
2559         return ret_val;
2560 }
2561
2562 /**
2563  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2564  *  @hw: pointer to the HW structure
2565  *
2566  *  Calculates the EEPROM section checksum by reading/adding each word of
2567  *  the EEPROM and then verifies that the sum of the EEPROM is
2568  *  equal to 0xBABA.
2569  **/
2570 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2571 {
2572         s32 ret_val = E1000_SUCCESS;
2573         u16 eeprom_regions_count = 1;
2574         u16 j, nvm_data;
2575         u16 nvm_offset;
2576
2577         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2578
2579         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2580         if (ret_val) {
2581                 DEBUGOUT("NVM Read Error\n");
2582                 goto out;
2583         }
2584
2585         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2586                 /* if chekcsums compatibility bit is set validate checksums
2587                  * for all 4 ports. */
2588                 eeprom_regions_count = 4;
2589         }
2590
2591         for (j = 0; j < eeprom_regions_count; j++) {
2592                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2593                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2594                                                                   nvm_offset);
2595                 if (ret_val != E1000_SUCCESS)
2596                         goto out;
2597         }
2598
2599 out:
2600         return ret_val;
2601 }
2602
2603 /**
2604  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2605  *  @hw: pointer to the HW structure
2606  *
2607  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2608  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2609  *  checksum and writes the value to the EEPROM.
2610  **/
2611 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2612 {
2613         s32 ret_val;
2614         u16 j, nvm_data;
2615         u16 nvm_offset;
2616
2617         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2618
2619         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2620         if (ret_val) {
2621                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2622                 goto out;
2623         }
2624
2625         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2626                 /* set compatibility bit to validate checksums appropriately */
2627                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2628                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2629                                             &nvm_data);
2630                 if (ret_val) {
2631                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2632                         goto out;
2633                 }
2634         }
2635
2636         for (j = 0; j < 4; j++) {
2637                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2638                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2639                 if (ret_val)
2640                         goto out;
2641         }
2642
2643 out:
2644         return ret_val;
2645 }
2646
2647 /**
2648  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2649  *  @hw: pointer to the HW structure
2650  *
2651  *  Calculates the EEPROM section checksum by reading/adding each word of
2652  *  the EEPROM and then verifies that the sum of the EEPROM is
2653  *  equal to 0xBABA.
2654  **/
2655 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2656 {
2657         s32 ret_val = E1000_SUCCESS;
2658         u16 j;
2659         u16 nvm_offset;
2660
2661         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2662
2663         for (j = 0; j < 4; j++) {
2664                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2665                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2666                                                                   nvm_offset);
2667                 if (ret_val != E1000_SUCCESS)
2668                         goto out;
2669         }
2670
2671 out:
2672         return ret_val;
2673 }
2674
2675 /**
2676  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2677  *  @hw: pointer to the HW structure
2678  *
2679  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2680  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2681  *  checksum and writes the value to the EEPROM.
2682  **/
2683 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2684 {
2685         s32 ret_val = E1000_SUCCESS;
2686         u16 j;
2687         u16 nvm_offset;
2688
2689         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2690
2691         for (j = 0; j < 4; j++) {
2692                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2693                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2694                 if (ret_val != E1000_SUCCESS)
2695                         goto out;
2696         }
2697
2698 out:
2699         return ret_val;
2700 }
2701
2702 /**
2703  *  e1000_set_eee_i350 - Enable/disable EEE support
2704  *  @hw: pointer to the HW structure
2705  *
2706  *  Enable/disable EEE based on setting in dev_spec structure.
2707  *
2708  **/
2709 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2710 {
2711         s32 ret_val = E1000_SUCCESS;
2712         u32 ipcnfg, eeer;
2713
2714         DEBUGFUNC("e1000_set_eee_i350");
2715
2716         if ((hw->mac.type < e1000_i350) ||
2717             (hw->phy.media_type != e1000_media_type_copper))
2718                 goto out;
2719         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2720         eeer = E1000_READ_REG(hw, E1000_EEER);
2721
2722         /* enable or disable per user setting */
2723         if (!(hw->dev_spec._82575.eee_disable)) {
2724                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2725
2726                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2727                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2728                          E1000_EEER_LPI_FC);
2729
2730                 /* This bit should not be set in normal operation. */
2731                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2732                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2733         } else {
2734                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2735                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2736                           E1000_EEER_LPI_FC);
2737         }
2738         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2739         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2740         E1000_READ_REG(hw, E1000_IPCNFG);
2741         E1000_READ_REG(hw, E1000_EEER);
2742 out:
2743
2744         return ret_val;
2745 }
2746
2747 /* Due to a hw errata, if the host tries to  configure the VFTA register
2748  * while performing queries from the BMC or DMA, then the VFTA in some
2749  * cases won't be written.
2750  */
2751
2752 /**
2753  *  e1000_clear_vfta_i350 - Clear VLAN filter table
2754  *  @hw: pointer to the HW structure
2755  *
2756  *  Clears the register array which contains the VLAN filter table by
2757  *  setting all the values to 0.
2758  **/
2759 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2760 {
2761         u32 offset;
2762         int i;
2763
2764         DEBUGFUNC("e1000_clear_vfta_350");
2765
2766         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2767                 for (i = 0; i < 10; i++)
2768                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2769
2770                 E1000_WRITE_FLUSH(hw);
2771         }
2772 }
2773
2774 /**
2775  *  e1000_write_vfta_i350 - Write value to VLAN filter table
2776  *  @hw: pointer to the HW structure
2777  *  @offset: register offset in VLAN filter table
2778  *  @value: register value written to VLAN filter table
2779  *
2780  *  Writes value at the given offset in the register array which stores
2781  *  the VLAN filter table.
2782  **/
2783 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2784 {
2785         int i;
2786
2787         DEBUGFUNC("e1000_write_vfta_350");
2788
2789         for (i = 0; i < 10; i++)
2790                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2791
2792         E1000_WRITE_FLUSH(hw);
2793 }
2794
2795
2796 /**
2797  *  e1000_set_i2c_bb - Enable I2C bit-bang
2798  *  @hw: pointer to the HW structure
2799  *
2800  *  Enable I2C bit-bang interface
2801  *
2802  **/
2803 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2804 {
2805         s32 ret_val = E1000_SUCCESS;
2806         u32 ctrl_ext, i2cparams;
2807
2808         DEBUGFUNC("e1000_set_i2c_bb");
2809
2810         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2811         ctrl_ext |= E1000_CTRL_I2C_ENA;
2812         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2813         E1000_WRITE_FLUSH(hw);
2814
2815         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2816         i2cparams |= E1000_I2CBB_EN;
2817         i2cparams |= E1000_I2C_DATA_OE_N;
2818         i2cparams |= E1000_I2C_CLK_OE_N;
2819         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2820         E1000_WRITE_FLUSH(hw);
2821
2822         return ret_val;
2823 }
2824
2825 /**
2826  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2827  *  @hw: pointer to hardware structure
2828  *  @byte_offset: byte offset to read
2829  *  @dev_addr: device address
2830  *  @data: value read
2831  *
2832  *  Performs byte read operation over I2C interface at
2833  *  a specified device address.
2834  **/
2835 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2836                                 u8 dev_addr, u8 *data)
2837 {
2838         s32 status = E1000_SUCCESS;
2839         u32 max_retry = 10;
2840         u32 retry = 1;
2841         u16 swfw_mask = 0;
2842
2843         bool nack = true;
2844
2845         DEBUGFUNC("e1000_read_i2c_byte_generic");
2846
2847         swfw_mask = E1000_SWFW_PHY0_SM;
2848
2849         do {
2850                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2851                     != E1000_SUCCESS) {
2852                         status = E1000_ERR_SWFW_SYNC;
2853                         goto read_byte_out;
2854                 }
2855
2856                 e1000_i2c_start(hw);
2857
2858                 /* Device Address and write indication */
2859                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2860                 if (status != E1000_SUCCESS)
2861                         goto fail;
2862
2863                 status = e1000_get_i2c_ack(hw);
2864                 if (status != E1000_SUCCESS)
2865                         goto fail;
2866
2867                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2868                 if (status != E1000_SUCCESS)
2869                         goto fail;
2870
2871                 status = e1000_get_i2c_ack(hw);
2872                 if (status != E1000_SUCCESS)
2873                         goto fail;
2874
2875                 e1000_i2c_start(hw);
2876
2877                 /* Device Address and read indication */
2878                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2879                 if (status != E1000_SUCCESS)
2880                         goto fail;
2881
2882                 status = e1000_get_i2c_ack(hw);
2883                 if (status != E1000_SUCCESS)
2884                         goto fail;
2885
2886                 status = e1000_clock_in_i2c_byte(hw, data);
2887                 if (status != E1000_SUCCESS)
2888                         goto fail;
2889
2890                 status = e1000_clock_out_i2c_bit(hw, nack);
2891                 if (status != E1000_SUCCESS)
2892                         goto fail;
2893
2894                 e1000_i2c_stop(hw);
2895                 break;
2896
2897 fail:
2898                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2899                 msec_delay(100);
2900                 e1000_i2c_bus_clear(hw);
2901                 retry++;
2902                 if (retry < max_retry)
2903                         DEBUGOUT("I2C byte read error - Retrying.\n");
2904                 else
2905                         DEBUGOUT("I2C byte read error.\n");
2906
2907         } while (retry < max_retry);
2908
2909         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2910
2911 read_byte_out:
2912
2913         return status;
2914 }
2915
2916 /**
2917  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2918  *  @hw: pointer to hardware structure
2919  *  @byte_offset: byte offset to write
2920  *  @dev_addr: device address
2921  *  @data: value to write
2922  *
2923  *  Performs byte write operation over I2C interface at
2924  *  a specified device address.
2925  **/
2926 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2927                                  u8 dev_addr, u8 data)
2928 {
2929         s32 status = E1000_SUCCESS;
2930         u32 max_retry = 1;
2931         u32 retry = 0;
2932         u16 swfw_mask = 0;
2933
2934         DEBUGFUNC("e1000_write_i2c_byte_generic");
2935
2936         swfw_mask = E1000_SWFW_PHY0_SM;
2937
2938         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2939                 status = E1000_ERR_SWFW_SYNC;
2940                 goto write_byte_out;
2941         }
2942
2943         do {
2944                 e1000_i2c_start(hw);
2945
2946                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2947                 if (status != E1000_SUCCESS)
2948                         goto fail;
2949
2950                 status = e1000_get_i2c_ack(hw);
2951                 if (status != E1000_SUCCESS)
2952                         goto fail;
2953
2954                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2955                 if (status != E1000_SUCCESS)
2956                         goto fail;
2957
2958                 status = e1000_get_i2c_ack(hw);
2959                 if (status != E1000_SUCCESS)
2960                         goto fail;
2961
2962                 status = e1000_clock_out_i2c_byte(hw, data);
2963                 if (status != E1000_SUCCESS)
2964                         goto fail;
2965
2966                 status = e1000_get_i2c_ack(hw);
2967                 if (status != E1000_SUCCESS)
2968                         goto fail;
2969
2970                 e1000_i2c_stop(hw);
2971                 break;
2972
2973 fail:
2974                 e1000_i2c_bus_clear(hw);
2975                 retry++;
2976                 if (retry < max_retry)
2977                         DEBUGOUT("I2C byte write error - Retrying.\n");
2978                 else
2979                         DEBUGOUT("I2C byte write error.\n");
2980         } while (retry < max_retry);
2981
2982         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2983
2984 write_byte_out:
2985
2986         return status;
2987 }
2988
2989 /**
2990  *  e1000_i2c_start - Sets I2C start condition
2991  *  @hw: pointer to hardware structure
2992  *
2993  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2994  **/
2995 STATIC void e1000_i2c_start(struct e1000_hw *hw)
2996 {
2997         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2998
2999         DEBUGFUNC("e1000_i2c_start");
3000
3001         /* Start condition must begin with data and clock high */
3002         e1000_set_i2c_data(hw, &i2cctl, 1);
3003         e1000_raise_i2c_clk(hw, &i2cctl);
3004
3005         /* Setup time for start condition (4.7us) */
3006         usec_delay(E1000_I2C_T_SU_STA);
3007
3008         e1000_set_i2c_data(hw, &i2cctl, 0);
3009
3010         /* Hold time for start condition (4us) */
3011         usec_delay(E1000_I2C_T_HD_STA);
3012
3013         e1000_lower_i2c_clk(hw, &i2cctl);
3014
3015         /* Minimum low period of clock is 4.7 us */
3016         usec_delay(E1000_I2C_T_LOW);
3017
3018 }
3019
3020 /**
3021  *  e1000_i2c_stop - Sets I2C stop condition
3022  *  @hw: pointer to hardware structure
3023  *
3024  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3025  **/
3026 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3027 {
3028         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3029
3030         DEBUGFUNC("e1000_i2c_stop");
3031
3032         /* Stop condition must begin with data low and clock high */
3033         e1000_set_i2c_data(hw, &i2cctl, 0);
3034         e1000_raise_i2c_clk(hw, &i2cctl);
3035
3036         /* Setup time for stop condition (4us) */
3037         usec_delay(E1000_I2C_T_SU_STO);
3038
3039         e1000_set_i2c_data(hw, &i2cctl, 1);
3040
3041         /* bus free time between stop and start (4.7us)*/
3042         usec_delay(E1000_I2C_T_BUF);
3043 }
3044
3045 /**
3046  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3047  *  @hw: pointer to hardware structure
3048  *  @data: data byte to clock in
3049  *
3050  *  Clocks in one byte data via I2C data/clock
3051  **/
3052 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3053 {
3054         s32 i;
3055         bool bit = 0;
3056
3057         DEBUGFUNC("e1000_clock_in_i2c_byte");
3058
3059         *data = 0;
3060         for (i = 7; i >= 0; i--) {
3061                 e1000_clock_in_i2c_bit(hw, &bit);
3062                 *data |= bit << i;
3063         }
3064
3065         return E1000_SUCCESS;
3066 }
3067
3068 /**
3069  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3070  *  @hw: pointer to hardware structure
3071  *  @data: data byte clocked out
3072  *
3073  *  Clocks out one byte data via I2C data/clock
3074  **/
3075 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3076 {
3077         s32 status = E1000_SUCCESS;
3078         s32 i;
3079         u32 i2cctl;
3080         bool bit = 0;
3081
3082         DEBUGFUNC("e1000_clock_out_i2c_byte");
3083
3084         for (i = 7; i >= 0; i--) {
3085                 bit = (data >> i) & 0x1;
3086                 status = e1000_clock_out_i2c_bit(hw, bit);
3087
3088                 if (status != E1000_SUCCESS)
3089                         break;
3090         }
3091
3092         /* Release SDA line (set high) */
3093         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3094
3095         i2cctl |= E1000_I2C_DATA_OE_N;
3096         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3097         E1000_WRITE_FLUSH(hw);
3098
3099         return status;
3100 }
3101
3102 /**
3103  *  e1000_get_i2c_ack - Polls for I2C ACK
3104  *  @hw: pointer to hardware structure
3105  *
3106  *  Clocks in/out one bit via I2C data/clock
3107  **/
3108 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3109 {
3110         s32 status = E1000_SUCCESS;
3111         u32 i = 0;
3112         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3113         u32 timeout = 10;
3114         bool ack = true;
3115
3116         DEBUGFUNC("e1000_get_i2c_ack");
3117
3118         e1000_raise_i2c_clk(hw, &i2cctl);
3119
3120         /* Minimum high period of clock is 4us */
3121         usec_delay(E1000_I2C_T_HIGH);
3122
3123         /* Wait until SCL returns high */
3124         for (i = 0; i < timeout; i++) {
3125                 usec_delay(1);
3126                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3127                 if (i2cctl & E1000_I2C_CLK_IN)
3128                         break;
3129         }
3130         if (!(i2cctl & E1000_I2C_CLK_IN))
3131                 return E1000_ERR_I2C;
3132
3133         ack = e1000_get_i2c_data(&i2cctl);
3134         if (ack) {
3135                 DEBUGOUT("I2C ack was not received.\n");
3136                 status = E1000_ERR_I2C;
3137         }
3138
3139         e1000_lower_i2c_clk(hw, &i2cctl);
3140
3141         /* Minimum low period of clock is 4.7 us */
3142         usec_delay(E1000_I2C_T_LOW);
3143
3144         return status;
3145 }
3146
3147 /**
3148  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3149  *  @hw: pointer to hardware structure
3150  *  @data: read data value
3151  *
3152  *  Clocks in one bit via I2C data/clock
3153  **/
3154 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3155 {
3156         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3157
3158         DEBUGFUNC("e1000_clock_in_i2c_bit");
3159
3160         e1000_raise_i2c_clk(hw, &i2cctl);
3161
3162         /* Minimum high period of clock is 4us */
3163         usec_delay(E1000_I2C_T_HIGH);
3164
3165         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3166         *data = e1000_get_i2c_data(&i2cctl);
3167
3168         e1000_lower_i2c_clk(hw, &i2cctl);
3169
3170         /* Minimum low period of clock is 4.7 us */
3171         usec_delay(E1000_I2C_T_LOW);
3172
3173         return E1000_SUCCESS;
3174 }
3175
3176 /**
3177  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3178  *  @hw: pointer to hardware structure
3179  *  @data: data value to write
3180  *
3181  *  Clocks out one bit via I2C data/clock
3182  **/
3183 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3184 {
3185         s32 status;
3186         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3187
3188         DEBUGFUNC("e1000_clock_out_i2c_bit");
3189
3190         status = e1000_set_i2c_data(hw, &i2cctl, data);
3191         if (status == E1000_SUCCESS) {
3192                 e1000_raise_i2c_clk(hw, &i2cctl);
3193
3194                 /* Minimum high period of clock is 4us */
3195                 usec_delay(E1000_I2C_T_HIGH);
3196
3197                 e1000_lower_i2c_clk(hw, &i2cctl);
3198
3199                 /* Minimum low period of clock is 4.7 us.
3200                  * This also takes care of the data hold time.
3201                  */
3202                 usec_delay(E1000_I2C_T_LOW);
3203         } else {
3204                 status = E1000_ERR_I2C;
3205                 DEBUGOUT1("I2C data was not set to %X\n", data);
3206         }
3207
3208         return status;
3209 }
3210 /**
3211  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3212  *  @hw: pointer to hardware structure
3213  *  @i2cctl: Current value of I2CCTL register
3214  *
3215  *  Raises the I2C clock line '0'->'1'
3216  **/
3217 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3218 {
3219         DEBUGFUNC("e1000_raise_i2c_clk");
3220
3221         *i2cctl |= E1000_I2C_CLK_OUT;
3222         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3223         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3224         E1000_WRITE_FLUSH(hw);
3225
3226         /* SCL rise time (1000ns) */
3227         usec_delay(E1000_I2C_T_RISE);
3228 }
3229
3230 /**
3231  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3232  *  @hw: pointer to hardware structure
3233  *  @i2cctl: Current value of I2CCTL register
3234  *
3235  *  Lowers the I2C clock line '1'->'0'
3236  **/
3237 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3238 {
3239
3240         DEBUGFUNC("e1000_lower_i2c_clk");
3241
3242         *i2cctl &= ~E1000_I2C_CLK_OUT;
3243         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3244         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3245         E1000_WRITE_FLUSH(hw);
3246
3247         /* SCL fall time (300ns) */
3248         usec_delay(E1000_I2C_T_FALL);
3249 }
3250
3251 /**
3252  *  e1000_set_i2c_data - Sets the I2C data bit
3253  *  @hw: pointer to hardware structure
3254  *  @i2cctl: Current value of I2CCTL register
3255  *  @data: I2C data value (0 or 1) to set
3256  *
3257  *  Sets the I2C data bit
3258  **/
3259 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3260 {
3261         s32 status = E1000_SUCCESS;
3262
3263         DEBUGFUNC("e1000_set_i2c_data");
3264
3265         if (data)
3266                 *i2cctl |= E1000_I2C_DATA_OUT;
3267         else
3268                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3269
3270         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3271         *i2cctl |= E1000_I2C_CLK_OE_N;
3272         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3273         E1000_WRITE_FLUSH(hw);
3274
3275         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3276         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3277
3278         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3279         if (data != e1000_get_i2c_data(i2cctl)) {
3280                 status = E1000_ERR_I2C;
3281                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3282         }
3283
3284         return status;
3285 }
3286
3287 /**
3288  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3289  *  @hw: pointer to hardware structure
3290  *  @i2cctl: Current value of I2CCTL register
3291  *
3292  *  Returns the I2C data bit value
3293  **/
3294 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3295 {
3296         bool data;
3297
3298         DEBUGFUNC("e1000_get_i2c_data");
3299
3300         if (*i2cctl & E1000_I2C_DATA_IN)
3301                 data = 1;
3302         else
3303                 data = 0;
3304
3305         return data;
3306 }
3307
3308 /**
3309  *  e1000_i2c_bus_clear - Clears the I2C bus
3310  *  @hw: pointer to hardware structure
3311  *
3312  *  Clears the I2C bus by sending nine clock pulses.
3313  *  Used when data line is stuck low.
3314  **/
3315 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3316 {
3317         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3318         u32 i;
3319
3320         DEBUGFUNC("e1000_i2c_bus_clear");
3321
3322         e1000_i2c_start(hw);
3323
3324         e1000_set_i2c_data(hw, &i2cctl, 1);
3325
3326         for (i = 0; i < 9; i++) {
3327                 e1000_raise_i2c_clk(hw, &i2cctl);
3328
3329                 /* Min high period of clock is 4us */
3330                 usec_delay(E1000_I2C_T_HIGH);
3331
3332                 e1000_lower_i2c_clk(hw, &i2cctl);
3333
3334                 /* Min low period of clock is 4.7us*/
3335                 usec_delay(E1000_I2C_T_LOW);
3336         }
3337
3338         e1000_i2c_start(hw);
3339
3340         /* Put the i2c bus back to default state */
3341         e1000_i2c_stop(hw);
3342 }
3343