lib/librte_pmd_e1000/e1000/e1000_hw.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _E1000_HW_H_
  35 #define _E1000_HW_H_
  36
  37 #include "e1000_osdep.h"
  38 #include "e1000_regs.h"
  39 #include "e1000_defines.h"
  40
  41 struct e1000_hw;
  42
  43 #define E1000_DEV_ID_82542                      0x1000
  44 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  45 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  46 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  47 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  48 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  49 #define E1000_DEV_ID_82544GC_LOM                0x100D
  50 #define E1000_DEV_ID_82540EM                    0x100E
  51 #define E1000_DEV_ID_82540EM_LOM                0x1015
  52 #define E1000_DEV_ID_82540EP_LOM                0x1016
  53 #define E1000_DEV_ID_82540EP                    0x1017
  54 #define E1000_DEV_ID_82540EP_LP                 0x101E
  55 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  56 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  57 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  58 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  59 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  60 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  61 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  62 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  63 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  64 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  65 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  66 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  67 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  69 #define E1000_DEV_ID_82541EI                    0x1013
  70 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  71 #define E1000_DEV_ID_82541ER_LOM                0x1014
  72 #define E1000_DEV_ID_82541ER                    0x1078
  73 #define E1000_DEV_ID_82541GI                    0x1076
  74 #define E1000_DEV_ID_82541GI_LF                 0x107C
  75 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  76 #define E1000_DEV_ID_82547EI                    0x1019
  77 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  78 #define E1000_DEV_ID_82547GI                    0x1075
  79 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  80 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  81 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  82 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  83 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  84 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  85 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  86 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  87 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  88 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  89 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  90 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  91 #define E1000_DEV_ID_82572EI                    0x10B9
  92 #define E1000_DEV_ID_82573E                     0x108B
  93 #define E1000_DEV_ID_82573E_IAMT                0x108C
  94 #define E1000_DEV_ID_82573L                     0x109A
  95 #define E1000_DEV_ID_82574L                     0x10D3
  96 #define E1000_DEV_ID_82574LA                    0x10F6
  97 #define E1000_DEV_ID_82583V                     0x150C
  98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 102 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 103 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 104 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 105 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 106 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 107 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 108 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 109 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 110 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 111 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 112 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 113 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 114 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 115 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 116 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 117 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 118 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 119 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 120 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 121 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 122 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 123 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 124 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 125
 126 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 127 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 128 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 129 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 130 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 131 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 132 #define E1000_DEV_ID_82576                      0x10C9
 133 #define E1000_DEV_ID_82576_FIBER                0x10E6
 134 #define E1000_DEV_ID_82576_SERDES               0x10E7
 135 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 136 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 137 #define E1000_DEV_ID_82576_NS                   0x150A
 138 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 139 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 140 #define E1000_DEV_ID_82576_VF                   0x10CA
 141 #define E1000_DEV_ID_82576_VF_HV                0x152D
 142 #define E1000_DEV_ID_I350_VF                    0x1520
 143 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 144 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 145 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 146 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 147 #define E1000_DEV_ID_82580_COPPER               0x150E
 148 #define E1000_DEV_ID_82580_FIBER                0x150F
 149 #define E1000_DEV_ID_82580_SERDES               0x1510
 150 #define E1000_DEV_ID_82580_SGMII                0x1511
 151 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 152 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 153 #define E1000_DEV_ID_I350_COPPER                0x1521
 154 #define E1000_DEV_ID_I350_FIBER                 0x1522
 155 #define E1000_DEV_ID_I350_SERDES                0x1523
 156 #define E1000_DEV_ID_I350_SGMII                 0x1524
 157 #define E1000_DEV_ID_I350_DA4                   0x1546
 158 #define E1000_DEV_ID_I210_COPPER                0x1533
 159 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 160 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 161 #define E1000_DEV_ID_I210_FIBER                 0x1536
 162 #define E1000_DEV_ID_I210_SERDES                0x1537
 163 #define E1000_DEV_ID_I210_SGMII                 0x1538
 164 #define E1000_DEV_ID_I211_COPPER                0x1539
 165 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 166 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 167 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 168 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 169 #define E1000_REVISION_0        0
 170 #define E1000_REVISION_1        1
 171 #define E1000_REVISION_2        2
 172 #define E1000_REVISION_3        3
 173 #define E1000_REVISION_4        4
 174
 175 #define E1000_FUNC_0            0
 176 #define E1000_FUNC_1            1
 177 #define E1000_FUNC_2            2
 178 #define E1000_FUNC_3            3
 179
 180 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 181 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 182 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 183 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 184
 185 enum e1000_mac_type {
 186         e1000_undefined = 0,
 187         e1000_82542,
 188         e1000_82543,
 189         e1000_82544,
 190         e1000_82540,
 191         e1000_82545,
 192         e1000_82545_rev_3,
 193         e1000_82546,
 194         e1000_82546_rev_3,
 195         e1000_82541,
 196         e1000_82541_rev_2,
 197         e1000_82547,
 198         e1000_82547_rev_2,
 199         e1000_82571,
 200         e1000_82572,
 201         e1000_82573,
 202         e1000_82574,
 203         e1000_82583,
 204         e1000_80003es2lan,
 205         e1000_ich8lan,
 206         e1000_ich9lan,
 207         e1000_ich10lan,
 208         e1000_pchlan,
 209         e1000_pch2lan,
 210         e1000_82575,
 211         e1000_82576,
 212         e1000_82580,
 213         e1000_i350,
 214         e1000_i210,
 215         e1000_i211,
 216         e1000_vfadapt,
 217         e1000_vfadapt_i350,
 218         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 219 };
 220
 221 enum e1000_media_type {
 222         e1000_media_type_unknown = 0,
 223         e1000_media_type_copper = 1,
 224         e1000_media_type_fiber = 2,
 225         e1000_media_type_internal_serdes = 3,
 226         e1000_num_media_types
 227 };
 228
 229 enum e1000_nvm_type {
 230         e1000_nvm_unknown = 0,
 231         e1000_nvm_none,
 232         e1000_nvm_eeprom_spi,
 233         e1000_nvm_eeprom_microwire,
 234         e1000_nvm_flash_hw,
 235         e1000_nvm_flash_sw
 236 };
 237
 238 enum e1000_nvm_override {
 239         e1000_nvm_override_none = 0,
 240         e1000_nvm_override_spi_small,
 241         e1000_nvm_override_spi_large,
 242         e1000_nvm_override_microwire_small,
 243         e1000_nvm_override_microwire_large
 244 };
 245
 246 enum e1000_phy_type {
 247         e1000_phy_unknown = 0,
 248         e1000_phy_none,
 249         e1000_phy_m88,
 250         e1000_phy_igp,
 251         e1000_phy_igp_2,
 252         e1000_phy_gg82563,
 253         e1000_phy_igp_3,
 254         e1000_phy_ife,
 255         e1000_phy_bm,
 256         e1000_phy_82578,
 257         e1000_phy_82577,
 258         e1000_phy_82579,
 259         e1000_phy_i217,
 260         e1000_phy_82580,
 261         e1000_phy_vf,
 262         e1000_phy_i210,
 263 };
 264
 265 enum e1000_bus_type {
 266         e1000_bus_type_unknown = 0,
 267         e1000_bus_type_pci,
 268         e1000_bus_type_pcix,
 269         e1000_bus_type_pci_express,
 270         e1000_bus_type_reserved
 271 };
 272
 273 enum e1000_bus_speed {
 274         e1000_bus_speed_unknown = 0,
 275         e1000_bus_speed_33,
 276         e1000_bus_speed_66,
 277         e1000_bus_speed_100,
 278         e1000_bus_speed_120,
 279         e1000_bus_speed_133,
 280         e1000_bus_speed_2500,
 281         e1000_bus_speed_5000,
 282         e1000_bus_speed_reserved
 283 };
 284
 285 enum e1000_bus_width {
 286         e1000_bus_width_unknown = 0,
 287         e1000_bus_width_pcie_x1,
 288         e1000_bus_width_pcie_x2,
 289         e1000_bus_width_pcie_x4 = 4,
 290         e1000_bus_width_pcie_x8 = 8,
 291         e1000_bus_width_32,
 292         e1000_bus_width_64,
 293         e1000_bus_width_reserved
 294 };
 295
 296 enum e1000_1000t_rx_status {
 297         e1000_1000t_rx_status_not_ok = 0,
 298         e1000_1000t_rx_status_ok,
 299         e1000_1000t_rx_status_undefined = 0xFF
 300 };
 301
 302 enum e1000_rev_polarity {
 303         e1000_rev_polarity_normal = 0,
 304         e1000_rev_polarity_reversed,
 305         e1000_rev_polarity_undefined = 0xFF
 306 };
 307
 308 enum e1000_fc_mode {
 309         e1000_fc_none = 0,
 310         e1000_fc_rx_pause,
 311         e1000_fc_tx_pause,
 312         e1000_fc_full,
 313         e1000_fc_default = 0xFF
 314 };
 315
 316 enum e1000_ffe_config {
 317         e1000_ffe_config_enabled = 0,
 318         e1000_ffe_config_active,
 319         e1000_ffe_config_blocked
 320 };
 321
 322 enum e1000_dsp_config {
 323         e1000_dsp_config_disabled = 0,
 324         e1000_dsp_config_enabled,
 325         e1000_dsp_config_activated,
 326         e1000_dsp_config_undefined = 0xFF
 327 };
 328
 329 enum e1000_ms_type {
 330         e1000_ms_hw_default = 0,
 331         e1000_ms_force_master,
 332         e1000_ms_force_slave,
 333         e1000_ms_auto
 334 };
 335
 336 enum e1000_smart_speed {
 337         e1000_smart_speed_default = 0,
 338         e1000_smart_speed_on,
 339         e1000_smart_speed_off
 340 };
 341
 342 enum e1000_serdes_link_state {
 343         e1000_serdes_link_down = 0,
 344         e1000_serdes_link_autoneg_progress,
 345         e1000_serdes_link_autoneg_complete,
 346         e1000_serdes_link_forced_up
 347 };
 348
 349 #define __le16 u16
 350 #define __le32 u32
 351 #define __le64 u64
 352 /* Receive Descriptor */
 353 struct e1000_rx_desc {
 354         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 355         __le16 length;      /* Length of data DMAed into data buffer */
 356         __le16 csum; /* Packet checksum */
 357         u8  status;  /* Descriptor status */
 358         u8  errors;  /* Descriptor Errors */
 359         __le16 special;
 360 };
 361
 362 /* Receive Descriptor - Extended */
 363 union e1000_rx_desc_extended {
 364         struct {
 365                 __le64 buffer_addr;
 366                 __le64 reserved;
 367         } read;
 368         struct {
 369                 struct {
 370                         __le32 mrq; /* Multiple Rx Queues */
 371                         union {
 372                                 __le32 rss; /* RSS Hash */
 373                                 struct {
 374                                         __le16 ip_id;  /* IP id */
 375                                         __le16 csum;   /* Packet Checksum */
 376                                 } csum_ip;
 377                         } hi_dword;
 378                 } lower;
 379                 struct {
 380                         __le32 status_error;  /* ext status/error */
 381                         __le16 length;
 382                         __le16 vlan; /* VLAN tag */
 383                 } upper;
 384         } wb;  /* writeback */
 385 };
 386
 387 #define MAX_PS_BUFFERS 4
 388 /* Receive Descriptor - Packet Split */
 389 union e1000_rx_desc_packet_split {
 390         struct {
 391                 /* one buffer for protocol header(s), three data buffers */
 392                 __le64 buffer_addr[MAX_PS_BUFFERS];
 393         } read;
 394         struct {
 395                 struct {
 396                         __le32 mrq;  /* Multiple Rx Queues */
 397                         union {
 398                                 __le32 rss; /* RSS Hash */
 399                                 struct {
 400                                         __le16 ip_id;    /* IP id */
 401                                         __le16 csum;     /* Packet Checksum */
 402                                 } csum_ip;
 403                         } hi_dword;
 404                 } lower;
 405                 struct {
 406                         __le32 status_error;  /* ext status/error */
 407                         __le16 length0;  /* length of buffer 0 */
 408                         __le16 vlan;  /* VLAN tag */
 409                 } middle;
 410                 struct {
 411                         __le16 header_status;
 412                         __le16 length[3];     /* length of buffers 1-3 */
 413                 } upper;
 414                 __le64 reserved;
 415         } wb; /* writeback */
 416 };
 417
 418 /* Transmit Descriptor */
 419 struct e1000_tx_desc {
 420         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 421         union {
 422                 __le32 data;
 423                 struct {
 424                         __le16 length;  /* Data buffer length */
 425                         u8 cso;  /* Checksum offset */
 426                         u8 cmd;  /* Descriptor control */
 427                 } flags;
 428         } lower;
 429         union {
 430                 __le32 data;
 431                 struct {
 432                         u8 status; /* Descriptor status */
 433                         u8 css;  /* Checksum start */
 434                         __le16 special;
 435                 } fields;
 436         } upper;
 437 };
 438
 439 /* Offload Context Descriptor */
 440 struct e1000_context_desc {
 441         union {
 442                 __le32 ip_config;
 443                 struct {
 444                         u8 ipcss;  /* IP checksum start */
 445                         u8 ipcso;  /* IP checksum offset */
 446                         __le16 ipcse;  /* IP checksum end */
 447                 } ip_fields;
 448         } lower_setup;
 449         union {
 450                 __le32 tcp_config;
 451                 struct {
 452                         u8 tucss;  /* TCP checksum start */
 453                         u8 tucso;  /* TCP checksum offset */
 454                         __le16 tucse;  /* TCP checksum end */
 455                 } tcp_fields;
 456         } upper_setup;
 457         __le32 cmd_and_length;
 458         union {
 459                 __le32 data;
 460                 struct {
 461                         u8 status;  /* Descriptor status */
 462                         u8 hdr_len;  /* Header length */
 463                         __le16 mss;  /* Maximum segment size */
 464                 } fields;
 465         } tcp_seg_setup;
 466 };
 467
 468 /* Offload data descriptor */
 469 struct e1000_data_desc {
 470         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 471         union {
 472                 __le32 data;
 473                 struct {
 474                         __le16 length;  /* Data buffer length */
 475                         u8 typ_len_ext;
 476                         u8 cmd;
 477                 } flags;
 478         } lower;
 479         union {
 480                 __le32 data;
 481                 struct {
 482                         u8 status;  /* Descriptor status */
 483                         u8 popts;  /* Packet Options */
 484                         __le16 special;
 485                 } fields;
 486         } upper;
 487 };
 488
 489 /* Statistics counters collected by the MAC */
 490 struct e1000_hw_stats {
 491         u64 crcerrs;
 492         u64 algnerrc;
 493         u64 symerrs;
 494         u64 rxerrc;
 495         u64 mpc;
 496         u64 scc;
 497         u64 ecol;
 498         u64 mcc;
 499         u64 latecol;
 500         u64 colc;
 501         u64 dc;
 502         u64 tncrs;
 503         u64 sec;
 504         u64 cexterr;
 505         u64 rlec;
 506         u64 xonrxc;
 507         u64 xontxc;
 508         u64 xoffrxc;
 509         u64 xofftxc;
 510         u64 fcruc;
 511         u64 prc64;
 512         u64 prc127;
 513         u64 prc255;
 514         u64 prc511;
 515         u64 prc1023;
 516         u64 prc1522;
 517         u64 gprc;
 518         u64 bprc;
 519         u64 mprc;
 520         u64 gptc;
 521         u64 gorc;
 522         u64 gotc;
 523         u64 rnbc;
 524         u64 ruc;
 525         u64 rfc;
 526         u64 roc;
 527         u64 rjc;
 528         u64 mgprc;
 529         u64 mgpdc;
 530         u64 mgptc;
 531         u64 tor;
 532         u64 tot;
 533         u64 tpr;
 534         u64 tpt;
 535         u64 ptc64;
 536         u64 ptc127;
 537         u64 ptc255;
 538         u64 ptc511;
 539         u64 ptc1023;
 540         u64 ptc1522;
 541         u64 mptc;
 542         u64 bptc;
 543         u64 tsctc;
 544         u64 tsctfc;
 545         u64 iac;
 546         u64 icrxptc;
 547         u64 icrxatc;
 548         u64 ictxptc;
 549         u64 ictxatc;
 550         u64 ictxqec;
 551         u64 ictxqmtc;
 552         u64 icrxdmtc;
 553         u64 icrxoc;
 554         u64 cbtmpc;
 555         u64 htdpmc;
 556         u64 cbrdpc;
 557         u64 cbrmpc;
 558         u64 rpthc;
 559         u64 hgptc;
 560         u64 htcbdpc;
 561         u64 hgorc;
 562         u64 hgotc;
 563         u64 lenerrs;
 564         u64 scvpc;
 565         u64 hrmpc;
 566         u64 doosync;
 567         u64 o2bgptc;
 568         u64 o2bspc;
 569         u64 b2ospc;
 570         u64 b2ogprc;
 571 };
 572
 573 struct e1000_vf_stats {
 574         u64 base_gprc;
 575         u64 base_gptc;
 576         u64 base_gorc;
 577         u64 base_gotc;
 578         u64 base_mprc;
 579         u64 base_gotlbc;
 580         u64 base_gptlbc;
 581         u64 base_gorlbc;
 582         u64 base_gprlbc;
 583
 584         u32 last_gprc;
 585         u32 last_gptc;
 586         u32 last_gorc;
 587         u32 last_gotc;
 588         u32 last_mprc;
 589         u32 last_gotlbc;
 590         u32 last_gptlbc;
 591         u32 last_gorlbc;
 592         u32 last_gprlbc;
 593
 594         u64 gprc;
 595         u64 gptc;
 596         u64 gorc;
 597         u64 gotc;
 598         u64 mprc;
 599         u64 gotlbc;
 600         u64 gptlbc;
 601         u64 gorlbc;
 602         u64 gprlbc;
 603 };
 604
 605 struct e1000_phy_stats {
 606         u32 idle_errors;
 607         u32 receive_errors;
 608 };
 609
 610 struct e1000_host_mng_dhcp_cookie {
 611         u32 signature;
 612         u8  status;
 613         u8  reserved0;
 614         u16 vlan_id;
 615         u32 reserved1;
 616         u16 reserved2;
 617         u8  reserved3;
 618         u8  checksum;
 619 };
 620
 621 /* Host Interface "Rev 1" */
 622 struct e1000_host_command_header {
 623         u8 command_id;
 624         u8 command_length;
 625         u8 command_options;
 626         u8 checksum;
 627 };
 628
 629 #define E1000_HI_MAX_DATA_LENGTH        252
 630 struct e1000_host_command_info {
 631         struct e1000_host_command_header command_header;
 632         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 633 };
 634
 635 /* Host Interface "Rev 2" */
 636 struct e1000_host_mng_command_header {
 637         u8  command_id;
 638         u8  checksum;
 639         u16 reserved1;
 640         u16 reserved2;
 641         u16 command_length;
 642 };
 643
 644 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 645 struct e1000_host_mng_command_info {
 646         struct e1000_host_mng_command_header command_header;
 647         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 648 };
 649
 650 #include "e1000_mac.h"
 651 #include "e1000_phy.h"
 652 #include "e1000_nvm.h"
 653 #include "e1000_manage.h"
 654 #include "e1000_mbx.h"
 655
 656 struct e1000_mac_operations {
 657         /* Function pointers for the MAC. */
 658         s32  (*init_params)(struct e1000_hw *);
 659         s32  (*id_led_init)(struct e1000_hw *);
 660         s32  (*blink_led)(struct e1000_hw *);
 661         s32  (*check_for_link)(struct e1000_hw *);
 662         bool (*check_mng_mode)(struct e1000_hw *hw);
 663         s32  (*cleanup_led)(struct e1000_hw *);
 664         void (*clear_hw_cntrs)(struct e1000_hw *);
 665         void (*clear_vfta)(struct e1000_hw *);
 666         s32  (*get_bus_info)(struct e1000_hw *);
 667         void (*set_lan_id)(struct e1000_hw *);
 668         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 669         s32  (*led_on)(struct e1000_hw *);
 670         s32  (*led_off)(struct e1000_hw *);
 671         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 672         s32  (*reset_hw)(struct e1000_hw *);
 673         s32  (*init_hw)(struct e1000_hw *);
 674         void (*shutdown_serdes)(struct e1000_hw *);
 675         void (*power_up_serdes)(struct e1000_hw *);
 676         s32  (*setup_link)(struct e1000_hw *);
 677         s32  (*setup_physical_interface)(struct e1000_hw *);
 678         s32  (*setup_led)(struct e1000_hw *);
 679         void (*write_vfta)(struct e1000_hw *, u32, u32);
 680         void (*config_collision_dist)(struct e1000_hw *);
 681         void (*rar_set)(struct e1000_hw *, u8*, u32);
 682         s32  (*read_mac_addr)(struct e1000_hw *);
 683         s32  (*validate_mdi_setting)(struct e1000_hw *);
 684         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 685         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 686                                      struct e1000_host_mng_command_header*);
 687         s32  (*mng_enable_host_if)(struct e1000_hw *);
 688         s32  (*wait_autoneg)(struct e1000_hw *);
 689         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 690         void (*release_swfw_sync)(struct e1000_hw *, u16);
 691 };
 692
 693 /*
 694  * When to use various PHY register access functions:
 695  *
 696  *                 Func   Caller
 697  *   Function      Does   Does    When to use
 698  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 699  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 700  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 701  *                                on different pages
 702  *   X_reg_page    A      L,P     for multiple accesses of different regs
 703  *                                on the same page
 704  *
 705  * Where X=[read|write], L=locking, P=sets page, A=register access
 706  *
 707  */
 708 struct e1000_phy_operations {
 709         s32  (*init_params)(struct e1000_hw *);
 710         s32  (*acquire)(struct e1000_hw *);
 711         s32  (*cfg_on_link_up)(struct e1000_hw *);
 712         s32  (*check_polarity)(struct e1000_hw *);
 713         s32  (*check_reset_block)(struct e1000_hw *);
 714         s32  (*commit)(struct e1000_hw *);
 715         s32  (*force_speed_duplex)(struct e1000_hw *);
 716         s32  (*get_cfg_done)(struct e1000_hw *hw);
 717         s32  (*get_cable_length)(struct e1000_hw *);
 718         s32  (*get_info)(struct e1000_hw *);
 719         s32  (*set_page)(struct e1000_hw *, u16);
 720         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 721         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 722         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 723         void (*release)(struct e1000_hw *);
 724         s32  (*reset)(struct e1000_hw *);
 725         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 726         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 727         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 728         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 729         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 730         void (*power_up)(struct e1000_hw *);
 731         void (*power_down)(struct e1000_hw *);
 732         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 733         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 734 };
 735
 736 struct e1000_nvm_operations {
 737         s32  (*init_params)(struct e1000_hw *);
 738         s32  (*acquire)(struct e1000_hw *);
 739         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 740         void (*release)(struct e1000_hw *);
 741         void (*reload)(struct e1000_hw *);
 742         s32  (*update)(struct e1000_hw *);
 743         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 744         s32  (*validate)(struct e1000_hw *);
 745         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 746 };
 747
 748 struct e1000_mac_info {
 749         struct e1000_mac_operations ops;
 750         u8 addr[ETH_ADDR_LEN];
 751         u8 perm_addr[ETH_ADDR_LEN];
 752
 753         enum e1000_mac_type type;
 754
 755         u32 collision_delta;
 756         u32 ledctl_default;
 757         u32 ledctl_mode1;
 758         u32 ledctl_mode2;
 759         u32 mc_filter_type;
 760         u32 tx_packet_delta;
 761         u32 txcw;
 762
 763         u16 current_ifs_val;
 764         u16 ifs_max_val;
 765         u16 ifs_min_val;
 766         u16 ifs_ratio;
 767         u16 ifs_step_size;
 768         u16 mta_reg_count;
 769         u16 uta_reg_count;
 770
 771         /* Maximum size of the MTA register table in all supported adapters */
 772         #define MAX_MTA_REG 128
 773         u32 mta_shadow[MAX_MTA_REG];
 774         u16 rar_entry_count;
 775
 776         u8  forced_speed_duplex;
 777
 778         bool adaptive_ifs;
 779         bool has_fwsm;
 780         bool arc_subsystem_valid;
 781         bool asf_firmware_present;
 782         bool autoneg;
 783         bool autoneg_failed;
 784         bool get_link_status;
 785         bool in_ifs_mode;
 786         bool report_tx_early;
 787         enum e1000_serdes_link_state serdes_link_state;
 788         bool serdes_has_link;
 789         bool tx_pkt_filtering;
 790 };
 791
 792 struct e1000_phy_info {
 793         struct e1000_phy_operations ops;
 794         enum e1000_phy_type type;
 795
 796         enum e1000_1000t_rx_status local_rx;
 797         enum e1000_1000t_rx_status remote_rx;
 798         enum e1000_ms_type ms_type;
 799         enum e1000_ms_type original_ms_type;
 800         enum e1000_rev_polarity cable_polarity;
 801         enum e1000_smart_speed smart_speed;
 802
 803         u32 addr;
 804         u32 id;
 805         u32 reset_delay_us; /* in usec */
 806         u32 revision;
 807
 808         enum e1000_media_type media_type;
 809
 810         u16 autoneg_advertised;
 811         u16 autoneg_mask;
 812         u16 cable_length;
 813         u16 max_cable_length;
 814         u16 min_cable_length;
 815
 816         u8 mdix;
 817
 818         bool disable_polarity_correction;
 819         bool is_mdix;
 820         bool polarity_correction;
 821         bool speed_downgraded;
 822         bool autoneg_wait_to_complete;
 823 };
 824
 825 struct e1000_nvm_info {
 826         struct e1000_nvm_operations ops;
 827         enum e1000_nvm_type type;
 828         enum e1000_nvm_override override;
 829
 830         u32 flash_bank_size;
 831         u32 flash_base_addr;
 832
 833         u16 word_size;
 834         u16 delay_usec;
 835         u16 address_bits;
 836         u16 opcode_bits;
 837         u16 page_size;
 838 };
 839
 840 struct e1000_bus_info {
 841         enum e1000_bus_type type;
 842         enum e1000_bus_speed speed;
 843         enum e1000_bus_width width;
 844
 845         u16 func;
 846         u16 pci_cmd_word;
 847 };
 848
 849 struct e1000_fc_info {
 850         u32 high_water;  /* Flow control high-water mark */
 851         u32 low_water;  /* Flow control low-water mark */
 852         u16 pause_time;  /* Flow control pause timer */
 853         u16 refresh_time;  /* Flow control refresh timer */
 854         bool send_xon;  /* Flow control send XON */
 855         bool strict_ieee;  /* Strict IEEE mode */
 856         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 857         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 858 };
 859
 860 struct e1000_mbx_operations {
 861         s32 (*init_params)(struct e1000_hw *hw);
 862         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 863         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 864         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 865         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 866         s32 (*check_for_msg)(struct e1000_hw *, u16);
 867         s32 (*check_for_ack)(struct e1000_hw *, u16);
 868         s32 (*check_for_rst)(struct e1000_hw *, u16);
 869 };
 870
 871 struct e1000_mbx_stats {
 872         u32 msgs_tx;
 873         u32 msgs_rx;
 874
 875         u32 acks;
 876         u32 reqs;
 877         u32 rsts;
 878 };
 879
 880 struct e1000_mbx_info {
 881         struct e1000_mbx_operations ops;
 882         struct e1000_mbx_stats stats;
 883         u32 timeout;
 884         u32 usec_delay;
 885         u16 size;
 886 };
 887
 888 struct e1000_dev_spec_82541 {
 889         enum e1000_dsp_config dsp_config;
 890         enum e1000_ffe_config ffe_config;
 891         u16 spd_default;
 892         bool phy_init_script;
 893 };
 894
 895 struct e1000_dev_spec_82542 {
 896         bool dma_fairness;
 897 };
 898
 899 struct e1000_dev_spec_82543 {
 900         u32  tbi_compatibility;
 901         bool dma_fairness;
 902         bool init_phy_disabled;
 903 };
 904
 905 struct e1000_dev_spec_82571 {
 906         bool laa_is_present;
 907         u32 smb_counter;
 908         E1000_MUTEX swflag_mutex;
 909 };
 910
 911 struct e1000_dev_spec_80003es2lan {
 912         bool  mdic_wa_enable;
 913 };
 914
 915 struct e1000_shadow_ram {
 916         u16  value;
 917         bool modified;
 918 };
 919
 920 #define E1000_SHADOW_RAM_WORDS  2048
 921
 922 struct e1000_dev_spec_ich8lan {
 923         bool kmrn_lock_loss_workaround_enabled;
 924         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 925         E1000_MUTEX nvm_mutex;
 926         E1000_MUTEX swflag_mutex;
 927         bool nvm_k1_enabled;
 928         bool eee_disable;
 929         u16 eee_lp_ability;
 930 };
 931
 932 struct e1000_dev_spec_82575 {
 933         bool sgmii_active;
 934         bool global_device_reset;
 935         bool eee_disable;
 936         bool module_plugged;
 937         u32 mtu;
 938         struct sfp_e1000_flags eth_flags;
 939 };
 940
 941 struct e1000_dev_spec_vf {
 942         u32 vf_number;
 943         u32 v2p_mailbox;
 944 };
 945
 946 struct e1000_hw {
 947         void *back;
 948
 949         u8 *hw_addr;
 950         u8 *flash_address;
 951         unsigned long io_base;
 952
 953         struct e1000_mac_info  mac;
 954         struct e1000_fc_info   fc;
 955         struct e1000_phy_info  phy;
 956         struct e1000_nvm_info  nvm;
 957         struct e1000_bus_info  bus;
 958         struct e1000_mbx_info mbx;
 959         struct e1000_host_mng_dhcp_cookie mng_cookie;
 960
 961         union {
 962                 struct e1000_dev_spec_82541 _82541;
 963                 struct e1000_dev_spec_82542 _82542;
 964                 struct e1000_dev_spec_82543 _82543;
 965                 struct e1000_dev_spec_82571 _82571;
 966                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 967                 struct e1000_dev_spec_ich8lan ich8lan;
 968                 struct e1000_dev_spec_82575 _82575;
 969                 struct e1000_dev_spec_vf vf;
 970         } dev_spec;
 971
 972         u16 device_id;
 973         u16 subsystem_vendor_id;
 974         u16 subsystem_device_id;
 975         u16 vendor_id;
 976
 977         u8  revision_id;
 978 };
 979
 980 #include "e1000_82541.h"
 981 #include "e1000_82543.h"
 982 #include "e1000_82571.h"
 983 #include "e1000_80003es2lan.h"
 984 #include "e1000_ich8lan.h"
 985 #include "e1000_82575.h"
 986 #include "e1000_i210.h"
 987
 988 /* These functions must be implemented by drivers */
 989 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 990 void e1000_pci_set_mwi(struct e1000_hw *hw);
 991 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 992 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 993 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 994 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 995
 996 #endif