lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 #define EM_EIAC                 0x000DC
  61
  62 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  63
  64
  65 static int eth_em_configure(struct rte_eth_dev *dev);
  66 static int eth_em_start(struct rte_eth_dev *dev);
  67 static void eth_em_stop(struct rte_eth_dev *dev);
  68 static void eth_em_close(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int eth_em_link_update(struct rte_eth_dev *dev,
  74                                 int wait_to_complete);
  75 static void eth_em_stats_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_stats *rte_stats);
  77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  78 static void eth_em_infos_get(struct rte_eth_dev *dev,
  79                                 struct rte_eth_dev_info *dev_info);
  80 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  81                                 struct rte_eth_fc_conf *fc_conf);
  82 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  83                                 struct rte_eth_fc_conf *fc_conf);
  84 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  88                                                         void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111 static int eth_em_led_on(struct rte_eth_dev *dev);
 112 static int eth_em_led_off(struct rte_eth_dev *dev);
 113
 114 static void em_intr_disable(struct e1000_hw *hw);
 115 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 116 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 117                 uint32_t index, uint32_t pool);
 118 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 119
 120 #define EM_FC_PAUSE_TIME 0x0680
 121 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 122 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 123
 124 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 125
 126 /*
 127  * The set of PCI devices this driver supports
 128  */
 129 static struct rte_pci_id pci_id_em_map[] = {
 130
 131 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 132 #include "rte_pci_dev_ids.h"
 133
 134 {.device_id = 0},
 135 };
 136
 137 static struct eth_dev_ops eth_em_ops = {
 138         .dev_configure        = eth_em_configure,
 139         .dev_start            = eth_em_start,
 140         .dev_stop             = eth_em_stop,
 141         .dev_close            = eth_em_close,
 142         .promiscuous_enable   = eth_em_promiscuous_enable,
 143         .promiscuous_disable  = eth_em_promiscuous_disable,
 144         .allmulticast_enable  = eth_em_allmulticast_enable,
 145         .allmulticast_disable = eth_em_allmulticast_disable,
 146         .link_update          = eth_em_link_update,
 147         .stats_get            = eth_em_stats_get,
 148         .stats_reset          = eth_em_stats_reset,
 149         .dev_infos_get        = eth_em_infos_get,
 150         .mtu_set              = eth_em_mtu_set,
 151         .vlan_filter_set      = eth_em_vlan_filter_set,
 152         .vlan_offload_set     = eth_em_vlan_offload_set,
 153         .rx_queue_setup       = eth_em_rx_queue_setup,
 154         .rx_queue_release     = eth_em_rx_queue_release,
 155         .rx_queue_count       = eth_em_rx_queue_count,
 156         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 157         .tx_queue_setup       = eth_em_tx_queue_setup,
 158         .tx_queue_release     = eth_em_tx_queue_release,
 159         .dev_led_on           = eth_em_led_on,
 160         .dev_led_off          = eth_em_led_off,
 161         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 162         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 163         .mac_addr_add         = eth_em_rar_set,
 164         .mac_addr_remove      = eth_em_rar_clear,
 165 };
 166
 167 /**
 168  * Atomically reads the link status information from global
 169  * structure rte_eth_dev.
 170  *
 171  * @param dev
 172  *   - Pointer to the structure rte_eth_dev to read from.
 173  *   - Pointer to the buffer to be saved with the link status.
 174  *
 175  * @return
 176  *   - On success, zero.
 177  *   - On failure, negative value.
 178  */
 179 static inline int
 180 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 181                                 struct rte_eth_link *link)
 182 {
 183         struct rte_eth_link *dst = link;
 184         struct rte_eth_link *src = &(dev->data->dev_link);
 185
 186         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 187                                         *(uint64_t *)src) == 0)
 188                 return -1;
 189
 190         return 0;
 191 }
 192
 193 /**
 194  * Atomically writes the link status information into global
 195  * structure rte_eth_dev.
 196  *
 197  * @param dev
 198  *   - Pointer to the structure rte_eth_dev to read from.
 199  *   - Pointer to the buffer to be saved with the link status.
 200  *
 201  * @return
 202  *   - On success, zero.
 203  *   - On failure, negative value.
 204  */
 205 static inline int
 206 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 207                                 struct rte_eth_link *link)
 208 {
 209         struct rte_eth_link *dst = &(dev->data->dev_link);
 210         struct rte_eth_link *src = link;
 211
 212         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 213                                         *(uint64_t *)src) == 0)
 214                 return -1;
 215
 216         return 0;
 217 }
 218
 219 static int
 220 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 221                 struct rte_eth_dev *eth_dev)
 222 {
 223         struct rte_pci_device *pci_dev;
 224         struct e1000_hw *hw =
 225                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 226         struct e1000_vfta * shadow_vfta =
 227                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 228
 229         pci_dev = eth_dev->pci_dev;
 230         eth_dev->dev_ops = &eth_em_ops;
 231         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 232         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 233
 234         /* for secondary processes, we don't initialise any further as primary
 235          * has already done this work. Only check we don't need a different
 236          * RX function */
 237         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 238                 if (eth_dev->data->scattered_rx)
 239                         eth_dev->rx_pkt_burst =
 240                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 241                 return 0;
 242         }
 243
 244         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 245         hw->device_id = pci_dev->id.device_id;
 246
 247         /* For ICH8 support we'll need to map the flash memory BAR */
 248
 249         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 250                         em_hw_init(hw) != 0) {
 251                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 252                         "failed to init HW",
 253                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 254                         pci_dev->id.device_id);
 255                 return -(ENODEV);
 256         }
 257
 258         /* Allocate memory for storing MAC addresses */
 259         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 260                         hw->mac.rar_entry_count, 0);
 261         if (eth_dev->data->mac_addrs == NULL) {
 262                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 263                         "store MAC addresses",
 264                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 265                 return -(ENOMEM);
 266         }
 267
 268         /* Copy the permanent MAC address */
 269         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 270                 eth_dev->data->mac_addrs);
 271
 272         /* initialize the vfta */
 273         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 274
 275         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 276                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 277                      pci_dev->id.device_id);
 278
 279         rte_intr_callback_register(&(pci_dev->intr_handle),
 280                 eth_em_interrupt_handler, (void *)eth_dev);
 281
 282         return (0);
 283 }
 284
 285 static struct eth_driver rte_em_pmd = {
 286         {
 287                 .name = "rte_em_pmd",
 288                 .id_table = pci_id_em_map,
 289                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 290         },
 291         .eth_dev_init = eth_em_dev_init,
 292         .dev_private_size = sizeof(struct e1000_adapter),
 293 };
 294
 295 static int
 296 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 297 {
 298         rte_eth_driver_register(&rte_em_pmd);
 299         return 0;
 300 }
 301
 302 static int
 303 em_hw_init(struct e1000_hw *hw)
 304 {
 305         int diag;
 306
 307         diag = hw->mac.ops.init_params(hw);
 308         if (diag != 0) {
 309                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 310                 return diag;
 311         }
 312         diag = hw->nvm.ops.init_params(hw);
 313         if (diag != 0) {
 314                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 315                 return diag;
 316         }
 317         diag = hw->phy.ops.init_params(hw);
 318         if (diag != 0) {
 319                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 320                 return diag;
 321         }
 322         (void) e1000_get_bus_info(hw);
 323
 324         hw->mac.autoneg = 1;
 325         hw->phy.autoneg_wait_to_complete = 0;
 326         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 327
 328         e1000_init_script_state_82541(hw, TRUE);
 329         e1000_set_tbi_compatibility_82543(hw, TRUE);
 330
 331         /* Copper options */
 332         if (hw->phy.media_type == e1000_media_type_copper) {
 333                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 334                 hw->phy.disable_polarity_correction = 0;
 335                 hw->phy.ms_type = e1000_ms_hw_default;
 336         }
 337
 338         /*
 339          * Start from a known state, this is important in reading the nvm
 340          * and mac from that.
 341          */
 342         e1000_reset_hw(hw);
 343
 344         /* Make sure we have a good EEPROM before we read from it */
 345         if (e1000_validate_nvm_checksum(hw) < 0) {
 346                 /*
 347                  * Some PCI-E parts fail the first check due to
 348                  * the link being in sleep state, call it again,
 349                  * if it fails a second time its a real issue.
 350                  */
 351                 diag = e1000_validate_nvm_checksum(hw);
 352                 if (diag < 0) {
 353                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 354                         goto error;
 355                 }
 356         }
 357
 358         /* Read the permanent MAC address out of the EEPROM */
 359         diag = e1000_read_mac_addr(hw);
 360         if (diag != 0) {
 361                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 362                 goto error;
 363         }
 364
 365         /* Now initialize the hardware */
 366         diag = em_hardware_init(hw);
 367         if (diag != 0) {
 368                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 369                 goto error;
 370         }
 371
 372         hw->mac.get_link_status = 1;
 373
 374         /* Indicate SOL/IDER usage */
 375         diag = e1000_check_reset_block(hw);
 376         if (diag < 0) {
 377                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 378                         "SOL/IDER session");
 379         }
 380         return (0);
 381
 382 error:
 383         em_hw_control_release(hw);
 384         return (diag);
 385 }
 386
 387 static int
 388 eth_em_configure(struct rte_eth_dev *dev)
 389 {
 390         struct e1000_interrupt *intr =
 391                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 392
 393         PMD_INIT_FUNC_TRACE();
 394         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 395         PMD_INIT_FUNC_TRACE();
 396
 397         return (0);
 398 }
 399
 400 static void
 401 em_set_pba(struct e1000_hw *hw)
 402 {
 403         uint32_t pba;
 404
 405         /*
 406          * Packet Buffer Allocation (PBA)
 407          * Writing PBA sets the receive portion of the buffer
 408          * the remainder is used for the transmit buffer.
 409          * Devices before the 82547 had a Packet Buffer of 64K.
 410          * After the 82547 the buffer was reduced to 40K.
 411          */
 412         switch (hw->mac.type) {
 413                 case e1000_82547:
 414                 case e1000_82547_rev_2:
 415                 /* 82547: Total Packet Buffer is 40K */
 416                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 417                         break;
 418                 case e1000_82571:
 419                 case e1000_82572:
 420                 case e1000_80003es2lan:
 421                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 422                         break;
 423                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 424                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 425                         break;
 426                 case e1000_82574:
 427                 case e1000_82583:
 428                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 429                         break;
 430                 case e1000_ich8lan:
 431                         pba = E1000_PBA_8K;
 432                         break;
 433                 case e1000_ich9lan:
 434                 case e1000_ich10lan:
 435                         pba = E1000_PBA_10K;
 436                         break;
 437                 case e1000_pchlan:
 438                 case e1000_pch2lan:
 439                         pba = E1000_PBA_26K;
 440                         break;
 441                 default:
 442                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 443         }
 444
 445         E1000_WRITE_REG(hw, E1000_PBA, pba);
 446 }
 447
 448 static int
 449 eth_em_start(struct rte_eth_dev *dev)
 450 {
 451         struct e1000_hw *hw =
 452                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 453         int ret, mask;
 454
 455         PMD_INIT_FUNC_TRACE();
 456
 457         eth_em_stop(dev);
 458
 459         e1000_power_up_phy(hw);
 460
 461         /* Set default PBA value */
 462         em_set_pba(hw);
 463
 464         /* Put the address into the Receive Address Array */
 465         e1000_rar_set(hw, hw->mac.addr, 0);
 466
 467         /*
 468          * With the 82571 adapter, RAR[0] may be overwritten
 469          * when the other port is reset, we make a duplicate
 470          * in RAR[14] for that eventuality, this assures
 471          * the interface continues to function.
 472          */
 473         if (hw->mac.type == e1000_82571) {
 474                 e1000_set_laa_state_82571(hw, TRUE);
 475                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 476         }
 477
 478         /* Initialize the hardware */
 479         if (em_hardware_init(hw)) {
 480                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 481                 return (-EIO);
 482         }
 483
 484         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 485
 486         /* Configure for OS presence */
 487         em_init_manageability(hw);
 488
 489         eth_em_tx_init(dev);
 490
 491         ret = eth_em_rx_init(dev);
 492         if (ret) {
 493                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 494                 em_dev_clear_queues(dev);
 495                 return ret;
 496         }
 497
 498         e1000_clear_hw_cntrs_base_generic(hw);
 499
 500         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 501                         ETH_VLAN_EXTEND_MASK;
 502         eth_em_vlan_offload_set(dev, mask);
 503
 504         /* Set Interrupt Throttling Rate to maximum allowed value. */
 505         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 506
 507         /* Setup link speed and duplex */
 508         switch (dev->data->dev_conf.link_speed) {
 509         case ETH_LINK_SPEED_AUTONEG:
 510                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 511                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 512                 else if (dev->data->dev_conf.link_duplex ==
 513                                         ETH_LINK_HALF_DUPLEX)
 514                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 515                 else if (dev->data->dev_conf.link_duplex ==
 516                                         ETH_LINK_FULL_DUPLEX)
 517                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 518                 else
 519                         goto error_invalid_config;
 520                 break;
 521         case ETH_LINK_SPEED_10:
 522                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 523                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 524                 else if (dev->data->dev_conf.link_duplex ==
 525                                         ETH_LINK_HALF_DUPLEX)
 526                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 527                 else if (dev->data->dev_conf.link_duplex ==
 528                                         ETH_LINK_FULL_DUPLEX)
 529                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 530                 else
 531                         goto error_invalid_config;
 532                 break;
 533         case ETH_LINK_SPEED_100:
 534                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 535                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 536                 else if (dev->data->dev_conf.link_duplex ==
 537                                         ETH_LINK_HALF_DUPLEX)
 538                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 539                 else if (dev->data->dev_conf.link_duplex ==
 540                                         ETH_LINK_FULL_DUPLEX)
 541                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 542                 else
 543                         goto error_invalid_config;
 544                 break;
 545         case ETH_LINK_SPEED_1000:
 546                 if ((dev->data->dev_conf.link_duplex ==
 547                                 ETH_LINK_AUTONEG_DUPLEX) ||
 548                         (dev->data->dev_conf.link_duplex ==
 549                                         ETH_LINK_FULL_DUPLEX))
 550                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 551                 else
 552                         goto error_invalid_config;
 553                 break;
 554         case ETH_LINK_SPEED_10000:
 555         default:
 556                 goto error_invalid_config;
 557         }
 558         e1000_setup_link(hw);
 559
 560         /* check if lsc interrupt feature is enabled */
 561         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 562                 ret = eth_em_interrupt_setup(dev);
 563                 if (ret) {
 564                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 565                         em_dev_clear_queues(dev);
 566                         return ret;
 567                 }
 568         }
 569
 570         PMD_INIT_LOG(DEBUG, "<<");
 571
 572         return (0);
 573
 574 error_invalid_config:
 575         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 576                      dev->data->dev_conf.link_speed,
 577                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 578         em_dev_clear_queues(dev);
 579         return (-EINVAL);
 580 }
 581
 582 /*********************************************************************
 583  *
 584  *  This routine disables all traffic on the adapter by issuing a
 585  *  global reset on the MAC.
 586  *
 587  **********************************************************************/
 588 static void
 589 eth_em_stop(struct rte_eth_dev *dev)
 590 {
 591         struct rte_eth_link link;
 592         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 593
 594         em_intr_disable(hw);
 595         e1000_reset_hw(hw);
 596         if (hw->mac.type >= e1000_82544)
 597                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 598
 599         /* Power down the phy. Needed to make the link go down */
 600         e1000_power_down_phy(hw);
 601
 602         em_dev_clear_queues(dev);
 603
 604         /* clear the recorded link status */
 605         memset(&link, 0, sizeof(link));
 606         rte_em_dev_atomic_write_link_status(dev, &link);
 607 }
 608
 609 static void
 610 eth_em_close(struct rte_eth_dev *dev)
 611 {
 612         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613
 614         eth_em_stop(dev);
 615         e1000_phy_hw_reset(hw);
 616         em_release_manageability(hw);
 617         em_hw_control_release(hw);
 618 }
 619
 620 static int
 621 em_get_rx_buffer_size(struct e1000_hw *hw)
 622 {
 623         uint32_t rx_buf_size;
 624
 625         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 626         return rx_buf_size;
 627 }
 628
 629 /*********************************************************************
 630  *
 631  *  Initialize the hardware
 632  *
 633  **********************************************************************/
 634 static int
 635 em_hardware_init(struct e1000_hw *hw)
 636 {
 637         uint32_t rx_buf_size;
 638         int diag;
 639
 640         /* Issue a global reset */
 641         e1000_reset_hw(hw);
 642
 643         /* Let the firmware know the OS is in control */
 644         em_hw_control_acquire(hw);
 645
 646         /*
 647          * These parameters control the automatic generation (Tx) and
 648          * response (Rx) to Ethernet PAUSE frames.
 649          * - High water mark should allow for at least two standard size (1518)
 650          *   frames to be received after sending an XOFF.
 651          * - Low water mark works best when it is very near the high water mark.
 652          *   This allows the receiver to restart by sending XON when it has
 653          *   drained a bit. Here we use an arbitrary value of 1500 which will
 654          *   restart after one full frame is pulled from the buffer. There
 655          *   could be several smaller frames in the buffer and if so they will
 656          *   not trigger the XON until their total number reduces the buffer
 657          *   by 1500.
 658          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 659          */
 660         rx_buf_size = em_get_rx_buffer_size(hw);
 661
 662         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 663         hw->fc.low_water = hw->fc.high_water - 1500;
 664
 665         if (hw->mac.type == e1000_80003es2lan)
 666                 hw->fc.pause_time = UINT16_MAX;
 667         else
 668                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 669
 670         hw->fc.send_xon = 1;
 671
 672         /* Set Flow control, use the tunable location if sane */
 673         if (em_fc_setting <= e1000_fc_full)
 674                 hw->fc.requested_mode = em_fc_setting;
 675         else
 676                 hw->fc.requested_mode = e1000_fc_none;
 677
 678         /* Workaround: no TX flow ctrl for PCH */
 679         if (hw->mac.type == e1000_pchlan)
 680                 hw->fc.requested_mode = e1000_fc_rx_pause;
 681
 682         /* Override - settings for PCH2LAN, ya its magic :) */
 683         if (hw->mac.type == e1000_pch2lan) {
 684                 hw->fc.high_water = 0x5C20;
 685                 hw->fc.low_water = 0x5048;
 686                 hw->fc.pause_time = 0x0650;
 687                 hw->fc.refresh_time = 0x0400;
 688         }
 689
 690         diag = e1000_init_hw(hw);
 691         if (diag < 0)
 692                 return (diag);
 693         e1000_check_for_link(hw);
 694         return (0);
 695 }
 696
 697 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 698 static void
 699 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 700 {
 701         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 702         struct e1000_hw_stats *stats =
 703                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 704         int pause_frames;
 705
 706         if(hw->phy.media_type == e1000_media_type_copper ||
 707                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 708                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 709                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 710         }
 711
 712         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 713         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 714         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 715         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 716
 717         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 718         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 719         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 720         stats->dc += E1000_READ_REG(hw, E1000_DC);
 721         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 722         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 723         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 724
 725         /*
 726          * For watchdog management we need to know if we have been
 727          * paused during the last interval, so capture that here.
 728          */
 729         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 730         stats->xoffrxc += pause_frames;
 731         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 732         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 733         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 734         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 735         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 736         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 737         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 738         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 739         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 740         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 741         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 742         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 743
 744         /*
 745          * For the 64-bit byte counters the low dword must be read first.
 746          * Both registers clear on the read of the high dword.
 747          */
 748
 749         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 750         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 751         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 752         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 753
 754         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 755         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 756         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 757         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 758         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 759
 760         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 761         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 762
 763         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 764         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 765         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 766         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 767         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 768         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 769         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 770         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 771         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 772         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 773
 774         /* Interrupt Counts */
 775
 776         if (hw->mac.type >= e1000_82571) {
 777                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 778                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 779                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 780                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 781                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 782                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 783                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 784                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 785                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 786         }
 787
 788         if (hw->mac.type >= e1000_82543) {
 789                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 790                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 791                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 792                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 793                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 794                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 795         }
 796
 797         if (rte_stats == NULL)
 798                 return;
 799
 800         /* Rx Errors */
 801         rte_stats->ibadcrc = stats->crcerrs;
 802         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
 803         rte_stats->imissed = stats->mpc;
 804         rte_stats->ierrors = rte_stats->ibadcrc +
 805                              rte_stats->ibadlen +
 806                              rte_stats->imissed +
 807                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 808
 809         /* Tx Errors */
 810         rte_stats->oerrors = stats->ecol + stats->latecol;
 811
 812         rte_stats->ipackets = stats->gprc;
 813         rte_stats->opackets = stats->gptc;
 814         rte_stats->ibytes   = stats->gorc;
 815         rte_stats->obytes   = stats->gotc;
 816
 817         /* XON/XOFF pause frames stats registers */
 818         rte_stats->tx_pause_xon  = stats->xontxc;
 819         rte_stats->rx_pause_xon  = stats->xonrxc;
 820         rte_stats->tx_pause_xoff = stats->xofftxc;
 821         rte_stats->rx_pause_xoff = stats->xoffrxc;
 822 }
 823
 824 static void
 825 eth_em_stats_reset(struct rte_eth_dev *dev)
 826 {
 827         struct e1000_hw_stats *hw_stats =
 828                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 829
 830         /* HW registers are cleared on read */
 831         eth_em_stats_get(dev, NULL);
 832
 833         /* Reset software totals */
 834         memset(hw_stats, 0, sizeof(*hw_stats));
 835 }
 836
 837 static uint32_t
 838 em_get_max_pktlen(const struct e1000_hw *hw)
 839 {
 840         switch (hw->mac.type) {
 841         case e1000_82571:
 842         case e1000_82572:
 843         case e1000_ich9lan:
 844         case e1000_ich10lan:
 845         case e1000_pch2lan:
 846         case e1000_82574:
 847         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 848                 return (0x2412);
 849         case e1000_pchlan:
 850                 return (0x1000);
 851         /* Adapters that do not support jumbo frames */
 852         case e1000_82583:
 853         case e1000_ich8lan:
 854                 return (ETHER_MAX_LEN);
 855         default:
 856                 return (MAX_JUMBO_FRAME_SIZE);
 857         }
 858 }
 859
 860 static void
 861 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 862 {
 863         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 864
 865         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 866         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 867         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 868
 869         /*
 870          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 871          * Unfortunatelly, all these nics have just one TX context.
 872          * So we have few choises for TX:
 873          * - Use just one TX queue.
 874          * - Allow cksum offload only for one TX queue.
 875          * - Don't allow TX cksum offload at all.
 876          * For now, option #1 was chosen.
 877          * To use second RX queue we have to use extended RX descriptor
 878          * (Multiple Receive Queues are mutually exclusive with UDP
 879          * fragmentation and are not supported when a legacy receive
 880          * descriptor format is used).
 881          * Which means separate RX routinies - as legacy nics (82540, 82545)
 882          * don't support extended RXD.
 883          * To avoid it we support just one RX queue for now (no RSS).
 884          */
 885
 886         dev_info->max_rx_queues = 1;
 887         dev_info->max_tx_queues = 1;
 888 }
 889
 890 /* return 0 means link status changed, -1 means not changed */
 891 static int
 892 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 893 {
 894         struct e1000_hw *hw =
 895                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 896         struct rte_eth_link link, old;
 897         int link_check, count;
 898
 899         link_check = 0;
 900         hw->mac.get_link_status = 1;
 901
 902         /* possible wait-to-complete in up to 9 seconds */
 903         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 904                 /* Read the real link status */
 905                 switch (hw->phy.media_type) {
 906                 case e1000_media_type_copper:
 907                         /* Do the work to read phy */
 908                         e1000_check_for_link(hw);
 909                         link_check = !hw->mac.get_link_status;
 910                         break;
 911
 912                 case e1000_media_type_fiber:
 913                         e1000_check_for_link(hw);
 914                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 915                                         E1000_STATUS_LU);
 916                         break;
 917
 918                 case e1000_media_type_internal_serdes:
 919                         e1000_check_for_link(hw);
 920                         link_check = hw->mac.serdes_has_link;
 921                         break;
 922
 923                 default:
 924                         break;
 925                 }
 926                 if (link_check || wait_to_complete == 0)
 927                         break;
 928                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 929         }
 930         memset(&link, 0, sizeof(link));
 931         rte_em_dev_atomic_read_link_status(dev, &link);
 932         old = link;
 933
 934         /* Now we check if a transition has happened */
 935         if (link_check && (link.link_status == 0)) {
 936                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 937                         &link.link_duplex);
 938                 link.link_status = 1;
 939         } else if (!link_check && (link.link_status == 1)) {
 940                 link.link_speed = 0;
 941                 link.link_duplex = 0;
 942                 link.link_status = 0;
 943         }
 944         rte_em_dev_atomic_write_link_status(dev, &link);
 945
 946         /* not changed */
 947         if (old.link_status == link.link_status)
 948                 return -1;
 949
 950         /* changed */
 951         return 0;
 952 }
 953
 954 /*
 955  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 956  * For ASF and Pass Through versions of f/w this means
 957  * that the driver is loaded. For AMT version type f/w
 958  * this means that the network i/f is open.
 959  */
 960 static void
 961 em_hw_control_acquire(struct e1000_hw *hw)
 962 {
 963         uint32_t ctrl_ext, swsm;
 964
 965         /* Let firmware know the driver has taken over */
 966         if (hw->mac.type == e1000_82573) {
 967                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 968                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 969
 970         } else {
 971                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 972                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 973                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 974         }
 975 }
 976
 977 /*
 978  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 979  * For ASF and Pass Through versions of f/w this means that the
 980  * driver is no longer loaded. For AMT versions of the
 981  * f/w this means that the network i/f is closed.
 982  */
 983 static void
 984 em_hw_control_release(struct e1000_hw *hw)
 985 {
 986         uint32_t ctrl_ext, swsm;
 987
 988         /* Let firmware taken over control of h/w */
 989         if (hw->mac.type == e1000_82573) {
 990                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 991                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 992         } else {
 993                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 994                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 995                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 996         }
 997 }
 998
 999 /*
1000  * Bit of a misnomer, what this really means is
1001  * to enable OS management of the system... aka
1002  * to disable special hardware management features.
1003  */
1004 static void
1005 em_init_manageability(struct e1000_hw *hw)
1006 {
1007         if (e1000_enable_mng_pass_thru(hw)) {
1008                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1009                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1010
1011                 /* disable hardware interception of ARP */
1012                 manc &= ~(E1000_MANC_ARP_EN);
1013
1014                 /* enable receiving management packets to the host */
1015                 manc |= E1000_MANC_EN_MNG2HOST;
1016                 manc2h |= 1 << 5;  /* Mng Port 623 */
1017                 manc2h |= 1 << 6;  /* Mng Port 664 */
1018                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1019                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1020         }
1021 }
1022
1023 /*
1024  * Give control back to hardware management
1025  * controller if there is one.
1026  */
1027 static void
1028 em_release_manageability(struct e1000_hw *hw)
1029 {
1030         uint32_t manc;
1031
1032         if (e1000_enable_mng_pass_thru(hw)) {
1033                 manc = E1000_READ_REG(hw, E1000_MANC);
1034
1035                 /* re-enable hardware interception of ARP */
1036                 manc |= E1000_MANC_ARP_EN;
1037                 manc &= ~E1000_MANC_EN_MNG2HOST;
1038
1039                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1040         }
1041 }
1042
1043 static void
1044 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1045 {
1046         struct e1000_hw *hw =
1047                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048         uint32_t rctl;
1049
1050         rctl = E1000_READ_REG(hw, E1000_RCTL);
1051         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1052         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1053 }
1054
1055 static void
1056 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1057 {
1058         struct e1000_hw *hw =
1059                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060         uint32_t rctl;
1061
1062         rctl = E1000_READ_REG(hw, E1000_RCTL);
1063         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1064         if (dev->data->all_multicast == 1)
1065                 rctl |= E1000_RCTL_MPE;
1066         else
1067                 rctl &= (~E1000_RCTL_MPE);
1068         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1069 }
1070
1071 static void
1072 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1073 {
1074         struct e1000_hw *hw =
1075                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1076         uint32_t rctl;
1077
1078         rctl = E1000_READ_REG(hw, E1000_RCTL);
1079         rctl |= E1000_RCTL_MPE;
1080         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1081 }
1082
1083 static void
1084 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1085 {
1086         struct e1000_hw *hw =
1087                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088         uint32_t rctl;
1089
1090         if (dev->data->promiscuous == 1)
1091                 return; /* must remain in all_multicast mode */
1092         rctl = E1000_READ_REG(hw, E1000_RCTL);
1093         rctl &= (~E1000_RCTL_MPE);
1094         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1095 }
1096
1097 static int
1098 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1099 {
1100         struct e1000_hw *hw =
1101                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1102         struct e1000_vfta * shadow_vfta =
1103                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1104         uint32_t vfta;
1105         uint32_t vid_idx;
1106         uint32_t vid_bit;
1107
1108         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1109                               E1000_VFTA_ENTRY_MASK);
1110         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1111         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1112         if (on)
1113                 vfta |= vid_bit;
1114         else
1115                 vfta &= ~vid_bit;
1116         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1117
1118         /* update local VFTA copy */
1119         shadow_vfta->vfta[vid_idx] = vfta;
1120
1121         return 0;
1122 }
1123
1124 static void
1125 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1126 {
1127         struct e1000_hw *hw =
1128                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129         uint32_t reg;
1130
1131         /* Filter Table Disable */
1132         reg = E1000_READ_REG(hw, E1000_RCTL);
1133         reg &= ~E1000_RCTL_CFIEN;
1134         reg &= ~E1000_RCTL_VFE;
1135         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1136 }
1137
1138 static void
1139 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1140 {
1141         struct e1000_hw *hw =
1142                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1143         struct e1000_vfta * shadow_vfta =
1144                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1145         uint32_t reg;
1146         int i;
1147
1148         /* Filter Table Enable, CFI not used for packet acceptance */
1149         reg = E1000_READ_REG(hw, E1000_RCTL);
1150         reg &= ~E1000_RCTL_CFIEN;
1151         reg |= E1000_RCTL_VFE;
1152         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1153
1154         /* restore vfta from local copy */
1155         for (i = 0; i < IGB_VFTA_SIZE; i++)
1156                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1157 }
1158
1159 static void
1160 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1161 {
1162         struct e1000_hw *hw =
1163                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164         uint32_t reg;
1165
1166         /* VLAN Mode Disable */
1167         reg = E1000_READ_REG(hw, E1000_CTRL);
1168         reg &= ~E1000_CTRL_VME;
1169         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1170
1171 }
1172
1173 static void
1174 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1175 {
1176         struct e1000_hw *hw =
1177                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178         uint32_t reg;
1179
1180         /* VLAN Mode Enable */
1181         reg = E1000_READ_REG(hw, E1000_CTRL);
1182         reg |= E1000_CTRL_VME;
1183         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1184 }
1185
1186 static void
1187 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1188 {
1189         if(mask & ETH_VLAN_STRIP_MASK){
1190                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1191                         em_vlan_hw_strip_enable(dev);
1192                 else
1193                         em_vlan_hw_strip_disable(dev);
1194         }
1195
1196         if(mask & ETH_VLAN_FILTER_MASK){
1197                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1198                         em_vlan_hw_filter_enable(dev);
1199                 else
1200                         em_vlan_hw_filter_disable(dev);
1201         }
1202 }
1203
1204 static void
1205 em_intr_disable(struct e1000_hw *hw)
1206 {
1207         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1208 }
1209
1210 /**
1211  * It enables the interrupt mask and then enable the interrupt.
1212  *
1213  * @param dev
1214  *  Pointer to struct rte_eth_dev.
1215  *
1216  * @return
1217  *  - On success, zero.
1218  *  - On failure, a negative value.
1219  */
1220 static int
1221 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1222 {
1223         struct e1000_hw *hw =
1224                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225
1226         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1227         rte_intr_enable(&(dev->pci_dev->intr_handle));
1228         return (0);
1229 }
1230
1231 /*
1232  * It reads ICR and gets interrupt causes, check it and set a bit flag
1233  * to update link status.
1234  *
1235  * @param dev
1236  *  Pointer to struct rte_eth_dev.
1237  *
1238  * @return
1239  *  - On success, zero.
1240  *  - On failure, a negative value.
1241  */
1242 static int
1243 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1244 {
1245         uint32_t icr;
1246         struct e1000_hw *hw =
1247                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         struct e1000_interrupt *intr =
1249                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1250
1251         /* read-on-clear nic registers here */
1252         icr = E1000_READ_REG(hw, E1000_ICR);
1253         if (icr & E1000_ICR_LSC) {
1254                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1255         }
1256
1257         return 0;
1258 }
1259
1260 /*
1261  * It executes link_update after knowing an interrupt is prsent.
1262  *
1263  * @param dev
1264  *  Pointer to struct rte_eth_dev.
1265  *
1266  * @return
1267  *  - On success, zero.
1268  *  - On failure, a negative value.
1269  */
1270 static int
1271 eth_em_interrupt_action(struct rte_eth_dev *dev)
1272 {
1273         struct e1000_hw *hw =
1274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         struct e1000_interrupt *intr =
1276                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1277         uint32_t tctl, rctl;
1278         struct rte_eth_link link;
1279         int ret;
1280
1281         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1282                 return -1;
1283
1284         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1285         rte_intr_enable(&(dev->pci_dev->intr_handle));
1286
1287         /* set get_link_status to check register later */
1288         hw->mac.get_link_status = 1;
1289         ret = eth_em_link_update(dev, 0);
1290
1291         /* check if link has changed */
1292         if (ret < 0)
1293                 return 0;
1294
1295         memset(&link, 0, sizeof(link));
1296         rte_em_dev_atomic_read_link_status(dev, &link);
1297         if (link.link_status) {
1298                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1299                              dev->data->port_id, (unsigned)link.link_speed,
1300                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1301                              "full-duplex" : "half-duplex");
1302         } else {
1303                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1304         }
1305         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1306                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1307                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1308         tctl = E1000_READ_REG(hw, E1000_TCTL);
1309         rctl = E1000_READ_REG(hw, E1000_RCTL);
1310         if (link.link_status) {
1311                 /* enable Tx/Rx */
1312                 tctl |= E1000_TCTL_EN;
1313                 rctl |= E1000_RCTL_EN;
1314         } else {
1315                 /* disable Tx/Rx */
1316                 tctl &= ~E1000_TCTL_EN;
1317                 rctl &= ~E1000_RCTL_EN;
1318         }
1319         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1320         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1321         E1000_WRITE_FLUSH(hw);
1322
1323         return 0;
1324 }
1325
1326 /**
1327  * Interrupt handler which shall be registered at first.
1328  *
1329  * @param handle
1330  *  Pointer to interrupt handle.
1331  * @param param
1332  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1333  *
1334  * @return
1335  *  void
1336  */
1337 static void
1338 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1339                                                         void *param)
1340 {
1341         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1342
1343         eth_em_interrupt_get_status(dev);
1344         eth_em_interrupt_action(dev);
1345         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1346 }
1347
1348 static int
1349 eth_em_led_on(struct rte_eth_dev *dev)
1350 {
1351         struct e1000_hw *hw;
1352
1353         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1355 }
1356
1357 static int
1358 eth_em_led_off(struct rte_eth_dev *dev)
1359 {
1360         struct e1000_hw *hw;
1361
1362         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1363         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1364 }
1365
1366 static int
1367 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1368 {
1369         struct e1000_hw *hw;
1370         uint32_t ctrl;
1371         int tx_pause;
1372         int rx_pause;
1373
1374         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375         fc_conf->pause_time = hw->fc.pause_time;
1376         fc_conf->high_water = hw->fc.high_water;
1377         fc_conf->low_water = hw->fc.low_water;
1378         fc_conf->send_xon = hw->fc.send_xon;
1379         fc_conf->autoneg = hw->mac.autoneg;
1380
1381         /*
1382          * Return rx_pause and tx_pause status according to actual setting of
1383          * the TFCE and RFCE bits in the CTRL register.
1384          */
1385         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1386         if (ctrl & E1000_CTRL_TFCE)
1387                 tx_pause = 1;
1388         else
1389                 tx_pause = 0;
1390
1391         if (ctrl & E1000_CTRL_RFCE)
1392                 rx_pause = 1;
1393         else
1394                 rx_pause = 0;
1395
1396         if (rx_pause && tx_pause)
1397                 fc_conf->mode = RTE_FC_FULL;
1398         else if (rx_pause)
1399                 fc_conf->mode = RTE_FC_RX_PAUSE;
1400         else if (tx_pause)
1401                 fc_conf->mode = RTE_FC_TX_PAUSE;
1402         else
1403                 fc_conf->mode = RTE_FC_NONE;
1404
1405         return 0;
1406 }
1407
1408 static int
1409 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1410 {
1411         struct e1000_hw *hw;
1412         int err;
1413         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1414                 e1000_fc_none,
1415                 e1000_fc_rx_pause,
1416                 e1000_fc_tx_pause,
1417                 e1000_fc_full
1418         };
1419         uint32_t rx_buf_size;
1420         uint32_t max_high_water;
1421         uint32_t rctl;
1422
1423         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1424         if (fc_conf->autoneg != hw->mac.autoneg)
1425                 return -ENOTSUP;
1426         rx_buf_size = em_get_rx_buffer_size(hw);
1427         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1428
1429         /* At least reserve one Ethernet frame for watermark */
1430         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1431         if ((fc_conf->high_water > max_high_water) ||
1432             (fc_conf->high_water < fc_conf->low_water)) {
1433                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1434                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1435                 return (-EINVAL);
1436         }
1437
1438         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1439         hw->fc.pause_time     = fc_conf->pause_time;
1440         hw->fc.high_water     = fc_conf->high_water;
1441         hw->fc.low_water      = fc_conf->low_water;
1442         hw->fc.send_xon       = fc_conf->send_xon;
1443
1444         err = e1000_setup_link_generic(hw);
1445         if (err == E1000_SUCCESS) {
1446
1447                 /* check if we want to forward MAC frames - driver doesn't have native
1448                  * capability to do that, so we'll write the registers ourselves */
1449
1450                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1451
1452                 /* set or clear MFLCN.PMCF bit depending on configuration */
1453                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1454                         rctl |= E1000_RCTL_PMCF;
1455                 else
1456                         rctl &= ~E1000_RCTL_PMCF;
1457
1458                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1459                 E1000_WRITE_FLUSH(hw);
1460
1461                 return 0;
1462         }
1463
1464         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1465         return (-EIO);
1466 }
1467
1468 static void
1469 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1470                 uint32_t index, __rte_unused uint32_t pool)
1471 {
1472         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1473
1474         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1475 }
1476
1477 static void
1478 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1479 {
1480         uint8_t addr[ETHER_ADDR_LEN];
1481         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1482
1483         memset(addr, 0, sizeof(addr));
1484
1485         e1000_rar_set(hw, addr, index);
1486 }
1487
1488 static int
1489 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1490 {
1491         struct rte_eth_dev_info dev_info;
1492         struct e1000_hw *hw;
1493         uint32_t frame_size;
1494         uint32_t rctl;
1495
1496         eth_em_infos_get(dev, &dev_info);
1497         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1498
1499         /* check that mtu is within the allowed range */
1500         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1501                 return -EINVAL;
1502
1503         /* refuse mtu that requires the support of scattered packets when this
1504          * feature has not been enabled before. */
1505         if (!dev->data->scattered_rx &&
1506             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1507                 return -EINVAL;
1508
1509         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510         rctl = E1000_READ_REG(hw, E1000_RCTL);
1511
1512         /* switch to jumbo mode if needed */
1513         if (frame_size > ETHER_MAX_LEN) {
1514                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1515                 rctl |= E1000_RCTL_LPE;
1516         } else {
1517                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1518                 rctl &= ~E1000_RCTL_LPE;
1519         }
1520         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1521
1522         /* update max frame size */
1523         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1524         return 0;
1525 }
1526
1527 struct rte_driver em_pmd_drv = {
1528         .type = PMD_PDEV,
1529         .init = rte_em_pmd_init,
1530 };
1531
1532 PMD_REGISTER_DRIVER(em_pmd_drv);