4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_interrupts.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
48 #include <rte_debug.h>
50 #include <rte_memory.h>
51 #include <rte_memcpy.h>
52 #include <rte_memzone.h>
53 #include <rte_launch.h>
54 #include <rte_tailq.h>
56 #include <rte_per_lcore.h>
57 #include <rte_lcore.h>
58 #include <rte_atomic.h>
59 #include <rte_branch_prediction.h>
61 #include <rte_mempool.h>
62 #include <rte_malloc.h>
64 #include <rte_ether.h>
65 #include <rte_ethdev.h>
66 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
73 #include "e1000_logs.h"
74 #include "e1000/e1000_api.h"
75 #include "e1000_ethdev.h"
76 #include "e1000/e1000_osdep.h"
78 #define E1000_TXD_VLAN_SHIFT 16
80 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
82 static inline struct rte_mbuf *
83 rte_rxmbuf_alloc(struct rte_mempool *mp)
87 m = __rte_mbuf_raw_alloc(mp);
88 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
92 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
93 (uint64_t) ((mb)->buf_physaddr + \
94 (uint64_t) ((char *)((mb)->pkt.data) - (char *)(mb)->buf_addr))
96 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
97 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
100 * Structure associated with each descriptor of the RX ring of a RX queue.
103 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
107 * Structure associated with each descriptor of the TX ring of a TX queue.
110 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
111 uint16_t next_id; /**< Index of next descriptor in ring. */
112 uint16_t last_id; /**< Index of last scattered descriptor. */
116 * Structure associated with each RX queue.
119 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
120 volatile struct e1000_rx_desc *rx_ring; /**< RX ring virtual address. */
121 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
122 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
123 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
124 struct em_rx_entry *sw_ring; /**< address of RX software ring. */
125 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
126 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
127 uint16_t nb_rx_desc; /**< number of RX descriptors. */
128 uint16_t rx_tail; /**< current value of RDT register. */
129 uint16_t nb_rx_hold; /**< number of held free RX desc. */
130 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
131 uint16_t queue_id; /**< RX queue index. */
132 uint8_t port_id; /**< Device port identifier. */
133 uint8_t pthresh; /**< Prefetch threshold register. */
134 uint8_t hthresh; /**< Host threshold register. */
135 uint8_t wthresh; /**< Write-back threshold register. */
136 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
140 * Hardware context number
143 EM_CTX_0 = 0, /**< CTX0 */
144 EM_CTX_NUM = 1, /**< CTX NUM */
148 * Structure to check if new context need be built
151 uint16_t flags; /**< ol_flags related to context build. */
152 uint32_t cmp_mask; /**< compare mask */
153 union rte_vlan_macip hdrlen; /**< L2 and L3 header lenghts */
157 * Structure associated with each TX queue.
160 volatile struct e1000_data_desc *tx_ring; /**< TX ring address */
161 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
162 struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */
163 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
164 uint16_t nb_tx_desc; /**< number of TX descriptors. */
165 uint16_t tx_tail; /**< Current value of TDT register. */
166 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
167 /**< Number of TX descriptors to use before RS bit is set. */
168 uint16_t tx_rs_thresh;
169 /** Number of TX descriptors used since RS bit was set. */
171 /** Index to last TX descriptor to have been cleaned. */
172 uint16_t last_desc_cleaned;
173 /** Total number of TX descriptors ready to be allocated. */
175 uint16_t queue_id; /**< TX queue index. */
176 uint8_t port_id; /**< Device port identifier. */
177 uint8_t pthresh; /**< Prefetch threshold register. */
178 uint8_t hthresh; /**< Host threshold register. */
179 uint8_t wthresh; /**< Write-back threshold register. */
180 struct em_ctx_info ctx_cache;
181 /**< Hardware context history.*/
185 #define RTE_PMD_USE_PREFETCH
188 #ifdef RTE_PMD_USE_PREFETCH
189 #define rte_em_prefetch(p) rte_prefetch0(p)
191 #define rte_em_prefetch(p) do {} while(0)
194 #ifdef RTE_PMD_PACKET_PREFETCH
195 #define rte_packet_prefetch(p) rte_prefetch1(p)
197 #define rte_packet_prefetch(p) do {} while(0)
200 #ifndef DEFAULT_TX_FREE_THRESH
201 #define DEFAULT_TX_FREE_THRESH 32
202 #endif /* DEFAULT_TX_FREE_THRESH */
204 #ifndef DEFAULT_TX_RS_THRESH
205 #define DEFAULT_TX_RS_THRESH 32
206 #endif /* DEFAULT_TX_RS_THRESH */
209 /*********************************************************************
213 **********************************************************************/
216 * Populates TX context descriptor.
219 em_set_xmit_ctx(struct em_tx_queue* txq,
220 volatile struct e1000_context_desc *ctx_txd,
222 union rte_vlan_macip hdrlen)
224 uint32_t cmp_mask, cmd_len;
225 uint16_t ipcse, l2len;
226 struct e1000_context_desc ctx;
229 cmd_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C;
231 l2len = hdrlen.f.l2_len;
232 ipcse = (uint16_t)(l2len + hdrlen.f.l3_len);
234 /* setup IPCS* fields */
235 ctx.lower_setup.ip_fields.ipcss = (uint8_t)l2len;
236 ctx.lower_setup.ip_fields.ipcso = (uint8_t)(l2len +
237 offsetof(struct ipv4_hdr, hdr_checksum));
240 * When doing checksum or TCP segmentation with IPv6 headers,
241 * IPCSE field should be set t0 0.
243 if (flags & PKT_TX_IP_CKSUM) {
244 ctx.lower_setup.ip_fields.ipcse =
245 (uint16_t)rte_cpu_to_le_16(ipcse - 1);
246 cmd_len |= E1000_TXD_CMD_IP;
247 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
249 ctx.lower_setup.ip_fields.ipcse = 0;
252 /* setup TUCS* fields */
253 ctx.upper_setup.tcp_fields.tucss = (uint8_t)ipcse;
254 ctx.upper_setup.tcp_fields.tucse = 0;
256 switch (flags & PKT_TX_L4_MASK) {
257 case PKT_TX_UDP_CKSUM:
258 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
259 offsetof(struct udp_hdr, dgram_cksum));
260 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
262 case PKT_TX_TCP_CKSUM:
263 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
264 offsetof(struct tcp_hdr, cksum));
265 cmd_len |= E1000_TXD_CMD_TCP;
266 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
269 ctx.upper_setup.tcp_fields.tucso = 0;
272 ctx.cmd_and_length = rte_cpu_to_le_32(cmd_len);
273 ctx.tcp_seg_setup.data = 0;
277 txq->ctx_cache.flags = flags;
278 txq->ctx_cache.cmp_mask = cmp_mask;
279 txq->ctx_cache.hdrlen = hdrlen;
283 * Check which hardware context can be used. Use the existing match
284 * or create a new context descriptor.
286 static inline uint32_t
287 what_ctx_update(struct em_tx_queue *txq, uint16_t flags,
288 union rte_vlan_macip hdrlen)
290 /* If match with the current context */
291 if (likely (txq->ctx_cache.flags == flags &&
292 ((txq->ctx_cache.hdrlen.data ^ hdrlen.data) &
293 txq->ctx_cache.cmp_mask) == 0))
300 /* Reset transmit descriptors after they have been used */
302 em_xmit_cleanup(struct em_tx_queue *txq)
304 struct em_tx_entry *sw_ring = txq->sw_ring;
305 volatile struct e1000_data_desc *txr = txq->tx_ring;
306 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
307 uint16_t nb_tx_desc = txq->nb_tx_desc;
308 uint16_t desc_to_clean_to;
309 uint16_t nb_tx_to_clean;
311 /* Determine the last descriptor needing to be cleaned */
312 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
313 if (desc_to_clean_to >= nb_tx_desc)
314 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
316 /* Check to make sure the last descriptor to clean is done */
317 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
318 if (! (txr[desc_to_clean_to].upper.fields.status & E1000_TXD_STAT_DD))
320 PMD_TX_FREE_LOG(DEBUG,
321 "TX descriptor %4u is not done"
322 "(port=%d queue=%d)",
324 txq->port_id, txq->queue_id);
325 /* Failed to clean any descriptors, better luck next time */
329 /* Figure out how many descriptors will be cleaned */
330 if (last_desc_cleaned > desc_to_clean_to)
331 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
334 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
337 PMD_TX_FREE_LOG(DEBUG,
338 "Cleaning %4u TX descriptors: %4u to %4u "
339 "(port=%d queue=%d)",
340 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
341 txq->port_id, txq->queue_id);
344 * The last descriptor to clean is done, so that means all the
345 * descriptors from the last descriptor that was cleaned
346 * up to the last descriptor with the RS bit set
347 * are done. Only reset the threshold descriptor.
349 txr[desc_to_clean_to].upper.fields.status = 0;
351 /* Update the txq to reflect the last descriptor that was cleaned */
352 txq->last_desc_cleaned = desc_to_clean_to;
353 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
359 static inline uint32_t
360 tx_desc_cksum_flags_to_upper(uint16_t ol_flags)
362 static const uint32_t l4_olinfo[2] = {0, E1000_TXD_POPTS_TXSM << 8};
363 static const uint32_t l3_olinfo[2] = {0, E1000_TXD_POPTS_IXSM << 8};
366 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
367 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
372 eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
375 struct em_tx_queue *txq;
376 struct em_tx_entry *sw_ring;
377 struct em_tx_entry *txe, *txn;
378 volatile struct e1000_data_desc *txr;
379 volatile struct e1000_data_desc *txd;
380 struct rte_mbuf *tx_pkt;
381 struct rte_mbuf *m_seg;
382 uint64_t buf_dma_addr;
384 uint32_t cmd_type_len;
394 union rte_vlan_macip hdrlen;
397 sw_ring = txq->sw_ring;
399 tx_id = txq->tx_tail;
400 txe = &sw_ring[tx_id];
402 /* Determine if the descriptor ring needs to be cleaned. */
403 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
404 em_xmit_cleanup(txq);
408 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
412 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
415 * Determine how many (if any) context descriptors
416 * are needed for offload functionality.
418 ol_flags = tx_pkt->ol_flags;
420 /* If hardware offload required */
421 tx_ol_req = (uint16_t)(ol_flags & (PKT_TX_IP_CKSUM |
424 hdrlen = tx_pkt->pkt.vlan_macip;
425 /* If new context to be built or reuse the exist ctx. */
426 ctx = what_ctx_update(txq, tx_ol_req, hdrlen);
428 /* Only allocate context descriptor if required*/
429 new_ctx = (ctx == EM_CTX_NUM);
433 * Keep track of how many descriptors are used this loop
434 * This will always be the number of segments + the number of
435 * Context descriptors required to transmit the packet
437 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
440 * The number of descriptors that must be allocated for a
441 * packet is the number of segments of that packet, plus 1
442 * Context Descriptor for the hardware offload, if any.
443 * Determine the last TX descriptor to allocate in the TX ring
444 * for the packet, starting from the current position (tx_id)
447 tx_last = (uint16_t) (tx_id + nb_used - 1);
450 if (tx_last >= txq->nb_tx_desc)
451 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
453 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
454 " tx_first=%u tx_last=%u\n",
455 (unsigned) txq->port_id,
456 (unsigned) txq->queue_id,
457 (unsigned) tx_pkt->pkt.pkt_len,
462 * Make sure there are enough TX descriptors available to
463 * transmit the entire packet.
464 * nb_used better be less than or equal to txq->tx_rs_thresh
466 while (unlikely (nb_used > txq->nb_tx_free)) {
467 PMD_TX_FREE_LOG(DEBUG,
468 "Not enough free TX descriptors "
469 "nb_used=%4u nb_free=%4u "
470 "(port=%d queue=%d)",
471 nb_used, txq->nb_tx_free,
472 txq->port_id, txq->queue_id);
474 if (em_xmit_cleanup(txq) != 0) {
475 /* Could not clean any descriptors */
483 * By now there are enough free TX descriptors to transmit
488 * Set common flags of all TX Data Descriptors.
490 * The following bits must be set in all Data Descriptors:
491 * - E1000_TXD_DTYP_DATA
492 * - E1000_TXD_DTYP_DEXT
494 * The following bits must be set in the first Data Descriptor
495 * and are ignored in the other ones:
496 * - E1000_TXD_POPTS_IXSM
497 * - E1000_TXD_POPTS_TXSM
499 * The following bits must be set in the last Data Descriptor
500 * and are ignored in the other ones:
501 * - E1000_TXD_CMD_VLE
502 * - E1000_TXD_CMD_IFCS
504 * The following bits must only be set in the last Data
506 * - E1000_TXD_CMD_EOP
508 * The following bits can be set in any Data Descriptor, but
509 * are only set in the last Data Descriptor:
512 cmd_type_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
516 /* Set VLAN Tag offload fields. */
517 if (ol_flags & PKT_TX_VLAN_PKT) {
518 cmd_type_len |= E1000_TXD_CMD_VLE;
519 popts_spec = tx_pkt->pkt.vlan_macip.f.vlan_tci <<
520 E1000_TXD_VLAN_SHIFT;
525 * Setup the TX Context Descriptor if required
528 volatile struct e1000_context_desc *ctx_txd;
530 ctx_txd = (volatile struct e1000_context_desc *)
533 txn = &sw_ring[txe->next_id];
534 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
536 if (txe->mbuf != NULL) {
537 rte_pktmbuf_free_seg(txe->mbuf);
541 em_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
544 txe->last_id = tx_last;
545 tx_id = txe->next_id;
550 * Setup the TX Data Descriptor,
551 * This path will go through
552 * whatever new/reuse the context descriptor
554 popts_spec |= tx_desc_cksum_flags_to_upper(ol_flags);
560 txn = &sw_ring[txe->next_id];
562 if (txe->mbuf != NULL)
563 rte_pktmbuf_free_seg(txe->mbuf);
567 * Set up Transmit Data Descriptor.
569 slen = m_seg->pkt.data_len;
570 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
572 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
573 txd->lower.data = rte_cpu_to_le_32(cmd_type_len | slen);
574 txd->upper.data = rte_cpu_to_le_32(popts_spec);
576 txe->last_id = tx_last;
577 tx_id = txe->next_id;
579 m_seg = m_seg->pkt.next;
580 } while (m_seg != NULL);
583 * The last packet data descriptor needs End Of Packet (EOP)
585 cmd_type_len |= E1000_TXD_CMD_EOP;
586 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
587 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
589 /* Set RS bit only on threshold packets' last descriptor */
590 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
591 PMD_TX_FREE_LOG(DEBUG,
592 "Setting RS bit on TXD id="
593 "%4u (port=%d queue=%d)",
594 tx_last, txq->port_id, txq->queue_id);
596 cmd_type_len |= E1000_TXD_CMD_RS;
598 /* Update txq RS bit counters */
601 txd->lower.data |= rte_cpu_to_le_32(cmd_type_len);
607 * Set the Transmit Descriptor Tail (TDT)
609 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
610 (unsigned) txq->port_id, (unsigned) txq->queue_id,
611 (unsigned) tx_id, (unsigned) nb_tx);
612 E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
613 txq->tx_tail = tx_id;
618 /*********************************************************************
622 **********************************************************************/
624 static inline uint16_t
625 rx_desc_status_to_pkt_flags(uint32_t rx_status)
629 /* Check if VLAN present */
630 pkt_flags = (uint16_t)((rx_status & E1000_RXD_STAT_VP) ?
631 PKT_RX_VLAN_PKT : 0);
636 static inline uint16_t
637 rx_desc_error_to_pkt_flags(uint32_t rx_error)
639 uint16_t pkt_flags = 0;
641 if (rx_error & E1000_RXD_ERR_IPE)
642 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
643 if (rx_error & E1000_RXD_ERR_TCPE)
644 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
649 eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
652 volatile struct e1000_rx_desc *rx_ring;
653 volatile struct e1000_rx_desc *rxdp;
654 struct em_rx_queue *rxq;
655 struct em_rx_entry *sw_ring;
656 struct em_rx_entry *rxe;
657 struct rte_mbuf *rxm;
658 struct rte_mbuf *nmb;
659 struct e1000_rx_desc rxd;
671 rx_id = rxq->rx_tail;
672 rx_ring = rxq->rx_ring;
673 sw_ring = rxq->sw_ring;
674 while (nb_rx < nb_pkts) {
676 * The order of operations here is important as the DD status
677 * bit must not be read after any other descriptor fields.
678 * rx_ring and rxdp are pointing to volatile data so the order
679 * of accesses cannot be reordered by the compiler. If they were
680 * not volatile, they could be reordered which could lead to
681 * using invalid descriptor fields when read from rxd.
683 rxdp = &rx_ring[rx_id];
684 status = rxdp->status;
685 if (! (status & E1000_RXD_STAT_DD))
692 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
693 * likely to be invalid and to be dropped by the various
694 * validation checks performed by the network stack.
696 * Allocate a new mbuf to replenish the RX ring descriptor.
697 * If the allocation fails:
698 * - arrange for that RX descriptor to be the first one
699 * being parsed the next time the receive function is
700 * invoked [on the same queue].
702 * - Stop parsing the RX ring and return immediately.
704 * This policy do not drop the packet received in the RX
705 * descriptor for which the allocation of a new mbuf failed.
706 * Thus, it allows that packet to be later retrieved if
707 * mbuf have been freed in the mean time.
708 * As a side effect, holding RX descriptors instead of
709 * systematically giving them back to the NIC may lead to
710 * RX ring exhaustion situations.
711 * However, the NIC can gracefully prevent such situations
712 * to happen by sending specific "back-pressure" flow control
713 * frames to its peer(s).
715 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
716 "status=0x%x pkt_len=%u\n",
717 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
718 (unsigned) rx_id, (unsigned) status,
719 (unsigned) rte_le_to_cpu_16(rxd.length));
721 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
723 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
725 (unsigned) rxq->port_id,
726 (unsigned) rxq->queue_id);
727 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
732 rxe = &sw_ring[rx_id];
734 if (rx_id == rxq->nb_rx_desc)
737 /* Prefetch next mbuf while processing current one. */
738 rte_em_prefetch(sw_ring[rx_id].mbuf);
741 * When next RX descriptor is on a cache-line boundary,
742 * prefetch the next 4 RX descriptors and the next 8 pointers
745 if ((rx_id & 0x3) == 0) {
746 rte_em_prefetch(&rx_ring[rx_id]);
747 rte_em_prefetch(&sw_ring[rx_id]);
750 /* Rearm RXD: attach new mbuf and reset status to zero. */
755 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
756 rxdp->buffer_addr = dma_addr;
760 * Initialize the returned mbuf.
761 * 1) setup generic mbuf fields:
762 * - number of segments,
765 * - RX port identifier.
766 * 2) integrate hardware offload data, if any:
768 * - IP checksum flag,
769 * - VLAN TCI, if any,
772 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.length) -
774 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
775 rte_packet_prefetch(rxm->pkt.data);
776 rxm->pkt.nb_segs = 1;
777 rxm->pkt.next = NULL;
778 rxm->pkt.pkt_len = pkt_len;
779 rxm->pkt.data_len = pkt_len;
780 rxm->pkt.in_port = rxq->port_id;
782 rxm->ol_flags = rx_desc_status_to_pkt_flags(status);
783 rxm->ol_flags = (uint16_t)(rxm->ol_flags |
784 rx_desc_error_to_pkt_flags(rxd.errors));
786 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
787 rxm->pkt.vlan_macip.f.vlan_tci = rte_le_to_cpu_16(rxd.special);
790 * Store the mbuf address into the next entry of the array
791 * of returned packets.
793 rx_pkts[nb_rx++] = rxm;
795 rxq->rx_tail = rx_id;
798 * If the number of free RX descriptors is greater than the RX free
799 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
801 * Update the RDT with the value of the last processed RX descriptor
802 * minus 1, to guarantee that the RDT register is never equal to the
803 * RDH register, which creates a "full" ring situtation from the
804 * hardware point of view...
806 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
807 if (nb_hold > rxq->rx_free_thresh) {
808 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
809 "nb_hold=%u nb_rx=%u\n",
810 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
811 (unsigned) rx_id, (unsigned) nb_hold,
813 rx_id = (uint16_t) ((rx_id == 0) ?
814 (rxq->nb_rx_desc - 1) : (rx_id - 1));
815 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
818 rxq->nb_rx_hold = nb_hold;
823 eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
826 struct em_rx_queue *rxq;
827 volatile struct e1000_rx_desc *rx_ring;
828 volatile struct e1000_rx_desc *rxdp;
829 struct em_rx_entry *sw_ring;
830 struct em_rx_entry *rxe;
831 struct rte_mbuf *first_seg;
832 struct rte_mbuf *last_seg;
833 struct rte_mbuf *rxm;
834 struct rte_mbuf *nmb;
835 struct e1000_rx_desc rxd;
836 uint64_t dma; /* Physical address of mbuf data buffer */
847 rx_id = rxq->rx_tail;
848 rx_ring = rxq->rx_ring;
849 sw_ring = rxq->sw_ring;
852 * Retrieve RX context of current packet, if any.
854 first_seg = rxq->pkt_first_seg;
855 last_seg = rxq->pkt_last_seg;
857 while (nb_rx < nb_pkts) {
860 * The order of operations here is important as the DD status
861 * bit must not be read after any other descriptor fields.
862 * rx_ring and rxdp are pointing to volatile data so the order
863 * of accesses cannot be reordered by the compiler. If they were
864 * not volatile, they could be reordered which could lead to
865 * using invalid descriptor fields when read from rxd.
867 rxdp = &rx_ring[rx_id];
868 status = rxdp->status;
869 if (! (status & E1000_RXD_STAT_DD))
876 * Allocate a new mbuf to replenish the RX ring descriptor.
877 * If the allocation fails:
878 * - arrange for that RX descriptor to be the first one
879 * being parsed the next time the receive function is
880 * invoked [on the same queue].
882 * - Stop parsing the RX ring and return immediately.
884 * This policy does not drop the packet received in the RX
885 * descriptor for which the allocation of a new mbuf failed.
886 * Thus, it allows that packet to be later retrieved if
887 * mbuf have been freed in the mean time.
888 * As a side effect, holding RX descriptors instead of
889 * systematically giving them back to the NIC may lead to
890 * RX ring exhaustion situations.
891 * However, the NIC can gracefully prevent such situations
892 * to happen by sending specific "back-pressure" flow control
893 * frames to its peer(s).
895 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
896 "status=0x%x data_len=%u\n",
897 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
898 (unsigned) rx_id, (unsigned) status,
899 (unsigned) rte_le_to_cpu_16(rxd.length));
901 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
903 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
904 "queue_id=%u\n", (unsigned) rxq->port_id,
905 (unsigned) rxq->queue_id);
906 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
911 rxe = &sw_ring[rx_id];
913 if (rx_id == rxq->nb_rx_desc)
916 /* Prefetch next mbuf while processing current one. */
917 rte_em_prefetch(sw_ring[rx_id].mbuf);
920 * When next RX descriptor is on a cache-line boundary,
921 * prefetch the next 4 RX descriptors and the next 8 pointers
924 if ((rx_id & 0x3) == 0) {
925 rte_em_prefetch(&rx_ring[rx_id]);
926 rte_em_prefetch(&sw_ring[rx_id]);
930 * Update RX descriptor with the physical address of the new
931 * data buffer of the new allocated mbuf.
935 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
936 rxdp->buffer_addr = dma;
940 * Set data length & data buffer address of mbuf.
942 data_len = rte_le_to_cpu_16(rxd.length);
943 rxm->pkt.data_len = data_len;
944 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
947 * If this is the first buffer of the received packet,
948 * set the pointer to the first mbuf of the packet and
949 * initialize its context.
950 * Otherwise, update the total length and the number of segments
951 * of the current scattered packet, and update the pointer to
952 * the last mbuf of the current packet.
954 if (first_seg == NULL) {
956 first_seg->pkt.pkt_len = data_len;
957 first_seg->pkt.nb_segs = 1;
959 first_seg->pkt.pkt_len += data_len;
960 first_seg->pkt.nb_segs++;
961 last_seg->pkt.next = rxm;
965 * If this is not the last buffer of the received packet,
966 * update the pointer to the last mbuf of the current scattered
967 * packet and continue to parse the RX ring.
969 if (! (status & E1000_RXD_STAT_EOP)) {
975 * This is the last buffer of the received packet.
976 * If the CRC is not stripped by the hardware:
977 * - Subtract the CRC length from the total packet length.
978 * - If the last buffer only contains the whole CRC or a part
979 * of it, free the mbuf associated to the last buffer.
980 * If part of the CRC is also contained in the previous
981 * mbuf, subtract the length of that CRC part from the
982 * data length of the previous mbuf.
984 rxm->pkt.next = NULL;
985 if (unlikely(rxq->crc_len > 0)) {
986 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
987 if (data_len <= ETHER_CRC_LEN) {
988 rte_pktmbuf_free_seg(rxm);
989 first_seg->pkt.nb_segs--;
990 last_seg->pkt.data_len = (uint16_t)
991 (last_seg->pkt.data_len -
992 (ETHER_CRC_LEN - data_len));
993 last_seg->pkt.next = NULL;
996 (uint16_t) (data_len - ETHER_CRC_LEN);
1000 * Initialize the first mbuf of the returned packet:
1001 * - RX port identifier,
1002 * - hardware offload data, if any:
1003 * - IP checksum flag,
1006 first_seg->pkt.in_port = rxq->port_id;
1008 first_seg->ol_flags = rx_desc_status_to_pkt_flags(status);
1009 first_seg->ol_flags = (uint16_t)(first_seg->ol_flags |
1010 rx_desc_error_to_pkt_flags(rxd.errors));
1012 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1013 rxm->pkt.vlan_macip.f.vlan_tci = rte_le_to_cpu_16(rxd.special);
1015 /* Prefetch data of first segment, if configured to do so. */
1016 rte_packet_prefetch(first_seg->pkt.data);
1019 * Store the mbuf address into the next entry of the array
1020 * of returned packets.
1022 rx_pkts[nb_rx++] = first_seg;
1025 * Setup receipt context for a new packet.
1031 * Record index of the next RX descriptor to probe.
1033 rxq->rx_tail = rx_id;
1036 * Save receive context.
1038 rxq->pkt_first_seg = first_seg;
1039 rxq->pkt_last_seg = last_seg;
1042 * If the number of free RX descriptors is greater than the RX free
1043 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1045 * Update the RDT with the value of the last processed RX descriptor
1046 * minus 1, to guarantee that the RDT register is never equal to the
1047 * RDH register, which creates a "full" ring situtation from the
1048 * hardware point of view...
1050 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1051 if (nb_hold > rxq->rx_free_thresh) {
1052 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1053 "nb_hold=%u nb_rx=%u\n",
1054 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1055 (unsigned) rx_id, (unsigned) nb_hold,
1057 rx_id = (uint16_t) ((rx_id == 0) ?
1058 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1059 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1062 rxq->nb_rx_hold = nb_hold;
1067 * Rings setup and release.
1069 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1070 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
1071 * This will also optimize cache line size effect.
1072 * H/W supports up to cache line size 128.
1074 #define EM_ALIGN 128
1077 * Maximum number of Ring Descriptors.
1079 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1080 * desscriptors should meet the following condition:
1081 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1083 #define EM_MIN_RING_DESC 32
1084 #define EM_MAX_RING_DESC 4096
1086 #define EM_MAX_BUF_SIZE 16384
1087 #define EM_RCTL_FLXBUF_STEP 1024
1089 static const struct rte_memzone *
1090 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1091 uint16_t queue_id, uint32_t ring_size, int socket_id)
1093 const struct rte_memzone *mz;
1094 char z_name[RTE_MEMZONE_NAMESIZE];
1096 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1097 dev->driver->pci_drv.name, ring_name, dev->data->port_id,
1100 if ((mz = rte_memzone_lookup(z_name)) != 0)
1103 #ifdef RTE_LIBRTE_XEN_DOM0
1104 return rte_memzone_reserve_bounded(z_name, ring_size,
1105 socket_id, 0, CACHE_LINE_SIZE, RTE_PGSIZE_2M);
1107 return rte_memzone_reserve(z_name, ring_size, socket_id, 0);
1112 em_tx_queue_release_mbufs(struct em_tx_queue *txq)
1116 if (txq->sw_ring != NULL) {
1117 for (i = 0; i != txq->nb_tx_desc; i++) {
1118 if (txq->sw_ring[i].mbuf != NULL) {
1119 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1120 txq->sw_ring[i].mbuf = NULL;
1127 em_tx_queue_release(struct em_tx_queue *txq)
1130 em_tx_queue_release_mbufs(txq);
1131 rte_free(txq->sw_ring);
1137 eth_em_tx_queue_release(void *txq)
1139 em_tx_queue_release(txq);
1142 /* (Re)set dynamic em_tx_queue fields to defaults */
1144 em_reset_tx_queue(struct em_tx_queue *txq)
1146 uint16_t i, nb_desc, prev;
1147 static const struct e1000_data_desc txd_init = {
1148 .upper.fields = {.status = E1000_TXD_STAT_DD},
1151 nb_desc = txq->nb_tx_desc;
1153 /* Initialize ring entries */
1155 prev = (uint16_t) (nb_desc - 1);
1157 for (i = 0; i < nb_desc; i++) {
1158 txq->tx_ring[i] = txd_init;
1159 txq->sw_ring[i].mbuf = NULL;
1160 txq->sw_ring[i].last_id = i;
1161 txq->sw_ring[prev].next_id = i;
1166 * Always allow 1 descriptor to be un-allocated to avoid
1167 * a H/W race condition
1169 txq->nb_tx_free = (uint16_t)(nb_desc - 1);
1170 txq->last_desc_cleaned = (uint16_t)(nb_desc - 1);
1171 txq->nb_tx_used = 0;
1174 memset((void*)&txq->ctx_cache, 0, sizeof (txq->ctx_cache));
1178 eth_em_tx_queue_setup(struct rte_eth_dev *dev,
1181 unsigned int socket_id,
1182 const struct rte_eth_txconf *tx_conf)
1184 const struct rte_memzone *tz;
1185 struct em_tx_queue *txq;
1186 struct e1000_hw *hw;
1188 uint16_t tx_rs_thresh, tx_free_thresh;
1190 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1193 * Validate number of transmit descriptors.
1194 * It must not exceed hardware maximum, and must be multiple
1197 if (((nb_desc * sizeof(*txq->tx_ring)) % EM_ALIGN) != 0 ||
1198 (nb_desc > EM_MAX_RING_DESC) ||
1199 (nb_desc < EM_MIN_RING_DESC)) {
1203 tx_free_thresh = tx_conf->tx_free_thresh;
1204 if (tx_free_thresh == 0)
1205 tx_free_thresh = (uint16_t)RTE_MIN(nb_desc / 4,
1206 DEFAULT_TX_FREE_THRESH);
1208 tx_rs_thresh = tx_conf->tx_rs_thresh;
1209 if (tx_rs_thresh == 0)
1210 tx_rs_thresh = (uint16_t)RTE_MIN(tx_free_thresh,
1211 DEFAULT_TX_RS_THRESH);
1213 if (tx_free_thresh >= (nb_desc - 3)) {
1214 RTE_LOG(ERR, PMD, "tx_free_thresh must be less than the "
1215 "number of TX descriptors minus 3. (tx_free_thresh=%u "
1216 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1217 (int)dev->data->port_id, (int)queue_idx);
1220 if (tx_rs_thresh > tx_free_thresh) {
1221 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1222 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1223 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1224 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1230 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1231 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1232 * by the NIC and all descriptors are written back after the NIC
1233 * accumulates WTHRESH descriptors.
1235 if (tx_conf->tx_thresh.wthresh != 0 && tx_rs_thresh != 1) {
1236 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1237 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1238 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1239 (int)dev->data->port_id, (int)queue_idx);
1243 /* Free memory prior to re-allocation if needed... */
1244 if (dev->data->tx_queues[queue_idx] != NULL) {
1245 em_tx_queue_release(dev->data->tx_queues[queue_idx]);
1246 dev->data->tx_queues[queue_idx] = NULL;
1250 * Allocate TX ring hardware descriptors. A memzone large enough to
1251 * handle the maximum ring size is allocated in order to allow for
1252 * resizing in later calls to the queue setup function.
1254 tsize = sizeof (txq->tx_ring[0]) * EM_MAX_RING_DESC;
1255 if ((tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx, tsize,
1256 socket_id)) == NULL)
1259 /* Allocate the tx queue data structure. */
1260 if ((txq = rte_zmalloc("ethdev TX queue", sizeof(*txq),
1261 CACHE_LINE_SIZE)) == NULL)
1264 /* Allocate software ring */
1265 if ((txq->sw_ring = rte_zmalloc("txq->sw_ring",
1266 sizeof(txq->sw_ring[0]) * nb_desc,
1267 CACHE_LINE_SIZE)) == NULL) {
1268 em_tx_queue_release(txq);
1272 txq->nb_tx_desc = nb_desc;
1273 txq->tx_free_thresh = tx_free_thresh;
1274 txq->tx_rs_thresh = tx_rs_thresh;
1275 txq->pthresh = tx_conf->tx_thresh.pthresh;
1276 txq->hthresh = tx_conf->tx_thresh.hthresh;
1277 txq->wthresh = tx_conf->tx_thresh.wthresh;
1278 if (txq->wthresh > 0 && hw->mac.type == e1000_82576)
1280 txq->queue_id = queue_idx;
1281 txq->port_id = dev->data->port_id;
1283 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
1284 #ifndef RTE_LIBRTE_XEN_DOM0
1285 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1287 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1289 txq->tx_ring = (struct e1000_data_desc *) tz->addr;
1291 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1292 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1294 em_reset_tx_queue(txq);
1296 dev->data->tx_queues[queue_idx] = txq;
1301 em_rx_queue_release_mbufs(struct em_rx_queue *rxq)
1305 if (rxq->sw_ring != NULL) {
1306 for (i = 0; i != rxq->nb_rx_desc; i++) {
1307 if (rxq->sw_ring[i].mbuf != NULL) {
1308 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1309 rxq->sw_ring[i].mbuf = NULL;
1316 em_rx_queue_release(struct em_rx_queue *rxq)
1319 em_rx_queue_release_mbufs(rxq);
1320 rte_free(rxq->sw_ring);
1326 eth_em_rx_queue_release(void *rxq)
1328 em_rx_queue_release(rxq);
1331 /* Reset dynamic em_rx_queue fields back to defaults */
1333 em_reset_rx_queue(struct em_rx_queue *rxq)
1336 rxq->nb_rx_hold = 0;
1337 rxq->pkt_first_seg = NULL;
1338 rxq->pkt_last_seg = NULL;
1342 eth_em_rx_queue_setup(struct rte_eth_dev *dev,
1345 unsigned int socket_id,
1346 const struct rte_eth_rxconf *rx_conf,
1347 struct rte_mempool *mp)
1349 const struct rte_memzone *rz;
1350 struct em_rx_queue *rxq;
1351 struct e1000_hw *hw;
1354 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 * Validate number of receive descriptors.
1358 * It must not exceed hardware maximum, and must be multiple
1361 if (((nb_desc * sizeof(rxq->rx_ring[0])) % EM_ALIGN) != 0 ||
1362 (nb_desc > EM_MAX_RING_DESC) ||
1363 (nb_desc < EM_MIN_RING_DESC)) {
1368 * EM devices don't support drop_en functionality
1370 if (rx_conf->rx_drop_en) {
1371 RTE_LOG(ERR, PMD, "drop_en functionality not supported by device\n");
1375 /* Free memory prior to re-allocation if needed. */
1376 if (dev->data->rx_queues[queue_idx] != NULL) {
1377 em_rx_queue_release(dev->data->rx_queues[queue_idx]);
1378 dev->data->rx_queues[queue_idx] = NULL;
1381 /* Allocate RX ring for max possible mumber of hardware descriptors. */
1382 rsize = sizeof (rxq->rx_ring[0]) * EM_MAX_RING_DESC;
1383 if ((rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx, rsize,
1384 socket_id)) == NULL)
1387 /* Allocate the RX queue data structure. */
1388 if ((rxq = rte_zmalloc("ethdev RX queue", sizeof(*rxq),
1389 CACHE_LINE_SIZE)) == NULL)
1392 /* Allocate software ring. */
1393 if ((rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1394 sizeof (rxq->sw_ring[0]) * nb_desc,
1395 CACHE_LINE_SIZE)) == NULL) {
1396 em_rx_queue_release(rxq);
1401 rxq->nb_rx_desc = nb_desc;
1402 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1403 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1404 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1405 if (rxq->wthresh > 0 && hw->mac.type == e1000_82576)
1408 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1409 rxq->queue_id = queue_idx;
1410 rxq->port_id = dev->data->port_id;
1411 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1414 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
1415 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));
1416 #ifndef RTE_LIBRTE_XEN_DOM0
1417 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1419 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1421 rxq->rx_ring = (struct e1000_rx_desc *) rz->addr;
1423 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1424 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1426 dev->data->rx_queues[queue_idx] = rxq;
1427 em_reset_rx_queue(rxq);
1433 eth_em_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1435 #define EM_RXQ_SCAN_INTERVAL 4
1436 volatile struct e1000_rx_desc *rxdp;
1437 struct em_rx_queue *rxq;
1440 if (rx_queue_id >= dev->data->nb_rx_queues) {
1441 PMD_RX_LOG(DEBUG,"Invalid RX queue_id=%d\n", rx_queue_id);
1445 rxq = dev->data->rx_queues[rx_queue_id];
1446 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1448 while ((desc < rxq->nb_rx_desc) &&
1449 (rxdp->status & E1000_RXD_STAT_DD)) {
1450 desc += EM_RXQ_SCAN_INTERVAL;
1451 rxdp += EM_RXQ_SCAN_INTERVAL;
1452 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1453 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1454 desc - rxq->nb_rx_desc]);
1461 eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset)
1463 volatile struct e1000_rx_desc *rxdp;
1464 struct em_rx_queue *rxq = rx_queue;
1467 if (unlikely(offset >= rxq->nb_rx_desc))
1469 desc = rxq->rx_tail + offset;
1470 if (desc >= rxq->nb_rx_desc)
1471 desc -= rxq->nb_rx_desc;
1473 rxdp = &rxq->rx_ring[desc];
1474 return !!(rxdp->status & E1000_RXD_STAT_DD);
1478 em_dev_clear_queues(struct rte_eth_dev *dev)
1481 struct em_tx_queue *txq;
1482 struct em_rx_queue *rxq;
1484 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1485 txq = dev->data->tx_queues[i];
1487 em_tx_queue_release_mbufs(txq);
1488 em_reset_tx_queue(txq);
1492 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1493 rxq = dev->data->rx_queues[i];
1495 em_rx_queue_release_mbufs(rxq);
1496 em_reset_rx_queue(rxq);
1502 * Takes as input/output parameter RX buffer size.
1503 * Returns (BSIZE | BSEX | FLXBUF) fields of RCTL register.
1506 em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp, uint32_t *bufsz)
1509 * For BSIZE & BSEX all configurable sizes are:
1510 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1511 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1512 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1513 * 2048: rctl |= E1000_RCTL_SZ_2048;
1514 * 1024: rctl |= E1000_RCTL_SZ_1024;
1515 * 512: rctl |= E1000_RCTL_SZ_512;
1516 * 256: rctl |= E1000_RCTL_SZ_256;
1518 static const struct {
1521 } bufsz_to_rctl[] = {
1522 {16384, (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX)},
1523 {8192, (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX)},
1524 {4096, (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX)},
1525 {2048, E1000_RCTL_SZ_2048},
1526 {1024, E1000_RCTL_SZ_1024},
1527 {512, E1000_RCTL_SZ_512},
1528 {256, E1000_RCTL_SZ_256},
1532 uint32_t rctl_bsize;
1534 rctl_bsize = *bufsz;
1537 * Starting from 82571 it is possible to specify RX buffer size
1538 * by RCTL.FLXBUF. When this field is different from zero, the
1539 * RX buffer size = RCTL.FLXBUF * 1K
1540 * (e.g. t is possible to specify RX buffer size 1,2,...,15KB).
1541 * It is working ok on real HW, but by some reason doesn't work
1542 * on VMware emulated 82574L.
1543 * So for now, always use BSIZE/BSEX to setup RX buffer size.
1544 * If you don't plan to use it on VMware emulated 82574L and
1545 * would like to specify RX buffer size in 1K granularity,
1546 * uncomment the following lines:
1547 * ***************************************************************
1548 * if (hwtyp >= e1000_82571 && hwtyp <= e1000_82574 &&
1549 * rctl_bsize >= EM_RCTL_FLXBUF_STEP) {
1550 * rctl_bsize /= EM_RCTL_FLXBUF_STEP;
1551 * *bufsz = rctl_bsize;
1552 * return (rctl_bsize << E1000_RCTL_FLXBUF_SHIFT &
1553 * E1000_RCTL_FLXBUF_MASK);
1555 * ***************************************************************
1558 for (i = 0; i != sizeof(bufsz_to_rctl) / sizeof(bufsz_to_rctl[0]);
1560 if (rctl_bsize >= bufsz_to_rctl[i].bufsz) {
1561 *bufsz = bufsz_to_rctl[i].bufsz;
1562 return (bufsz_to_rctl[i].rctl);
1566 /* Should never happen. */
1571 em_alloc_rx_queue_mbufs(struct em_rx_queue *rxq)
1573 struct em_rx_entry *rxe = rxq->sw_ring;
1576 static const struct e1000_rx_desc rxd_init = {
1580 /* Initialize software ring entries */
1581 for (i = 0; i < rxq->nb_rx_desc; i++) {
1582 volatile struct e1000_rx_desc *rxd;
1583 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1586 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1587 "queue_id=%hu\n", rxq->queue_id);
1588 em_rx_queue_release(rxq);
1592 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
1594 /* Clear HW ring memory */
1595 rxq->rx_ring[i] = rxd_init;
1597 rxd = &rxq->rx_ring[i];
1598 rxd->buffer_addr = dma_addr;
1605 /*********************************************************************
1607 * Enable receive unit.
1609 **********************************************************************/
1611 eth_em_rx_init(struct rte_eth_dev *dev)
1613 struct e1000_hw *hw;
1614 struct em_rx_queue *rxq;
1618 uint32_t rctl_bsize;
1622 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625 * Make sure receives are disabled while setting
1626 * up the descriptor ring.
1628 rctl = E1000_READ_REG(hw, E1000_RCTL);
1629 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1631 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1633 /* Disable extended descriptor type. */
1634 rfctl &= ~E1000_RFCTL_EXTEN;
1635 /* Disable accelerated acknowledge */
1636 if (hw->mac.type == e1000_82574)
1637 rfctl |= E1000_RFCTL_ACK_DIS;
1639 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1642 * XXX TEMPORARY WORKAROUND: on some systems with 82573
1643 * long latencies are observed, like Lenovo X60. This
1644 * change eliminates the problem, but since having positive
1645 * values in RDTR is a known source of problems on other
1646 * platforms another solution is being sought.
1648 if (hw->mac.type == e1000_82573)
1649 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
1651 dev->rx_pkt_burst = (eth_rx_burst_t)eth_em_recv_pkts;
1653 /* Determine RX bufsize. */
1654 rctl_bsize = EM_MAX_BUF_SIZE;
1655 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1656 struct rte_pktmbuf_pool_private *mbp_priv;
1659 rxq = dev->data->rx_queues[i];
1660 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
1661 buf_size = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1662 rctl_bsize = RTE_MIN(rctl_bsize, buf_size);
1665 rctl |= em_rctl_bsize(hw->mac.type, &rctl_bsize);
1667 /* Configure and enable each RX queue. */
1668 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1672 rxq = dev->data->rx_queues[i];
1674 /* Allocate buffers for descriptor rings and setup queue */
1675 ret = em_alloc_rx_queue_mbufs(rxq);
1680 * Reset crc_len in case it was changed after queue setup by a
1684 (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1687 bus_addr = rxq->rx_ring_phys_addr;
1688 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1690 sizeof(*rxq->rx_ring));
1691 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1692 (uint32_t)(bus_addr >> 32));
1693 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1695 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1696 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1698 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1699 rxdctl &= 0xFE000000;
1700 rxdctl |= rxq->pthresh & 0x3F;
1701 rxdctl |= (rxq->hthresh & 0x3F) << 8;
1702 rxdctl |= (rxq->wthresh & 0x3F) << 16;
1703 rxdctl |= E1000_RXDCTL_GRAN;
1704 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1707 * Due to EM devices not having any sort of hardware
1708 * limit for packet length, jumbo frame of any size
1709 * can be accepted, thus we have to enable scattered
1710 * rx if jumbo frames are enabled (or if buffer size
1711 * is too small to accomodate non-jumbo packets)
1712 * to avoid splitting packets that don't fit into
1715 if (dev->data->dev_conf.rxmode.jumbo_frame ||
1716 rctl_bsize < ETHER_MAX_LEN) {
1718 (eth_rx_burst_t)eth_em_recv_scattered_pkts;
1719 dev->data->scattered_rx = 1;
1724 * Setup the Checksum Register.
1725 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1727 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1729 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
1730 rxcsum |= E1000_RXCSUM_IPOFL;
1732 rxcsum &= ~E1000_RXCSUM_IPOFL;
1733 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1735 /* No MRQ or RSS support for now */
1737 /* Set early receive threshold on appropriate hw */
1738 if ((hw->mac.type == e1000_ich9lan ||
1739 hw->mac.type == e1000_pch2lan ||
1740 hw->mac.type == e1000_ich10lan) &&
1741 dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1742 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1743 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
1744 E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
1747 if (hw->mac.type == e1000_pch2lan) {
1748 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1749 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
1751 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
1754 /* Setup the Receive Control Register. */
1755 if (dev->data->dev_conf.rxmode.hw_strip_crc)
1756 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1758 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1760 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1761 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1762 E1000_RCTL_RDMTS_HALF |
1763 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1765 /* Make sure VLAN Filters are off. */
1766 rctl &= ~E1000_RCTL_VFE;
1767 /* Don't store bad packets. */
1768 rctl &= ~E1000_RCTL_SBP;
1769 /* Legacy descriptor type. */
1770 rctl &= ~E1000_RCTL_DTYP_MASK;
1773 * Configure support of jumbo frames, if any.
1775 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1776 rctl |= E1000_RCTL_LPE;
1778 rctl &= ~E1000_RCTL_LPE;
1780 /* Enable Receives. */
1781 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1786 /*********************************************************************
1788 * Enable transmit unit.
1790 **********************************************************************/
1792 eth_em_tx_init(struct rte_eth_dev *dev)
1794 struct e1000_hw *hw;
1795 struct em_tx_queue *txq;
1800 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802 /* Setup the Base and Length of the Tx Descriptor Rings. */
1803 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1806 txq = dev->data->tx_queues[i];
1807 bus_addr = txq->tx_ring_phys_addr;
1808 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1810 sizeof(*txq->tx_ring));
1811 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1812 (uint32_t)(bus_addr >> 32));
1813 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1815 /* Setup the HW Tx Head and Tail descriptor pointers. */
1816 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1817 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1819 /* Setup Transmit threshold registers. */
1820 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1822 * bit 22 is reserved, on some models should always be 0,
1823 * on others - always 1.
1825 txdctl &= E1000_TXDCTL_COUNT_DESC;
1826 txdctl |= txq->pthresh & 0x3F;
1827 txdctl |= (txq->hthresh & 0x3F) << 8;
1828 txdctl |= (txq->wthresh & 0x3F) << 16;
1829 txdctl |= E1000_TXDCTL_GRAN;
1830 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1833 /* Program the Transmit Control Register. */
1834 tctl = E1000_READ_REG(hw, E1000_TCTL);
1835 tctl &= ~E1000_TCTL_CT;
1836 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1837 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1839 /* This write will effectively turn on the transmit unit. */
1840 E1000_WRITE_REG(hw, E1000_TCTL, tctl);