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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "e1000/e1000_defines.h"
53 #include "e1000/e1000_regs.h"
54 #include "e1000/e1000_hw.h"
55 #include "e1000_ethdev.h"
58 void eth_random_addr(uint8_t *addr)
60 uint64_t rand = rte_rand();
61 uint8_t *p = (uint8_t*)&rand;
63 rte_memcpy(addr, p, ETHER_ADDR_LEN);
64 addr[0] &= 0xfe; /* clear multicast bit */
65 addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
68 static inline uint16_t
69 dev_num_vf(struct rte_eth_dev *eth_dev)
71 return eth_dev->pci_dev->max_vfs;
75 int igb_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
77 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
78 struct e1000_vf_info *vfinfo =
79 *E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
82 for (vfn = 0; vfn < vf_num; vfn++) {
83 eth_random_addr(vf_mac_addr);
84 /* keep the random address as default */
85 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
93 igb_mb_intr_setup(struct rte_eth_dev *dev)
95 struct e1000_interrupt *intr =
96 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
98 intr->mask |= E1000_ICR_VMMB;
103 void igb_pf_host_init(struct rte_eth_dev *eth_dev)
105 struct e1000_vf_info **vfinfo =
106 E1000_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
107 struct e1000_hw *hw =
108 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
112 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
113 if (0 == (vf_num = dev_num_vf(eth_dev)))
116 if (hw->mac.type == e1000_i350)
118 else if(hw->mac.type == e1000_82576)
119 /* per datasheet, it should be 2, but 1 seems correct */
124 *vfinfo = rte_zmalloc("vf_info", sizeof(struct e1000_vf_info) * vf_num, 0);
126 rte_panic("Cannot allocate memory for private VF data\n");
128 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_8_POOLS;
129 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
130 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
131 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
133 igb_vf_perm_addr_gen(eth_dev, vf_num);
135 /* set mb interrupt mask */
136 igb_mb_intr_setup(eth_dev);
141 #define E1000_RAH_POOLSEL_SHIFT (18)
142 int igb_pf_host_configure(struct rte_eth_dev *eth_dev)
146 struct e1000_hw *hw =
147 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
152 if (0 == (vf_num = dev_num_vf(eth_dev)))
155 /* enable VMDq and set the default pool for PF */
156 vtctl = E1000_READ_REG(hw, E1000_VT_CTL);
157 vtctl &= ~E1000_VT_CTL_DEFAULT_POOL_MASK;
158 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
159 << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
160 vtctl |= E1000_VT_CTL_VM_REPL_EN;
161 E1000_WRITE_REG(hw, E1000_VT_CTL, vtctl);
163 /* Enable pools reserved to PF only */
164 E1000_WRITE_REG(hw, E1000_VFRE, (~0) << vf_num);
165 E1000_WRITE_REG(hw, E1000_VFTE, (~0) << vf_num);
167 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
168 if (hw->mac.type == e1000_i350)
169 E1000_WRITE_REG(hw, E1000_TXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
171 E1000_WRITE_REG(hw, E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
173 /* clear VMDq map to perment rar 0 */
174 rah = E1000_READ_REG(hw, E1000_RAH(0));
175 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
176 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
178 /* clear VMDq map to scan rar 32 */
179 rah = E1000_READ_REG(hw, E1000_RAH(hw->mac.rar_entry_count));
180 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
181 E1000_WRITE_REG(hw, E1000_RAH(hw->mac.rar_entry_count), rah);
183 /* set VMDq map to default PF pool */
184 rah = E1000_READ_REG(hw, E1000_RAH(0));
185 rah |= (0x1 << (RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx +
186 E1000_RAH_POOLSEL_SHIFT));
187 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
190 * enable vlan filtering and allow all vlan tags through
192 vlanctrl = E1000_READ_REG(hw, E1000_RCTL);
193 vlanctrl |= E1000_RCTL_VFE ; /* enable vlan filters */
194 E1000_WRITE_REG(hw, E1000_RCTL, vlanctrl);
196 /* VFTA - enable all vlan filters */
197 for (i = 0; i < IGB_VFTA_SIZE; i++) {
198 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, 0xFFFFFFFF);
201 /* Enable/Disable MAC Anti-Spoofing */
202 e1000_vmdq_set_anti_spoofing_pf(hw, FALSE, vf_num);
208 set_rx_mode(struct rte_eth_dev *dev)
210 struct rte_eth_dev_data *dev_data =
211 (struct rte_eth_dev_data*)dev->data->dev_private;
212 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
213 uint32_t fctrl, vmolr = E1000_VMOLR_BAM | E1000_VMOLR_AUPE;
214 uint16_t vfn = dev_num_vf(dev);
216 /* Check for Promiscuous and All Multicast modes */
217 fctrl = E1000_READ_REG(hw, E1000_RCTL);
219 /* set all bits that we expect to always be set */
220 fctrl &= ~E1000_RCTL_SBP; /* disable store-bad-packets */
221 fctrl |= E1000_RCTL_BAM;;
223 /* clear the bits we are changing the status of */
224 fctrl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
226 if (dev_data->promiscuous) {
227 fctrl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
228 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
230 if (dev_data->all_multicast) {
231 fctrl |= E1000_RCTL_MPE;
232 vmolr |= E1000_VMOLR_MPME;
234 vmolr |= E1000_VMOLR_ROMPE;
238 if ((hw->mac.type == e1000_82576) ||
239 (hw->mac.type == e1000_i350)) {
240 vmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) &
241 ~(E1000_VMOLR_MPME | E1000_VMOLR_ROMPE |
243 E1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);
246 E1000_WRITE_REG(hw, E1000_RCTL, fctrl);
250 igb_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
252 struct e1000_hw *hw =
253 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
254 struct e1000_vf_info *vfinfo =
255 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
256 uint32_t vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));
258 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE |
259 E1000_VMOLR_BAM | E1000_VMOLR_AUPE);
260 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);
262 E1000_WRITE_REG(hw, E1000_VMVIR(vf), 0);
264 /* reset multicast table array for vf */
265 vfinfo[vf].num_vf_mc_hashes = 0;
272 igb_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
274 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
277 /* enable transmit and receive for vf */
278 reg = E1000_READ_REG(hw, E1000_VFTE);
279 reg |= (reg | (1 << vf));
280 E1000_WRITE_REG(hw, E1000_VFTE, reg);
282 reg = E1000_READ_REG(hw, E1000_VFRE);
283 reg |= (reg | (1 << vf));
284 E1000_WRITE_REG(hw, E1000_VFRE, reg);
286 igb_vf_reset_event(dev, vf);
290 igb_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
292 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
293 struct e1000_vf_info *vfinfo =
294 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
295 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
296 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
297 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
300 igb_vf_reset_msg(dev, vf);
302 hw->mac.ops.rar_set(hw, vf_mac, rar_entry);
303 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry));
304 rah |= (0x1 << (vf + E1000_RAH_POOLSEL_SHIFT));
305 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);
307 /* reply to reset with ack and vf mac address */
308 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
309 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
310 e1000_write_mbx(hw, msgbuf, 3, vf);
316 igb_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
318 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
319 struct e1000_vf_info *vfinfo =
320 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
321 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
322 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
324 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
325 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
326 hw->mac.ops.rar_set(hw, new_mac, rar_entry);
333 igb_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
339 int entries = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >>
340 E1000_VT_MSGINFO_SHIFT;
341 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
342 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
343 struct e1000_vf_info *vfinfo =
344 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
346 /* only so many hash values supported */
347 entries = RTE_MIN(entries, E1000_MAX_VF_MC_ENTRIES);
350 * salt away the number of multi cast addresses assigned
351 * to this VF for later use to restore when the PF multi cast
354 vfinfo->num_vf_mc_hashes = (uint16_t)entries;
357 * VFs are limited to using the MTA hash table for their multicast
360 for (i = 0; i < entries; i++) {
361 vfinfo->vf_mc_hashes[i] = hash_list[i];
364 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
365 vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F;
366 vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F;
367 mta_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, vector_reg);
368 mta_reg |= (1 << vector_bit);
369 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, vector_reg, mta_reg);
376 igb_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
379 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
380 struct e1000_vf_info *vfinfo =
381 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
382 uint32_t vid_idx, vid_bit, vfta;
384 add = (msgbuf[0] & E1000_VT_MSGINFO_MASK)
385 >> E1000_VT_MSGINFO_SHIFT;
386 vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
389 vfinfo[vf].vlan_count++;
390 else if (vfinfo[vf].vlan_count)
391 vfinfo[vf].vlan_count--;
393 vid_idx = (uint32_t)((vid >> E1000_VFTA_ENTRY_SHIFT) &
394 E1000_VFTA_ENTRY_MASK);
395 vid_bit = (uint32_t)(1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
396 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
402 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
403 E1000_WRITE_FLUSH(hw);
409 igb_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
411 uint16_t mbx_size = E1000_VFMAILBOX_SIZE;
412 uint32_t msgbuf[E1000_VFMAILBOX_SIZE];
414 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
416 retval = e1000_read_mbx(hw, msgbuf, mbx_size, vf);
418 RTE_LOG(ERR, PMD, "Error mbx recv msg from VF %d\n", vf);
422 /* do nothing with the message already processed */
423 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
426 /* flush the ack before we write any messages back */
427 E1000_WRITE_FLUSH(hw);
429 /* perform VF reset */
430 if (msgbuf[0] == E1000_VF_RESET) {
431 return igb_vf_reset(dev, vf, msgbuf);
434 /* check & process VF to PF mailbox message */
435 switch ((msgbuf[0] & 0xFFFF)) {
436 case E1000_VF_SET_MAC_ADDR:
437 retval = igb_vf_set_mac_addr(dev, vf, msgbuf);
439 case E1000_VF_SET_MULTICAST:
440 retval = igb_vf_set_multicast(dev, vf, msgbuf);
442 case E1000_VF_SET_VLAN:
443 retval = igb_vf_set_vlan(dev, vf, msgbuf);
446 RTE_LOG(DEBUG, PMD, "Unhandled Msg %8.8x\n", (unsigned) msgbuf[0]);
447 retval = E1000_ERR_MBX;
451 /* response the VF according to the message process result */
453 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
455 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
457 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
459 e1000_write_mbx(hw, msgbuf, 1, vf);
465 igb_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
467 uint32_t msg = E1000_VT_MSGTYPE_NACK;
468 struct e1000_hw *hw =
469 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
471 e1000_write_mbx(hw, &msg, 1, vf);
474 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev)
477 struct e1000_hw *hw =
478 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
480 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
481 /* check & process vf function level reset */
482 if (!e1000_check_for_rst(hw, vf))
483 igb_vf_reset_event(eth_dev, vf);
485 /* check & process vf mailbox messages */
486 if (!e1000_check_for_msg(hw, vf))
487 igb_rcv_msg_from_vf(eth_dev, vf);
489 /* check & process acks from vf */
490 if (!e1000_check_for_ack(hw, vf))
491 igb_rcv_ack_from_vf(eth_dev, vf);