lib/librte_pmd_e1000/igb_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35
  36 #include <endian.h>
  37 #include <stdio.h>
  38 #include <stdlib.h>
  39 #include <string.h>
  40 #include <errno.h>
  41 #include <stdint.h>
  42 #include <stdarg.h>
  43 #include <inttypes.h>
  44
  45 #include <rte_interrupts.h>
  46 #include <rte_byteorder.h>
  47 #include <rte_common.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_memory.h>
  52 #include <rte_memcpy.h>
  53 #include <rte_memzone.h>
  54 #include <rte_launch.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_per_lcore.h>
  58 #include <rte_lcore.h>
  59 #include <rte_atomic.h>
  60 #include <rte_branch_prediction.h>
  61 #include <rte_ring.h>
  62 #include <rte_mempool.h>
  63 #include <rte_malloc.h>
  64 #include <rte_mbuf.h>
  65 #include <rte_ether.h>
  66 #include <rte_ethdev.h>
  67 #include <rte_prefetch.h>
  68 #include <rte_udp.h>
  69 #include <rte_tcp.h>
  70 #include <rte_sctp.h>
  71 #include <rte_string_fns.h>
  72
  73 #include "e1000_logs.h"
  74 #include "e1000/e1000_api.h"
  75 #include "e1000_ethdev.h"
  76
  77 static inline struct rte_mbuf *
  78 rte_rxmbuf_alloc(struct rte_mempool *mp)
  79 {
  80         struct rte_mbuf *m;
  81
  82         m = __rte_mbuf_raw_alloc(mp);
  83         __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
  84         return (m);
  85 }
  86
  87 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  88         (uint64_t) ((mb)->buf_physaddr +                   \
  89                         (uint64_t) ((char *)((mb)->pkt.data) -     \
  90                                 (char *)(mb)->buf_addr))
  91
  92 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  93         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  94
  95 /**
  96  * Structure associated with each descriptor of the RX ring of a RX queue.
  97  */
  98 struct igb_rx_entry {
  99         struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
 100 };
 101
 102 /**
 103  * Structure associated with each descriptor of the TX ring of a TX queue.
 104  */
 105 struct igb_tx_entry {
 106         struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
 107         uint16_t next_id; /**< Index of next descriptor in ring. */
 108         uint16_t last_id; /**< Index of last scattered descriptor. */
 109 };
 110
 111 /**
 112  * Structure associated with each RX queue.
 113  */
 114 struct igb_rx_queue {
 115         struct rte_mempool  *mb_pool;   /**< mbuf pool to populate RX ring. */
 116         volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
 117         uint64_t            rx_ring_phys_addr; /**< RX ring DMA address. */
 118         volatile uint32_t   *rdt_reg_addr; /**< RDT register address. */
 119         volatile uint32_t   *rdh_reg_addr; /**< RDH register address. */
 120         struct igb_rx_entry *sw_ring;   /**< address of RX software ring. */
 121         struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
 122         struct rte_mbuf *pkt_last_seg;  /**< Last segment of current packet. */
 123         uint16_t            nb_rx_desc; /**< number of RX descriptors. */
 124         uint16_t            rx_tail;    /**< current value of RDT register. */
 125         uint16_t            nb_rx_hold; /**< number of held free RX desc. */
 126         uint16_t            rx_free_thresh; /**< max free RX desc to hold. */
 127         uint16_t            queue_id;   /**< RX queue index. */
 128         uint16_t            reg_idx;    /**< RX queue register index. */
 129         uint8_t             port_id;    /**< Device port identifier. */
 130         uint8_t             pthresh;    /**< Prefetch threshold register. */
 131         uint8_t             hthresh;    /**< Host threshold register. */
 132         uint8_t             wthresh;    /**< Write-back threshold register. */
 133         uint8_t             crc_len;    /**< 0 if CRC stripped, 4 otherwise. */
 134         uint8_t             drop_en;  /**< If not 0, set SRRCTL.Drop_En. */
 135 };
 136
 137 /**
 138  * Hardware context number
 139  */
 140 enum igb_advctx_num {
 141         IGB_CTX_0    = 0, /**< CTX0    */
 142         IGB_CTX_1    = 1, /**< CTX1    */
 143         IGB_CTX_NUM  = 2, /**< CTX_NUM */
 144 };
 145
 146 /**
 147  * Strucutre to check if new context need be built
 148  */
 149 struct igb_advctx_info {
 150         uint16_t flags;           /**< ol_flags related to context build. */
 151         uint32_t cmp_mask;        /**< compare mask for vlan_macip_lens */
 152         union rte_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */
 153 };
 154
 155 /**
 156  * Structure associated with each TX queue.
 157  */
 158 struct igb_tx_queue {
 159         volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
 160         uint64_t               tx_ring_phys_addr; /**< TX ring DMA address. */
 161         struct igb_tx_entry    *sw_ring; /**< virtual address of SW ring. */
 162         volatile uint32_t      *tdt_reg_addr; /**< Address of TDT register. */
 163         uint32_t               txd_type;      /**< Device-specific TXD type */
 164         uint16_t               nb_tx_desc;    /**< number of TX descriptors. */
 165         uint16_t               tx_tail; /**< Current value of TDT register. */
 166         uint16_t               tx_head;
 167         /**< Index of first used TX descriptor. */
 168         uint16_t               queue_id; /**< TX queue index. */
 169         uint16_t               reg_idx;  /**< TX queue register index. */
 170         uint8_t                port_id;  /**< Device port identifier. */
 171         uint8_t                pthresh;  /**< Prefetch threshold register. */
 172         uint8_t                hthresh;  /**< Host threshold register. */
 173         uint8_t                wthresh;  /**< Write-back threshold register. */
 174         uint32_t               ctx_curr;
 175         /**< Current used hardware descriptor. */
 176         uint32_t               ctx_start;
 177         /**< Start context position for transmit queue. */
 178         struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
 179         /**< Hardware context history.*/
 180 };
 181
 182 #if 1
 183 #define RTE_PMD_USE_PREFETCH
 184 #endif
 185
 186 #ifdef RTE_PMD_USE_PREFETCH
 187 #define rte_igb_prefetch(p)     rte_prefetch0(p)
 188 #else
 189 #define rte_igb_prefetch(p)     do {} while(0)
 190 #endif
 191
 192 #ifdef RTE_PMD_PACKET_PREFETCH
 193 #define rte_packet_prefetch(p) rte_prefetch1(p)
 194 #else
 195 #define rte_packet_prefetch(p)  do {} while(0)
 196 #endif
 197
 198 /*
 199  * Macro for VMDq feature for 1 GbE NIC.
 200  */
 201 #define E1000_VMOLR_SIZE                        (8)
 202
 203 /*********************************************************************
 204  *
 205  *  TX function
 206  *
 207  **********************************************************************/
 208
 209 /*
 210  * Advanced context descriptor are almost same between igb/ixgbe
 211  * This is a separate function, looking for optimization opportunity here
 212  * Rework required to go with the pre-defined values.
 213  */
 214
 215 static inline void
 216 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
 217                 volatile struct e1000_adv_tx_context_desc *ctx_txd,
 218                 uint16_t ol_flags, uint32_t vlan_macip_lens)
 219 {
 220         uint32_t type_tucmd_mlhl;
 221         uint32_t mss_l4len_idx;
 222         uint32_t ctx_idx, ctx_curr;
 223         uint32_t cmp_mask;
 224
 225         ctx_curr = txq->ctx_curr;
 226         ctx_idx = ctx_curr + txq->ctx_start;
 227
 228         cmp_mask = 0;
 229         type_tucmd_mlhl = 0;
 230
 231         if (ol_flags & PKT_TX_VLAN_PKT) {
 232                 cmp_mask |= TX_VLAN_CMP_MASK;
 233         }
 234
 235         if (ol_flags & PKT_TX_IP_CKSUM) {
 236                 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
 237                 cmp_mask |= TX_MAC_LEN_CMP_MASK;
 238         }
 239
 240         /* Specify which HW CTX to upload. */
 241         mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
 242         switch (ol_flags & PKT_TX_L4_MASK) {
 243         case PKT_TX_UDP_CKSUM:
 244                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
 245                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 246                 mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 247                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 248                 break;
 249         case PKT_TX_TCP_CKSUM:
 250                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
 251                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 252                 mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 253                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 254                 break;
 255         case PKT_TX_SCTP_CKSUM:
 256                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
 257                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 258                 mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 259                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 260                 break;
 261         default:
 262                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
 263                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 264                 break;
 265         }
 266
 267         txq->ctx_cache[ctx_curr].flags           = ol_flags;
 268         txq->ctx_cache[ctx_curr].cmp_mask        = cmp_mask;
 269         txq->ctx_cache[ctx_curr].vlan_macip_lens.data =
 270                 vlan_macip_lens & cmp_mask;
 271
 272         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 273         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 274         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 275         ctx_txd->seqnum_seed     = 0;
 276 }
 277
 278 /*
 279  * Check which hardware context can be used. Use the existing match
 280  * or create a new context descriptor.
 281  */
 282 static inline uint32_t
 283 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
 284                 uint32_t vlan_macip_lens)
 285 {
 286         /* If match with the current context */
 287         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 288                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 289                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 290                         return txq->ctx_curr;
 291         }
 292
 293         /* If match with the second context */
 294         txq->ctx_curr ^= 1;
 295         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 296                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 297                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 298                         return txq->ctx_curr;
 299         }
 300
 301         /* Mismatch, use the previous context */
 302         return (IGB_CTX_NUM);
 303 }
 304
 305 static inline uint32_t
 306 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
 307 {
 308         static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
 309         static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
 310         uint32_t tmp;
 311
 312         tmp  = l4_olinfo[(ol_flags & PKT_TX_L4_MASK)  != PKT_TX_L4_NO_CKSUM];
 313         tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
 314         return tmp;
 315 }
 316
 317 static inline uint32_t
 318 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
 319 {
 320         static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
 321         return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
 322 }
 323
 324 uint16_t
 325 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 326                uint16_t nb_pkts)
 327 {
 328         struct igb_tx_queue *txq;
 329         struct igb_tx_entry *sw_ring;
 330         struct igb_tx_entry *txe, *txn;
 331         volatile union e1000_adv_tx_desc *txr;
 332         volatile union e1000_adv_tx_desc *txd;
 333         struct rte_mbuf     *tx_pkt;
 334         struct rte_mbuf     *m_seg;
 335         uint64_t buf_dma_addr;
 336         uint32_t olinfo_status;
 337         uint32_t cmd_type_len;
 338         uint32_t pkt_len;
 339         uint16_t slen;
 340         uint16_t ol_flags;
 341         uint16_t tx_end;
 342         uint16_t tx_id;
 343         uint16_t tx_last;
 344         uint16_t nb_tx;
 345         uint16_t tx_ol_req;
 346         uint32_t new_ctx = 0;
 347         uint32_t ctx = 0;
 348         uint32_t vlan_macip_lens;
 349
 350         txq = tx_queue;
 351         sw_ring = txq->sw_ring;
 352         txr     = txq->tx_ring;
 353         tx_id   = txq->tx_tail;
 354         txe = &sw_ring[tx_id];
 355
 356         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 357                 tx_pkt = *tx_pkts++;
 358                 pkt_len = tx_pkt->pkt.pkt_len;
 359
 360                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
 361
 362                 /*
 363                  * The number of descriptors that must be allocated for a
 364                  * packet is the number of segments of that packet, plus 1
 365                  * Context Descriptor for the VLAN Tag Identifier, if any.
 366                  * Determine the last TX descriptor to allocate in the TX ring
 367                  * for the packet, starting from the current position (tx_id)
 368                  * in the ring.
 369                  */
 370                 tx_last = (uint16_t) (tx_id + tx_pkt->pkt.nb_segs - 1);
 371
 372                 ol_flags = tx_pkt->ol_flags;
 373                 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
 374                 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
 375
 376                 /* If a Context Descriptor need be built . */
 377                 if (tx_ol_req) {
 378                         ctx = what_advctx_update(txq, tx_ol_req,
 379                                 vlan_macip_lens);
 380                         /* Only allocate context descriptor if required*/
 381                         new_ctx = (ctx == IGB_CTX_NUM);
 382                         ctx = txq->ctx_curr;
 383                         tx_last = (uint16_t) (tx_last + new_ctx);
 384                 }
 385                 if (tx_last >= txq->nb_tx_desc)
 386                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 387
 388                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 389                            " tx_first=%u tx_last=%u\n",
 390                            (unsigned) txq->port_id,
 391                            (unsigned) txq->queue_id,
 392                            (unsigned) pkt_len,
 393                            (unsigned) tx_id,
 394                            (unsigned) tx_last);
 395
 396                 /*
 397                  * Check if there are enough free descriptors in the TX ring
 398                  * to transmit the next packet.
 399                  * This operation is based on the two following rules:
 400                  *
 401                  *   1- Only check that the last needed TX descriptor can be
 402                  *      allocated (by construction, if that descriptor is free,
 403                  *      all intermediate ones are also free).
 404                  *
 405                  *      For this purpose, the index of the last TX descriptor
 406                  *      used for a packet (the "last descriptor" of a packet)
 407                  *      is recorded in the TX entries (the last one included)
 408                  *      that are associated with all TX descriptors allocated
 409                  *      for that packet.
 410                  *
 411                  *   2- Avoid to allocate the last free TX descriptor of the
 412                  *      ring, in order to never set the TDT register with the
 413                  *      same value stored in parallel by the NIC in the TDH
 414                  *      register, which makes the TX engine of the NIC enter
 415                  *      in a deadlock situation.
 416                  *
 417                  *      By extension, avoid to allocate a free descriptor that
 418                  *      belongs to the last set of free descriptors allocated
 419                  *      to the same packet previously transmitted.
 420                  */
 421
 422                 /*
 423                  * The "last descriptor" of the previously sent packet, if any,
 424                  * which used the last descriptor to allocate.
 425                  */
 426                 tx_end = sw_ring[tx_last].last_id;
 427
 428                 /*
 429                  * The next descriptor following that "last descriptor" in the
 430                  * ring.
 431                  */
 432                 tx_end = sw_ring[tx_end].next_id;
 433
 434                 /*
 435                  * The "last descriptor" associated with that next descriptor.
 436                  */
 437                 tx_end = sw_ring[tx_end].last_id;
 438
 439                 /*
 440                  * Check that this descriptor is free.
 441                  */
 442                 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
 443                         if (nb_tx == 0)
 444                                 return (0);
 445                         goto end_of_tx;
 446                 }
 447
 448                 /*
 449                  * Set common flags of all TX Data Descriptors.
 450                  *
 451                  * The following bits must be set in all Data Descriptors:
 452                  *   - E1000_ADVTXD_DTYP_DATA
 453                  *   - E1000_ADVTXD_DCMD_DEXT
 454                  *
 455                  * The following bits must be set in the first Data Descriptor
 456                  * and are ignored in the other ones:
 457                  *   - E1000_ADVTXD_DCMD_IFCS
 458                  *   - E1000_ADVTXD_MAC_1588
 459                  *   - E1000_ADVTXD_DCMD_VLE
 460                  *
 461                  * The following bits must only be set in the last Data
 462                  * Descriptor:
 463                  *   - E1000_TXD_CMD_EOP
 464                  *
 465                  * The following bits can be set in any Data Descriptor, but
 466                  * are only set in the last Data Descriptor:
 467                  *   - E1000_TXD_CMD_RS
 468                  */
 469                 cmd_type_len = txq->txd_type |
 470                         E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
 471                 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
 472 #if defined(RTE_LIBRTE_IEEE1588)
 473                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 474                         cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
 475 #endif
 476                 if (tx_ol_req) {
 477                         /* Setup TX Advanced context descriptor if required */
 478                         if (new_ctx) {
 479                                 volatile struct e1000_adv_tx_context_desc *
 480                                     ctx_txd;
 481
 482                                 ctx_txd = (volatile struct
 483                                     e1000_adv_tx_context_desc *)
 484                                     &txr[tx_id];
 485
 486                                 txn = &sw_ring[txe->next_id];
 487                                 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
 488
 489                                 if (txe->mbuf != NULL) {
 490                                         rte_pktmbuf_free_seg(txe->mbuf);
 491                                         txe->mbuf = NULL;
 492                                 }
 493
 494                                 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 495                                     vlan_macip_lens);
 496
 497                                 txe->last_id = tx_last;
 498                                 tx_id = txe->next_id;
 499                                 txe = txn;
 500                         }
 501
 502                         /* Setup the TX Advanced Data Descriptor */
 503                         cmd_type_len  |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
 504                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 505                         olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
 506                 }
 507
 508                 m_seg = tx_pkt;
 509                 do {
 510                         txn = &sw_ring[txe->next_id];
 511                         txd = &txr[tx_id];
 512
 513                         if (txe->mbuf != NULL)
 514                                 rte_pktmbuf_free_seg(txe->mbuf);
 515                         txe->mbuf = m_seg;
 516
 517                         /*
 518                          * Set up transmit descriptor.
 519                          */
 520                         slen = (uint16_t) m_seg->pkt.data_len;
 521                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
 522                         txd->read.buffer_addr =
 523                                 rte_cpu_to_le_64(buf_dma_addr);
 524                         txd->read.cmd_type_len =
 525                                 rte_cpu_to_le_32(cmd_type_len | slen);
 526                         txd->read.olinfo_status =
 527                                 rte_cpu_to_le_32(olinfo_status);
 528                         txe->last_id = tx_last;
 529                         tx_id = txe->next_id;
 530                         txe = txn;
 531                         m_seg = m_seg->pkt.next;
 532                 } while (m_seg != NULL);
 533
 534                 /*
 535                  * The last packet data descriptor needs End Of Packet (EOP)
 536                  * and Report Status (RS).
 537                  */
 538                 txd->read.cmd_type_len |=
 539                         rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
 540         }
 541  end_of_tx:
 542         rte_wmb();
 543
 544         /*
 545          * Set the Transmit Descriptor Tail (TDT).
 546          */
 547         E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
 548         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 549                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 550                    (unsigned) tx_id, (unsigned) nb_tx);
 551         txq->tx_tail = tx_id;
 552
 553         return (nb_tx);
 554 }
 555
 556 /*********************************************************************
 557  *
 558  *  RX functions
 559  *
 560  **********************************************************************/
 561 static inline uint16_t
 562 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
 563 {
 564         uint16_t pkt_flags;
 565
 566         static uint16_t ip_pkt_types_map[16] = {
 567                 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
 568                 PKT_RX_IPV6_HDR, 0, 0, 0,
 569                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 570                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 571         };
 572
 573 #if defined(RTE_LIBRTE_IEEE1588)
 574         static uint32_t ip_pkt_etqf_map[8] = {
 575                 0, 0, 0, PKT_RX_IEEE1588_PTP,
 576                 0, 0, 0, 0,
 577         };
 578
 579         pkt_flags = (uint16_t)((hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ?
 580                                 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
 581                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
 582 #else
 583         pkt_flags = (uint16_t)((hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ? 0 :
 584                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
 585 #endif
 586         return (uint16_t)(pkt_flags | (((hl_tp_rs & 0x0F) == 0) ?
 587                                                 0 : PKT_RX_RSS_HASH));
 588 }
 589
 590 static inline uint16_t
 591 rx_desc_status_to_pkt_flags(uint32_t rx_status)
 592 {
 593         uint16_t pkt_flags;
 594
 595         /* Check if VLAN present */
 596         pkt_flags = (uint16_t)((rx_status & E1000_RXD_STAT_VP) ?
 597                                                 PKT_RX_VLAN_PKT : 0);
 598
 599 #if defined(RTE_LIBRTE_IEEE1588)
 600         if (rx_status & E1000_RXD_STAT_TMST)
 601                 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
 602 #endif
 603         return pkt_flags;
 604 }
 605
 606 static inline uint16_t
 607 rx_desc_error_to_pkt_flags(uint32_t rx_status)
 608 {
 609         /*
 610          * Bit 30: IPE, IPv4 checksum error
 611          * Bit 29: L4I, L4I integrity error
 612          */
 613
 614         static uint16_t error_to_pkt_flags_map[4] = {
 615                 0,  PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
 616                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
 617         };
 618         return error_to_pkt_flags_map[(rx_status >>
 619                 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
 620 }
 621
 622 uint16_t
 623 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 624                uint16_t nb_pkts)
 625 {
 626         struct igb_rx_queue *rxq;
 627         volatile union e1000_adv_rx_desc *rx_ring;
 628         volatile union e1000_adv_rx_desc *rxdp;
 629         struct igb_rx_entry *sw_ring;
 630         struct igb_rx_entry *rxe;
 631         struct rte_mbuf *rxm;
 632         struct rte_mbuf *nmb;
 633         union e1000_adv_rx_desc rxd;
 634         uint64_t dma_addr;
 635         uint32_t staterr;
 636         uint32_t hlen_type_rss;
 637         uint16_t pkt_len;
 638         uint16_t rx_id;
 639         uint16_t nb_rx;
 640         uint16_t nb_hold;
 641         uint16_t pkt_flags;
 642
 643         nb_rx = 0;
 644         nb_hold = 0;
 645         rxq = rx_queue;
 646         rx_id = rxq->rx_tail;
 647         rx_ring = rxq->rx_ring;
 648         sw_ring = rxq->sw_ring;
 649         while (nb_rx < nb_pkts) {
 650                 /*
 651                  * The order of operations here is important as the DD status
 652                  * bit must not be read after any other descriptor fields.
 653                  * rx_ring and rxdp are pointing to volatile data so the order
 654                  * of accesses cannot be reordered by the compiler. If they were
 655                  * not volatile, they could be reordered which could lead to
 656                  * using invalid descriptor fields when read from rxd.
 657                  */
 658                 rxdp = &rx_ring[rx_id];
 659                 staterr = rxdp->wb.upper.status_error;
 660                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 661                         break;
 662                 rxd = *rxdp;
 663
 664                 /*
 665                  * End of packet.
 666                  *
 667                  * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
 668                  * likely to be invalid and to be dropped by the various
 669                  * validation checks performed by the network stack.
 670                  *
 671                  * Allocate a new mbuf to replenish the RX ring descriptor.
 672                  * If the allocation fails:
 673                  *    - arrange for that RX descriptor to be the first one
 674                  *      being parsed the next time the receive function is
 675                  *      invoked [on the same queue].
 676                  *
 677                  *    - Stop parsing the RX ring and return immediately.
 678                  *
 679                  * This policy do not drop the packet received in the RX
 680                  * descriptor for which the allocation of a new mbuf failed.
 681                  * Thus, it allows that packet to be later retrieved if
 682                  * mbuf have been freed in the mean time.
 683                  * As a side effect, holding RX descriptors instead of
 684                  * systematically giving them back to the NIC may lead to
 685                  * RX ring exhaustion situations.
 686                  * However, the NIC can gracefully prevent such situations
 687                  * to happen by sending specific "back-pressure" flow control
 688                  * frames to its peer(s).
 689                  */
 690                 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
 691                            "staterr=0x%x pkt_len=%u\n",
 692                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 693                            (unsigned) rx_id, (unsigned) staterr,
 694                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 695
 696                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 697                 if (nmb == NULL) {
 698                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 699                                    "queue_id=%u\n", (unsigned) rxq->port_id,
 700                                    (unsigned) rxq->queue_id);
 701                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 702                         break;
 703                 }
 704
 705                 nb_hold++;
 706                 rxe = &sw_ring[rx_id];
 707                 rx_id++;
 708                 if (rx_id == rxq->nb_rx_desc)
 709                         rx_id = 0;
 710
 711                 /* Prefetch next mbuf while processing current one. */
 712                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 713
 714                 /*
 715                  * When next RX descriptor is on a cache-line boundary,
 716                  * prefetch the next 4 RX descriptors and the next 8 pointers
 717                  * to mbufs.
 718                  */
 719                 if ((rx_id & 0x3) == 0) {
 720                         rte_igb_prefetch(&rx_ring[rx_id]);
 721                         rte_igb_prefetch(&sw_ring[rx_id]);
 722                 }
 723
 724                 rxm = rxe->mbuf;
 725                 rxe->mbuf = nmb;
 726                 dma_addr =
 727                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 728                 rxdp->read.hdr_addr = dma_addr;
 729                 rxdp->read.pkt_addr = dma_addr;
 730
 731                 /*
 732                  * Initialize the returned mbuf.
 733                  * 1) setup generic mbuf fields:
 734                  *    - number of segments,
 735                  *    - next segment,
 736                  *    - packet length,
 737                  *    - RX port identifier.
 738                  * 2) integrate hardware offload data, if any:
 739                  *    - RSS flag & hash,
 740                  *    - IP checksum flag,
 741                  *    - VLAN TCI, if any,
 742                  *    - error flags.
 743                  */
 744                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
 745                                       rxq->crc_len);
 746                 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
 747                 rte_packet_prefetch(rxm->pkt.data);
 748                 rxm->pkt.nb_segs = 1;
 749                 rxm->pkt.next = NULL;
 750                 rxm->pkt.pkt_len = pkt_len;
 751                 rxm->pkt.data_len = pkt_len;
 752                 rxm->pkt.in_port = rxq->port_id;
 753
 754                 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
 755                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
 756                 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
 757                 rxm->pkt.vlan_macip.f.vlan_tci =
 758                         rte_le_to_cpu_16(rxd.wb.upper.vlan);
 759
 760                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
 761                 pkt_flags = (uint16_t)(pkt_flags |
 762                                 rx_desc_status_to_pkt_flags(staterr));
 763                 pkt_flags = (uint16_t)(pkt_flags |
 764                                 rx_desc_error_to_pkt_flags(staterr));
 765                 rxm->ol_flags = pkt_flags;
 766
 767                 /*
 768                  * Store the mbuf address into the next entry of the array
 769                  * of returned packets.
 770                  */
 771                 rx_pkts[nb_rx++] = rxm;
 772         }
 773         rxq->rx_tail = rx_id;
 774
 775         /*
 776          * If the number of free RX descriptors is greater than the RX free
 777          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 778          * register.
 779          * Update the RDT with the value of the last processed RX descriptor
 780          * minus 1, to guarantee that the RDT register is never equal to the
 781          * RDH register, which creates a "full" ring situtation from the
 782          * hardware point of view...
 783          */
 784         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
 785         if (nb_hold > rxq->rx_free_thresh) {
 786                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 787                            "nb_hold=%u nb_rx=%u\n",
 788                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 789                            (unsigned) rx_id, (unsigned) nb_hold,
 790                            (unsigned) nb_rx);
 791                 rx_id = (uint16_t) ((rx_id == 0) ?
 792                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
 793                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
 794                 nb_hold = 0;
 795         }
 796         rxq->nb_rx_hold = nb_hold;
 797         return (nb_rx);
 798 }
 799
 800 uint16_t
 801 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 802                          uint16_t nb_pkts)
 803 {
 804         struct igb_rx_queue *rxq;
 805         volatile union e1000_adv_rx_desc *rx_ring;
 806         volatile union e1000_adv_rx_desc *rxdp;
 807         struct igb_rx_entry *sw_ring;
 808         struct igb_rx_entry *rxe;
 809         struct rte_mbuf *first_seg;
 810         struct rte_mbuf *last_seg;
 811         struct rte_mbuf *rxm;
 812         struct rte_mbuf *nmb;
 813         union e1000_adv_rx_desc rxd;
 814         uint64_t dma; /* Physical address of mbuf data buffer */
 815         uint32_t staterr;
 816         uint32_t hlen_type_rss;
 817         uint16_t rx_id;
 818         uint16_t nb_rx;
 819         uint16_t nb_hold;
 820         uint16_t data_len;
 821         uint16_t pkt_flags;
 822
 823         nb_rx = 0;
 824         nb_hold = 0;
 825         rxq = rx_queue;
 826         rx_id = rxq->rx_tail;
 827         rx_ring = rxq->rx_ring;
 828         sw_ring = rxq->sw_ring;
 829
 830         /*
 831          * Retrieve RX context of current packet, if any.
 832          */
 833         first_seg = rxq->pkt_first_seg;
 834         last_seg = rxq->pkt_last_seg;
 835
 836         while (nb_rx < nb_pkts) {
 837         next_desc:
 838                 /*
 839                  * The order of operations here is important as the DD status
 840                  * bit must not be read after any other descriptor fields.
 841                  * rx_ring and rxdp are pointing to volatile data so the order
 842                  * of accesses cannot be reordered by the compiler. If they were
 843                  * not volatile, they could be reordered which could lead to
 844                  * using invalid descriptor fields when read from rxd.
 845                  */
 846                 rxdp = &rx_ring[rx_id];
 847                 staterr = rxdp->wb.upper.status_error;
 848                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 849                         break;
 850                 rxd = *rxdp;
 851
 852                 /*
 853                  * Descriptor done.
 854                  *
 855                  * Allocate a new mbuf to replenish the RX ring descriptor.
 856                  * If the allocation fails:
 857                  *    - arrange for that RX descriptor to be the first one
 858                  *      being parsed the next time the receive function is
 859                  *      invoked [on the same queue].
 860                  *
 861                  *    - Stop parsing the RX ring and return immediately.
 862                  *
 863                  * This policy does not drop the packet received in the RX
 864                  * descriptor for which the allocation of a new mbuf failed.
 865                  * Thus, it allows that packet to be later retrieved if
 866                  * mbuf have been freed in the mean time.
 867                  * As a side effect, holding RX descriptors instead of
 868                  * systematically giving them back to the NIC may lead to
 869                  * RX ring exhaustion situations.
 870                  * However, the NIC can gracefully prevent such situations
 871                  * to happen by sending specific "back-pressure" flow control
 872                  * frames to its peer(s).
 873                  */
 874                 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
 875                            "staterr=0x%x data_len=%u\n",
 876                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 877                            (unsigned) rx_id, (unsigned) staterr,
 878                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 879
 880                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 881                 if (nmb == NULL) {
 882                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 883                                    "queue_id=%u\n", (unsigned) rxq->port_id,
 884                                    (unsigned) rxq->queue_id);
 885                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 886                         break;
 887                 }
 888
 889                 nb_hold++;
 890                 rxe = &sw_ring[rx_id];
 891                 rx_id++;
 892                 if (rx_id == rxq->nb_rx_desc)
 893                         rx_id = 0;
 894
 895                 /* Prefetch next mbuf while processing current one. */
 896                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 897
 898                 /*
 899                  * When next RX descriptor is on a cache-line boundary,
 900                  * prefetch the next 4 RX descriptors and the next 8 pointers
 901                  * to mbufs.
 902                  */
 903                 if ((rx_id & 0x3) == 0) {
 904                         rte_igb_prefetch(&rx_ring[rx_id]);
 905                         rte_igb_prefetch(&sw_ring[rx_id]);
 906                 }
 907
 908                 /*
 909                  * Update RX descriptor with the physical address of the new
 910                  * data buffer of the new allocated mbuf.
 911                  */
 912                 rxm = rxe->mbuf;
 913                 rxe->mbuf = nmb;
 914                 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 915                 rxdp->read.pkt_addr = dma;
 916                 rxdp->read.hdr_addr = dma;
 917
 918                 /*
 919                  * Set data length & data buffer address of mbuf.
 920                  */
 921                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
 922                 rxm->pkt.data_len = data_len;
 923                 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
 924
 925                 /*
 926                  * If this is the first buffer of the received packet,
 927                  * set the pointer to the first mbuf of the packet and
 928                  * initialize its context.
 929                  * Otherwise, update the total length and the number of segments
 930                  * of the current scattered packet, and update the pointer to
 931                  * the last mbuf of the current packet.
 932                  */
 933                 if (first_seg == NULL) {
 934                         first_seg = rxm;
 935                         first_seg->pkt.pkt_len = data_len;
 936                         first_seg->pkt.nb_segs = 1;
 937                 } else {
 938                         first_seg->pkt.pkt_len += data_len;
 939                         first_seg->pkt.nb_segs++;
 940                         last_seg->pkt.next = rxm;
 941                 }
 942
 943                 /*
 944                  * If this is not the last buffer of the received packet,
 945                  * update the pointer to the last mbuf of the current scattered
 946                  * packet and continue to parse the RX ring.
 947                  */
 948                 if (! (staterr & E1000_RXD_STAT_EOP)) {
 949                         last_seg = rxm;
 950                         goto next_desc;
 951                 }
 952
 953                 /*
 954                  * This is the last buffer of the received packet.
 955                  * If the CRC is not stripped by the hardware:
 956                  *   - Subtract the CRC length from the total packet length.
 957                  *   - If the last buffer only contains the whole CRC or a part
 958                  *     of it, free the mbuf associated to the last buffer.
 959                  *     If part of the CRC is also contained in the previous
 960                  *     mbuf, subtract the length of that CRC part from the
 961                  *     data length of the previous mbuf.
 962                  */
 963                 rxm->pkt.next = NULL;
 964                 if (unlikely(rxq->crc_len > 0)) {
 965                         first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
 966                         if (data_len <= ETHER_CRC_LEN) {
 967                                 rte_pktmbuf_free_seg(rxm);
 968                                 first_seg->pkt.nb_segs--;
 969                                 last_seg->pkt.data_len = (uint16_t)
 970                                         (last_seg->pkt.data_len -
 971                                          (ETHER_CRC_LEN - data_len));
 972                                 last_seg->pkt.next = NULL;
 973                         } else
 974                                 rxm->pkt.data_len =
 975                                         (uint16_t) (data_len - ETHER_CRC_LEN);
 976                 }
 977
 978                 /*
 979                  * Initialize the first mbuf of the returned packet:
 980                  *    - RX port identifier,
 981                  *    - hardware offload data, if any:
 982                  *      - RSS flag & hash,
 983                  *      - IP checksum flag,
 984                  *      - VLAN TCI, if any,
 985                  *      - error flags.
 986                  */
 987                 first_seg->pkt.in_port = rxq->port_id;
 988                 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
 989
 990                 /*
 991                  * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
 992                  * set in the pkt_flags field.
 993                  */
 994                 first_seg->pkt.vlan_macip.f.vlan_tci =
 995                         rte_le_to_cpu_16(rxd.wb.upper.vlan);
 996                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
 997                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
 998                 pkt_flags = (uint16_t)(pkt_flags |
 999                                 rx_desc_status_to_pkt_flags(staterr));
1000                 pkt_flags = (uint16_t)(pkt_flags |
1001                                 rx_desc_error_to_pkt_flags(staterr));
1002                 first_seg->ol_flags = pkt_flags;
1003
1004                 /* Prefetch data of first segment, if configured to do so. */
1005                 rte_packet_prefetch(first_seg->pkt.data);
1006
1007                 /*
1008                  * Store the mbuf address into the next entry of the array
1009                  * of returned packets.
1010                  */
1011                 rx_pkts[nb_rx++] = first_seg;
1012
1013                 /*
1014                  * Setup receipt context for a new packet.
1015                  */
1016                 first_seg = NULL;
1017         }
1018
1019         /*
1020          * Record index of the next RX descriptor to probe.
1021          */
1022         rxq->rx_tail = rx_id;
1023
1024         /*
1025          * Save receive context.
1026          */
1027         rxq->pkt_first_seg = first_seg;
1028         rxq->pkt_last_seg = last_seg;
1029
1030         /*
1031          * If the number of free RX descriptors is greater than the RX free
1032          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1033          * register.
1034          * Update the RDT with the value of the last processed RX descriptor
1035          * minus 1, to guarantee that the RDT register is never equal to the
1036          * RDH register, which creates a "full" ring situtation from the
1037          * hardware point of view...
1038          */
1039         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1040         if (nb_hold > rxq->rx_free_thresh) {
1041                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1042                            "nb_hold=%u nb_rx=%u\n",
1043                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1044                            (unsigned) rx_id, (unsigned) nb_hold,
1045                            (unsigned) nb_rx);
1046                 rx_id = (uint16_t) ((rx_id == 0) ?
1047                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1048                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1049                 nb_hold = 0;
1050         }
1051         rxq->nb_rx_hold = nb_hold;
1052         return (nb_rx);
1053 }
1054
1055 /*
1056  * Rings setup and release.
1057  *
1058  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1059  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
1060  * This will also optimize cache line size effect.
1061  * H/W supports up to cache line size 128.
1062  */
1063 #define IGB_ALIGN 128
1064
1065 /*
1066  * Maximum number of Ring Descriptors.
1067  *
1068  * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1069  * desscriptors should meet the following condition:
1070  *      (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1071  */
1072 #define IGB_MIN_RING_DESC 32
1073 #define IGB_MAX_RING_DESC 4096
1074
1075 static const struct rte_memzone *
1076 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1077                       uint16_t queue_id, uint32_t ring_size, int socket_id)
1078 {
1079         char z_name[RTE_MEMZONE_NAMESIZE];
1080         const struct rte_memzone *mz;
1081
1082         rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1083                         dev->driver->pci_drv.name, ring_name,
1084                                 dev->data->port_id, queue_id);
1085         mz = rte_memzone_lookup(z_name);
1086         if (mz)
1087                 return mz;
1088
1089         return rte_memzone_reserve_aligned(z_name, ring_size,
1090                         socket_id, 0, IGB_ALIGN);
1091 }
1092
1093 static void
1094 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1095 {
1096         unsigned i;
1097
1098         if (txq->sw_ring != NULL) {
1099                 for (i = 0; i < txq->nb_tx_desc; i++) {
1100                         if (txq->sw_ring[i].mbuf != NULL) {
1101                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1102                                 txq->sw_ring[i].mbuf = NULL;
1103                         }
1104                 }
1105         }
1106 }
1107
1108 static void
1109 igb_tx_queue_release(struct igb_tx_queue *txq)
1110 {
1111         if (txq != NULL) {
1112                 igb_tx_queue_release_mbufs(txq);
1113                 rte_free(txq->sw_ring);
1114                 rte_free(txq);
1115         }
1116 }
1117
1118 void
1119 eth_igb_tx_queue_release(void *txq)
1120 {
1121         igb_tx_queue_release(txq);
1122 }
1123
1124 static void
1125 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1126 {
1127         txq->tx_head = 0;
1128         txq->tx_tail = 0;
1129         txq->ctx_curr = 0;
1130         memset((void*)&txq->ctx_cache, 0,
1131                 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1132 }
1133
1134 static void
1135 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1136 {
1137         static const union e1000_adv_tx_desc zeroed_desc;
1138         struct igb_tx_entry *txe = txq->sw_ring;
1139         uint16_t i, prev;
1140         struct e1000_hw *hw;
1141
1142         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1143         /* Zero out HW ring memory */
1144         for (i = 0; i < txq->nb_tx_desc; i++) {
1145                 txq->tx_ring[i] = zeroed_desc;
1146         }
1147
1148         /* Initialize ring entries */
1149         prev = (uint16_t)(txq->nb_tx_desc - 1);
1150         for (i = 0; i < txq->nb_tx_desc; i++) {
1151                 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1152
1153                 txd->wb.status = E1000_TXD_STAT_DD;
1154                 txe[i].mbuf = NULL;
1155                 txe[i].last_id = i;
1156                 txe[prev].next_id = i;
1157                 prev = i;
1158         }
1159
1160         txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1161         /* 82575 specific, each tx queue will use 2 hw contexts */
1162         if (hw->mac.type == e1000_82575)
1163                 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1164
1165         igb_reset_tx_queue_stat(txq);
1166 }
1167
1168 int
1169 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1170                          uint16_t queue_idx,
1171                          uint16_t nb_desc,
1172                          unsigned int socket_id,
1173                          const struct rte_eth_txconf *tx_conf)
1174 {
1175         const struct rte_memzone *tz;
1176         struct igb_tx_queue *txq;
1177         struct e1000_hw     *hw;
1178         uint32_t size;
1179
1180         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181
1182         /*
1183          * Validate number of transmit descriptors.
1184          * It must not exceed hardware maximum, and must be multiple
1185          * of IGB_ALIGN.
1186          */
1187         if (((nb_desc * sizeof(union e1000_adv_tx_desc)) % IGB_ALIGN) != 0 ||
1188             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1189                 return -EINVAL;
1190         }
1191
1192         /*
1193          * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1194          * driver.
1195          */
1196         if (tx_conf->tx_free_thresh != 0)
1197                 RTE_LOG(WARNING, PMD,
1198                         "The tx_free_thresh parameter is not "
1199                         "used for the 1G driver.\n");
1200         if (tx_conf->tx_rs_thresh != 0)
1201                 RTE_LOG(WARNING, PMD,
1202                         "The tx_rs_thresh parameter is not "
1203                         "used for the 1G driver.\n");
1204         if (tx_conf->tx_thresh.wthresh == 0)
1205                 RTE_LOG(WARNING, PMD,
1206                         "To improve 1G driver performance, consider setting "
1207                         "the TX WTHRESH value to 4, 8, or 16.\n");
1208
1209         /* Free memory prior to re-allocation if needed */
1210         if (dev->data->tx_queues[queue_idx] != NULL)
1211                 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1212
1213         /* First allocate the tx queue data structure */
1214         txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1215                                                         CACHE_LINE_SIZE);
1216         if (txq == NULL)
1217                 return (-ENOMEM);
1218
1219         /*
1220          * Allocate TX ring hardware descriptors. A memzone large enough to
1221          * handle the maximum ring size is allocated in order to allow for
1222          * resizing in later calls to the queue setup function.
1223          */
1224         size = sizeof(union e1000_adv_tx_desc) * IGB_MAX_RING_DESC;
1225         tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1226                                         size, socket_id);
1227         if (tz == NULL) {
1228                 igb_tx_queue_release(txq);
1229                 return (-ENOMEM);
1230         }
1231
1232         txq->nb_tx_desc = nb_desc;
1233         txq->pthresh = tx_conf->tx_thresh.pthresh;
1234         txq->hthresh = tx_conf->tx_thresh.hthresh;
1235         txq->wthresh = tx_conf->tx_thresh.wthresh;
1236         txq->queue_id = queue_idx;
1237         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1238                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1239         txq->port_id = dev->data->port_id;
1240
1241         txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1242         txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1243         txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1244
1245         /* Allocate software ring */
1246         txq->sw_ring = rte_zmalloc("txq->sw_ring",
1247                                    sizeof(struct igb_tx_entry) * nb_desc,
1248                                    CACHE_LINE_SIZE);
1249         if (txq->sw_ring == NULL) {
1250                 igb_tx_queue_release(txq);
1251                 return (-ENOMEM);
1252         }
1253         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1254                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1255
1256         igb_reset_tx_queue(txq, dev);
1257         dev->tx_pkt_burst = eth_igb_xmit_pkts;
1258         dev->data->tx_queues[queue_idx] = txq;
1259
1260         return (0);
1261 }
1262
1263 static void
1264 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1265 {
1266         unsigned i;
1267
1268         if (rxq->sw_ring != NULL) {
1269                 for (i = 0; i < rxq->nb_rx_desc; i++) {
1270                         if (rxq->sw_ring[i].mbuf != NULL) {
1271                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1272                                 rxq->sw_ring[i].mbuf = NULL;
1273                         }
1274                 }
1275         }
1276 }
1277
1278 static void
1279 igb_rx_queue_release(struct igb_rx_queue *rxq)
1280 {
1281         if (rxq != NULL) {
1282                 igb_rx_queue_release_mbufs(rxq);
1283                 rte_free(rxq->sw_ring);
1284                 rte_free(rxq);
1285         }
1286 }
1287
1288 void
1289 eth_igb_rx_queue_release(void *rxq)
1290 {
1291         igb_rx_queue_release(rxq);
1292 }
1293
1294 static void
1295 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1296 {
1297         static const union e1000_adv_rx_desc zeroed_desc;
1298         unsigned i;
1299
1300         /* Zero out HW ring memory */
1301         for (i = 0; i < rxq->nb_rx_desc; i++) {
1302                 rxq->rx_ring[i] = zeroed_desc;
1303         }
1304
1305         rxq->rx_tail = 0;
1306         rxq->pkt_first_seg = NULL;
1307         rxq->pkt_last_seg = NULL;
1308 }
1309
1310 int
1311 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1312                          uint16_t queue_idx,
1313                          uint16_t nb_desc,
1314                          unsigned int socket_id,
1315                          const struct rte_eth_rxconf *rx_conf,
1316                          struct rte_mempool *mp)
1317 {
1318         const struct rte_memzone *rz;
1319         struct igb_rx_queue *rxq;
1320         struct e1000_hw     *hw;
1321         unsigned int size;
1322
1323         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324
1325         /*
1326          * Validate number of receive descriptors.
1327          * It must not exceed hardware maximum, and must be multiple
1328          * of IGB_ALIGN.
1329          */
1330         if (((nb_desc * sizeof(union e1000_adv_rx_desc)) % IGB_ALIGN) != 0 ||
1331             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1332                 return (-EINVAL);
1333         }
1334
1335         /* Free memory prior to re-allocation if needed */
1336         if (dev->data->rx_queues[queue_idx] != NULL) {
1337                 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1338                 dev->data->rx_queues[queue_idx] = NULL;
1339         }
1340
1341         /* First allocate the RX queue data structure. */
1342         rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1343                           CACHE_LINE_SIZE);
1344         if (rxq == NULL)
1345                 return (-ENOMEM);
1346         rxq->mb_pool = mp;
1347         rxq->nb_rx_desc = nb_desc;
1348         rxq->pthresh = rx_conf->rx_thresh.pthresh;
1349         rxq->hthresh = rx_conf->rx_thresh.hthresh;
1350         rxq->wthresh = rx_conf->rx_thresh.wthresh;
1351         rxq->drop_en = rx_conf->rx_drop_en;
1352         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1353         rxq->queue_id = queue_idx;
1354         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1355                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1356         rxq->port_id = dev->data->port_id;
1357         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1358                                   ETHER_CRC_LEN);
1359
1360         /*
1361          *  Allocate RX ring hardware descriptors. A memzone large enough to
1362          *  handle the maximum ring size is allocated in order to allow for
1363          *  resizing in later calls to the queue setup function.
1364          */
1365         size = sizeof(union e1000_adv_rx_desc) * IGB_MAX_RING_DESC;
1366         rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx, size, socket_id);
1367         if (rz == NULL) {
1368                 igb_rx_queue_release(rxq);
1369                 return (-ENOMEM);
1370         }
1371         rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1372         rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1373         rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1374         rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1375
1376         /* Allocate software ring. */
1377         rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1378                                    sizeof(struct igb_rx_entry) * nb_desc,
1379                                    CACHE_LINE_SIZE);
1380         if (rxq->sw_ring == NULL) {
1381                 igb_rx_queue_release(rxq);
1382                 return (-ENOMEM);
1383         }
1384         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1385                      rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1386
1387         dev->data->rx_queues[queue_idx] = rxq;
1388         igb_reset_rx_queue(rxq);
1389
1390         return 0;
1391 }
1392
1393 uint32_t
1394 eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1395 {
1396 #define IGB_RXQ_SCAN_INTERVAL 4
1397         volatile union e1000_adv_rx_desc *rxdp;
1398         struct igb_rx_queue *rxq;
1399         uint32_t desc = 0;
1400
1401         if (rx_queue_id >= dev->data->nb_rx_queues) {
1402                 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
1403                 return 0;
1404         }
1405
1406         rxq = dev->data->rx_queues[rx_queue_id];
1407         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1408
1409         while ((desc < rxq->nb_rx_desc) &&
1410                 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1411                 desc += IGB_RXQ_SCAN_INTERVAL;
1412                 rxdp += IGB_RXQ_SCAN_INTERVAL;
1413                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1414                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1415                                 desc - rxq->nb_rx_desc]);
1416         }
1417
1418         return 0;
1419 }
1420
1421 int
1422 eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
1423 {
1424         volatile union e1000_adv_rx_desc *rxdp;
1425         struct igb_rx_queue *rxq = rx_queue;
1426         uint32_t desc;
1427
1428         if (unlikely(offset >= rxq->nb_rx_desc))
1429                 return 0;
1430         desc = rxq->rx_tail + offset;
1431         if (desc >= rxq->nb_rx_desc)
1432                 desc -= rxq->nb_rx_desc;
1433
1434         rxdp = &rxq->rx_ring[desc];
1435         return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
1436 }
1437
1438 void
1439 igb_dev_clear_queues(struct rte_eth_dev *dev)
1440 {
1441         uint16_t i;
1442         struct igb_tx_queue *txq;
1443         struct igb_rx_queue *rxq;
1444
1445         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1446                 txq = dev->data->tx_queues[i];
1447                 if (txq != NULL) {
1448                         igb_tx_queue_release_mbufs(txq);
1449                         igb_reset_tx_queue(txq, dev);
1450                 }
1451         }
1452
1453         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1454                 rxq = dev->data->rx_queues[i];
1455                 if (rxq != NULL) {
1456                         igb_rx_queue_release_mbufs(rxq);
1457                         igb_reset_rx_queue(rxq);
1458                 }
1459         }
1460 }
1461
1462 /**
1463  * Receive Side Scaling (RSS).
1464  * See section 7.1.1.7 in the following document:
1465  *     "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1466  *
1467  * Principles:
1468  * The source and destination IP addresses of the IP header and the source and
1469  * destination ports of TCP/UDP headers, if any, of received packets are hashed
1470  * against a configurable random key to compute a 32-bit RSS hash result.
1471  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1472  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
1473  * RSS output index which is used as the RX queue index where to store the
1474  * received packets.
1475  * The following output is supplied in the RX write-back descriptor:
1476  *     - 32-bit result of the Microsoft RSS hash function,
1477  *     - 4-bit RSS type field.
1478  */
1479
1480 /*
1481  * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1482  * Used as the default key.
1483  */
1484 static uint8_t rss_intel_key[40] = {
1485         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1486         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1487         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1488         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1489         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1490 };
1491
1492 static void
1493 igb_rss_disable(struct rte_eth_dev *dev)
1494 {
1495         struct e1000_hw *hw;
1496         uint32_t mrqc;
1497
1498         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1500         mrqc &= ~E1000_MRQC_ENABLE_MASK;
1501         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1502 }
1503
1504 static void
1505 igb_rss_configure(struct rte_eth_dev *dev)
1506 {
1507         struct e1000_hw *hw;
1508         uint8_t *hash_key;
1509         uint32_t rss_key;
1510         uint32_t mrqc;
1511         uint32_t shift;
1512         uint16_t rss_hf;
1513         uint16_t i;
1514
1515         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1516
1517         rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
1518         if (rss_hf == 0) /* Disable RSS. */ {
1519                 igb_rss_disable(dev);
1520                 return;
1521         }
1522         hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
1523         if (hash_key == NULL)
1524                 hash_key = rss_intel_key; /* Default hash key. */
1525
1526         /* Fill in RSS hash key. */
1527         for (i = 0; i < 10; i++) {
1528                 rss_key  = hash_key[(i * 4)];
1529                 rss_key |= hash_key[(i * 4) + 1] << 8;
1530                 rss_key |= hash_key[(i * 4) + 2] << 16;
1531                 rss_key |= hash_key[(i * 4) + 3] << 24;
1532                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1533         }
1534
1535         /* Fill in redirection table. */
1536         shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1537         for (i = 0; i < 128; i++) {
1538                 union e1000_reta {
1539                         uint32_t dword;
1540                         uint8_t  bytes[4];
1541                 } reta;
1542                 uint8_t q_idx;
1543
1544                 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1545                                    i % dev->data->nb_rx_queues : 0);
1546                 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1547                 if ((i & 3) == 3)
1548                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1549         }
1550
1551         /* Set configured hashing functions in MRQC register. */
1552         mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1553         if (rss_hf & ETH_RSS_IPV4)
1554                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1555         if (rss_hf & ETH_RSS_IPV4_TCP)
1556                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1557         if (rss_hf & ETH_RSS_IPV6)
1558                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1559         if (rss_hf & ETH_RSS_IPV6_EX)
1560                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1561         if (rss_hf & ETH_RSS_IPV6_TCP)
1562                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1563         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1564                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1565         if (rss_hf & ETH_RSS_IPV4_UDP)
1566                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1567         if (rss_hf & ETH_RSS_IPV6_UDP)
1568                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1569         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1570                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1571         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1572 }
1573
1574 /*
1575  * Check if the mac type support VMDq or not.
1576  * Return 1 if it supports, otherwise, return 0.
1577  */
1578 static int
1579 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
1580 {
1581         const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582
1583         switch (hw->mac.type) {
1584         case e1000_82576:
1585         case e1000_82580:
1586         case e1000_i350:
1587                 return 1;
1588         case e1000_82540:
1589         case e1000_82541:
1590         case e1000_82542:
1591         case e1000_82543:
1592         case e1000_82544:
1593         case e1000_82545:
1594         case e1000_82546:
1595         case e1000_82547:
1596         case e1000_82571:
1597         case e1000_82572:
1598         case e1000_82573:
1599         case e1000_82574:
1600         case e1000_82583:
1601         case e1000_i210:
1602         case e1000_i211:
1603         default:
1604                 PMD_INIT_LOG(ERR, "Cannot support VMDq feature\n");
1605                 return 0;
1606         }
1607 }
1608
1609 static int
1610 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
1611 {
1612         struct rte_eth_vmdq_rx_conf *cfg;
1613         struct e1000_hw *hw;
1614         uint32_t mrqc, vt_ctl, vmolr, rctl;
1615         int i;
1616
1617         PMD_INIT_LOG(DEBUG, ">>");
1618         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1620
1621         /* Check if mac type can support VMDq, return value of 0 means NOT support */
1622         if (igb_is_vmdq_supported(dev) == 0)
1623                 return -1;
1624
1625         igb_rss_disable(dev);
1626
1627         /* RCTL: eanble VLAN filter */
1628         rctl = E1000_READ_REG(hw, E1000_RCTL);
1629         rctl |= E1000_RCTL_VFE;
1630         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1631
1632         /* MRQC: enable vmdq */
1633         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1634         mrqc |= E1000_MRQC_ENABLE_VMDQ;
1635         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1636
1637         /* VTCTL:  pool selection according to VLAN tag */
1638         vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1639         if (cfg->enable_default_pool)
1640                 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1641         vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
1642         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1643
1644         /*
1645          * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
1646          * Both 82576 and 82580 support it
1647          */
1648         if (hw->mac.type != e1000_i350) {
1649                 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1650                         vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1651                         vmolr |= E1000_VMOLR_STRVLAN;
1652                         E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1653                 }
1654         }
1655
1656         /* VFTA - enable all vlan filters */
1657         for (i = 0; i < IGB_VFTA_SIZE; i++)
1658                 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
1659
1660         /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
1661         if (hw->mac.type != e1000_82580)
1662                 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
1663
1664         /*
1665          * RAH/RAL - allow pools to read specific mac addresses
1666          * In this case, all pools should be able to read from mac addr 0
1667          */
1668         E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
1669         E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
1670
1671         /* VLVF: set up filters for vlan tags as configured */
1672         for (i = 0; i < cfg->nb_pool_maps; i++) {
1673                 /* set vlan id in VF register and set the valid bit */
1674                 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
1675                         (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
1676                         ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
1677                         E1000_VLVF_POOLSEL_MASK)));
1678         }
1679
1680         E1000_WRITE_FLUSH(hw);
1681
1682         return 0;
1683 }
1684
1685
1686 /*********************************************************************
1687  *
1688  *  Enable receive unit.
1689  *
1690  **********************************************************************/
1691
1692 static int
1693 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1694 {
1695         struct igb_rx_entry *rxe = rxq->sw_ring;
1696         uint64_t dma_addr;
1697         unsigned i;
1698
1699         /* Initialize software ring entries. */
1700         for (i = 0; i < rxq->nb_rx_desc; i++) {
1701                 volatile union e1000_adv_rx_desc *rxd;
1702                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1703
1704                 if (mbuf == NULL) {
1705                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1706                                 "queue_id=%hu\n", rxq->queue_id);
1707                         igb_rx_queue_release(rxq);
1708                         return (-ENOMEM);
1709                 }
1710                 dma_addr =
1711                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
1712                 rxd = &rxq->rx_ring[i];
1713                 rxd->read.hdr_addr = dma_addr;
1714                 rxd->read.pkt_addr = dma_addr;
1715                 rxe[i].mbuf = mbuf;
1716         }
1717
1718         return 0;
1719 }
1720
1721 #define E1000_MRQC_DEF_Q_SHIFT               (3)
1722 static int
1723 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
1724 {
1725         struct e1000_hw *hw =
1726                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         uint32_t mrqc;
1728
1729         if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
1730                 /*
1731                 * SRIOV active scheme
1732                 * FIXME if support RSS together with VMDq & SRIOV
1733                 */
1734                 mrqc = E1000_MRQC_ENABLE_VMDQ;
1735                 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
1736                 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
1737                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1738         } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
1739                 /*
1740                 * SRIOV inactive scheme
1741                 */
1742                 if (dev->data->nb_rx_queues > 1)
1743                         switch (dev->data->dev_conf.rxmode.mq_mode) {
1744                         case ETH_MQ_RX_NONE:
1745                                 /* if mq_mode not assign, we use rss mode.*/
1746                         case ETH_MQ_RX_RSS:
1747                                 igb_rss_configure(dev);
1748                                 break;
1749                         case ETH_MQ_RX_VMDQ_ONLY:
1750                                 /*Configure general VMDQ only RX parameters*/
1751                                 igb_vmdq_rx_hw_configure(dev);
1752                                 break;
1753                         default:
1754                                 igb_rss_disable(dev);
1755                                 break;
1756                         }
1757                 else
1758                         igb_rss_disable(dev);
1759         }
1760
1761         return 0;
1762 }
1763
1764 int
1765 eth_igb_rx_init(struct rte_eth_dev *dev)
1766 {
1767         struct e1000_hw     *hw;
1768         struct igb_rx_queue *rxq;
1769         struct rte_pktmbuf_pool_private *mbp_priv;
1770         uint32_t rctl;
1771         uint32_t rxcsum;
1772         uint32_t srrctl;
1773         uint16_t buf_size;
1774         uint16_t rctl_bsize;
1775         uint16_t i;
1776         int ret;
1777
1778         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779         srrctl = 0;
1780
1781         /*
1782          * Make sure receives are disabled while setting
1783          * up the descriptor ring.
1784          */
1785         rctl = E1000_READ_REG(hw, E1000_RCTL);
1786         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1787
1788         /*
1789          * Configure support of jumbo frames, if any.
1790          */
1791         if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1792                 rctl |= E1000_RCTL_LPE;
1793
1794                 /*
1795                  * Set maximum packet length by default, and might be updated
1796                  * together with enabling/disabling dual VLAN.
1797                  */
1798                 E1000_WRITE_REG(hw, E1000_RLPML,
1799                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1800                                                 VLAN_TAG_SIZE);
1801         } else
1802                 rctl &= ~E1000_RCTL_LPE;
1803
1804         /* Configure and enable each RX queue. */
1805         rctl_bsize = 0;
1806         dev->rx_pkt_burst = eth_igb_recv_pkts;
1807         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1808                 uint64_t bus_addr;
1809                 uint32_t rxdctl;
1810
1811                 rxq = dev->data->rx_queues[i];
1812
1813                 /* Allocate buffers for descriptor rings and set up queue */
1814                 ret = igb_alloc_rx_queue_mbufs(rxq);
1815                 if (ret)
1816                         return ret;
1817
1818                 /*
1819                  * Reset crc_len in case it was changed after queue setup by a
1820                  *  call to configure
1821                  */
1822                 rxq->crc_len =
1823                         (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1824                                                         0 : ETHER_CRC_LEN);
1825
1826                 bus_addr = rxq->rx_ring_phys_addr;
1827                 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
1828                                 rxq->nb_rx_desc *
1829                                 sizeof(union e1000_adv_rx_desc));
1830                 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
1831                                 (uint32_t)(bus_addr >> 32));
1832                 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
1833
1834                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1835
1836                 /*
1837                  * Configure RX buffer size.
1838                  */
1839                 mbp_priv = (struct rte_pktmbuf_pool_private *)
1840                         ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
1841                 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
1842                                        RTE_PKTMBUF_HEADROOM);
1843                 if (buf_size >= 1024) {
1844                         /*
1845                          * Configure the BSIZEPACKET field of the SRRCTL
1846                          * register of the queue.
1847                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
1848                          * If this field is equal to 0b, then RCTL.BSIZE
1849                          * determines the RX packet buffer size.
1850                          */
1851                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
1852                                    E1000_SRRCTL_BSIZEPKT_MASK);
1853                         buf_size = (uint16_t) ((srrctl &
1854                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
1855                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
1856
1857                         /* It adds dual VLAN length for supporting dual VLAN */
1858                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
1859                                                 2 * VLAN_TAG_SIZE) > buf_size){
1860                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1861                                 dev->data->scattered_rx = 1;
1862                         }
1863                 } else {
1864                         /*
1865                          * Use BSIZE field of the device RCTL register.
1866                          */
1867                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
1868                                 rctl_bsize = buf_size;
1869                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1870                         dev->data->scattered_rx = 1;
1871                 }
1872
1873                 /* Set if packets are dropped when no descriptors available */
1874                 if (rxq->drop_en)
1875                         srrctl |= E1000_SRRCTL_DROP_EN;
1876
1877                 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
1878
1879                 /* Enable this RX queue. */
1880                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
1881                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1882                 rxdctl &= 0xFFF00000;
1883                 rxdctl |= (rxq->pthresh & 0x1F);
1884                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
1885                 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
1886                 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
1887         }
1888
1889         /*
1890          * Setup BSIZE field of RCTL register, if needed.
1891          * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
1892          * register, since the code above configures the SRRCTL register of
1893          * the RX queue in such a case.
1894          * All configurable sizes are:
1895          * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1896          *  8192: rctl |= (E1000_RCTL_SZ_8192  | E1000_RCTL_BSEX);
1897          *  4096: rctl |= (E1000_RCTL_SZ_4096  | E1000_RCTL_BSEX);
1898          *  2048: rctl |= E1000_RCTL_SZ_2048;
1899          *  1024: rctl |= E1000_RCTL_SZ_1024;
1900          *   512: rctl |= E1000_RCTL_SZ_512;
1901          *   256: rctl |= E1000_RCTL_SZ_256;
1902          */
1903         if (rctl_bsize > 0) {
1904                 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
1905                         rctl |= E1000_RCTL_SZ_512;
1906                 else /* 256 <= buf_size < 512 - use 256 */
1907                         rctl |= E1000_RCTL_SZ_256;
1908         }
1909
1910         /*
1911          * Configure RSS if device configured with multiple RX queues.
1912          */
1913         igb_dev_mq_rx_configure(dev);
1914
1915         /* Update the rctl since igb_dev_mq_rx_configure may change its value */
1916         rctl |= E1000_READ_REG(hw, E1000_RCTL);
1917
1918         /*
1919          * Setup the Checksum Register.
1920          * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1921          */
1922         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1923         rxcsum |= E1000_RXCSUM_PCSD;
1924
1925         /* Enable both L3/L4 rx checksum offload */
1926         if (dev->data->dev_conf.rxmode.hw_ip_checksum)
1927                 rxcsum |= (E1000_RXCSUM_IPOFL  | E1000_RXCSUM_TUOFL);
1928         else
1929                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
1930         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1931
1932         /* Setup the Receive Control Register. */
1933         if (dev->data->dev_conf.rxmode.hw_strip_crc) {
1934                 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1935
1936                 /* set STRCRC bit in all queues */
1937                 if (hw->mac.type == e1000_i350 ||
1938                     hw->mac.type == e1000_i210 ||
1939                     hw->mac.type == e1000_i211 ||
1940                     hw->mac.type == e1000_i354) {
1941                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1942                                 rxq = dev->data->rx_queues[i];
1943                                 uint32_t dvmolr = E1000_READ_REG(hw,
1944                                         E1000_DVMOLR(rxq->reg_idx));
1945                                 dvmolr |= E1000_DVMOLR_STRCRC;
1946                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
1947                         }
1948                 }
1949         } else {
1950                 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1951
1952                 /* clear STRCRC bit in all queues */
1953                 if (hw->mac.type == e1000_i350 ||
1954                     hw->mac.type == e1000_i210 ||
1955                     hw->mac.type == e1000_i211 ||
1956                     hw->mac.type == e1000_i354) {
1957                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1958                                 rxq = dev->data->rx_queues[i];
1959                                 uint32_t dvmolr = E1000_READ_REG(hw,
1960                                         E1000_DVMOLR(rxq->reg_idx));
1961                                 dvmolr &= ~E1000_DVMOLR_STRCRC;
1962                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
1963                         }
1964                 }
1965         }
1966
1967         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1968         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1969                 E1000_RCTL_RDMTS_HALF |
1970                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1971
1972         /* Make sure VLAN Filters are off. */
1973         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
1974                 rctl &= ~E1000_RCTL_VFE;
1975         /* Don't store bad packets. */
1976         rctl &= ~E1000_RCTL_SBP;
1977
1978         /* Enable Receives. */
1979         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1980
1981         /*
1982          * Setup the HW Rx Head and Tail Descriptor Pointers.
1983          * This needs to be done after enable.
1984          */
1985         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1986                 rxq = dev->data->rx_queues[i];
1987                 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
1988                 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
1989         }
1990
1991         return 0;
1992 }
1993
1994 /*********************************************************************
1995  *
1996  *  Enable transmit unit.
1997  *
1998  **********************************************************************/
1999 void
2000 eth_igb_tx_init(struct rte_eth_dev *dev)
2001 {
2002         struct e1000_hw     *hw;
2003         struct igb_tx_queue *txq;
2004         uint32_t tctl;
2005         uint32_t txdctl;
2006         uint16_t i;
2007
2008         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009
2010         /* Setup the Base and Length of the Tx Descriptor Rings. */
2011         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2012                 uint64_t bus_addr;
2013                 txq = dev->data->tx_queues[i];
2014                 bus_addr = txq->tx_ring_phys_addr;
2015
2016                 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2017                                 txq->nb_tx_desc *
2018                                 sizeof(union e1000_adv_tx_desc));
2019                 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2020                                 (uint32_t)(bus_addr >> 32));
2021                 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2022
2023                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2024                 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2025                 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2026
2027                 /* Setup Transmit threshold registers. */
2028                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2029                 txdctl |= txq->pthresh & 0x1F;
2030                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2031                 txdctl |= ((txq->wthresh & 0x1F) << 16);
2032                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2033                 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2034         }
2035
2036         /* Program the Transmit Control Register. */
2037         tctl = E1000_READ_REG(hw, E1000_TCTL);
2038         tctl &= ~E1000_TCTL_CT;
2039         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2040                  (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2041
2042         e1000_config_collision_dist(hw);
2043
2044         /* This write will effectively turn on the transmit unit. */
2045         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2046 }
2047
2048 /*********************************************************************
2049  *
2050  *  Enable VF receive unit.
2051  *
2052  **********************************************************************/
2053 int
2054 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2055 {
2056         struct e1000_hw     *hw;
2057         struct igb_rx_queue *rxq;
2058         struct rte_pktmbuf_pool_private *mbp_priv;
2059         uint32_t srrctl;
2060         uint16_t buf_size;
2061         uint16_t rctl_bsize;
2062         uint16_t i;
2063         int ret;
2064
2065         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066
2067         /* Configure and enable each RX queue. */
2068         rctl_bsize = 0;
2069         dev->rx_pkt_burst = eth_igb_recv_pkts;
2070         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2071                 uint64_t bus_addr;
2072                 uint32_t rxdctl;
2073
2074                 rxq = dev->data->rx_queues[i];
2075
2076                 /* Allocate buffers for descriptor rings and set up queue */
2077                 ret = igb_alloc_rx_queue_mbufs(rxq);
2078                 if (ret)
2079                         return ret;
2080
2081                 bus_addr = rxq->rx_ring_phys_addr;
2082                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2083                                 rxq->nb_rx_desc *
2084                                 sizeof(union e1000_adv_rx_desc));
2085                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2086                                 (uint32_t)(bus_addr >> 32));
2087                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2088
2089                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2090
2091                 /*
2092                  * Configure RX buffer size.
2093                  */
2094                 mbp_priv = (struct rte_pktmbuf_pool_private *)
2095                         ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
2096                 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
2097                                        RTE_PKTMBUF_HEADROOM);
2098                 if (buf_size >= 1024) {
2099                         /*
2100                          * Configure the BSIZEPACKET field of the SRRCTL
2101                          * register of the queue.
2102                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
2103                          * If this field is equal to 0b, then RCTL.BSIZE
2104                          * determines the RX packet buffer size.
2105                          */
2106                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2107                                    E1000_SRRCTL_BSIZEPKT_MASK);
2108                         buf_size = (uint16_t) ((srrctl &
2109                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
2110                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
2111
2112                         /* It adds dual VLAN length for supporting dual VLAN */
2113                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2114                                                 2 * VLAN_TAG_SIZE) > buf_size){
2115                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2116                                 dev->data->scattered_rx = 1;
2117                         }
2118                 } else {
2119                         /*
2120                          * Use BSIZE field of the device RCTL register.
2121                          */
2122                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2123                                 rctl_bsize = buf_size;
2124                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2125                         dev->data->scattered_rx = 1;
2126                 }
2127
2128                 /* Set if packets are dropped when no descriptors available */
2129                 if (rxq->drop_en)
2130                         srrctl |= E1000_SRRCTL_DROP_EN;
2131
2132                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2133
2134                 /* Enable this RX queue. */
2135                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2136                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2137                 rxdctl &= 0xFFF00000;
2138                 rxdctl |= (rxq->pthresh & 0x1F);
2139                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2140                 if (hw->mac.type == e1000_82576) {
2141                         /*
2142                          * Workaround of 82576 VF Erratum
2143                          * force set WTHRESH to 1
2144                          * to avoid Write-Back not triggered sometimes
2145                          */
2146                         rxdctl |= 0x10000;
2147                         PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !\n");
2148                 }
2149                 else
2150                         rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2151                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2152         }
2153
2154         /*
2155          * Setup the HW Rx Head and Tail Descriptor Pointers.
2156          * This needs to be done after enable.
2157          */
2158         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                 rxq = dev->data->rx_queues[i];
2160                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2161                 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2162         }
2163
2164         return 0;
2165 }
2166
2167 /*********************************************************************
2168  *
2169  *  Enable VF transmit unit.
2170  *
2171  **********************************************************************/
2172 void
2173 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2174 {
2175         struct e1000_hw     *hw;
2176         struct igb_tx_queue *txq;
2177         uint32_t txdctl;
2178         uint16_t i;
2179
2180         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2181
2182         /* Setup the Base and Length of the Tx Descriptor Rings. */
2183         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2184                 uint64_t bus_addr;
2185
2186                 txq = dev->data->tx_queues[i];
2187                 bus_addr = txq->tx_ring_phys_addr;
2188                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2189                                 txq->nb_tx_desc *
2190                                 sizeof(union e1000_adv_tx_desc));
2191                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2192                                 (uint32_t)(bus_addr >> 32));
2193                 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2194
2195                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2196                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2197                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2198
2199                 /* Setup Transmit threshold registers. */
2200                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2201                 txdctl |= txq->pthresh & 0x1F;
2202                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2203                 if (hw->mac.type == e1000_82576) {
2204                         /*
2205                          * Workaround of 82576 VF Erratum
2206                          * force set WTHRESH to 1
2207                          * to avoid Write-Back not triggered sometimes
2208                          */
2209                         txdctl |= 0x10000;
2210                         PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !\n");
2211                 }
2212                 else
2213                         txdctl |= ((txq->wthresh & 0x1F) << 16);
2214                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2215                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2216         }
2217
2218 }
2219