lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 #define I40E_DEFAULT_RX_FREE_THRESH  32
  62 #define I40E_DEFAULT_RX_PTHRESH      8
  63 #define I40E_DEFAULT_RX_HTHRESH      8
  64 #define I40E_DEFAULT_RX_WTHRESH      0
  65
  66 #define I40E_DEFAULT_TX_FREE_THRESH  32
  67 #define I40E_DEFAULT_TX_PTHRESH      32
  68 #define I40E_DEFAULT_TX_HTHRESH      0
  69 #define I40E_DEFAULT_TX_WTHRESH      0
  70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  71
  72 /* Maximun number of MAC addresses */
  73 #define I40E_NUM_MACADDR_MAX       64
  74 #define I40E_CLEAR_PXE_WAIT_MS     200
  75
  76 /* Maximun number of capability elements */
  77 #define I40E_MAX_CAP_ELE_NUM       128
  78
  79 /* Wait count and inteval */
  80 #define I40E_CHK_Q_ENA_COUNT       1000
  81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  82
  83 /* Maximun number of VSI */
  84 #define I40E_MAX_NUM_VSIS          (384UL)
  85
  86 /* Bit shift and mask */
  87 #define I40E_16_BIT_SHIFT 16
  88 #define I40E_16_BIT_MASK  0xFFFF
  89 #define I40E_32_BIT_SHIFT 32
  90 #define I40E_32_BIT_MASK  0xFFFFFFFF
  91 #define I40E_48_BIT_SHIFT 48
  92 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  93
  94 /* Default queue interrupt throttling time in microseconds*/
  95 #define I40E_ITR_INDEX_DEFAULT          0
  96 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  97 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  98
  99 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 100
 101 static int eth_i40e_dev_init(\
 102                         __attribute__((unused)) struct eth_driver *eth_drv,
 103                         struct rte_eth_dev *eth_dev);
 104 static int i40e_dev_configure(struct rte_eth_dev *dev);
 105 static int i40e_dev_start(struct rte_eth_dev *dev);
 106 static void i40e_dev_stop(struct rte_eth_dev *dev);
 107 static void i40e_dev_close(struct rte_eth_dev *dev);
 108 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 113 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 114 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 115                                struct rte_eth_stats *stats);
 116 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 117 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 118                                             uint16_t queue_id,
 119                                             uint8_t stat_idx,
 120                                             uint8_t is_rx);
 121 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 122                               struct rte_eth_dev_info *dev_info);
 123 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 124                                 uint16_t vlan_id,
 125                                 int on);
 126 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 127 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 128 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 129                                       uint16_t queue,
 130                                       int on);
 131 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 132 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 133 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 134 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 135                               struct rte_eth_fc_conf *fc_conf);
 136 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 137                                        struct rte_eth_pfc_conf *pfc_conf);
 138 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 139                           struct ether_addr *mac_addr,
 140                           uint32_t index,
 141                           uint32_t pool);
 142 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 143 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 144                                     struct rte_eth_rss_reta *reta_conf);
 145 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                                    struct rte_eth_rss_reta *reta_conf);
 147
 148 static int i40e_get_cap(struct i40e_hw *hw);
 149 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 150 static int i40e_pf_setup(struct i40e_pf *pf);
 151 static int i40e_vsi_init(struct i40e_vsi *vsi);
 152 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 153                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 154 static void i40e_stat_update_48(struct i40e_hw *hw,
 155                                uint32_t hireg,
 156                                uint32_t loreg,
 157                                bool offset_loaded,
 158                                uint64_t *offset,
 159                                uint64_t *stat);
 160 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 161 static void i40e_dev_interrupt_handler(
 162                 __rte_unused struct rte_intr_handle *handle, void *param);
 163 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 164                                 uint32_t base, uint32_t num);
 165 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 166 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 167                         uint32_t base);
 168 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 169                         uint16_t num);
 170 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 171 static int i40e_veb_release(struct i40e_veb *veb);
 172 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 173                                                 struct i40e_vsi *vsi);
 174 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 175 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 176 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 177                                              struct i40e_macvlan_filter *mv_f,
 178                                              int num,
 179                                              struct ether_addr *addr);
 180 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 181                                              struct i40e_macvlan_filter *mv_f,
 182                                              int num,
 183                                              uint16_t vlan);
 184 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 185 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 186                                     struct rte_eth_rss_conf *rss_conf);
 187 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 188                                       struct rte_eth_rss_conf *rss_conf);
 189 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 190                                 struct rte_eth_udp_tunnel *udp_tunnel);
 191 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 192                                 struct rte_eth_udp_tunnel *udp_tunnel);
 193 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 194                                 enum rte_filter_type filter_type,
 195                                 enum rte_filter_op filter_op,
 196                                 void *arg);
 197
 198 /* Default hash key buffer for RSS */
 199 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 200
 201 static struct rte_pci_id pci_id_i40e_map[] = {
 202 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 203 #include "rte_pci_dev_ids.h"
 204 { .vendor_id = 0, /* sentinel */ },
 205 };
 206
 207 static struct eth_dev_ops i40e_eth_dev_ops = {
 208         .dev_configure                = i40e_dev_configure,
 209         .dev_start                    = i40e_dev_start,
 210         .dev_stop                     = i40e_dev_stop,
 211         .dev_close                    = i40e_dev_close,
 212         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 213         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 214         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 215         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 216         .dev_set_link_up              = i40e_dev_set_link_up,
 217         .dev_set_link_down            = i40e_dev_set_link_down,
 218         .link_update                  = i40e_dev_link_update,
 219         .stats_get                    = i40e_dev_stats_get,
 220         .stats_reset                  = i40e_dev_stats_reset,
 221         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 222         .dev_infos_get                = i40e_dev_info_get,
 223         .vlan_filter_set              = i40e_vlan_filter_set,
 224         .vlan_tpid_set                = i40e_vlan_tpid_set,
 225         .vlan_offload_set             = i40e_vlan_offload_set,
 226         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 227         .vlan_pvid_set                = i40e_vlan_pvid_set,
 228         .rx_queue_start               = i40e_dev_rx_queue_start,
 229         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 230         .tx_queue_start               = i40e_dev_tx_queue_start,
 231         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 232         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 233         .rx_queue_release             = i40e_dev_rx_queue_release,
 234         .rx_queue_count               = i40e_dev_rx_queue_count,
 235         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 236         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 237         .tx_queue_release             = i40e_dev_tx_queue_release,
 238         .dev_led_on                   = i40e_dev_led_on,
 239         .dev_led_off                  = i40e_dev_led_off,
 240         .flow_ctrl_set                = i40e_flow_ctrl_set,
 241         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 242         .mac_addr_add                 = i40e_macaddr_add,
 243         .mac_addr_remove              = i40e_macaddr_remove,
 244         .reta_update                  = i40e_dev_rss_reta_update,
 245         .reta_query                   = i40e_dev_rss_reta_query,
 246         .rss_hash_update              = i40e_dev_rss_hash_update,
 247         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 248         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 249         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 250         .filter_ctrl                  = i40e_dev_filter_ctrl,
 251 };
 252
 253 static struct eth_driver rte_i40e_pmd = {
 254         {
 255                 .name = "rte_i40e_pmd",
 256                 .id_table = pci_id_i40e_map,
 257                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 258         },
 259         .eth_dev_init = eth_i40e_dev_init,
 260         .dev_private_size = sizeof(struct i40e_adapter),
 261 };
 262
 263 static inline int
 264 i40e_prev_power_of_2(int n)
 265 {
 266        int p = n;
 267
 268        --p;
 269        p |= p >> 1;
 270        p |= p >> 2;
 271        p |= p >> 4;
 272        p |= p >> 8;
 273        p |= p >> 16;
 274        if (p == (n - 1))
 275                return n;
 276        p >>= 1;
 277
 278        return ++p;
 279 }
 280
 281 static inline int
 282 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 283                                      struct rte_eth_link *link)
 284 {
 285         struct rte_eth_link *dst = link;
 286         struct rte_eth_link *src = &(dev->data->dev_link);
 287
 288         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 289                                         *(uint64_t *)src) == 0)
 290                 return -1;
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 297                                       struct rte_eth_link *link)
 298 {
 299         struct rte_eth_link *dst = &(dev->data->dev_link);
 300         struct rte_eth_link *src = link;
 301
 302         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 303                                         *(uint64_t *)src) == 0)
 304                 return -1;
 305
 306         return 0;
 307 }
 308
 309 /*
 310  * Driver initialization routine.
 311  * Invoked once at EAL init time.
 312  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 313  */
 314 static int
 315 rte_i40e_pmd_init(const char *name __rte_unused,
 316                   const char *params __rte_unused)
 317 {
 318         PMD_INIT_FUNC_TRACE();
 319         rte_eth_driver_register(&rte_i40e_pmd);
 320
 321         return 0;
 322 }
 323
 324 static struct rte_driver rte_i40e_driver = {
 325         .type = PMD_PDEV,
 326         .init = rte_i40e_pmd_init,
 327 };
 328
 329 PMD_REGISTER_DRIVER(rte_i40e_driver);
 330
 331 static int
 332 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 333                   struct rte_eth_dev *dev)
 334 {
 335         struct rte_pci_device *pci_dev;
 336         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 338         struct i40e_vsi *vsi;
 339         int ret;
 340         uint32_t len;
 341         uint8_t aq_fail = 0;
 342
 343         PMD_INIT_FUNC_TRACE();
 344
 345         dev->dev_ops = &i40e_eth_dev_ops;
 346         dev->rx_pkt_burst = i40e_recv_pkts;
 347         dev->tx_pkt_burst = i40e_xmit_pkts;
 348
 349         /* for secondary processes, we don't initialise any further as primary
 350          * has already done this work. Only check we don't need a different
 351          * RX function */
 352         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 353                 if (dev->data->scattered_rx)
 354                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 355                 return 0;
 356         }
 357         pci_dev = dev->pci_dev;
 358         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 359         pf->adapter->eth_dev = dev;
 360         pf->dev_data = dev->data;
 361
 362         hw->back = I40E_PF_TO_ADAPTER(pf);
 363         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 364         if (!hw->hw_addr) {
 365                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 366                              "as address is NULL");
 367                 return -ENODEV;
 368         }
 369
 370         hw->vendor_id = pci_dev->id.vendor_id;
 371         hw->device_id = pci_dev->id.device_id;
 372         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 373         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 374         hw->bus.device = pci_dev->addr.devid;
 375         hw->bus.func = pci_dev->addr.function;
 376
 377         /* Make sure all is clean before doing PF reset */
 378         i40e_clear_hw(hw);
 379
 380         /* Reset here to make sure all is clean for each PF */
 381         ret = i40e_pf_reset(hw);
 382         if (ret) {
 383                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 384                 return ret;
 385         }
 386
 387         /* Initialize the shared code (base driver) */
 388         ret = i40e_init_shared_code(hw);
 389         if (ret) {
 390                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 391                 return ret;
 392         }
 393
 394         /* Initialize the parameters for adminq */
 395         i40e_init_adminq_parameter(hw);
 396         ret = i40e_init_adminq(hw);
 397         if (ret != I40E_SUCCESS) {
 398                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 399                 return -EIO;
 400         }
 401         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 402                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 403                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 404                      ((hw->nvm.version >> 12) & 0xf),
 405                      ((hw->nvm.version >> 4) & 0xff),
 406                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 407
 408         /* Disable LLDP */
 409         ret = i40e_aq_stop_lldp(hw, true, NULL);
 410         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 411                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 412
 413         /* Clear PXE mode */
 414         i40e_clear_pxe_mode(hw);
 415
 416         /* Get hw capabilities */
 417         ret = i40e_get_cap(hw);
 418         if (ret != I40E_SUCCESS) {
 419                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 420                 goto err_get_capabilities;
 421         }
 422
 423         /* Initialize parameters for PF */
 424         ret = i40e_pf_parameter_init(dev);
 425         if (ret != 0) {
 426                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 427                 goto err_parameter_init;
 428         }
 429
 430         /* Initialize the queue management */
 431         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 432         if (ret < 0) {
 433                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 434                 goto err_qp_pool_init;
 435         }
 436         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 437                                 hw->func_caps.num_msix_vectors - 1);
 438         if (ret < 0) {
 439                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 440                 goto err_msix_pool_init;
 441         }
 442
 443         /* Initialize lan hmc */
 444         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 445                                 hw->func_caps.num_rx_qp, 0, 0);
 446         if (ret != I40E_SUCCESS) {
 447                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 448                 goto err_init_lan_hmc;
 449         }
 450
 451         /* Configure lan hmc */
 452         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 453         if (ret != I40E_SUCCESS) {
 454                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 455                 goto err_configure_lan_hmc;
 456         }
 457
 458         /* Get and check the mac address */
 459         i40e_get_mac_addr(hw, hw->mac.addr);
 460         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 461                 PMD_INIT_LOG(ERR, "mac address is not valid");
 462                 ret = -EIO;
 463                 goto err_get_mac_addr;
 464         }
 465         /* Copy the permanent MAC address */
 466         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 467                         (struct ether_addr *) hw->mac.perm_addr);
 468
 469         /* Disable flow control */
 470         hw->fc.requested_mode = I40E_FC_NONE;
 471         i40e_set_fc(hw, &aq_fail, TRUE);
 472
 473         /* PF setup, which includes VSI setup */
 474         ret = i40e_pf_setup(pf);
 475         if (ret) {
 476                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 477                 goto err_setup_pf_switch;
 478         }
 479
 480         vsi = pf->main_vsi;
 481
 482         /* Disable double vlan by default */
 483         i40e_vsi_config_double_vlan(vsi, FALSE);
 484
 485         if (!vsi->max_macaddrs)
 486                 len = ETHER_ADDR_LEN;
 487         else
 488                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 489
 490         /* Should be after VSI initialized */
 491         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 492         if (!dev->data->mac_addrs) {
 493                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 494                                         "for storing mac address");
 495                 goto err_get_mac_addr;
 496         }
 497         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 498                                         &dev->data->mac_addrs[0]);
 499
 500         /* initialize pf host driver to setup SRIOV resource if applicable */
 501         i40e_pf_host_init(dev);
 502
 503         /* register callback func to eal lib */
 504         rte_intr_callback_register(&(pci_dev->intr_handle),
 505                 i40e_dev_interrupt_handler, (void *)dev);
 506
 507         /* configure and enable device interrupt */
 508         i40e_pf_config_irq0(hw);
 509         i40e_pf_enable_irq0(hw);
 510
 511         /* enable uio intr after callback register */
 512         rte_intr_enable(&(pci_dev->intr_handle));
 513
 514         return 0;
 515
 516 err_setup_pf_switch:
 517         rte_free(pf->main_vsi);
 518 err_get_mac_addr:
 519 err_configure_lan_hmc:
 520         (void)i40e_shutdown_lan_hmc(hw);
 521 err_init_lan_hmc:
 522         i40e_res_pool_destroy(&pf->msix_pool);
 523 err_msix_pool_init:
 524         i40e_res_pool_destroy(&pf->qp_pool);
 525 err_qp_pool_init:
 526 err_parameter_init:
 527 err_get_capabilities:
 528         (void)i40e_shutdown_adminq(hw);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 i40e_dev_configure(struct rte_eth_dev *dev)
 535 {
 536         return i40e_dev_init_vlan(dev);
 537 }
 538
 539 void
 540 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 541 {
 542         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 543         uint16_t msix_vect = vsi->msix_intr;
 544         uint16_t i;
 545
 546         for (i = 0; i < vsi->nb_qps; i++) {
 547                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 548                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 549                 rte_wmb();
 550         }
 551
 552         if (vsi->type != I40E_VSI_SRIOV) {
 553                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 554                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 555                                 msix_vect - 1), 0);
 556         } else {
 557                 uint32_t reg;
 558                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 559                         vsi->user_param + (msix_vect - 1);
 560
 561                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 562         }
 563         I40E_WRITE_FLUSH(hw);
 564 }
 565
 566 static inline uint16_t
 567 i40e_calc_itr_interval(int16_t interval)
 568 {
 569         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 570                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 571
 572         /* Convert to hardware count, as writing each 1 represents 2 us */
 573         return (interval/2);
 574 }
 575
 576 void
 577 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 578 {
 579         uint32_t val;
 580         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 581         uint16_t msix_vect = vsi->msix_intr;
 582         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 583         int i;
 584
 585         for (i = 0; i < vsi->nb_qps; i++)
 586                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 587
 588         /* Bind all RX queues to allocated MSIX interrupt */
 589         for (i = 0; i < vsi->nb_qps; i++) {
 590                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 591                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 592                         ((vsi->base_queue + i + 1) <<
 593                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 594                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 595                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 596
 597                 if (i == vsi->nb_qps - 1)
 598                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 599                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 600         }
 601
 602         /* Write first RX queue to Link list register as the head element */
 603         if (vsi->type != I40E_VSI_SRIOV) {
 604                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 605                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 606                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 607
 608                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 609                                 msix_vect - 1), interval);
 610
 611                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 612                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 613                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 614         }
 615         else {
 616                 uint32_t reg;
 617                 /* num_msix_vectors_vf needs to minus irq0 */
 618                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 619                         vsi->user_param + (msix_vect - 1);
 620
 621                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 622                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 623                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 624         }
 625
 626         I40E_WRITE_FLUSH(hw);
 627 }
 628
 629 static void
 630 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 631 {
 632         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 633         uint16_t interval = i40e_calc_itr_interval(\
 634                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 635
 636         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 637                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 638                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 639                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 640                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 641 }
 642
 643 static void
 644 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 645 {
 646         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 647
 648         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 649 }
 650
 651 static inline uint8_t
 652 i40e_parse_link_speed(uint16_t eth_link_speed)
 653 {
 654         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 655
 656         switch (eth_link_speed) {
 657         case ETH_LINK_SPEED_40G:
 658                 link_speed = I40E_LINK_SPEED_40GB;
 659                 break;
 660         case ETH_LINK_SPEED_20G:
 661                 link_speed = I40E_LINK_SPEED_20GB;
 662                 break;
 663         case ETH_LINK_SPEED_10G:
 664                 link_speed = I40E_LINK_SPEED_10GB;
 665                 break;
 666         case ETH_LINK_SPEED_1000:
 667                 link_speed = I40E_LINK_SPEED_1GB;
 668                 break;
 669         case ETH_LINK_SPEED_100:
 670                 link_speed = I40E_LINK_SPEED_100MB;
 671                 break;
 672         }
 673
 674         return link_speed;
 675 }
 676
 677 static int
 678 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 679 {
 680         enum i40e_status_code status;
 681         struct i40e_aq_get_phy_abilities_resp phy_ab;
 682         struct i40e_aq_set_phy_config phy_conf;
 683         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 684                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 685                         I40E_AQ_PHY_FLAG_LOW_POWER;
 686         const uint8_t advt = I40E_LINK_SPEED_40GB |
 687                         I40E_LINK_SPEED_10GB |
 688                         I40E_LINK_SPEED_1GB |
 689                         I40E_LINK_SPEED_100MB;
 690         int ret = -ENOTSUP;
 691
 692         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 693                                               NULL);
 694         if (status)
 695                 return ret;
 696
 697         memset(&phy_conf, 0, sizeof(phy_conf));
 698
 699         /* bits 0-2 use the values from get_phy_abilities_resp */
 700         abilities &= ~mask;
 701         abilities |= phy_ab.abilities & mask;
 702
 703         /* update ablities and speed */
 704         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 705                 phy_conf.link_speed = advt;
 706         else
 707                 phy_conf.link_speed = force_speed;
 708
 709         phy_conf.abilities = abilities;
 710
 711         /* use get_phy_abilities_resp value for the rest */
 712         phy_conf.phy_type = phy_ab.phy_type;
 713         phy_conf.eee_capability = phy_ab.eee_capability;
 714         phy_conf.eeer = phy_ab.eeer_val;
 715         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 716
 717         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 718                     phy_ab.abilities, phy_ab.link_speed);
 719         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 720                     phy_conf.abilities, phy_conf.link_speed);
 721
 722         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 723         if (status)
 724                 return ret;
 725
 726         return I40E_SUCCESS;
 727 }
 728
 729 static int
 730 i40e_apply_link_speed(struct rte_eth_dev *dev)
 731 {
 732         uint8_t speed;
 733         uint8_t abilities = 0;
 734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 735         struct rte_eth_conf *conf = &dev->data->dev_conf;
 736
 737         speed = i40e_parse_link_speed(conf->link_speed);
 738         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 739         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 740                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 741         else
 742                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 743
 744         return i40e_phy_conf_link(hw, abilities, speed);
 745 }
 746
 747 static int
 748 i40e_dev_start(struct rte_eth_dev *dev)
 749 {
 750         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 752         struct i40e_vsi *vsi = pf->main_vsi;
 753         int ret;
 754
 755         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 756                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 757                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 758                              dev->data->dev_conf.link_duplex,
 759                              dev->data->port_id);
 760                 return -EINVAL;
 761         }
 762
 763         /* Initialize VSI */
 764         ret = i40e_vsi_init(vsi);
 765         if (ret != I40E_SUCCESS) {
 766                 PMD_DRV_LOG(ERR, "Failed to init VSI");
 767                 goto err_up;
 768         }
 769
 770         /* Map queues with MSIX interrupt */
 771         i40e_vsi_queues_bind_intr(vsi);
 772         i40e_vsi_enable_queues_intr(vsi);
 773
 774         /* Enable all queues which have been configured */
 775         ret = i40e_vsi_switch_queues(vsi, TRUE);
 776         if (ret != I40E_SUCCESS) {
 777                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 778                 goto err_up;
 779         }
 780
 781         /* Enable receiving broadcast packets */
 782         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 783                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 784                 if (ret != I40E_SUCCESS)
 785                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 786         }
 787
 788         /* Apply link configure */
 789         ret = i40e_apply_link_speed(dev);
 790         if (I40E_SUCCESS != ret) {
 791                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 792                 goto err_up;
 793         }
 794
 795         return I40E_SUCCESS;
 796
 797 err_up:
 798         i40e_vsi_switch_queues(vsi, FALSE);
 799
 800         return ret;
 801 }
 802
 803 static void
 804 i40e_dev_stop(struct rte_eth_dev *dev)
 805 {
 806         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 807         struct i40e_vsi *vsi = pf->main_vsi;
 808
 809         /* Disable all queues */
 810         i40e_vsi_switch_queues(vsi, FALSE);
 811
 812         /* Set link down */
 813         i40e_dev_set_link_down(dev);
 814
 815         /* un-map queues with interrupt registers */
 816         i40e_vsi_disable_queues_intr(vsi);
 817         i40e_vsi_queues_unbind_intr(vsi);
 818 }
 819
 820 static void
 821 i40e_dev_close(struct rte_eth_dev *dev)
 822 {
 823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 825         uint32_t reg;
 826
 827         PMD_INIT_FUNC_TRACE();
 828
 829         i40e_dev_stop(dev);
 830
 831         /* Disable interrupt */
 832         i40e_pf_disable_irq0(hw);
 833         rte_intr_disable(&(dev->pci_dev->intr_handle));
 834
 835         /* shutdown and destroy the HMC */
 836         i40e_shutdown_lan_hmc(hw);
 837
 838         /* release all the existing VSIs and VEBs */
 839         i40e_vsi_release(pf->main_vsi);
 840
 841         /* shutdown the adminq */
 842         i40e_aq_queue_shutdown(hw, true);
 843         i40e_shutdown_adminq(hw);
 844
 845         i40e_res_pool_destroy(&pf->qp_pool);
 846         i40e_res_pool_destroy(&pf->msix_pool);
 847
 848         /* force a PF reset to clean anything leftover */
 849         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 850         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 851                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 852         I40E_WRITE_FLUSH(hw);
 853 }
 854
 855 static void
 856 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 857 {
 858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 859         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 860         struct i40e_vsi *vsi = pf->main_vsi;
 861         int status;
 862
 863         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 864                                                         true, NULL);
 865         if (status != I40E_SUCCESS)
 866                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 867
 868         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 869                                                         TRUE, NULL);
 870         if (status != I40E_SUCCESS)
 871                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 872
 873 }
 874
 875 static void
 876 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 877 {
 878         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 880         struct i40e_vsi *vsi = pf->main_vsi;
 881         int status;
 882
 883         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 884                                                         false, NULL);
 885         if (status != I40E_SUCCESS)
 886                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 887
 888         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 889                                                         false, NULL);
 890         if (status != I40E_SUCCESS)
 891                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 892 }
 893
 894 static void
 895 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 896 {
 897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 899         struct i40e_vsi *vsi = pf->main_vsi;
 900         int ret;
 901
 902         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 903         if (ret != I40E_SUCCESS)
 904                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 905 }
 906
 907 static void
 908 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 909 {
 910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912         struct i40e_vsi *vsi = pf->main_vsi;
 913         int ret;
 914
 915         if (dev->data->promiscuous == 1)
 916                 return; /* must remain in all_multicast mode */
 917
 918         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 919                                 vsi->seid, FALSE, NULL);
 920         if (ret != I40E_SUCCESS)
 921                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 922 }
 923
 924 /*
 925  * Set device link up.
 926  */
 927 static int
 928 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 929 {
 930         /* re-apply link speed setting */
 931         return i40e_apply_link_speed(dev);
 932 }
 933
 934 /*
 935  * Set device link down.
 936  */
 937 static int
 938 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 939 {
 940         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 941         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 943
 944         return i40e_phy_conf_link(hw, abilities, speed);
 945 }
 946
 947 int
 948 i40e_dev_link_update(struct rte_eth_dev *dev,
 949                      __rte_unused int wait_to_complete)
 950 {
 951         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 952         struct i40e_link_status link_status;
 953         struct rte_eth_link link, old;
 954         int status;
 955
 956         memset(&link, 0, sizeof(link));
 957         memset(&old, 0, sizeof(old));
 958         memset(&link_status, 0, sizeof(link_status));
 959         rte_i40e_dev_atomic_read_link_status(dev, &old);
 960
 961         /* Get link status information from hardware */
 962         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 963         if (status != I40E_SUCCESS) {
 964                 link.link_speed = ETH_LINK_SPEED_100;
 965                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 966                 PMD_DRV_LOG(ERR, "Failed to get link info");
 967                 goto out;
 968         }
 969
 970         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 971
 972         if (!link.link_status)
 973                 goto out;
 974
 975         /* i40e uses full duplex only */
 976         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 977
 978         /* Parse the link status */
 979         switch (link_status.link_speed) {
 980         case I40E_LINK_SPEED_100MB:
 981                 link.link_speed = ETH_LINK_SPEED_100;
 982                 break;
 983         case I40E_LINK_SPEED_1GB:
 984                 link.link_speed = ETH_LINK_SPEED_1000;
 985                 break;
 986         case I40E_LINK_SPEED_10GB:
 987                 link.link_speed = ETH_LINK_SPEED_10G;
 988                 break;
 989         case I40E_LINK_SPEED_20GB:
 990                 link.link_speed = ETH_LINK_SPEED_20G;
 991                 break;
 992         case I40E_LINK_SPEED_40GB:
 993                 link.link_speed = ETH_LINK_SPEED_40G;
 994                 break;
 995         default:
 996                 link.link_speed = ETH_LINK_SPEED_100;
 997                 break;
 998         }
 999
1000 out:
1001         rte_i40e_dev_atomic_write_link_status(dev, &link);
1002         if (link.link_status == old.link_status)
1003                 return -1;
1004
1005         return 0;
1006 }
1007
1008 /* Get all the statistics of a VSI */
1009 void
1010 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1011 {
1012         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1013         struct i40e_eth_stats *nes = &vsi->eth_stats;
1014         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1015         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1016
1017         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1018                             vsi->offset_loaded, &oes->rx_bytes,
1019                             &nes->rx_bytes);
1020         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1021                             vsi->offset_loaded, &oes->rx_unicast,
1022                             &nes->rx_unicast);
1023         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1024                             vsi->offset_loaded, &oes->rx_multicast,
1025                             &nes->rx_multicast);
1026         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1027                             vsi->offset_loaded, &oes->rx_broadcast,
1028                             &nes->rx_broadcast);
1029         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1030                             &oes->rx_discards, &nes->rx_discards);
1031         /* GLV_REPC not supported */
1032         /* GLV_RMPC not supported */
1033         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1034                             &oes->rx_unknown_protocol,
1035                             &nes->rx_unknown_protocol);
1036         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1037                             vsi->offset_loaded, &oes->tx_bytes,
1038                             &nes->tx_bytes);
1039         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1040                             vsi->offset_loaded, &oes->tx_unicast,
1041                             &nes->tx_unicast);
1042         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1043                             vsi->offset_loaded, &oes->tx_multicast,
1044                             &nes->tx_multicast);
1045         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1046                             vsi->offset_loaded,  &oes->tx_broadcast,
1047                             &nes->tx_broadcast);
1048         /* GLV_TDPC not supported */
1049         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1050                             &oes->tx_errors, &nes->tx_errors);
1051         vsi->offset_loaded = true;
1052
1053         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1054                     vsi->vsi_id);
1055         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1056         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1057         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1058         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1059         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1060         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1061                     nes->rx_unknown_protocol);
1062         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1063         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1064         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1065         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1066         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1067         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1068         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1069                     vsi->vsi_id);
1070 }
1071
1072 /* Get all statistics of a port */
1073 static void
1074 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1075 {
1076         uint32_t i;
1077         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1079         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1080         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1081
1082         /* Get statistics of struct i40e_eth_stats */
1083         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1084                             I40E_GLPRT_GORCL(hw->port),
1085                             pf->offset_loaded, &os->eth.rx_bytes,
1086                             &ns->eth.rx_bytes);
1087         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1088                             I40E_GLPRT_UPRCL(hw->port),
1089                             pf->offset_loaded, &os->eth.rx_unicast,
1090                             &ns->eth.rx_unicast);
1091         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1092                             I40E_GLPRT_MPRCL(hw->port),
1093                             pf->offset_loaded, &os->eth.rx_multicast,
1094                             &ns->eth.rx_multicast);
1095         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1096                             I40E_GLPRT_BPRCL(hw->port),
1097                             pf->offset_loaded, &os->eth.rx_broadcast,
1098                             &ns->eth.rx_broadcast);
1099         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1100                             pf->offset_loaded, &os->eth.rx_discards,
1101                             &ns->eth.rx_discards);
1102         /* GLPRT_REPC not supported */
1103         /* GLPRT_RMPC not supported */
1104         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1105                             pf->offset_loaded,
1106                             &os->eth.rx_unknown_protocol,
1107                             &ns->eth.rx_unknown_protocol);
1108         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1109                             I40E_GLPRT_GOTCL(hw->port),
1110                             pf->offset_loaded, &os->eth.tx_bytes,
1111                             &ns->eth.tx_bytes);
1112         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1113                             I40E_GLPRT_UPTCL(hw->port),
1114                             pf->offset_loaded, &os->eth.tx_unicast,
1115                             &ns->eth.tx_unicast);
1116         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1117                             I40E_GLPRT_MPTCL(hw->port),
1118                             pf->offset_loaded, &os->eth.tx_multicast,
1119                             &ns->eth.tx_multicast);
1120         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1121                             I40E_GLPRT_BPTCL(hw->port),
1122                             pf->offset_loaded, &os->eth.tx_broadcast,
1123                             &ns->eth.tx_broadcast);
1124         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1125                             pf->offset_loaded, &os->eth.tx_discards,
1126                             &ns->eth.tx_discards);
1127         /* GLPRT_TEPC not supported */
1128
1129         /* additional port specific stats */
1130         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1131                             pf->offset_loaded, &os->tx_dropped_link_down,
1132                             &ns->tx_dropped_link_down);
1133         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1134                             pf->offset_loaded, &os->crc_errors,
1135                             &ns->crc_errors);
1136         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1137                             pf->offset_loaded, &os->illegal_bytes,
1138                             &ns->illegal_bytes);
1139         /* GLPRT_ERRBC not supported */
1140         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1141                             pf->offset_loaded, &os->mac_local_faults,
1142                             &ns->mac_local_faults);
1143         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1144                             pf->offset_loaded, &os->mac_remote_faults,
1145                             &ns->mac_remote_faults);
1146         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1147                             pf->offset_loaded, &os->rx_length_errors,
1148                             &ns->rx_length_errors);
1149         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1150                             pf->offset_loaded, &os->link_xon_rx,
1151                             &ns->link_xon_rx);
1152         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1153                             pf->offset_loaded, &os->link_xoff_rx,
1154                             &ns->link_xoff_rx);
1155         for (i = 0; i < 8; i++) {
1156                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1157                                     pf->offset_loaded,
1158                                     &os->priority_xon_rx[i],
1159                                     &ns->priority_xon_rx[i]);
1160                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1161                                     pf->offset_loaded,
1162                                     &os->priority_xoff_rx[i],
1163                                     &ns->priority_xoff_rx[i]);
1164         }
1165         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1166                             pf->offset_loaded, &os->link_xon_tx,
1167                             &ns->link_xon_tx);
1168         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1169                             pf->offset_loaded, &os->link_xoff_tx,
1170                             &ns->link_xoff_tx);
1171         for (i = 0; i < 8; i++) {
1172                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1173                                     pf->offset_loaded,
1174                                     &os->priority_xon_tx[i],
1175                                     &ns->priority_xon_tx[i]);
1176                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1177                                     pf->offset_loaded,
1178                                     &os->priority_xoff_tx[i],
1179                                     &ns->priority_xoff_tx[i]);
1180                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1181                                     pf->offset_loaded,
1182                                     &os->priority_xon_2_xoff[i],
1183                                     &ns->priority_xon_2_xoff[i]);
1184         }
1185         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1186                             I40E_GLPRT_PRC64L(hw->port),
1187                             pf->offset_loaded, &os->rx_size_64,
1188                             &ns->rx_size_64);
1189         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1190                             I40E_GLPRT_PRC127L(hw->port),
1191                             pf->offset_loaded, &os->rx_size_127,
1192                             &ns->rx_size_127);
1193         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1194                             I40E_GLPRT_PRC255L(hw->port),
1195                             pf->offset_loaded, &os->rx_size_255,
1196                             &ns->rx_size_255);
1197         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1198                             I40E_GLPRT_PRC511L(hw->port),
1199                             pf->offset_loaded, &os->rx_size_511,
1200                             &ns->rx_size_511);
1201         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1202                             I40E_GLPRT_PRC1023L(hw->port),
1203                             pf->offset_loaded, &os->rx_size_1023,
1204                             &ns->rx_size_1023);
1205         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1206                             I40E_GLPRT_PRC1522L(hw->port),
1207                             pf->offset_loaded, &os->rx_size_1522,
1208                             &ns->rx_size_1522);
1209         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1210                             I40E_GLPRT_PRC9522L(hw->port),
1211                             pf->offset_loaded, &os->rx_size_big,
1212                             &ns->rx_size_big);
1213         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1214                             pf->offset_loaded, &os->rx_undersize,
1215                             &ns->rx_undersize);
1216         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1217                             pf->offset_loaded, &os->rx_fragments,
1218                             &ns->rx_fragments);
1219         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1220                             pf->offset_loaded, &os->rx_oversize,
1221                             &ns->rx_oversize);
1222         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1223                             pf->offset_loaded, &os->rx_jabber,
1224                             &ns->rx_jabber);
1225         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1226                             I40E_GLPRT_PTC64L(hw->port),
1227                             pf->offset_loaded, &os->tx_size_64,
1228                             &ns->tx_size_64);
1229         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1230                             I40E_GLPRT_PTC127L(hw->port),
1231                             pf->offset_loaded, &os->tx_size_127,
1232                             &ns->tx_size_127);
1233         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1234                             I40E_GLPRT_PTC255L(hw->port),
1235                             pf->offset_loaded, &os->tx_size_255,
1236                             &ns->tx_size_255);
1237         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1238                             I40E_GLPRT_PTC511L(hw->port),
1239                             pf->offset_loaded, &os->tx_size_511,
1240                             &ns->tx_size_511);
1241         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1242                             I40E_GLPRT_PTC1023L(hw->port),
1243                             pf->offset_loaded, &os->tx_size_1023,
1244                             &ns->tx_size_1023);
1245         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1246                             I40E_GLPRT_PTC1522L(hw->port),
1247                             pf->offset_loaded, &os->tx_size_1522,
1248                             &ns->tx_size_1522);
1249         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1250                             I40E_GLPRT_PTC9522L(hw->port),
1251                             pf->offset_loaded, &os->tx_size_big,
1252                             &ns->tx_size_big);
1253         /* GLPRT_MSPDC not supported */
1254         /* GLPRT_XEC not supported */
1255
1256         pf->offset_loaded = true;
1257
1258         if (pf->main_vsi)
1259                 i40e_update_vsi_stats(pf->main_vsi);
1260
1261         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1262                                                 ns->eth.rx_broadcast;
1263         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1264                                                 ns->eth.tx_broadcast;
1265         stats->ibytes   = ns->eth.rx_bytes;
1266         stats->obytes   = ns->eth.tx_bytes;
1267         stats->oerrors  = ns->eth.tx_errors;
1268         stats->imcasts  = ns->eth.rx_multicast;
1269
1270         /* Rx Errors */
1271         stats->ibadcrc  = ns->crc_errors;
1272         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1273                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1274         stats->imissed  = ns->eth.rx_discards;
1275         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1276
1277         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1278         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1279         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1280         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1281         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1282         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1283         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1284                     ns->eth.rx_unknown_protocol);
1285         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1286         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1287         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1288         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1289         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1290         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1291
1292         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1293                     ns->tx_dropped_link_down);
1294         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1295         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1296                     ns->illegal_bytes);
1297         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1298         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1299                     ns->mac_local_faults);
1300         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1301                     ns->mac_remote_faults);
1302         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1303                     ns->rx_length_errors);
1304         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1305         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1306         for (i = 0; i < 8; i++) {
1307                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1308                                 i, ns->priority_xon_rx[i]);
1309                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1310                                 i, ns->priority_xoff_rx[i]);
1311         }
1312         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1313         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1314         for (i = 0; i < 8; i++) {
1315                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1316                                 i, ns->priority_xon_tx[i]);
1317                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1318                                 i, ns->priority_xoff_tx[i]);
1319                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1320                                 i, ns->priority_xon_2_xoff[i]);
1321         }
1322         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1323         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1324         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1325         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1326         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1327         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1328         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1329         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1330         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1331         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1332         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1333         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1334         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1335         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1336         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1337         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1338         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1339         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1340         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1341                         ns->mac_short_packet_dropped);
1342         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1343                     ns->checksum_error);
1344         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1345 }
1346
1347 /* Reset the statistics */
1348 static void
1349 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1350 {
1351         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1352
1353         /* It results in reloading the start point of each counter */
1354         pf->offset_loaded = false;
1355 }
1356
1357 static int
1358 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1359                                  __rte_unused uint16_t queue_id,
1360                                  __rte_unused uint8_t stat_idx,
1361                                  __rte_unused uint8_t is_rx)
1362 {
1363         PMD_INIT_FUNC_TRACE();
1364
1365         return -ENOSYS;
1366 }
1367
1368 static void
1369 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1370 {
1371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1372         struct i40e_vsi *vsi = pf->main_vsi;
1373
1374         dev_info->max_rx_queues = vsi->nb_qps;
1375         dev_info->max_tx_queues = vsi->nb_qps;
1376         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1377         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1378         dev_info->max_mac_addrs = vsi->max_macaddrs;
1379         dev_info->max_vfs = dev->pci_dev->max_vfs;
1380         dev_info->rx_offload_capa =
1381                 DEV_RX_OFFLOAD_VLAN_STRIP |
1382                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1383                 DEV_RX_OFFLOAD_UDP_CKSUM |
1384                 DEV_RX_OFFLOAD_TCP_CKSUM;
1385         dev_info->tx_offload_capa =
1386                 DEV_TX_OFFLOAD_VLAN_INSERT |
1387                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1388                 DEV_TX_OFFLOAD_UDP_CKSUM |
1389                 DEV_TX_OFFLOAD_TCP_CKSUM |
1390                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1391
1392         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1393                 .rx_thresh = {
1394                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1395                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1396                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1397                 },
1398                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1399                 .rx_drop_en = 0,
1400         };
1401
1402         dev_info->default_txconf = (struct rte_eth_txconf) {
1403                 .tx_thresh = {
1404                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1405                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1406                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1407                 },
1408                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1409                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1410                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1411         };
1412
1413 }
1414
1415 static int
1416 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1417 {
1418         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1419         struct i40e_vsi *vsi = pf->main_vsi;
1420         PMD_INIT_FUNC_TRACE();
1421
1422         if (on)
1423                 return i40e_vsi_add_vlan(vsi, vlan_id);
1424         else
1425                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1426 }
1427
1428 static void
1429 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1430                    __rte_unused uint16_t tpid)
1431 {
1432         PMD_INIT_FUNC_TRACE();
1433 }
1434
1435 static void
1436 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1437 {
1438         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1439         struct i40e_vsi *vsi = pf->main_vsi;
1440
1441         if (mask & ETH_VLAN_STRIP_MASK) {
1442                 /* Enable or disable VLAN stripping */
1443                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1444                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1445                 else
1446                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1447         }
1448
1449         if (mask & ETH_VLAN_EXTEND_MASK) {
1450                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1451                         i40e_vsi_config_double_vlan(vsi, TRUE);
1452                 else
1453                         i40e_vsi_config_double_vlan(vsi, FALSE);
1454         }
1455 }
1456
1457 static void
1458 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1459                           __rte_unused uint16_t queue,
1460                           __rte_unused int on)
1461 {
1462         PMD_INIT_FUNC_TRACE();
1463 }
1464
1465 static int
1466 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1467 {
1468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1469         struct i40e_vsi *vsi = pf->main_vsi;
1470         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1471         struct i40e_vsi_vlan_pvid_info info;
1472
1473         memset(&info, 0, sizeof(info));
1474         info.on = on;
1475         if (info.on)
1476                 info.config.pvid = pvid;
1477         else {
1478                 info.config.reject.tagged =
1479                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1480                 info.config.reject.untagged =
1481                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1482         }
1483
1484         return i40e_vsi_vlan_pvid_set(vsi, &info);
1485 }
1486
1487 static int
1488 i40e_dev_led_on(struct rte_eth_dev *dev)
1489 {
1490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491         uint32_t mode = i40e_led_get(hw);
1492
1493         if (mode == 0)
1494                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1495
1496         return 0;
1497 }
1498
1499 static int
1500 i40e_dev_led_off(struct rte_eth_dev *dev)
1501 {
1502         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503         uint32_t mode = i40e_led_get(hw);
1504
1505         if (mode != 0)
1506                 i40e_led_set(hw, 0, false);
1507
1508         return 0;
1509 }
1510
1511 static int
1512 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1513                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1514 {
1515         PMD_INIT_FUNC_TRACE();
1516
1517         return -ENOSYS;
1518 }
1519
1520 static int
1521 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1522                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1523 {
1524         PMD_INIT_FUNC_TRACE();
1525
1526         return -ENOSYS;
1527 }
1528
1529 /* Add a MAC address, and update filters */
1530 static void
1531 i40e_macaddr_add(struct rte_eth_dev *dev,
1532                  struct ether_addr *mac_addr,
1533                  __attribute__((unused)) uint32_t index,
1534                  __attribute__((unused)) uint32_t pool)
1535 {
1536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538         struct i40e_vsi *vsi = pf->main_vsi;
1539         struct ether_addr old_mac;
1540         int ret;
1541
1542         if (!is_valid_assigned_ether_addr(mac_addr)) {
1543                 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1544                 return;
1545         }
1546
1547         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1548                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1549                 return;
1550         }
1551
1552         /* Write mac address */
1553         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1554                                         mac_addr->addr_bytes, NULL);
1555         if (ret != I40E_SUCCESS) {
1556                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1557                 return;
1558         }
1559
1560         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1561         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1562                         ETHER_ADDR_LEN);
1563
1564         ret = i40e_vsi_add_mac(vsi, mac_addr);
1565         if (ret != I40E_SUCCESS) {
1566                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1567                 return;
1568         }
1569
1570         ether_addr_copy(mac_addr, &pf->dev_addr);
1571         i40e_vsi_delete_mac(vsi, &old_mac);
1572 }
1573
1574 /* Remove a MAC address, and update filters */
1575 static void
1576 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1577 {
1578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1579         struct i40e_vsi *vsi = pf->main_vsi;
1580         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1581         struct ether_addr *macaddr;
1582         int ret;
1583         struct i40e_hw *hw =
1584                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585
1586         if (index >= vsi->max_macaddrs)
1587                 return;
1588
1589         macaddr = &(data->mac_addrs[index]);
1590         if (!is_valid_assigned_ether_addr(macaddr))
1591                 return;
1592
1593         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1594                                         hw->mac.perm_addr, NULL);
1595         if (ret != I40E_SUCCESS) {
1596                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1597                 return;
1598         }
1599
1600         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1601
1602         ret = i40e_vsi_delete_mac(vsi, macaddr);
1603         if (ret != I40E_SUCCESS)
1604                 return;
1605
1606         /* Clear device address as it has been removed */
1607         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1608                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1609 }
1610
1611 static int
1612 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1613                          struct rte_eth_rss_reta *reta_conf)
1614 {
1615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616         uint32_t lut, l;
1617         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1618
1619         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1620                 if (i < max)
1621                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1622                 else
1623                         mask = (uint8_t)((reta_conf->mask_hi >>
1624                                                 (i - max)) & 0xF);
1625
1626                 if (!mask)
1627                         continue;
1628
1629                 if (mask == 0xF)
1630                         l = 0;
1631                 else
1632                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1633
1634                 for (j = 0, lut = 0; j < 4; j++) {
1635                         if (mask & (0x1 << j))
1636                                 lut |= reta_conf->reta[i + j] << (8 * j);
1637                         else
1638                                 lut |= l & (0xFF << (8 * j));
1639                 }
1640                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1641         }
1642
1643         return 0;
1644 }
1645
1646 static int
1647 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1648                         struct rte_eth_rss_reta *reta_conf)
1649 {
1650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651         uint32_t lut;
1652         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1653
1654         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1655                 if (i < max)
1656                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1657                 else
1658                         mask = (uint8_t)((reta_conf->mask_hi >>
1659                                                 (i - max)) & 0xF);
1660
1661                 if (!mask)
1662                         continue;
1663
1664                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1665                 for (j = 0; j < 4; j++) {
1666                         if (mask & (0x1 << j))
1667                                 reta_conf->reta[i + j] =
1668                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1669                 }
1670         }
1671
1672         return 0;
1673 }
1674
1675 /**
1676  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1677  * @hw:   pointer to the HW structure
1678  * @mem:  pointer to mem struct to fill out
1679  * @size: size of memory requested
1680  * @alignment: what to align the allocation to
1681  **/
1682 enum i40e_status_code
1683 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1684                         struct i40e_dma_mem *mem,
1685                         u64 size,
1686                         u32 alignment)
1687 {
1688         static uint64_t id = 0;
1689         const struct rte_memzone *mz = NULL;
1690         char z_name[RTE_MEMZONE_NAMESIZE];
1691
1692         if (!mem)
1693                 return I40E_ERR_PARAM;
1694
1695         id++;
1696         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1697 #ifdef RTE_LIBRTE_XEN_DOM0
1698         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1699                                                         RTE_PGSIZE_2M);
1700 #else
1701         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1702 #endif
1703         if (!mz)
1704                 return I40E_ERR_NO_MEMORY;
1705
1706         mem->id = id;
1707         mem->size = size;
1708         mem->va = mz->addr;
1709 #ifdef RTE_LIBRTE_XEN_DOM0
1710         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1711 #else
1712         mem->pa = mz->phys_addr;
1713 #endif
1714
1715         return I40E_SUCCESS;
1716 }
1717
1718 /**
1719  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1720  * @hw:   pointer to the HW structure
1721  * @mem:  ptr to mem struct to free
1722  **/
1723 enum i40e_status_code
1724 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1725                     struct i40e_dma_mem *mem)
1726 {
1727         if (!mem || !mem->va)
1728                 return I40E_ERR_PARAM;
1729
1730         mem->va = NULL;
1731         mem->pa = (u64)0;
1732
1733         return I40E_SUCCESS;
1734 }
1735
1736 /**
1737  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1738  * @hw:   pointer to the HW structure
1739  * @mem:  pointer to mem struct to fill out
1740  * @size: size of memory requested
1741  **/
1742 enum i40e_status_code
1743 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1744                          struct i40e_virt_mem *mem,
1745                          u32 size)
1746 {
1747         if (!mem)
1748                 return I40E_ERR_PARAM;
1749
1750         mem->size = size;
1751         mem->va = rte_zmalloc("i40e", size, 0);
1752
1753         if (mem->va)
1754                 return I40E_SUCCESS;
1755         else
1756                 return I40E_ERR_NO_MEMORY;
1757 }
1758
1759 /**
1760  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1761  * @hw:   pointer to the HW structure
1762  * @mem:  pointer to mem struct to free
1763  **/
1764 enum i40e_status_code
1765 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1766                      struct i40e_virt_mem *mem)
1767 {
1768         if (!mem)
1769                 return I40E_ERR_PARAM;
1770
1771         rte_free(mem->va);
1772         mem->va = NULL;
1773
1774         return I40E_SUCCESS;
1775 }
1776
1777 void
1778 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1779 {
1780         rte_spinlock_init(&sp->spinlock);
1781 }
1782
1783 void
1784 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1785 {
1786         rte_spinlock_lock(&sp->spinlock);
1787 }
1788
1789 void
1790 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1791 {
1792         rte_spinlock_unlock(&sp->spinlock);
1793 }
1794
1795 void
1796 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1797 {
1798         return;
1799 }
1800
1801 /**
1802  * Get the hardware capabilities, which will be parsed
1803  * and saved into struct i40e_hw.
1804  */
1805 static int
1806 i40e_get_cap(struct i40e_hw *hw)
1807 {
1808         struct i40e_aqc_list_capabilities_element_resp *buf;
1809         uint16_t len, size = 0;
1810         int ret;
1811
1812         /* Calculate a huge enough buff for saving response data temporarily */
1813         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1814                                                 I40E_MAX_CAP_ELE_NUM;
1815         buf = rte_zmalloc("i40e", len, 0);
1816         if (!buf) {
1817                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1818                 return I40E_ERR_NO_MEMORY;
1819         }
1820
1821         /* Get, parse the capabilities and save it to hw */
1822         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1823                         i40e_aqc_opc_list_func_capabilities, NULL);
1824         if (ret != I40E_SUCCESS)
1825                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1826
1827         /* Free the temporary buffer after being used */
1828         rte_free(buf);
1829
1830         return ret;
1831 }
1832
1833 static int
1834 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1835 {
1836         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1837         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1838         uint16_t sum_queues = 0, sum_vsis;
1839
1840         /* First check if FW support SRIOV */
1841         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1842                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1843                 return -EINVAL;
1844         }
1845
1846         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1847         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1848         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1849         /* Allocate queues for pf */
1850         if (hw->func_caps.rss) {
1851                 pf->flags |= I40E_FLAG_RSS;
1852                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1853                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1854                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1855         } else
1856                 pf->lan_nb_qps = 1;
1857         sum_queues = pf->lan_nb_qps;
1858         /* Default VSI is not counted in */
1859         sum_vsis = 0;
1860         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1861
1862         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1863                 pf->flags |= I40E_FLAG_SRIOV;
1864                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1865                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1866                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1867                                      "max supported %u.",
1868                                      dev->pci_dev->max_vfs,
1869                                      hw->func_caps.num_vfs);
1870                         return -EINVAL;
1871                 }
1872                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1873                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1874                                      "max support %u queues.",
1875                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1876                         return -EINVAL;
1877                 }
1878                 pf->vf_num = dev->pci_dev->max_vfs;
1879                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1880                 sum_vsis   += pf->vf_num;
1881                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1882                              pf->vf_num, pf->vf_nb_qps);
1883         } else
1884                 pf->vf_num = 0;
1885
1886         if (hw->func_caps.vmdq) {
1887                 pf->flags |= I40E_FLAG_VMDQ;
1888                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1889                 sum_queues += pf->vmdq_nb_qps;
1890                 sum_vsis += 1;
1891                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1892         }
1893
1894         if (hw->func_caps.fd) {
1895                 pf->flags |= I40E_FLAG_FDIR;
1896                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1897                 /**
1898                  * Each flow director consumes one VSI and one queue,
1899                  * but can't calculate out predictably here.
1900                  */
1901         }
1902
1903         if (sum_vsis > pf->max_num_vsi ||
1904                 sum_queues > hw->func_caps.num_rx_qp) {
1905                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1906                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1907                              pf->max_num_vsi, sum_vsis);
1908                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1909                              hw->func_caps.num_rx_qp, sum_queues);
1910                 return -EINVAL;
1911         }
1912
1913         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1914          * cause */
1915         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1916                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1917                              sum_vsis, hw->func_caps.num_msix_vectors);
1918                 return -EINVAL;
1919         }
1920         return I40E_SUCCESS;
1921 }
1922
1923 static int
1924 i40e_pf_get_switch_config(struct i40e_pf *pf)
1925 {
1926         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1927         struct i40e_aqc_get_switch_config_resp *switch_config;
1928         struct i40e_aqc_switch_config_element_resp *element;
1929         uint16_t start_seid = 0, num_reported;
1930         int ret;
1931
1932         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1933                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1934         if (!switch_config) {
1935                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1936                 return -ENOMEM;
1937         }
1938
1939         /* Get the switch configurations */
1940         ret = i40e_aq_get_switch_config(hw, switch_config,
1941                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1942         if (ret != I40E_SUCCESS) {
1943                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1944                 goto fail;
1945         }
1946         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1947         if (num_reported != 1) { /* The number should be 1 */
1948                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1949                 goto fail;
1950         }
1951
1952         /* Parse the switch configuration elements */
1953         element = &(switch_config->element[0]);
1954         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1955                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1956                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1957         } else
1958                 PMD_DRV_LOG(INFO, "Unknown element type");
1959
1960 fail:
1961         rte_free(switch_config);
1962
1963         return ret;
1964 }
1965
1966 static int
1967 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1968                         uint32_t num)
1969 {
1970         struct pool_entry *entry;
1971
1972         if (pool == NULL || num == 0)
1973                 return -EINVAL;
1974
1975         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1976         if (entry == NULL) {
1977                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1978                 return -ENOMEM;
1979         }
1980
1981         /* queue heap initialize */
1982         pool->num_free = num;
1983         pool->num_alloc = 0;
1984         pool->base = base;
1985         LIST_INIT(&pool->alloc_list);
1986         LIST_INIT(&pool->free_list);
1987
1988         /* Initialize element  */
1989         entry->base = 0;
1990         entry->len = num;
1991
1992         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1993         return 0;
1994 }
1995
1996 static void
1997 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1998 {
1999         struct pool_entry *entry;
2000
2001         if (pool == NULL)
2002                 return;
2003
2004         LIST_FOREACH(entry, &pool->alloc_list, next) {
2005                 LIST_REMOVE(entry, next);
2006                 rte_free(entry);
2007         }
2008
2009         LIST_FOREACH(entry, &pool->free_list, next) {
2010                 LIST_REMOVE(entry, next);
2011                 rte_free(entry);
2012         }
2013
2014         pool->num_free = 0;
2015         pool->num_alloc = 0;
2016         pool->base = 0;
2017         LIST_INIT(&pool->alloc_list);
2018         LIST_INIT(&pool->free_list);
2019 }
2020
2021 static int
2022 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2023                        uint32_t base)
2024 {
2025         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2026         uint32_t pool_offset;
2027         int insert;
2028
2029         if (pool == NULL) {
2030                 PMD_DRV_LOG(ERR, "Invalid parameter");
2031                 return -EINVAL;
2032         }
2033
2034         pool_offset = base - pool->base;
2035         /* Lookup in alloc list */
2036         LIST_FOREACH(entry, &pool->alloc_list, next) {
2037                 if (entry->base == pool_offset) {
2038                         valid_entry = entry;
2039                         LIST_REMOVE(entry, next);
2040                         break;
2041                 }
2042         }
2043
2044         /* Not find, return */
2045         if (valid_entry == NULL) {
2046                 PMD_DRV_LOG(ERR, "Failed to find entry");
2047                 return -EINVAL;
2048         }
2049
2050         /**
2051          * Found it, move it to free list  and try to merge.
2052          * In order to make merge easier, always sort it by qbase.
2053          * Find adjacent prev and last entries.
2054          */
2055         prev = next = NULL;
2056         LIST_FOREACH(entry, &pool->free_list, next) {
2057                 if (entry->base > valid_entry->base) {
2058                         next = entry;
2059                         break;
2060                 }
2061                 prev = entry;
2062         }
2063
2064         insert = 0;
2065         /* Try to merge with next one*/
2066         if (next != NULL) {
2067                 /* Merge with next one */
2068                 if (valid_entry->base + valid_entry->len == next->base) {
2069                         next->base = valid_entry->base;
2070                         next->len += valid_entry->len;
2071                         rte_free(valid_entry);
2072                         valid_entry = next;
2073                         insert = 1;
2074                 }
2075         }
2076
2077         if (prev != NULL) {
2078                 /* Merge with previous one */
2079                 if (prev->base + prev->len == valid_entry->base) {
2080                         prev->len += valid_entry->len;
2081                         /* If it merge with next one, remove next node */
2082                         if (insert == 1) {
2083                                 LIST_REMOVE(valid_entry, next);
2084                                 rte_free(valid_entry);
2085                         } else {
2086                                 rte_free(valid_entry);
2087                                 insert = 1;
2088                         }
2089                 }
2090         }
2091
2092         /* Not find any entry to merge, insert */
2093         if (insert == 0) {
2094                 if (prev != NULL)
2095                         LIST_INSERT_AFTER(prev, valid_entry, next);
2096                 else if (next != NULL)
2097                         LIST_INSERT_BEFORE(next, valid_entry, next);
2098                 else /* It's empty list, insert to head */
2099                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2100         }
2101
2102         pool->num_free += valid_entry->len;
2103         pool->num_alloc -= valid_entry->len;
2104
2105         return 0;
2106 }
2107
2108 static int
2109 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2110                        uint16_t num)
2111 {
2112         struct pool_entry *entry, *valid_entry;
2113
2114         if (pool == NULL || num == 0) {
2115                 PMD_DRV_LOG(ERR, "Invalid parameter");
2116                 return -EINVAL;
2117         }
2118
2119         if (pool->num_free < num) {
2120                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2121                             num, pool->num_free);
2122                 return -ENOMEM;
2123         }
2124
2125         valid_entry = NULL;
2126         /* Lookup  in free list and find most fit one */
2127         LIST_FOREACH(entry, &pool->free_list, next) {
2128                 if (entry->len >= num) {
2129                         /* Find best one */
2130                         if (entry->len == num) {
2131                                 valid_entry = entry;
2132                                 break;
2133                         }
2134                         if (valid_entry == NULL || valid_entry->len > entry->len)
2135                                 valid_entry = entry;
2136                 }
2137         }
2138
2139         /* Not find one to satisfy the request, return */
2140         if (valid_entry == NULL) {
2141                 PMD_DRV_LOG(ERR, "No valid entry found");
2142                 return -ENOMEM;
2143         }
2144         /**
2145          * The entry have equal queue number as requested,
2146          * remove it from alloc_list.
2147          */
2148         if (valid_entry->len == num) {
2149                 LIST_REMOVE(valid_entry, next);
2150         } else {
2151                 /**
2152                  * The entry have more numbers than requested,
2153                  * create a new entry for alloc_list and minus its
2154                  * queue base and number in free_list.
2155                  */
2156                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2157                 if (entry == NULL) {
2158                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2159                                     "resource pool");
2160                         return -ENOMEM;
2161                 }
2162                 entry->base = valid_entry->base;
2163                 entry->len = num;
2164                 valid_entry->base += num;
2165                 valid_entry->len -= num;
2166                 valid_entry = entry;
2167         }
2168
2169         /* Insert it into alloc list, not sorted */
2170         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2171
2172         pool->num_free -= valid_entry->len;
2173         pool->num_alloc += valid_entry->len;
2174
2175         return (valid_entry->base + pool->base);
2176 }
2177
2178 /**
2179  * bitmap_is_subset - Check whether src2 is subset of src1
2180  **/
2181 static inline int
2182 bitmap_is_subset(uint8_t src1, uint8_t src2)
2183 {
2184         return !((src1 ^ src2) & src2);
2185 }
2186
2187 static int
2188 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2189 {
2190         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2191
2192         /* If DCB is not supported, only default TC is supported */
2193         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2194                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2195                 return -EINVAL;
2196         }
2197
2198         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2199                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2200                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2201                             enabled_tcmap);
2202                 return -EINVAL;
2203         }
2204         return I40E_SUCCESS;
2205 }
2206
2207 int
2208 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2209                                 struct i40e_vsi_vlan_pvid_info *info)
2210 {
2211         struct i40e_hw *hw;
2212         struct i40e_vsi_context ctxt;
2213         uint8_t vlan_flags = 0;
2214         int ret;
2215
2216         if (vsi == NULL || info == NULL) {
2217                 PMD_DRV_LOG(ERR, "invalid parameters");
2218                 return I40E_ERR_PARAM;
2219         }
2220
2221         if (info->on) {
2222                 vsi->info.pvid = info->config.pvid;
2223                 /**
2224                  * If insert pvid is enabled, only tagged pkts are
2225                  * allowed to be sent out.
2226                  */
2227                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2228                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2229         } else {
2230                 vsi->info.pvid = 0;
2231                 if (info->config.reject.tagged == 0)
2232                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2233
2234                 if (info->config.reject.untagged == 0)
2235                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2236         }
2237         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2238                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2239         vsi->info.port_vlan_flags |= vlan_flags;
2240         vsi->info.valid_sections =
2241                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2242         memset(&ctxt, 0, sizeof(ctxt));
2243         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2244         ctxt.seid = vsi->seid;
2245
2246         hw = I40E_VSI_TO_HW(vsi);
2247         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2248         if (ret != I40E_SUCCESS)
2249                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2250
2251         return ret;
2252 }
2253
2254 static int
2255 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2256 {
2257         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2258         int i, ret;
2259         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2260
2261         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2262         if (ret != I40E_SUCCESS)
2263                 return ret;
2264
2265         if (!vsi->seid) {
2266                 PMD_DRV_LOG(ERR, "seid not valid");
2267                 return -EINVAL;
2268         }
2269
2270         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2271         tc_bw_data.tc_valid_bits = enabled_tcmap;
2272         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2273                 tc_bw_data.tc_bw_credits[i] =
2274                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2275
2276         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2277         if (ret != I40E_SUCCESS) {
2278                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2279                 return ret;
2280         }
2281
2282         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2283                                         sizeof(vsi->info.qs_handle));
2284         return I40E_SUCCESS;
2285 }
2286
2287 static int
2288 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2289                                  struct i40e_aqc_vsi_properties_data *info,
2290                                  uint8_t enabled_tcmap)
2291 {
2292         int ret, total_tc = 0, i;
2293         uint16_t qpnum_per_tc, bsf, qp_idx;
2294
2295         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2296         if (ret != I40E_SUCCESS)
2297                 return ret;
2298
2299         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2300                 if (enabled_tcmap & (1 << i))
2301                         total_tc++;
2302         vsi->enabled_tc = enabled_tcmap;
2303
2304         /* Number of queues per enabled TC */
2305         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2306         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2307         bsf = rte_bsf32(qpnum_per_tc);
2308
2309         /* Adjust the queue number to actual queues that can be applied */
2310         vsi->nb_qps = qpnum_per_tc * total_tc;
2311
2312         /**
2313          * Configure TC and queue mapping parameters, for enabled TC,
2314          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2315          * default queue will serve it.
2316          */
2317         qp_idx = 0;
2318         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2319                 if (vsi->enabled_tc & (1 << i)) {
2320                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2321                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2322                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2323                         qp_idx += qpnum_per_tc;
2324                 } else
2325                         info->tc_mapping[i] = 0;
2326         }
2327
2328         /* Associate queue number with VSI */
2329         if (vsi->type == I40E_VSI_SRIOV) {
2330                 info->mapping_flags |=
2331                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2332                 for (i = 0; i < vsi->nb_qps; i++)
2333                         info->queue_mapping[i] =
2334                                 rte_cpu_to_le_16(vsi->base_queue + i);
2335         } else {
2336                 info->mapping_flags |=
2337                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2338                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2339         }
2340         info->valid_sections =
2341                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2342
2343         return I40E_SUCCESS;
2344 }
2345
2346 static int
2347 i40e_veb_release(struct i40e_veb *veb)
2348 {
2349         struct i40e_vsi *vsi;
2350         struct i40e_hw *hw;
2351
2352         if (veb == NULL || veb->associate_vsi == NULL)
2353                 return -EINVAL;
2354
2355         if (!TAILQ_EMPTY(&veb->head)) {
2356                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2357                 return -EACCES;
2358         }
2359
2360         vsi = veb->associate_vsi;
2361         hw = I40E_VSI_TO_HW(vsi);
2362
2363         vsi->uplink_seid = veb->uplink_seid;
2364         i40e_aq_delete_element(hw, veb->seid, NULL);
2365         rte_free(veb);
2366         vsi->veb = NULL;
2367         return I40E_SUCCESS;
2368 }
2369
2370 /* Setup a veb */
2371 static struct i40e_veb *
2372 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2373 {
2374         struct i40e_veb *veb;
2375         int ret;
2376         struct i40e_hw *hw;
2377
2378         if (NULL == pf || vsi == NULL) {
2379                 PMD_DRV_LOG(ERR, "veb setup failed, "
2380                             "associated VSI shouldn't null");
2381                 return NULL;
2382         }
2383         hw = I40E_PF_TO_HW(pf);
2384
2385         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2386         if (!veb) {
2387                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2388                 goto fail;
2389         }
2390
2391         veb->associate_vsi = vsi;
2392         TAILQ_INIT(&veb->head);
2393         veb->uplink_seid = vsi->uplink_seid;
2394
2395         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2396                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2397
2398         if (ret != I40E_SUCCESS) {
2399                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2400                             hw->aq.asq_last_status);
2401                 goto fail;
2402         }
2403
2404         /* get statistics index */
2405         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2406                                 &veb->stats_idx, NULL, NULL, NULL);
2407         if (ret != I40E_SUCCESS) {
2408                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2409                             hw->aq.asq_last_status);
2410                 goto fail;
2411         }
2412
2413         /* Get VEB bandwidth, to be implemented */
2414         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2415         vsi->uplink_seid = veb->seid;
2416
2417         return veb;
2418 fail:
2419         rte_free(veb);
2420         return NULL;
2421 }
2422
2423 int
2424 i40e_vsi_release(struct i40e_vsi *vsi)
2425 {
2426         struct i40e_pf *pf;
2427         struct i40e_hw *hw;
2428         struct i40e_vsi_list *vsi_list;
2429         int ret;
2430         struct i40e_mac_filter *f;
2431
2432         if (!vsi)
2433                 return I40E_SUCCESS;
2434
2435         pf = I40E_VSI_TO_PF(vsi);
2436         hw = I40E_VSI_TO_HW(vsi);
2437
2438         /* VSI has child to attach, release child first */
2439         if (vsi->veb) {
2440                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2441                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2442                                 return -1;
2443                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2444                 }
2445                 i40e_veb_release(vsi->veb);
2446         }
2447
2448         /* Remove all macvlan filters of the VSI */
2449         i40e_vsi_remove_all_macvlan_filter(vsi);
2450         TAILQ_FOREACH(f, &vsi->mac_list, next)
2451                 rte_free(f);
2452
2453         if (vsi->type != I40E_VSI_MAIN) {
2454                 /* Remove vsi from parent's sibling list */
2455                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2456                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2457                         return I40E_ERR_PARAM;
2458                 }
2459                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2460                                 &vsi->sib_vsi_list, list);
2461
2462                 /* Remove all switch element of the VSI */
2463                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2464                 if (ret != I40E_SUCCESS)
2465                         PMD_DRV_LOG(ERR, "Failed to delete element");
2466         }
2467         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2468
2469         if (vsi->type != I40E_VSI_SRIOV)
2470                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2471         rte_free(vsi);
2472
2473         return I40E_SUCCESS;
2474 }
2475
2476 static int
2477 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2478 {
2479         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2480         struct i40e_aqc_remove_macvlan_element_data def_filter;
2481         int ret;
2482
2483         if (vsi->type != I40E_VSI_MAIN)
2484                 return I40E_ERR_CONFIG;
2485         memset(&def_filter, 0, sizeof(def_filter));
2486         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2487                                         ETH_ADDR_LEN);
2488         def_filter.vlan_tag = 0;
2489         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2490                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2491         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2492         if (ret != I40E_SUCCESS) {
2493                 struct i40e_mac_filter *f;
2494
2495                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2496                             "macvlan filter");
2497                 /* It needs to add the permanent mac into mac list */
2498                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2499                 if (f == NULL) {
2500                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2501                         return I40E_ERR_NO_MEMORY;
2502                 }
2503                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2504                                 ETH_ADDR_LEN);
2505                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2506                 vsi->mac_num++;
2507
2508                 return ret;
2509         }
2510
2511         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2512 }
2513
2514 static int
2515 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2516 {
2517         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2518         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2519         struct i40e_hw *hw = &vsi->adapter->hw;
2520         i40e_status ret;
2521         int i;
2522
2523         memset(&bw_config, 0, sizeof(bw_config));
2524         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2525         if (ret != I40E_SUCCESS) {
2526                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2527                             hw->aq.asq_last_status);
2528                 return ret;
2529         }
2530
2531         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2532         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2533                                         &ets_sla_config, NULL);
2534         if (ret != I40E_SUCCESS) {
2535                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2536                             "configuration %u", hw->aq.asq_last_status);
2537                 return ret;
2538         }
2539
2540         /* Not store the info yet, just print out */
2541         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2542         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2543         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2544                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2545                             ets_sla_config.share_credits[i]);
2546                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2547                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2548                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2549                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2550                             (i * 4));
2551         }
2552
2553         return 0;
2554 }
2555
2556 /* Setup a VSI */
2557 struct i40e_vsi *
2558 i40e_vsi_setup(struct i40e_pf *pf,
2559                enum i40e_vsi_type type,
2560                struct i40e_vsi *uplink_vsi,
2561                uint16_t user_param)
2562 {
2563         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2564         struct i40e_vsi *vsi;
2565         int ret;
2566         struct i40e_vsi_context ctxt;
2567         struct ether_addr broadcast =
2568                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2569
2570         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2571                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2572                             "VSI link shouldn't be NULL");
2573                 return NULL;
2574         }
2575
2576         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2577                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2578                             "uplink VSI should be NULL");
2579                 return NULL;
2580         }
2581
2582         /* If uplink vsi didn't setup VEB, create one first */
2583         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2584                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2585
2586                 if (NULL == uplink_vsi->veb) {
2587                         PMD_DRV_LOG(ERR, "VEB setup failed");
2588                         return NULL;
2589                 }
2590         }
2591
2592         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2593         if (!vsi) {
2594                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2595                 return NULL;
2596         }
2597         TAILQ_INIT(&vsi->mac_list);
2598         vsi->type = type;
2599         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2600         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2601         vsi->parent_vsi = uplink_vsi;
2602         vsi->user_param = user_param;
2603         /* Allocate queues */
2604         switch (vsi->type) {
2605         case I40E_VSI_MAIN  :
2606                 vsi->nb_qps = pf->lan_nb_qps;
2607                 break;
2608         case I40E_VSI_SRIOV :
2609                 vsi->nb_qps = pf->vf_nb_qps;
2610                 break;
2611         default:
2612                 goto fail_mem;
2613         }
2614         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2615         if (ret < 0) {
2616                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2617                                 vsi->seid, ret);
2618                 goto fail_mem;
2619         }
2620         vsi->base_queue = ret;
2621
2622         /* VF has MSIX interrupt in VF range, don't allocate here */
2623         if (type != I40E_VSI_SRIOV) {
2624                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2625                 if (ret < 0) {
2626                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2627                         goto fail_queue_alloc;
2628                 }
2629                 vsi->msix_intr = ret;
2630         } else
2631                 vsi->msix_intr = 0;
2632         /* Add VSI */
2633         if (type == I40E_VSI_MAIN) {
2634                 /* For main VSI, no need to add since it's default one */
2635                 vsi->uplink_seid = pf->mac_seid;
2636                 vsi->seid = pf->main_vsi_seid;
2637                 /* Bind queues with specific MSIX interrupt */
2638                 /**
2639                  * Needs 2 interrupt at least, one for misc cause which will
2640                  * enabled from OS side, Another for queues binding the
2641                  * interrupt from device side only.
2642                  */
2643
2644                 /* Get default VSI parameters from hardware */
2645                 memset(&ctxt, 0, sizeof(ctxt));
2646                 ctxt.seid = vsi->seid;
2647                 ctxt.pf_num = hw->pf_id;
2648                 ctxt.uplink_seid = vsi->uplink_seid;
2649                 ctxt.vf_num = 0;
2650                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2651                 if (ret != I40E_SUCCESS) {
2652                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2653                         goto fail_msix_alloc;
2654                 }
2655                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2656                         sizeof(struct i40e_aqc_vsi_properties_data));
2657                 vsi->vsi_id = ctxt.vsi_number;
2658                 vsi->info.valid_sections = 0;
2659
2660                 /* Configure tc, enabled TC0 only */
2661                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2662                         I40E_SUCCESS) {
2663                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2664                         goto fail_msix_alloc;
2665                 }
2666
2667                 /* TC, queue mapping */
2668                 memset(&ctxt, 0, sizeof(ctxt));
2669                 vsi->info.valid_sections |=
2670                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2671                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2672                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2673                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2674                         sizeof(struct i40e_aqc_vsi_properties_data));
2675                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2676                                                 I40E_DEFAULT_TCMAP);
2677                 if (ret != I40E_SUCCESS) {
2678                         PMD_DRV_LOG(ERR, "Failed to configure "
2679                                     "TC queue mapping");
2680                         goto fail_msix_alloc;
2681                 }
2682                 ctxt.seid = vsi->seid;
2683                 ctxt.pf_num = hw->pf_id;
2684                 ctxt.uplink_seid = vsi->uplink_seid;
2685                 ctxt.vf_num = 0;
2686
2687                 /* Update VSI parameters */
2688                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2689                 if (ret != I40E_SUCCESS) {
2690                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2691                         goto fail_msix_alloc;
2692                 }
2693
2694                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2695                                                 sizeof(vsi->info.tc_mapping));
2696                 (void)rte_memcpy(&vsi->info.queue_mapping,
2697                                 &ctxt.info.queue_mapping,
2698                         sizeof(vsi->info.queue_mapping));
2699                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2700                 vsi->info.valid_sections = 0;
2701
2702                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2703                                 ETH_ADDR_LEN);
2704
2705                 /**
2706                  * Updating default filter settings are necessary to prevent
2707                  * reception of tagged packets.
2708                  * Some old firmware configurations load a default macvlan
2709                  * filter which accepts both tagged and untagged packets.
2710                  * The updating is to use a normal filter instead if needed.
2711                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2712                  * The firmware with correct configurations load the default
2713                  * macvlan filter which is expected and cannot be removed.
2714                  */
2715                 i40e_update_default_filter_setting(vsi);
2716         } else if (type == I40E_VSI_SRIOV) {
2717                 memset(&ctxt, 0, sizeof(ctxt));
2718                 /**
2719                  * For other VSI, the uplink_seid equals to uplink VSI's
2720                  * uplink_seid since they share same VEB
2721                  */
2722                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2723                 ctxt.pf_num = hw->pf_id;
2724                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2725                 ctxt.uplink_seid = vsi->uplink_seid;
2726                 ctxt.connection_type = 0x1;
2727                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2728
2729                 /* Configure switch ID */
2730                 ctxt.info.valid_sections |=
2731                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2732                 ctxt.info.switch_id =
2733                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2734                 /* Configure port/vlan */
2735                 ctxt.info.valid_sections |=
2736                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2737                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2738                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2739                                                 I40E_DEFAULT_TCMAP);
2740                 if (ret != I40E_SUCCESS) {
2741                         PMD_DRV_LOG(ERR, "Failed to configure "
2742                                     "TC queue mapping");
2743                         goto fail_msix_alloc;
2744                 }
2745                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2746                 ctxt.info.valid_sections |=
2747                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2748                 /**
2749                  * Since VSI is not created yet, only configure parameter,
2750                  * will add vsi below.
2751                  */
2752         }
2753         else {
2754                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2755                 goto fail_msix_alloc;
2756         }
2757
2758         if (vsi->type != I40E_VSI_MAIN) {
2759                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2760                 if (ret) {
2761                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2762                                     hw->aq.asq_last_status);
2763                         goto fail_msix_alloc;
2764                 }
2765                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2766                 vsi->info.valid_sections = 0;
2767                 vsi->seid = ctxt.seid;
2768                 vsi->vsi_id = ctxt.vsi_number;
2769                 vsi->sib_vsi_list.vsi = vsi;
2770                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2771                                 &vsi->sib_vsi_list, list);
2772         }
2773
2774         /* MAC/VLAN configuration */
2775         ret = i40e_vsi_add_mac(vsi, &broadcast);
2776         if (ret != I40E_SUCCESS) {
2777                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2778                 goto fail_msix_alloc;
2779         }
2780
2781         /* Get VSI BW information */
2782         i40e_vsi_dump_bw_config(vsi);
2783         return vsi;
2784 fail_msix_alloc:
2785         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2786 fail_queue_alloc:
2787         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2788 fail_mem:
2789         rte_free(vsi);
2790         return NULL;
2791 }
2792
2793 /* Configure vlan stripping on or off */
2794 int
2795 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2796 {
2797         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2798         struct i40e_vsi_context ctxt;
2799         uint8_t vlan_flags;
2800         int ret = I40E_SUCCESS;
2801
2802         /* Check if it has been already on or off */
2803         if (vsi->info.valid_sections &
2804                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2805                 if (on) {
2806                         if ((vsi->info.port_vlan_flags &
2807                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2808                                 return 0; /* already on */
2809                 } else {
2810                         if ((vsi->info.port_vlan_flags &
2811                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2812                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2813                                 return 0; /* already off */
2814                 }
2815         }
2816
2817         if (on)
2818                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2819         else
2820                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2821         vsi->info.valid_sections =
2822                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2823         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2824         vsi->info.port_vlan_flags |= vlan_flags;
2825         ctxt.seid = vsi->seid;
2826         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2827         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2828         if (ret)
2829                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2830                             on ? "enable" : "disable");
2831
2832         return ret;
2833 }
2834
2835 static int
2836 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2837 {
2838         struct rte_eth_dev_data *data = dev->data;
2839         int ret;
2840
2841         /* Apply vlan offload setting */
2842         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2843
2844         /* Apply double-vlan setting, not implemented yet */
2845
2846         /* Apply pvid setting */
2847         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2848                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2849         if (ret)
2850                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2851
2852         return ret;
2853 }
2854
2855 static int
2856 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2857 {
2858         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2859
2860         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2861 }
2862
2863 static int
2864 i40e_update_flow_control(struct i40e_hw *hw)
2865 {
2866 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2867         struct i40e_link_status link_status;
2868         uint32_t rxfc = 0, txfc = 0, reg;
2869         uint8_t an_info;
2870         int ret;
2871
2872         memset(&link_status, 0, sizeof(link_status));
2873         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2874         if (ret != I40E_SUCCESS) {
2875                 PMD_DRV_LOG(ERR, "Failed to get link status information");
2876                 goto write_reg; /* Disable flow control */
2877         }
2878
2879         an_info = hw->phy.link_info.an_info;
2880         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2881                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2882                 ret = I40E_ERR_NOT_READY;
2883                 goto write_reg; /* Disable flow control */
2884         }
2885         /**
2886          * If link auto negotiation is enabled, flow control needs to
2887          * be configured according to it
2888          */
2889         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2890         case I40E_LINK_PAUSE_RXTX:
2891                 rxfc = 1;
2892                 txfc = 1;
2893                 hw->fc.current_mode = I40E_FC_FULL;
2894                 break;
2895         case I40E_AQ_LINK_PAUSE_RX:
2896                 rxfc = 1;
2897                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2898                 break;
2899         case I40E_AQ_LINK_PAUSE_TX:
2900                 txfc = 1;
2901                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2902                 break;
2903         default:
2904                 hw->fc.current_mode = I40E_FC_NONE;
2905                 break;
2906         }
2907
2908 write_reg:
2909         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2910                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2911         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2912         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2913         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2914         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2915
2916         return ret;
2917 }
2918
2919 /* PF setup */
2920 static int
2921 i40e_pf_setup(struct i40e_pf *pf)
2922 {
2923         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2924         struct i40e_filter_control_settings settings;
2925         struct rte_eth_dev_data *dev_data = pf->dev_data;
2926         struct i40e_vsi *vsi;
2927         int ret;
2928
2929         /* Clear all stats counters */
2930         pf->offset_loaded = FALSE;
2931         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2932         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2933
2934         ret = i40e_pf_get_switch_config(pf);
2935         if (ret != I40E_SUCCESS) {
2936                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2937                 return ret;
2938         }
2939
2940         /* VSI setup */
2941         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2942         if (!vsi) {
2943                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2944                 return I40E_ERR_NOT_READY;
2945         }
2946         pf->main_vsi = vsi;
2947         dev_data->nb_rx_queues = vsi->nb_qps;
2948         dev_data->nb_tx_queues = vsi->nb_qps;
2949
2950         /* Configure filter control */
2951         memset(&settings, 0, sizeof(settings));
2952         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2953         /* Enable ethtype and macvlan filters */
2954         settings.enable_ethtype = TRUE;
2955         settings.enable_macvlan = TRUE;
2956         ret = i40e_set_filter_control(hw, &settings);
2957         if (ret)
2958                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2959                                                                 ret);
2960
2961         /* Update flow control according to the auto negotiation */
2962         i40e_update_flow_control(hw);
2963
2964         return I40E_SUCCESS;
2965 }
2966
2967 int
2968 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2969 {
2970         uint32_t reg;
2971         uint16_t j;
2972
2973         /**
2974          * Set or clear TX Queue Disable flags,
2975          * which is required by hardware.
2976          */
2977         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2978         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2979
2980         /* Wait until the request is finished */
2981         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2982                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2983                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2984                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2985                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2986                                                         & 0x1))) {
2987                         break;
2988                 }
2989         }
2990         if (on) {
2991                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2992                         return I40E_SUCCESS; /* already on, skip next steps */
2993
2994                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2995                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2996         } else {
2997                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2998                         return I40E_SUCCESS; /* already off, skip next steps */
2999                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3000         }
3001         /* Write the register */
3002         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3003         /* Check the result */
3004         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3005                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3006                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3007                 if (on) {
3008                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3009                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3010                                 break;
3011                 } else {
3012                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3013                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3014                                 break;
3015                 }
3016         }
3017         /* Check if it is timeout */
3018         if (j >= I40E_CHK_Q_ENA_COUNT) {
3019                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3020                             (on ? "enable" : "disable"), q_idx);
3021                 return I40E_ERR_TIMEOUT;
3022         }
3023
3024         return I40E_SUCCESS;
3025 }
3026
3027 /* Swith on or off the tx queues */
3028 static int
3029 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3030 {
3031         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3032         struct i40e_tx_queue *txq;
3033         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3034         uint16_t i;
3035         int ret;
3036
3037         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3038                 txq = dev_data->tx_queues[i];
3039                 /* Don't operate the queue if not configured or
3040                  * if starting only per queue */
3041                 if (!txq->q_set || (on && txq->tx_deferred_start))
3042                         continue;
3043                 if (on)
3044                         ret = i40e_dev_tx_queue_start(dev, i);
3045                 else
3046                         ret = i40e_dev_tx_queue_stop(dev, i);
3047                 if ( ret != I40E_SUCCESS)
3048                         return ret;
3049         }
3050
3051         return I40E_SUCCESS;
3052 }
3053
3054 int
3055 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3056 {
3057         uint32_t reg;
3058         uint16_t j;
3059
3060         /* Wait until the request is finished */
3061         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3062                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3063                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3064                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3065                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3066                         break;
3067         }
3068
3069         if (on) {
3070                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3071                         return I40E_SUCCESS; /* Already on, skip next steps */
3072                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3073         } else {
3074                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3075                         return I40E_SUCCESS; /* Already off, skip next steps */
3076                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3077         }
3078
3079         /* Write the register */
3080         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3081         /* Check the result */
3082         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3083                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3084                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3085                 if (on) {
3086                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3087                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3088                                 break;
3089                 } else {
3090                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3091                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3092                                 break;
3093                 }
3094         }
3095
3096         /* Check if it is timeout */
3097         if (j >= I40E_CHK_Q_ENA_COUNT) {
3098                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3099                             (on ? "enable" : "disable"), q_idx);
3100                 return I40E_ERR_TIMEOUT;
3101         }
3102
3103         return I40E_SUCCESS;
3104 }
3105 /* Switch on or off the rx queues */
3106 static int
3107 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3108 {
3109         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3110         struct i40e_rx_queue *rxq;
3111         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3112         uint16_t i;
3113         int ret;
3114
3115         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3116                 rxq = dev_data->rx_queues[i];
3117                 /* Don't operate the queue if not configured or
3118                  * if starting only per queue */
3119                 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3120                         continue;
3121                 if (on)
3122                         ret = i40e_dev_rx_queue_start(dev, i);
3123                 else
3124                         ret = i40e_dev_rx_queue_stop(dev, i);
3125                 if (ret != I40E_SUCCESS)
3126                         return ret;
3127         }
3128
3129         return I40E_SUCCESS;
3130 }
3131
3132 /* Switch on or off all the rx/tx queues */
3133 int
3134 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3135 {
3136         int ret;
3137
3138         if (on) {
3139                 /* enable rx queues before enabling tx queues */
3140                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3141                 if (ret) {
3142                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3143                         return ret;
3144                 }
3145                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3146         } else {
3147                 /* Stop tx queues before stopping rx queues */
3148                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3149                 if (ret) {
3150                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3151                         return ret;
3152                 }
3153                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3154         }
3155
3156         return ret;
3157 }
3158
3159 /* Initialize VSI for TX */
3160 static int
3161 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3162 {
3163         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3164         struct rte_eth_dev_data *data = pf->dev_data;
3165         uint16_t i;
3166         uint32_t ret = I40E_SUCCESS;
3167
3168         for (i = 0; i < data->nb_tx_queues; i++) {
3169                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3170                 if (ret != I40E_SUCCESS)
3171                         break;
3172         }
3173
3174         return ret;
3175 }
3176
3177 /* Initialize VSI for RX */
3178 static int
3179 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3180 {
3181         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3182         struct rte_eth_dev_data *data = pf->dev_data;
3183         int ret = I40E_SUCCESS;
3184         uint16_t i;
3185
3186         i40e_pf_config_mq_rx(pf);
3187         for (i = 0; i < data->nb_rx_queues; i++) {
3188                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3189                 if (ret != I40E_SUCCESS) {
3190                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3191                                     "initialization");
3192                         break;
3193                 }
3194         }
3195
3196         return ret;
3197 }
3198
3199 /* Initialize VSI */
3200 static int
3201 i40e_vsi_init(struct i40e_vsi *vsi)
3202 {
3203         int err;
3204
3205         err = i40e_vsi_tx_init(vsi);
3206         if (err) {
3207                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3208                 return err;
3209         }
3210         err = i40e_vsi_rx_init(vsi);
3211         if (err) {
3212                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3213                 return err;
3214         }
3215
3216         return err;
3217 }
3218
3219 static void
3220 i40e_stat_update_32(struct i40e_hw *hw,
3221                    uint32_t reg,
3222                    bool offset_loaded,
3223                    uint64_t *offset,
3224                    uint64_t *stat)
3225 {
3226         uint64_t new_data;
3227
3228         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3229         if (!offset_loaded)
3230                 *offset = new_data;
3231
3232         if (new_data >= *offset)
3233                 *stat = (uint64_t)(new_data - *offset);
3234         else
3235                 *stat = (uint64_t)((new_data +
3236                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3237 }
3238
3239 static void
3240 i40e_stat_update_48(struct i40e_hw *hw,
3241                    uint32_t hireg,
3242                    uint32_t loreg,
3243                    bool offset_loaded,
3244                    uint64_t *offset,
3245                    uint64_t *stat)
3246 {
3247         uint64_t new_data;
3248
3249         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3250         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3251                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3252
3253         if (!offset_loaded)
3254                 *offset = new_data;
3255
3256         if (new_data >= *offset)
3257                 *stat = new_data - *offset;
3258         else
3259                 *stat = (uint64_t)((new_data +
3260                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3261
3262         *stat &= I40E_48_BIT_MASK;
3263 }
3264
3265 /* Disable IRQ0 */
3266 void
3267 i40e_pf_disable_irq0(struct i40e_hw *hw)
3268 {
3269         /* Disable all interrupt types */
3270         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3271         I40E_WRITE_FLUSH(hw);
3272 }
3273
3274 /* Enable IRQ0 */
3275 void
3276 i40e_pf_enable_irq0(struct i40e_hw *hw)
3277 {
3278         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3279                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3280                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3281                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3282         I40E_WRITE_FLUSH(hw);
3283 }
3284
3285 static void
3286 i40e_pf_config_irq0(struct i40e_hw *hw)
3287 {
3288         uint32_t enable;
3289
3290         /* read pending request and disable first */
3291         i40e_pf_disable_irq0(hw);
3292         /**
3293          * Enable all interrupt error options to detect possible errors,
3294          * other informative int are ignored
3295          */
3296         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3297                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3298                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3299                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3300                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3301                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3302                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3303                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3304
3305         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3306         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3307                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3308
3309         /* Link no queues with irq0 */
3310         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3311                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3312 }
3313
3314 static void
3315 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3316 {
3317         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319         int i;
3320         uint16_t abs_vf_id;
3321         uint32_t index, offset, val;
3322
3323         if (!pf->vfs)
3324                 return;
3325         /**
3326          * Try to find which VF trigger a reset, use absolute VF id to access
3327          * since the reg is global register.
3328          */
3329         for (i = 0; i < pf->vf_num; i++) {
3330                 abs_vf_id = hw->func_caps.vf_base_id + i;
3331                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3332                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3333                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3334                 /* VFR event occured */
3335                 if (val & (0x1 << offset)) {
3336                         int ret;
3337
3338                         /* Clear the event first */
3339                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3340                                                         (0x1 << offset));
3341                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3342                         /**
3343                          * Only notify a VF reset event occured,
3344                          * don't trigger another SW reset
3345                          */
3346                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3347                         if (ret != I40E_SUCCESS)
3348                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3349                 }
3350         }
3351 }
3352
3353 static void
3354 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3355 {
3356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357         struct i40e_arq_event_info info;
3358         uint16_t pending, opcode;
3359         int ret;
3360
3361         info.buf_len = I40E_AQ_BUF_SZ;
3362         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3363         if (!info.msg_buf) {
3364                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3365                 return;
3366         }
3367
3368         pending = 1;
3369         while (pending) {
3370                 ret = i40e_clean_arq_element(hw, &info, &pending);
3371
3372                 if (ret != I40E_SUCCESS) {
3373                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3374                                     "aq_err: %u", hw->aq.asq_last_status);
3375                         break;
3376                 }
3377                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3378
3379                 switch (opcode) {
3380                 case i40e_aqc_opc_send_msg_to_pf:
3381                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3382                         i40e_pf_host_handle_vf_msg(dev,
3383                                         rte_le_to_cpu_16(info.desc.retval),
3384                                         rte_le_to_cpu_32(info.desc.cookie_high),
3385                                         rte_le_to_cpu_32(info.desc.cookie_low),
3386                                         info.msg_buf,
3387                                         info.msg_len);
3388                         break;
3389                 default:
3390                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3391                                     opcode);
3392                         break;
3393                 }
3394         }
3395         rte_free(info.msg_buf);
3396 }
3397
3398 /**
3399  * Interrupt handler triggered by NIC  for handling
3400  * specific interrupt.
3401  *
3402  * @param handle
3403  *  Pointer to interrupt handle.
3404  * @param param
3405  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3406  *
3407  * @return
3408  *  void
3409  */
3410 static void
3411 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3412                            void *param)
3413 {
3414         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3416         uint32_t cause, enable;
3417
3418         i40e_pf_disable_irq0(hw);
3419
3420         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3421         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3422
3423         /* Shared IRQ case, return */
3424         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3425                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3426                             "no INT event to process", hw->pf_id);
3427                 goto done;
3428         }
3429
3430         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3431                 PMD_DRV_LOG(INFO, "INT:Link status changed");
3432                 i40e_dev_link_update(dev, 0);
3433         }
3434
3435         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3436                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3437
3438         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3439                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3440
3441         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3442                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3443
3444         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3445                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3446
3447         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3448                 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3449
3450         /* Add processing func to deal with VF reset vent */
3451         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3452                 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3453                 i40e_dev_handle_vfr_event(dev);
3454         }
3455         /* Find admin queue event */
3456         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3457                 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3458                 i40e_dev_handle_aq_msg(dev);
3459         }
3460
3461 done:
3462         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3463         /* Re-enable interrupt from device side */
3464         i40e_pf_enable_irq0(hw);
3465         /* Re-enable interrupt from host side */
3466         rte_intr_enable(&(dev->pci_dev->intr_handle));
3467 }
3468
3469 static int
3470 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3471                          struct i40e_macvlan_filter *filter,
3472                          int total)
3473 {
3474         int ele_num, ele_buff_size;
3475         int num, actual_num, i;
3476         int ret = I40E_SUCCESS;
3477         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3478         struct i40e_aqc_add_macvlan_element_data *req_list;
3479
3480         if (filter == NULL  || total == 0)
3481                 return I40E_ERR_PARAM;
3482         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3483         ele_buff_size = hw->aq.asq_buf_size;
3484
3485         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3486         if (req_list == NULL) {
3487                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3488                 return I40E_ERR_NO_MEMORY;
3489         }
3490
3491         num = 0;
3492         do {
3493                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3494                 memset(req_list, 0, ele_buff_size);
3495
3496                 for (i = 0; i < actual_num; i++) {
3497                         (void)rte_memcpy(req_list[i].mac_addr,
3498                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3499                         req_list[i].vlan_tag =
3500                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3501                         req_list[i].flags = rte_cpu_to_le_16(\
3502                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3503                         req_list[i].queue_number = 0;
3504                 }
3505
3506                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3507                                                 actual_num, NULL);
3508                 if (ret != I40E_SUCCESS) {
3509                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3510                         goto DONE;
3511                 }
3512                 num += actual_num;
3513         } while (num < total);
3514
3515 DONE:
3516         rte_free(req_list);
3517         return ret;
3518 }
3519
3520 static int
3521 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3522                             struct i40e_macvlan_filter *filter,
3523                             int total)
3524 {
3525         int ele_num, ele_buff_size;
3526         int num, actual_num, i;
3527         int ret = I40E_SUCCESS;
3528         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3529         struct i40e_aqc_remove_macvlan_element_data *req_list;
3530
3531         if (filter == NULL  || total == 0)
3532                 return I40E_ERR_PARAM;
3533
3534         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3535         ele_buff_size = hw->aq.asq_buf_size;
3536
3537         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3538         if (req_list == NULL) {
3539                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3540                 return I40E_ERR_NO_MEMORY;
3541         }
3542
3543         num = 0;
3544         do {
3545                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3546                 memset(req_list, 0, ele_buff_size);
3547
3548                 for (i = 0; i < actual_num; i++) {
3549                         (void)rte_memcpy(req_list[i].mac_addr,
3550                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3551                         req_list[i].vlan_tag =
3552                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3553                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3554                 }
3555
3556                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3557                                                 actual_num, NULL);
3558                 if (ret != I40E_SUCCESS) {
3559                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3560                         goto DONE;
3561                 }
3562                 num += actual_num;
3563         } while (num < total);
3564
3565 DONE:
3566         rte_free(req_list);
3567         return ret;
3568 }
3569
3570 /* Find out specific MAC filter */
3571 static struct i40e_mac_filter *
3572 i40e_find_mac_filter(struct i40e_vsi *vsi,
3573                          struct ether_addr *macaddr)
3574 {
3575         struct i40e_mac_filter *f;
3576
3577         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3578                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3579                         return f;
3580         }
3581
3582         return NULL;
3583 }
3584
3585 static bool
3586 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3587                          uint16_t vlan_id)
3588 {
3589         uint32_t vid_idx, vid_bit;
3590
3591         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3592         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3593
3594         if (vsi->vfta[vid_idx] & vid_bit)
3595                 return 1;
3596         else
3597                 return 0;
3598 }
3599
3600 static void
3601 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3602                          uint16_t vlan_id, bool on)
3603 {
3604         uint32_t vid_idx, vid_bit;
3605
3606 #define UINT32_BIT_MASK      0x1F
3607 #define VALID_VLAN_BIT_MASK  0xFFF
3608         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3609          *  element first, then find the bits it belongs to
3610          */
3611         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3612                   sizeof(uint32_t));
3613         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3614
3615         if (on)
3616                 vsi->vfta[vid_idx] |= vid_bit;
3617         else
3618                 vsi->vfta[vid_idx] &= ~vid_bit;
3619 }
3620
3621 /**
3622  * Find all vlan options for specific mac addr,
3623  * return with actual vlan found.
3624  */
3625 static inline int
3626 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3627                            struct i40e_macvlan_filter *mv_f,
3628                            int num, struct ether_addr *addr)
3629 {
3630         int i;
3631         uint32_t j, k;
3632
3633         /**
3634          * Not to use i40e_find_vlan_filter to decrease the loop time,
3635          * although the code looks complex.
3636           */
3637         if (num < vsi->vlan_num)
3638                 return I40E_ERR_PARAM;
3639
3640         i = 0;
3641         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3642                 if (vsi->vfta[j]) {
3643                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3644                                 if (vsi->vfta[j] & (1 << k)) {
3645                                         if (i > num - 1) {
3646                                                 PMD_DRV_LOG(ERR, "vlan number "
3647                                                             "not match");
3648                                                 return I40E_ERR_PARAM;
3649                                         }
3650                                         (void)rte_memcpy(&mv_f[i].macaddr,
3651                                                         addr, ETH_ADDR_LEN);
3652                                         mv_f[i].vlan_id =
3653                                                 j * I40E_UINT32_BIT_SIZE + k;
3654                                         i++;
3655                                 }
3656                         }
3657                 }
3658         }
3659         return I40E_SUCCESS;
3660 }
3661
3662 static inline int
3663 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3664                            struct i40e_macvlan_filter *mv_f,
3665                            int num,
3666                            uint16_t vlan)
3667 {
3668         int i = 0;
3669         struct i40e_mac_filter *f;
3670
3671         if (num < vsi->mac_num)
3672                 return I40E_ERR_PARAM;
3673
3674         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3675                 if (i > num - 1) {
3676                         PMD_DRV_LOG(ERR, "buffer number not match");
3677                         return I40E_ERR_PARAM;
3678                 }
3679                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3680                 mv_f[i].vlan_id = vlan;
3681                 i++;
3682         }
3683
3684         return I40E_SUCCESS;
3685 }
3686
3687 static int
3688 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3689 {
3690         int i, num;
3691         struct i40e_mac_filter *f;
3692         struct i40e_macvlan_filter *mv_f;
3693         int ret = I40E_SUCCESS;
3694
3695         if (vsi == NULL || vsi->mac_num == 0)
3696                 return I40E_ERR_PARAM;
3697
3698         /* Case that no vlan is set */
3699         if (vsi->vlan_num == 0)
3700                 num = vsi->mac_num;
3701         else
3702                 num = vsi->mac_num * vsi->vlan_num;
3703
3704         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3705         if (mv_f == NULL) {
3706                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3707                 return I40E_ERR_NO_MEMORY;
3708         }
3709
3710         i = 0;
3711         if (vsi->vlan_num == 0) {
3712                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3713                         (void)rte_memcpy(&mv_f[i].macaddr,
3714                                 &f->macaddr, ETH_ADDR_LEN);
3715                         mv_f[i].vlan_id = 0;
3716                         i++;
3717                 }
3718         } else {
3719                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3720                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3721                                         vsi->vlan_num, &f->macaddr);
3722                         if (ret != I40E_SUCCESS)
3723                                 goto DONE;
3724                         i += vsi->vlan_num;
3725                 }
3726         }
3727
3728         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3729 DONE:
3730         rte_free(mv_f);
3731
3732         return ret;
3733 }
3734
3735 int
3736 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3737 {
3738         struct i40e_macvlan_filter *mv_f;
3739         int mac_num;
3740         int ret = I40E_SUCCESS;
3741
3742         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3743                 return I40E_ERR_PARAM;
3744
3745         /* If it's already set, just return */
3746         if (i40e_find_vlan_filter(vsi,vlan))
3747                 return I40E_SUCCESS;
3748
3749         mac_num = vsi->mac_num;
3750
3751         if (mac_num == 0) {
3752                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3753                 return I40E_ERR_PARAM;
3754         }
3755
3756         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3757
3758         if (mv_f == NULL) {
3759                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3760                 return I40E_ERR_NO_MEMORY;
3761         }
3762
3763         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3764
3765         if (ret != I40E_SUCCESS)
3766                 goto DONE;
3767
3768         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3769
3770         if (ret != I40E_SUCCESS)
3771                 goto DONE;
3772
3773         i40e_set_vlan_filter(vsi, vlan, 1);
3774
3775         vsi->vlan_num++;
3776         ret = I40E_SUCCESS;
3777 DONE:
3778         rte_free(mv_f);
3779         return ret;
3780 }
3781
3782 int
3783 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3784 {
3785         struct i40e_macvlan_filter *mv_f;
3786         int mac_num;
3787         int ret = I40E_SUCCESS;
3788
3789         /**
3790          * Vlan 0 is the generic filter for untagged packets
3791          * and can't be removed.
3792          */
3793         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3794                 return I40E_ERR_PARAM;
3795
3796         /* If can't find it, just return */
3797         if (!i40e_find_vlan_filter(vsi, vlan))
3798                 return I40E_ERR_PARAM;
3799
3800         mac_num = vsi->mac_num;
3801
3802         if (mac_num == 0) {
3803                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3804                 return I40E_ERR_PARAM;
3805         }
3806
3807         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3808
3809         if (mv_f == NULL) {
3810                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3811                 return I40E_ERR_NO_MEMORY;
3812         }
3813
3814         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3815
3816         if (ret != I40E_SUCCESS)
3817                 goto DONE;
3818
3819         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3820
3821         if (ret != I40E_SUCCESS)
3822                 goto DONE;
3823
3824         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3825         if (vsi->vlan_num == 1) {
3826                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3827                 if (ret != I40E_SUCCESS)
3828                         goto DONE;
3829
3830                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3831                 if (ret != I40E_SUCCESS)
3832                         goto DONE;
3833         }
3834
3835         i40e_set_vlan_filter(vsi, vlan, 0);
3836
3837         vsi->vlan_num--;
3838         ret = I40E_SUCCESS;
3839 DONE:
3840         rte_free(mv_f);
3841         return ret;
3842 }
3843
3844 int
3845 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3846 {
3847         struct i40e_mac_filter *f;
3848         struct i40e_macvlan_filter *mv_f;
3849         int vlan_num;
3850         int ret = I40E_SUCCESS;
3851
3852         /* If it's add and we've config it, return */
3853         f = i40e_find_mac_filter(vsi, addr);
3854         if (f != NULL)
3855                 return I40E_SUCCESS;
3856
3857         /**
3858          * If vlan_num is 0, that's the first time to add mac,
3859          * set mask for vlan_id 0.
3860          */
3861         if (vsi->vlan_num == 0) {
3862                 i40e_set_vlan_filter(vsi, 0, 1);
3863                 vsi->vlan_num = 1;
3864         }
3865
3866         vlan_num = vsi->vlan_num;
3867
3868         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3869         if (mv_f == NULL) {
3870                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3871                 return I40E_ERR_NO_MEMORY;
3872         }
3873
3874         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3875         if (ret != I40E_SUCCESS)
3876                 goto DONE;
3877
3878         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3879         if (ret != I40E_SUCCESS)
3880                 goto DONE;
3881
3882         /* Add the mac addr into mac list */
3883         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3884         if (f == NULL) {
3885                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3886                 ret = I40E_ERR_NO_MEMORY;
3887                 goto DONE;
3888         }
3889         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3890         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3891         vsi->mac_num++;
3892
3893         ret = I40E_SUCCESS;
3894 DONE:
3895         rte_free(mv_f);
3896
3897         return ret;
3898 }
3899
3900 int
3901 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3902 {
3903         struct i40e_mac_filter *f;
3904         struct i40e_macvlan_filter *mv_f;
3905         int vlan_num;
3906         int ret = I40E_SUCCESS;
3907
3908         /* Can't find it, return an error */
3909         f = i40e_find_mac_filter(vsi, addr);
3910         if (f == NULL)
3911                 return I40E_ERR_PARAM;
3912
3913         vlan_num = vsi->vlan_num;
3914         if (vlan_num == 0) {
3915                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
3916                 return I40E_ERR_PARAM;
3917         }
3918         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3919         if (mv_f == NULL) {
3920                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3921                 return I40E_ERR_NO_MEMORY;
3922         }
3923
3924         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3925         if (ret != I40E_SUCCESS)
3926                 goto DONE;
3927
3928         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3929         if (ret != I40E_SUCCESS)
3930                 goto DONE;
3931
3932         /* Remove the mac addr into mac list */
3933         TAILQ_REMOVE(&vsi->mac_list, f, next);
3934         rte_free(f);
3935         vsi->mac_num--;
3936
3937         ret = I40E_SUCCESS;
3938 DONE:
3939         rte_free(mv_f);
3940         return ret;
3941 }
3942
3943 /* Configure hash enable flags for RSS */
3944 uint64_t
3945 i40e_config_hena(uint64_t flags)
3946 {
3947         uint64_t hena = 0;
3948
3949         if (!flags)
3950                 return hena;
3951
3952         if (flags & ETH_RSS_NONF_IPV4_UDP)
3953                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3954         if (flags & ETH_RSS_NONF_IPV4_TCP)
3955                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3956         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3957                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3958         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3959                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3960         if (flags & ETH_RSS_FRAG_IPV4)
3961                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3962         if (flags & ETH_RSS_NONF_IPV6_UDP)
3963                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3964         if (flags & ETH_RSS_NONF_IPV6_TCP)
3965                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3966         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3967                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3968         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3969                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3970         if (flags & ETH_RSS_FRAG_IPV6)
3971                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3972         if (flags & ETH_RSS_L2_PAYLOAD)
3973                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3974
3975         return hena;
3976 }
3977
3978 /* Parse the hash enable flags */
3979 uint64_t
3980 i40e_parse_hena(uint64_t flags)
3981 {
3982         uint64_t rss_hf = 0;
3983
3984         if (!flags)
3985                 return rss_hf;
3986
3987         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3988                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3989         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3990                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3991         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3992                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3993         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3994                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3995         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3996                 rss_hf |= ETH_RSS_FRAG_IPV4;
3997         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3998                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3999         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4000                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4001         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4002                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4003         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4004                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4005         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4006                 rss_hf |= ETH_RSS_FRAG_IPV6;
4007         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4008                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4009
4010         return rss_hf;
4011 }
4012
4013 /* Disable RSS */
4014 static void
4015 i40e_pf_disable_rss(struct i40e_pf *pf)
4016 {
4017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4018         uint64_t hena;
4019
4020         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4021         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4022         hena &= ~I40E_RSS_HENA_ALL;
4023         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4024         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4025         I40E_WRITE_FLUSH(hw);
4026 }
4027
4028 static int
4029 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4030 {
4031         uint32_t *hash_key;
4032         uint8_t hash_key_len;
4033         uint64_t rss_hf;
4034         uint16_t i;
4035         uint64_t hena;
4036
4037         hash_key = (uint32_t *)(rss_conf->rss_key);
4038         hash_key_len = rss_conf->rss_key_len;
4039         if (hash_key != NULL && hash_key_len >=
4040                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4041                 /* Fill in RSS hash key */
4042                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4043                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4044         }
4045
4046         rss_hf = rss_conf->rss_hf;
4047         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4048         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4049         hena &= ~I40E_RSS_HENA_ALL;
4050         hena |= i40e_config_hena(rss_hf);
4051         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4052         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4053         I40E_WRITE_FLUSH(hw);
4054
4055         return 0;
4056 }
4057
4058 static int
4059 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4060                          struct rte_eth_rss_conf *rss_conf)
4061 {
4062         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4064         uint64_t hena;
4065
4066         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4067         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4068         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4069                 if (rss_hf != 0) /* Enable RSS */
4070                         return -EINVAL;
4071                 return 0; /* Nothing to do */
4072         }
4073         /* RSS enabled */
4074         if (rss_hf == 0) /* Disable RSS */
4075                 return -EINVAL;
4076
4077         return i40e_hw_rss_hash_set(hw, rss_conf);
4078 }
4079
4080 static int
4081 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4082                            struct rte_eth_rss_conf *rss_conf)
4083 {
4084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4086         uint64_t hena;
4087         uint16_t i;
4088
4089         if (hash_key != NULL) {
4090                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4091                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4092                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4093         }
4094         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4095         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4096         rss_conf->rss_hf = i40e_parse_hena(hena);
4097
4098         return 0;
4099 }
4100
4101 static int
4102 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4103 {
4104         uint8_t i;
4105
4106         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4107                 if (pf->vxlan_ports[i] == port)
4108                         return i;
4109         }
4110
4111         return -1;
4112 }
4113
4114 static int
4115 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4116 {
4117         int  idx, ret;
4118         uint8_t filter_idx;
4119         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4120
4121         idx = i40e_get_vxlan_port_idx(pf, port);
4122
4123         /* Check if port already exists */
4124         if (idx >= 0) {
4125                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4126                 return -EINVAL;
4127         }
4128
4129         /* Now check if there is space to add the new port */
4130         idx = i40e_get_vxlan_port_idx(pf, 0);
4131         if (idx < 0) {
4132                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4133                         "not adding port %d", port);
4134                 return -ENOSPC;
4135         }
4136
4137         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4138                                         &filter_idx, NULL);
4139         if (ret < 0) {
4140                 PMD_DRV_LOG(ERR, "Failed to add VxLAN UDP port %d", port);
4141                 return -1;
4142         }
4143
4144         PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4145                          port,  filter_index);
4146
4147         /* New port: add it and mark its index in the bitmap */
4148         pf->vxlan_ports[idx] = port;
4149         pf->vxlan_bitmap |= (1 << idx);
4150
4151         if (!(pf->flags & I40E_FLAG_VXLAN))
4152                 pf->flags |= I40E_FLAG_VXLAN;
4153
4154         return 0;
4155 }
4156
4157 static int
4158 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4159 {
4160         int idx;
4161         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4162
4163         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4164                 PMD_DRV_LOG(ERR, "VxLAN UDP port was not configured.");
4165                 return -EINVAL;
4166         }
4167
4168         idx = i40e_get_vxlan_port_idx(pf, port);
4169
4170         if (idx < 0) {
4171                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4172                 return -EINVAL;
4173         }
4174
4175         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4176                 PMD_DRV_LOG(ERR, "Failed to delete VxLAN UDP port %d", port);
4177                 return -1;
4178         }
4179
4180         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4181                         port, idx);
4182
4183         pf->vxlan_ports[idx] = 0;
4184         pf->vxlan_bitmap &= ~(1 << idx);
4185
4186         if (!pf->vxlan_bitmap)
4187                 pf->flags &= ~I40E_FLAG_VXLAN;
4188
4189         return 0;
4190 }
4191
4192 /* Add UDP tunneling port */
4193 static int
4194 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4195                         struct rte_eth_udp_tunnel *udp_tunnel)
4196 {
4197         int ret = 0;
4198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4199
4200         if (udp_tunnel == NULL)
4201                 return -EINVAL;
4202
4203         switch (udp_tunnel->prot_type) {
4204         case RTE_TUNNEL_TYPE_VXLAN:
4205                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4206                 break;
4207
4208         case RTE_TUNNEL_TYPE_GENEVE:
4209         case RTE_TUNNEL_TYPE_TEREDO:
4210                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4211                 ret = -1;
4212                 break;
4213
4214         default:
4215                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4216                 ret = -1;
4217                 break;
4218         }
4219
4220         return ret;
4221 }
4222
4223 /* Remove UDP tunneling port */
4224 static int
4225 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4226                         struct rte_eth_udp_tunnel *udp_tunnel)
4227 {
4228         int ret = 0;
4229         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4230
4231         if (udp_tunnel == NULL)
4232                 return -EINVAL;
4233
4234         switch (udp_tunnel->prot_type) {
4235         case RTE_TUNNEL_TYPE_VXLAN:
4236                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4237                 break;
4238         case RTE_TUNNEL_TYPE_GENEVE:
4239         case RTE_TUNNEL_TYPE_TEREDO:
4240                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4241                 ret = -1;
4242                 break;
4243         default:
4244                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4245                 ret = -1;
4246                 break;
4247         }
4248
4249         return ret;
4250 }
4251
4252 /* Configure RSS */
4253 static int
4254 i40e_pf_config_rss(struct i40e_pf *pf)
4255 {
4256         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4257         struct rte_eth_rss_conf rss_conf;
4258         uint32_t i, lut = 0;
4259         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4260
4261         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4262                 if (j == num)
4263                         j = 0;
4264                 lut = (lut << 8) | (j & ((0x1 <<
4265                         hw->func_caps.rss_table_entry_width) - 1));
4266                 if ((i & 3) == 3)
4267                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4268         }
4269
4270         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4271         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4272                 i40e_pf_disable_rss(pf);
4273                 return 0;
4274         }
4275         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4276                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4277                 /* Calculate the default hash key */
4278                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4279                         rss_key_default[i] = (uint32_t)rte_rand();
4280                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4281                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4282                                                         sizeof(uint32_t);
4283         }
4284
4285         return i40e_hw_rss_hash_set(hw, &rss_conf);
4286 }
4287
4288 static int
4289 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4290 {
4291         if (!pf->dev_data->sriov.active) {
4292                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4293                 case ETH_MQ_RX_RSS:
4294                         i40e_pf_config_rss(pf);
4295                         break;
4296                 default:
4297                         i40e_pf_disable_rss(pf);
4298                         break;
4299                 }
4300         }
4301
4302         return 0;
4303 }
4304
4305 static int
4306 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4307                      enum rte_filter_type filter_type,
4308                      enum rte_filter_op filter_op,
4309                      void *arg)
4310 {
4311         int ret = 0;
4312         (void)filter_op;
4313         (void)arg;
4314
4315         if (dev == NULL)
4316                 return -EINVAL;
4317
4318         switch (filter_type) {
4319         default:
4320                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4321                                                         filter_type);
4322                 ret = -EINVAL;
4323                 break;
4324         }
4325
4326         return ret;
4327 }