lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_register_x710_int.h"
  54 #include "i40e/i40e_prototype.h"
  55 #include "i40e/i40e_adminq_cmd.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59 #include "i40e_pf.h"
  60
  61 /* Maximun number of MAC addresses */
  62 #define I40E_NUM_MACADDR_MAX       64
  63 #define I40E_CLEAR_PXE_WAIT_MS     200
  64
  65 /* Maximun number of capability elements */
  66 #define I40E_MAX_CAP_ELE_NUM       128
  67
  68 /* Wait count and inteval */
  69 #define I40E_CHK_Q_ENA_COUNT       1000
  70 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  71
  72 /* Maximun number of VSI */
  73 #define I40E_MAX_NUM_VSIS          (384UL)
  74
  75 /* Bit shift and mask */
  76 #define I40E_16_BIT_SHIFT 16
  77 #define I40E_16_BIT_MASK  0xFFFF
  78 #define I40E_32_BIT_SHIFT 32
  79 #define I40E_32_BIT_MASK  0xFFFFFFFF
  80 #define I40E_48_BIT_SHIFT 48
  81 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  82
  83 /* Default queue interrupt throttling time in microseconds*/
  84 #define I40E_ITR_INDEX_DEFAULT          0
  85 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  86 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  87
  88 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  89
  90 #define I40E_RSS_OFFLOAD_ALL ( \
  91         ETH_RSS_NONF_IPV4_UDP | \
  92         ETH_RSS_NONF_IPV4_TCP | \
  93         ETH_RSS_NONF_IPV4_SCTP | \
  94         ETH_RSS_NONF_IPV4_OTHER | \
  95         ETH_RSS_FRAG_IPV4 | \
  96         ETH_RSS_NONF_IPV6_UDP | \
  97         ETH_RSS_NONF_IPV6_TCP | \
  98         ETH_RSS_NONF_IPV6_SCTP | \
  99         ETH_RSS_NONF_IPV6_OTHER | \
 100         ETH_RSS_FRAG_IPV6 | \
 101         ETH_RSS_L2_PAYLOAD)
 102
 103 /* All bits of RSS hash enable */
 104 #define I40E_RSS_HENA_ALL ( \
 105         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
 106         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
 107         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
 108         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
 109         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
 110         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
 111         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
 112         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
 113         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
 114         (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
 115         (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
 116         (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
 117         (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
 118         (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
 119
 120 static int eth_i40e_dev_init(\
 121                         __attribute__((unused)) struct eth_driver *eth_drv,
 122                         struct rte_eth_dev *eth_dev);
 123 static int i40e_dev_configure(struct rte_eth_dev *dev);
 124 static int i40e_dev_start(struct rte_eth_dev *dev);
 125 static void i40e_dev_stop(struct rte_eth_dev *dev);
 126 static void i40e_dev_close(struct rte_eth_dev *dev);
 127 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 128 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 129 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 130 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 131 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 132                                struct rte_eth_stats *stats);
 133 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 134 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 135                                             uint16_t queue_id,
 136                                             uint8_t stat_idx,
 137                                             uint8_t is_rx);
 138 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 139                               struct rte_eth_dev_info *dev_info);
 140 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 141                                 uint16_t vlan_id,
 142                                 int on);
 143 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 144 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 145 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 146                                       uint16_t queue,
 147                                       int on);
 148 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 149 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 150 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 151 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 152                               struct rte_eth_fc_conf *fc_conf);
 153 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 154                                        struct rte_eth_pfc_conf *pfc_conf);
 155 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 156                           struct ether_addr *mac_addr,
 157                           uint32_t index,
 158                           uint32_t pool);
 159 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 160 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 161                                     struct rte_eth_rss_reta *reta_conf);
 162 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 163                                    struct rte_eth_rss_reta *reta_conf);
 164
 165 static int i40e_get_cap(struct i40e_hw *hw);
 166 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 167 static int i40e_pf_setup(struct i40e_pf *pf);
 168 static int i40e_vsi_init(struct i40e_vsi *vsi);
 169 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 170                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 171 static void i40e_stat_update_48(struct i40e_hw *hw,
 172                                uint32_t hireg,
 173                                uint32_t loreg,
 174                                bool offset_loaded,
 175                                uint64_t *offset,
 176                                uint64_t *stat);
 177 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 178 static void i40e_dev_interrupt_handler(
 179                 __rte_unused struct rte_intr_handle *handle, void *param);
 180 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 181                                 uint32_t base, uint32_t num);
 182 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 183 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 184                         uint32_t base);
 185 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 186                         uint16_t num);
 187 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 188 static int i40e_veb_release(struct i40e_veb *veb);
 189 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 190                                                 struct i40e_vsi *vsi);
 191 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 192 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 194                                              struct i40e_macvlan_filter *mv_f,
 195                                              int num,
 196                                              struct ether_addr *addr);
 197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 198                                              struct i40e_macvlan_filter *mv_f,
 199                                              int num,
 200                                              uint16_t vlan);
 201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 203                                     struct rte_eth_rss_conf *rss_conf);
 204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 205                                       struct rte_eth_rss_conf *rss_conf);
 206
 207 /* Default hash key buffer for RSS */
 208 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 209
 210 static struct rte_pci_id pci_id_i40e_map[] = {
 211 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 212 #include "rte_pci_dev_ids.h"
 213 { .vendor_id = 0, /* sentinel */ },
 214 };
 215
 216 static struct eth_dev_ops i40e_eth_dev_ops = {
 217         .dev_configure                = i40e_dev_configure,
 218         .dev_start                    = i40e_dev_start,
 219         .dev_stop                     = i40e_dev_stop,
 220         .dev_close                    = i40e_dev_close,
 221         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 222         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 223         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 224         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 225         .link_update                  = i40e_dev_link_update,
 226         .stats_get                    = i40e_dev_stats_get,
 227         .stats_reset                  = i40e_dev_stats_reset,
 228         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 229         .dev_infos_get                = i40e_dev_info_get,
 230         .vlan_filter_set              = i40e_vlan_filter_set,
 231         .vlan_tpid_set                = i40e_vlan_tpid_set,
 232         .vlan_offload_set             = i40e_vlan_offload_set,
 233         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 234         .vlan_pvid_set                = i40e_vlan_pvid_set,
 235         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 236         .rx_queue_release             = i40e_dev_rx_queue_release,
 237         .rx_queue_count               = i40e_dev_rx_queue_count,
 238         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 239         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 240         .tx_queue_release             = i40e_dev_tx_queue_release,
 241         .dev_led_on                   = i40e_dev_led_on,
 242         .dev_led_off                  = i40e_dev_led_off,
 243         .flow_ctrl_set                = i40e_flow_ctrl_set,
 244         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 245         .mac_addr_add                 = i40e_macaddr_add,
 246         .mac_addr_remove              = i40e_macaddr_remove,
 247         .reta_update                  = i40e_dev_rss_reta_update,
 248         .reta_query                   = i40e_dev_rss_reta_query,
 249         .rss_hash_update              = i40e_dev_rss_hash_update,
 250         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 251 };
 252
 253 static struct eth_driver rte_i40e_pmd = {
 254         {
 255                 .name = "rte_i40e_pmd",
 256                 .id_table = pci_id_i40e_map,
 257                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 258         },
 259         .eth_dev_init = eth_i40e_dev_init,
 260         .dev_private_size = sizeof(struct i40e_adapter),
 261 };
 262
 263 static inline int
 264 i40e_prev_power_of_2(int n)
 265 {
 266        int p = n;
 267
 268        --p;
 269        p |= p >> 1;
 270        p |= p >> 2;
 271        p |= p >> 4;
 272        p |= p >> 8;
 273        p |= p >> 16;
 274        if (p == (n - 1))
 275                return n;
 276        p >>= 1;
 277
 278        return ++p;
 279 }
 280
 281 static inline int
 282 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 283                                      struct rte_eth_link *link)
 284 {
 285         struct rte_eth_link *dst = link;
 286         struct rte_eth_link *src = &(dev->data->dev_link);
 287
 288         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 289                                         *(uint64_t *)src) == 0)
 290                 return -1;
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 297                                       struct rte_eth_link *link)
 298 {
 299         struct rte_eth_link *dst = &(dev->data->dev_link);
 300         struct rte_eth_link *src = link;
 301
 302         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 303                                         *(uint64_t *)src) == 0)
 304                 return -1;
 305
 306         return 0;
 307 }
 308
 309 /*
 310  * Driver initialization routine.
 311  * Invoked once at EAL init time.
 312  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 313  */
 314 static int
 315 rte_i40e_pmd_init(const char *name __rte_unused,
 316                   const char *params __rte_unused)
 317 {
 318         PMD_INIT_FUNC_TRACE();
 319         rte_eth_driver_register(&rte_i40e_pmd);
 320
 321         return 0;
 322 }
 323
 324 static struct rte_driver rte_i40e_driver = {
 325         .type = PMD_PDEV,
 326         .init = rte_i40e_pmd_init,
 327 };
 328
 329 PMD_REGISTER_DRIVER(rte_i40e_driver);
 330
 331 static int
 332 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 333                   struct rte_eth_dev *dev)
 334 {
 335         struct rte_pci_device *pci_dev;
 336         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 338         struct i40e_vsi *vsi;
 339         int ret;
 340         uint32_t len;
 341         uint8_t aq_fail = 0;
 342
 343         PMD_INIT_FUNC_TRACE();
 344
 345         dev->dev_ops = &i40e_eth_dev_ops;
 346         dev->rx_pkt_burst = i40e_recv_pkts;
 347         dev->tx_pkt_burst = i40e_xmit_pkts;
 348
 349         /* for secondary processes, we don't initialise any further as primary
 350          * has already done this work. Only check we don't need a different
 351          * RX function */
 352         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 353                 if (dev->data->scattered_rx)
 354                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 355                 return 0;
 356         }
 357         pci_dev = dev->pci_dev;
 358         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 359         pf->adapter->eth_dev = dev;
 360         pf->dev_data = dev->data;
 361
 362         hw->back = I40E_PF_TO_ADAPTER(pf);
 363         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 364         if (!hw->hw_addr) {
 365                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 366                                         "as address is NULL\n");
 367                 return -ENODEV;
 368         }
 369
 370         hw->vendor_id = pci_dev->id.vendor_id;
 371         hw->device_id = pci_dev->id.device_id;
 372         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 373         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 374         hw->bus.device = pci_dev->addr.devid;
 375         hw->bus.func = pci_dev->addr.function;
 376
 377         /* Make sure all is clean before doing PF reset */
 378         i40e_clear_hw(hw);
 379
 380         /* Reset here to make sure all is clean for each PF */
 381         ret = i40e_pf_reset(hw);
 382         if (ret) {
 383                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 384                 return ret;
 385         }
 386
 387         /* Initialize the shared code (base driver) */
 388         ret = i40e_init_shared_code(hw);
 389         if (ret) {
 390                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 391                 return ret;
 392         }
 393
 394         /* Initialize the parameters for adminq */
 395         i40e_init_adminq_parameter(hw);
 396         ret = i40e_init_adminq(hw);
 397         if (ret != I40E_SUCCESS) {
 398                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 399                 return -EIO;
 400         }
 401         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM "
 402                         "%02d.%02d.%02d eetrack %04x\n",
 403                         hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 404                         hw->aq.api_maj_ver, hw->aq.api_min_ver,
 405                         ((hw->nvm.version >> 12) & 0xf),
 406                         ((hw->nvm.version >> 4) & 0xff),
 407                         (hw->nvm.version & 0xf), hw->nvm.eetrack);
 408
 409         /* Disable LLDP */
 410         ret = i40e_aq_stop_lldp(hw, true, NULL);
 411         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 412                 PMD_INIT_LOG(INFO, "Failed to stop lldp\n");
 413
 414         /* Clear PXE mode */
 415         i40e_clear_pxe_mode(hw);
 416
 417         /* Get hw capabilities */
 418         ret = i40e_get_cap(hw);
 419         if (ret != I40E_SUCCESS) {
 420                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 421                 goto err_get_capabilities;
 422         }
 423
 424         /* Initialize parameters for PF */
 425         ret = i40e_pf_parameter_init(dev);
 426         if (ret != 0) {
 427                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 428                 goto err_parameter_init;
 429         }
 430
 431         /* Initialize the queue management */
 432         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 433         if (ret < 0) {
 434                 PMD_INIT_LOG(ERR, "Failed to init queue pool\n");
 435                 goto err_qp_pool_init;
 436         }
 437         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 438                                 hw->func_caps.num_msix_vectors - 1);
 439         if (ret < 0) {
 440                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool\n");
 441                 goto err_msix_pool_init;
 442         }
 443
 444         /* Initialize lan hmc */
 445         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 446                                 hw->func_caps.num_rx_qp, 0, 0);
 447         if (ret != I40E_SUCCESS) {
 448                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 449                 goto err_init_lan_hmc;
 450         }
 451
 452         /* Configure lan hmc */
 453         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 454         if (ret != I40E_SUCCESS) {
 455                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 456                 goto err_configure_lan_hmc;
 457         }
 458
 459         /* Get and check the mac address */
 460         i40e_get_mac_addr(hw, hw->mac.addr);
 461         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 462                 PMD_INIT_LOG(ERR, "mac address is not valid");
 463                 ret = -EIO;
 464                 goto err_get_mac_addr;
 465         }
 466         /* Copy the permanent MAC address */
 467         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 468                         (struct ether_addr *) hw->mac.perm_addr);
 469
 470         /* Disable flow control */
 471         hw->fc.requested_mode = I40E_FC_NONE;
 472         i40e_set_fc(hw, &aq_fail, TRUE);
 473
 474         /* PF setup, which includes VSI setup */
 475         ret = i40e_pf_setup(pf);
 476         if (ret) {
 477                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 478                 goto err_setup_pf_switch;
 479         }
 480
 481         vsi = pf->main_vsi;
 482
 483         /* Disable double vlan by default */
 484         i40e_vsi_config_double_vlan(vsi, FALSE);
 485
 486         if (!vsi->max_macaddrs)
 487                 len = ETHER_ADDR_LEN;
 488         else
 489                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 490
 491         /* Should be after VSI initialized */
 492         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 493         if (!dev->data->mac_addrs) {
 494                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 495                                         "for storing mac address");
 496                 goto err_get_mac_addr;
 497         }
 498         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 499                                         &dev->data->mac_addrs[0]);
 500
 501         /* initialize pf host driver to setup SRIOV resource if applicable */
 502         i40e_pf_host_init(dev);
 503
 504         /* register callback func to eal lib */
 505         rte_intr_callback_register(&(pci_dev->intr_handle),
 506                 i40e_dev_interrupt_handler, (void *)dev);
 507
 508         /* configure and enable device interrupt */
 509         i40e_pf_config_irq0(hw);
 510         i40e_pf_enable_irq0(hw);
 511
 512         /* enable uio intr after callback register */
 513         rte_intr_enable(&(pci_dev->intr_handle));
 514
 515         return 0;
 516
 517 err_setup_pf_switch:
 518         rte_free(pf->main_vsi);
 519 err_get_mac_addr:
 520 err_configure_lan_hmc:
 521         (void)i40e_shutdown_lan_hmc(hw);
 522 err_init_lan_hmc:
 523         i40e_res_pool_destroy(&pf->msix_pool);
 524 err_msix_pool_init:
 525         i40e_res_pool_destroy(&pf->qp_pool);
 526 err_qp_pool_init:
 527 err_parameter_init:
 528 err_get_capabilities:
 529         (void)i40e_shutdown_adminq(hw);
 530
 531         return ret;
 532 }
 533
 534 static int
 535 i40e_dev_configure(struct rte_eth_dev *dev)
 536 {
 537         return i40e_dev_init_vlan(dev);
 538 }
 539
 540 void
 541 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 542 {
 543         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 544         uint16_t msix_vect = vsi->msix_intr;
 545         uint16_t i;
 546
 547         for (i = 0; i < vsi->nb_qps; i++) {
 548                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 549                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 550                 rte_wmb();
 551         }
 552
 553         if (vsi->type != I40E_VSI_SRIOV) {
 554                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 555                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 556                                 msix_vect - 1), 0);
 557         } else {
 558                 uint32_t reg;
 559                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 560                         vsi->user_param + (msix_vect - 1);
 561
 562                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 563         }
 564         I40E_WRITE_FLUSH(hw);
 565 }
 566
 567 static inline uint16_t
 568 i40e_calc_itr_interval(int16_t interval)
 569 {
 570         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 571                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 572
 573         /* Convert to hardware count, as writing each 1 represents 2 us */
 574         return (interval/2);
 575 }
 576
 577 void
 578 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 579 {
 580         uint32_t val;
 581         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 582         uint16_t msix_vect = vsi->msix_intr;
 583         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 584         int i;
 585
 586         for (i = 0; i < vsi->nb_qps; i++)
 587                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 588
 589         /* Bind all RX queues to allocated MSIX interrupt */
 590         for (i = 0; i < vsi->nb_qps; i++) {
 591                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 592                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 593                         ((vsi->base_queue + i + 1) <<
 594                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 595                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 596                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 597
 598                 if (i == vsi->nb_qps - 1)
 599                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 600                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 601         }
 602
 603         /* Write first RX queue to Link list register as the head element */
 604         if (vsi->type != I40E_VSI_SRIOV) {
 605                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 606                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 607                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 608
 609                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 610                                 msix_vect - 1), interval);
 611
 612                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 613                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 614                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 615         }
 616         else {
 617                 uint32_t reg;
 618                 /* num_msix_vectors_vf needs to minus irq0 */
 619                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 620                         vsi->user_param + (msix_vect - 1);
 621
 622                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 623                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 624                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 625         }
 626
 627         I40E_WRITE_FLUSH(hw);
 628 }
 629
 630 static void
 631 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 632 {
 633         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 634         uint16_t interval = i40e_calc_itr_interval(\
 635                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 636
 637         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 638                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 639                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 640                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 641                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 642 }
 643
 644 static void
 645 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 646 {
 647         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 648
 649         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 650 }
 651
 652 static int
 653 i40e_dev_start(struct rte_eth_dev *dev)
 654 {
 655         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 657         struct i40e_vsi *vsi = pf->main_vsi;
 658         int ret;
 659
 660         /* Initialize VSI */
 661         ret = i40e_vsi_init(vsi);
 662         if (ret != I40E_SUCCESS) {
 663                 PMD_DRV_LOG(ERR, "Failed to init VSI\n");
 664                 goto err_up;
 665         }
 666
 667         /* Map queues with MSIX interrupt */
 668         i40e_vsi_queues_bind_intr(vsi);
 669         i40e_vsi_enable_queues_intr(vsi);
 670
 671         /* Enable all queues which have been configured */
 672         ret = i40e_vsi_switch_queues(vsi, TRUE);
 673         if (ret != I40E_SUCCESS) {
 674                 PMD_DRV_LOG(ERR, "Failed to enable VSI\n");
 675                 goto err_up;
 676         }
 677
 678         /* Enable receiving broadcast packets */
 679         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 680                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 681                 if (ret != I40E_SUCCESS)
 682                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast\n");
 683         }
 684
 685         return I40E_SUCCESS;
 686
 687 err_up:
 688         i40e_vsi_switch_queues(vsi, FALSE);
 689         i40e_dev_clear_queues(dev);
 690
 691         return ret;
 692 }
 693
 694 static void
 695 i40e_dev_stop(struct rte_eth_dev *dev)
 696 {
 697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 698         struct i40e_vsi *vsi = pf->main_vsi;
 699
 700         /* Disable all queues */
 701         i40e_vsi_switch_queues(vsi, FALSE);
 702
 703         /* Clear all queues and release memory */
 704         i40e_dev_clear_queues(dev);
 705
 706         /* un-map queues with interrupt registers */
 707         i40e_vsi_disable_queues_intr(vsi);
 708         i40e_vsi_queues_unbind_intr(vsi);
 709 }
 710
 711 static void
 712 i40e_dev_close(struct rte_eth_dev *dev)
 713 {
 714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 716         uint32_t reg;
 717
 718         PMD_INIT_FUNC_TRACE();
 719
 720         i40e_dev_stop(dev);
 721
 722         /* Disable interrupt */
 723         i40e_pf_disable_irq0(hw);
 724         rte_intr_disable(&(dev->pci_dev->intr_handle));
 725
 726         /* shutdown and destroy the HMC */
 727         i40e_shutdown_lan_hmc(hw);
 728
 729         /* release all the existing VSIs and VEBs */
 730         i40e_vsi_release(pf->main_vsi);
 731
 732         /* shutdown the adminq */
 733         i40e_aq_queue_shutdown(hw, true);
 734         i40e_shutdown_adminq(hw);
 735
 736         i40e_res_pool_destroy(&pf->qp_pool);
 737         i40e_res_pool_destroy(&pf->msix_pool);
 738
 739         /* force a PF reset to clean anything leftover */
 740         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 741         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 742                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 743         I40E_WRITE_FLUSH(hw);
 744 }
 745
 746 static void
 747 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 748 {
 749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 751         struct i40e_vsi *vsi = pf->main_vsi;
 752         int status;
 753
 754         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 755                                                         true, NULL);
 756         if (status != I40E_SUCCESS)
 757                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous\n");
 758 }
 759
 760 static void
 761 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 762 {
 763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 765         struct i40e_vsi *vsi = pf->main_vsi;
 766         int status;
 767
 768         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 769                                                         false, NULL);
 770         if (status != I40E_SUCCESS)
 771                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous\n");
 772 }
 773
 774 static void
 775 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 776 {
 777         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 779         struct i40e_vsi *vsi = pf->main_vsi;
 780         int ret;
 781
 782         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 783         if (ret != I40E_SUCCESS)
 784                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
 785 }
 786
 787 static void
 788 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 789 {
 790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 792         struct i40e_vsi *vsi = pf->main_vsi;
 793         int ret;
 794
 795         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 796                                 vsi->seid, FALSE, NULL);
 797         if (ret != I40E_SUCCESS)
 798                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
 799 }
 800
 801 int
 802 i40e_dev_link_update(struct rte_eth_dev *dev,
 803                      __rte_unused int wait_to_complete)
 804 {
 805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 806         struct i40e_link_status link_status;
 807         struct rte_eth_link link, old;
 808         int status;
 809
 810         memset(&link, 0, sizeof(link));
 811         memset(&old, 0, sizeof(old));
 812         memset(&link_status, 0, sizeof(link_status));
 813         rte_i40e_dev_atomic_read_link_status(dev, &old);
 814
 815         /* Get link status information from hardware */
 816         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 817         if (status != I40E_SUCCESS) {
 818                 link.link_speed = ETH_LINK_SPEED_100;
 819                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 820                 PMD_DRV_LOG(ERR, "Failed to get link info\n");
 821                 goto out;
 822         }
 823
 824         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 825
 826         if (!link.link_status)
 827                 goto out;
 828
 829         /* i40e uses full duplex only */
 830         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 831
 832         /* Parse the link status */
 833         switch (link_status.link_speed) {
 834         case I40E_LINK_SPEED_100MB:
 835                 link.link_speed = ETH_LINK_SPEED_100;
 836                 break;
 837         case I40E_LINK_SPEED_1GB:
 838                 link.link_speed = ETH_LINK_SPEED_1000;
 839                 break;
 840         case I40E_LINK_SPEED_10GB:
 841                 link.link_speed = ETH_LINK_SPEED_10G;
 842                 break;
 843         case I40E_LINK_SPEED_20GB:
 844                 link.link_speed = ETH_LINK_SPEED_20G;
 845                 break;
 846         case I40E_LINK_SPEED_40GB:
 847                 link.link_speed = ETH_LINK_SPEED_40G;
 848                 break;
 849         default:
 850                 link.link_speed = ETH_LINK_SPEED_100;
 851                 break;
 852         }
 853
 854 out:
 855         rte_i40e_dev_atomic_write_link_status(dev, &link);
 856         if (link.link_status == old.link_status)
 857                 return -1;
 858
 859         return 0;
 860 }
 861
 862 /* Get all the statistics of a VSI */
 863 void
 864 i40e_update_vsi_stats(struct i40e_vsi *vsi)
 865 {
 866         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 867         struct i40e_eth_stats *nes = &vsi->eth_stats;
 868         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 869         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
 870
 871         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
 872                             vsi->offset_loaded, &oes->rx_bytes,
 873                             &nes->rx_bytes);
 874         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
 875                             vsi->offset_loaded, &oes->rx_unicast,
 876                             &nes->rx_unicast);
 877         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
 878                             vsi->offset_loaded, &oes->rx_multicast,
 879                             &nes->rx_multicast);
 880         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
 881                             vsi->offset_loaded, &oes->rx_broadcast,
 882                             &nes->rx_broadcast);
 883         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
 884                             &oes->rx_discards, &nes->rx_discards);
 885         /* GLV_REPC not supported */
 886         /* GLV_RMPC not supported */
 887         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
 888                             &oes->rx_unknown_protocol,
 889                             &nes->rx_unknown_protocol);
 890         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
 891                             vsi->offset_loaded, &oes->tx_bytes,
 892                             &nes->tx_bytes);
 893         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
 894                             vsi->offset_loaded, &oes->tx_unicast,
 895                             &nes->tx_unicast);
 896         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
 897                             vsi->offset_loaded, &oes->tx_multicast,
 898                             &nes->tx_multicast);
 899         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
 900                             vsi->offset_loaded,  &oes->tx_broadcast,
 901                             &nes->tx_broadcast);
 902         /* GLV_TDPC not supported */
 903         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
 904                             &oes->tx_errors, &nes->tx_errors);
 905         vsi->offset_loaded = true;
 906
 907 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
 908         printf("***************** VSI[%u] stats start *******************\n",
 909                                                                 vsi->vsi_id);
 910         printf("rx_bytes:            %lu\n", nes->rx_bytes);
 911         printf("rx_unicast:          %lu\n", nes->rx_unicast);
 912         printf("rx_multicast:        %lu\n", nes->rx_multicast);
 913         printf("rx_broadcast:        %lu\n", nes->rx_broadcast);
 914         printf("rx_discards:         %lu\n", nes->rx_discards);
 915         printf("rx_unknown_protocol: %lu\n", nes->rx_unknown_protocol);
 916         printf("tx_bytes:            %lu\n", nes->tx_bytes);
 917         printf("tx_unicast:          %lu\n", nes->tx_unicast);
 918         printf("tx_multicast:        %lu\n", nes->tx_multicast);
 919         printf("tx_broadcast:        %lu\n", nes->tx_broadcast);
 920         printf("tx_discards:         %lu\n", nes->tx_discards);
 921         printf("tx_errors:           %lu\n", nes->tx_errors);
 922         printf("***************** VSI[%u] stats end *******************\n",
 923                                                                 vsi->vsi_id);
 924 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
 925 }
 926
 927 /* Get all statistics of a port */
 928 static void
 929 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 930 {
 931         uint32_t i;
 932         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 933         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 934         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
 935         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
 936
 937         /* Get statistics of struct i40e_eth_stats */
 938         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
 939                             I40E_GLPRT_GORCL(hw->port),
 940                             pf->offset_loaded, &os->eth.rx_bytes,
 941                             &ns->eth.rx_bytes);
 942         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
 943                             I40E_GLPRT_UPRCL(hw->port),
 944                             pf->offset_loaded, &os->eth.rx_unicast,
 945                             &ns->eth.rx_unicast);
 946         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
 947                             I40E_GLPRT_MPRCL(hw->port),
 948                             pf->offset_loaded, &os->eth.rx_multicast,
 949                             &ns->eth.rx_multicast);
 950         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
 951                             I40E_GLPRT_BPRCL(hw->port),
 952                             pf->offset_loaded, &os->eth.rx_broadcast,
 953                             &ns->eth.rx_broadcast);
 954         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
 955                             pf->offset_loaded, &os->eth.rx_discards,
 956                             &ns->eth.rx_discards);
 957         /* GLPRT_REPC not supported */
 958         /* GLPRT_RMPC not supported */
 959         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
 960                             pf->offset_loaded,
 961                             &os->eth.rx_unknown_protocol,
 962                             &ns->eth.rx_unknown_protocol);
 963         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
 964                             I40E_GLPRT_GOTCL(hw->port),
 965                             pf->offset_loaded, &os->eth.tx_bytes,
 966                             &ns->eth.tx_bytes);
 967         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
 968                             I40E_GLPRT_UPTCL(hw->port),
 969                             pf->offset_loaded, &os->eth.tx_unicast,
 970                             &ns->eth.tx_unicast);
 971         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
 972                             I40E_GLPRT_MPTCL(hw->port),
 973                             pf->offset_loaded, &os->eth.tx_multicast,
 974                             &ns->eth.tx_multicast);
 975         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
 976                             I40E_GLPRT_BPTCL(hw->port),
 977                             pf->offset_loaded, &os->eth.tx_broadcast,
 978                             &ns->eth.tx_broadcast);
 979         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
 980                             pf->offset_loaded, &os->eth.tx_discards,
 981                             &ns->eth.tx_discards);
 982         /* GLPRT_TEPC not supported */
 983
 984         /* additional port specific stats */
 985         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
 986                             pf->offset_loaded, &os->tx_dropped_link_down,
 987                             &ns->tx_dropped_link_down);
 988         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
 989                             pf->offset_loaded, &os->crc_errors,
 990                             &ns->crc_errors);
 991         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
 992                             pf->offset_loaded, &os->illegal_bytes,
 993                             &ns->illegal_bytes);
 994         /* GLPRT_ERRBC not supported */
 995         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
 996                             pf->offset_loaded, &os->mac_local_faults,
 997                             &ns->mac_local_faults);
 998         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
 999                             pf->offset_loaded, &os->mac_remote_faults,
1000                             &ns->mac_remote_faults);
1001         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1002                             pf->offset_loaded, &os->rx_length_errors,
1003                             &ns->rx_length_errors);
1004         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1005                             pf->offset_loaded, &os->link_xon_rx,
1006                             &ns->link_xon_rx);
1007         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1008                             pf->offset_loaded, &os->link_xoff_rx,
1009                             &ns->link_xoff_rx);
1010         for (i = 0; i < 8; i++) {
1011                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1012                                     pf->offset_loaded,
1013                                     &os->priority_xon_rx[i],
1014                                     &ns->priority_xon_rx[i]);
1015                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1016                                     pf->offset_loaded,
1017                                     &os->priority_xoff_rx[i],
1018                                     &ns->priority_xoff_rx[i]);
1019         }
1020         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1021                             pf->offset_loaded, &os->link_xon_tx,
1022                             &ns->link_xon_tx);
1023         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1024                             pf->offset_loaded, &os->link_xoff_tx,
1025                             &ns->link_xoff_tx);
1026         for (i = 0; i < 8; i++) {
1027                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1028                                     pf->offset_loaded,
1029                                     &os->priority_xon_tx[i],
1030                                     &ns->priority_xon_tx[i]);
1031                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1032                                     pf->offset_loaded,
1033                                     &os->priority_xoff_tx[i],
1034                                     &ns->priority_xoff_tx[i]);
1035                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1036                                     pf->offset_loaded,
1037                                     &os->priority_xon_2_xoff[i],
1038                                     &ns->priority_xon_2_xoff[i]);
1039         }
1040         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1041                             I40E_GLPRT_PRC64L(hw->port),
1042                             pf->offset_loaded, &os->rx_size_64,
1043                             &ns->rx_size_64);
1044         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1045                             I40E_GLPRT_PRC127L(hw->port),
1046                             pf->offset_loaded, &os->rx_size_127,
1047                             &ns->rx_size_127);
1048         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1049                             I40E_GLPRT_PRC255L(hw->port),
1050                             pf->offset_loaded, &os->rx_size_255,
1051                             &ns->rx_size_255);
1052         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1053                             I40E_GLPRT_PRC511L(hw->port),
1054                             pf->offset_loaded, &os->rx_size_511,
1055                             &ns->rx_size_511);
1056         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1057                             I40E_GLPRT_PRC1023L(hw->port),
1058                             pf->offset_loaded, &os->rx_size_1023,
1059                             &ns->rx_size_1023);
1060         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1061                             I40E_GLPRT_PRC1522L(hw->port),
1062                             pf->offset_loaded, &os->rx_size_1522,
1063                             &ns->rx_size_1522);
1064         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1065                             I40E_GLPRT_PRC9522L(hw->port),
1066                             pf->offset_loaded, &os->rx_size_big,
1067                             &ns->rx_size_big);
1068         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1069                             pf->offset_loaded, &os->rx_undersize,
1070                             &ns->rx_undersize);
1071         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1072                             pf->offset_loaded, &os->rx_fragments,
1073                             &ns->rx_fragments);
1074         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1075                             pf->offset_loaded, &os->rx_oversize,
1076                             &ns->rx_oversize);
1077         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1078                             pf->offset_loaded, &os->rx_jabber,
1079                             &ns->rx_jabber);
1080         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1081                             I40E_GLPRT_PTC64L(hw->port),
1082                             pf->offset_loaded, &os->tx_size_64,
1083                             &ns->tx_size_64);
1084         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1085                             I40E_GLPRT_PTC127L(hw->port),
1086                             pf->offset_loaded, &os->tx_size_127,
1087                             &ns->tx_size_127);
1088         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1089                             I40E_GLPRT_PTC255L(hw->port),
1090                             pf->offset_loaded, &os->tx_size_255,
1091                             &ns->tx_size_255);
1092         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1093                             I40E_GLPRT_PTC511L(hw->port),
1094                             pf->offset_loaded, &os->tx_size_511,
1095                             &ns->tx_size_511);
1096         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1097                             I40E_GLPRT_PTC1023L(hw->port),
1098                             pf->offset_loaded, &os->tx_size_1023,
1099                             &ns->tx_size_1023);
1100         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1101                             I40E_GLPRT_PTC1522L(hw->port),
1102                             pf->offset_loaded, &os->tx_size_1522,
1103                             &ns->tx_size_1522);
1104         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1105                             I40E_GLPRT_PTC9522L(hw->port),
1106                             pf->offset_loaded, &os->tx_size_big,
1107                             &ns->tx_size_big);
1108         /* GLPRT_MSPDC not supported */
1109         /* GLPRT_XEC not supported */
1110
1111         pf->offset_loaded = true;
1112
1113         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1114                                                 ns->eth.rx_broadcast;
1115         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1116                                                 ns->eth.tx_broadcast;
1117         stats->ibytes   = ns->eth.rx_bytes;
1118         stats->obytes   = ns->eth.tx_bytes;
1119         stats->oerrors  = ns->eth.tx_errors;
1120         stats->imcasts  = ns->eth.rx_multicast;
1121
1122         if (pf->main_vsi)
1123                 i40e_update_vsi_stats(pf->main_vsi);
1124
1125 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1126         printf("***************** PF stats start *******************\n");
1127         printf("rx_bytes:            %lu\n", ns->eth.rx_bytes);
1128         printf("rx_unicast:          %lu\n", ns->eth.rx_unicast);
1129         printf("rx_multicast:        %lu\n", ns->eth.rx_multicast);
1130         printf("rx_broadcast:        %lu\n", ns->eth.rx_broadcast);
1131         printf("rx_discards:         %lu\n", ns->eth.rx_discards);
1132         printf("rx_unknown_protocol: %lu\n", ns->eth.rx_unknown_protocol);
1133         printf("tx_bytes:            %lu\n", ns->eth.tx_bytes);
1134         printf("tx_unicast:          %lu\n", ns->eth.tx_unicast);
1135         printf("tx_multicast:        %lu\n", ns->eth.tx_multicast);
1136         printf("tx_broadcast:        %lu\n", ns->eth.tx_broadcast);
1137         printf("tx_discards:         %lu\n", ns->eth.tx_discards);
1138         printf("tx_errors:           %lu\n", ns->eth.tx_errors);
1139
1140         printf("tx_dropped_link_down:     %lu\n", ns->tx_dropped_link_down);
1141         printf("crc_errors:               %lu\n", ns->crc_errors);
1142         printf("illegal_bytes:            %lu\n", ns->illegal_bytes);
1143         printf("error_bytes:              %lu\n", ns->error_bytes);
1144         printf("mac_local_faults:         %lu\n", ns->mac_local_faults);
1145         printf("mac_remote_faults:        %lu\n", ns->mac_remote_faults);
1146         printf("rx_length_errors:         %lu\n", ns->rx_length_errors);
1147         printf("link_xon_rx:              %lu\n", ns->link_xon_rx);
1148         printf("link_xoff_rx:             %lu\n", ns->link_xoff_rx);
1149         for (i = 0; i < 8; i++) {
1150                 printf("priority_xon_rx[%d]:      %lu\n",
1151                                 i, ns->priority_xon_rx[i]);
1152                 printf("priority_xoff_rx[%d]:     %lu\n",
1153                                 i, ns->priority_xoff_rx[i]);
1154         }
1155         printf("link_xon_tx:              %lu\n", ns->link_xon_tx);
1156         printf("link_xoff_tx:             %lu\n", ns->link_xoff_tx);
1157         for (i = 0; i < 8; i++) {
1158                 printf("priority_xon_tx[%d]:      %lu\n",
1159                                 i, ns->priority_xon_tx[i]);
1160                 printf("priority_xoff_tx[%d]:     %lu\n",
1161                                 i, ns->priority_xoff_tx[i]);
1162                 printf("priority_xon_2_xoff[%d]:  %lu\n",
1163                                 i, ns->priority_xon_2_xoff[i]);
1164         }
1165         printf("rx_size_64:               %lu\n", ns->rx_size_64);
1166         printf("rx_size_127:              %lu\n", ns->rx_size_127);
1167         printf("rx_size_255:              %lu\n", ns->rx_size_255);
1168         printf("rx_size_511:              %lu\n", ns->rx_size_511);
1169         printf("rx_size_1023:             %lu\n", ns->rx_size_1023);
1170         printf("rx_size_1522:             %lu\n", ns->rx_size_1522);
1171         printf("rx_size_big:              %lu\n", ns->rx_size_big);
1172         printf("rx_undersize:             %lu\n", ns->rx_undersize);
1173         printf("rx_fragments:             %lu\n", ns->rx_fragments);
1174         printf("rx_oversize:              %lu\n", ns->rx_oversize);
1175         printf("rx_jabber:                %lu\n", ns->rx_jabber);
1176         printf("tx_size_64:               %lu\n", ns->tx_size_64);
1177         printf("tx_size_127:              %lu\n", ns->tx_size_127);
1178         printf("tx_size_255:              %lu\n", ns->tx_size_255);
1179         printf("tx_size_511:              %lu\n", ns->tx_size_511);
1180         printf("tx_size_1023:             %lu\n", ns->tx_size_1023);
1181         printf("tx_size_1522:             %lu\n", ns->tx_size_1522);
1182         printf("tx_size_big:              %lu\n", ns->tx_size_big);
1183         printf("mac_short_packet_dropped: %lu\n",
1184                         ns->mac_short_packet_dropped);
1185         printf("checksum_error:           %lu\n", ns->checksum_error);
1186         printf("***************** PF stats end ********************\n");
1187 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1188 }
1189
1190 /* Reset the statistics */
1191 static void
1192 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1193 {
1194         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1195
1196         /* It results in reloading the start point of each counter */
1197         pf->offset_loaded = false;
1198 }
1199
1200 static int
1201 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1202                                  __rte_unused uint16_t queue_id,
1203                                  __rte_unused uint8_t stat_idx,
1204                                  __rte_unused uint8_t is_rx)
1205 {
1206         PMD_INIT_FUNC_TRACE();
1207
1208         return -ENOSYS;
1209 }
1210
1211 static void
1212 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1213 {
1214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1215         struct i40e_vsi *vsi = pf->main_vsi;
1216
1217         dev_info->max_rx_queues = vsi->nb_qps;
1218         dev_info->max_tx_queues = vsi->nb_qps;
1219         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1220         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1221         dev_info->max_mac_addrs = vsi->max_macaddrs;
1222         dev_info->max_vfs = dev->pci_dev->max_vfs;
1223         dev_info->rx_offload_capa =
1224                 DEV_RX_OFFLOAD_VLAN_STRIP |
1225                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1226                 DEV_RX_OFFLOAD_UDP_CKSUM |
1227                 DEV_RX_OFFLOAD_TCP_CKSUM;
1228         dev_info->tx_offload_capa =
1229                 DEV_TX_OFFLOAD_VLAN_INSERT |
1230                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1231                 DEV_TX_OFFLOAD_UDP_CKSUM |
1232                 DEV_TX_OFFLOAD_TCP_CKSUM |
1233                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1234 }
1235
1236 static int
1237 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1238 {
1239         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240         struct i40e_vsi *vsi = pf->main_vsi;
1241         PMD_INIT_FUNC_TRACE();
1242
1243         if (on)
1244                 return i40e_vsi_add_vlan(vsi, vlan_id);
1245         else
1246                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1247 }
1248
1249 static void
1250 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1251                    __rte_unused uint16_t tpid)
1252 {
1253         PMD_INIT_FUNC_TRACE();
1254 }
1255
1256 static void
1257 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1258 {
1259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1260         struct i40e_vsi *vsi = pf->main_vsi;
1261
1262         if (mask & ETH_VLAN_STRIP_MASK) {
1263                 /* Enable or disable VLAN stripping */
1264                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1265                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1266                 else
1267                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1268         }
1269
1270         if (mask & ETH_VLAN_EXTEND_MASK) {
1271                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1272                         i40e_vsi_config_double_vlan(vsi, TRUE);
1273                 else
1274                         i40e_vsi_config_double_vlan(vsi, FALSE);
1275         }
1276 }
1277
1278 static void
1279 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1280                           __rte_unused uint16_t queue,
1281                           __rte_unused int on)
1282 {
1283         PMD_INIT_FUNC_TRACE();
1284 }
1285
1286 static int
1287 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1288 {
1289         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1290         struct i40e_vsi *vsi = pf->main_vsi;
1291         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1292         struct i40e_vsi_vlan_pvid_info info;
1293
1294         memset(&info, 0, sizeof(info));
1295         info.on = on;
1296         if (info.on)
1297                 info.config.pvid = pvid;
1298         else {
1299                 info.config.reject.tagged =
1300                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1301                 info.config.reject.untagged =
1302                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1303         }
1304
1305         return i40e_vsi_vlan_pvid_set(vsi, &info);
1306 }
1307
1308 static int
1309 i40e_dev_led_on(struct rte_eth_dev *dev)
1310 {
1311         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312         uint32_t mode = i40e_led_get(hw);
1313
1314         if (mode == 0)
1315                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1316
1317         return 0;
1318 }
1319
1320 static int
1321 i40e_dev_led_off(struct rte_eth_dev *dev)
1322 {
1323         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         uint32_t mode = i40e_led_get(hw);
1325
1326         if (mode != 0)
1327                 i40e_led_set(hw, 0, false);
1328
1329         return 0;
1330 }
1331
1332 static int
1333 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1334                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1335 {
1336         PMD_INIT_FUNC_TRACE();
1337
1338         return -ENOSYS;
1339 }
1340
1341 static int
1342 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1343                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1344 {
1345         PMD_INIT_FUNC_TRACE();
1346
1347         return -ENOSYS;
1348 }
1349
1350 /* Add a MAC address, and update filters */
1351 static void
1352 i40e_macaddr_add(struct rte_eth_dev *dev,
1353                  struct ether_addr *mac_addr,
1354                  __attribute__((unused)) uint32_t index,
1355                  __attribute__((unused)) uint32_t pool)
1356 {
1357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1358         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         struct i40e_vsi *vsi = pf->main_vsi;
1360         struct ether_addr old_mac;
1361         int ret;
1362
1363         if (!is_valid_assigned_ether_addr(mac_addr)) {
1364                 PMD_DRV_LOG(ERR, "Invalid ethernet address\n");
1365                 return;
1366         }
1367
1368         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1369                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address\n");
1370                 return;
1371         }
1372
1373         /* Write mac address */
1374         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1375                                         mac_addr->addr_bytes, NULL);
1376         if (ret != I40E_SUCCESS) {
1377                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1378                 return;
1379         }
1380
1381         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1382         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1383                         ETHER_ADDR_LEN);
1384
1385         ret = i40e_vsi_add_mac(vsi, mac_addr);
1386         if (ret != I40E_SUCCESS) {
1387                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
1388                 return;
1389         }
1390
1391         ether_addr_copy(mac_addr, &pf->dev_addr);
1392         i40e_vsi_delete_mac(vsi, &old_mac);
1393 }
1394
1395 /* Remove a MAC address, and update filters */
1396 static void
1397 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1398 {
1399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1400         struct i40e_vsi *vsi = pf->main_vsi;
1401         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1402         struct ether_addr *macaddr;
1403         int ret;
1404         struct i40e_hw *hw =
1405                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406
1407         if (index >= vsi->max_macaddrs)
1408                 return;
1409
1410         macaddr = &(data->mac_addrs[index]);
1411         if (!is_valid_assigned_ether_addr(macaddr))
1412                 return;
1413
1414         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1415                                         hw->mac.perm_addr, NULL);
1416         if (ret != I40E_SUCCESS) {
1417                 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1418                 return;
1419         }
1420
1421         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1422
1423         ret = i40e_vsi_delete_mac(vsi, macaddr);
1424         if (ret != I40E_SUCCESS)
1425                 return;
1426
1427         /* Clear device address as it has been removed */
1428         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1429                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1430 }
1431
1432 static int
1433 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1434                          struct rte_eth_rss_reta *reta_conf)
1435 {
1436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437         uint32_t lut, l;
1438         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1439
1440         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1441                 if (i < max)
1442                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1443                 else
1444                         mask = (uint8_t)((reta_conf->mask_hi >>
1445                                                 (i - max)) & 0xF);
1446
1447                 if (!mask)
1448                         continue;
1449
1450                 if (mask == 0xF)
1451                         l = 0;
1452                 else
1453                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1454
1455                 for (j = 0, lut = 0; j < 4; j++) {
1456                         if (mask & (0x1 << j))
1457                                 lut |= reta_conf->reta[i + j] << (8 * j);
1458                         else
1459                                 lut |= l & (0xFF << (8 * j));
1460                 }
1461                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int
1468 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1469                         struct rte_eth_rss_reta *reta_conf)
1470 {
1471         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472         uint32_t lut;
1473         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1474
1475         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1476                 if (i < max)
1477                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1478                 else
1479                         mask = (uint8_t)((reta_conf->mask_hi >>
1480                                                 (i - max)) & 0xF);
1481
1482                 if (!mask)
1483                         continue;
1484
1485                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1486                 for (j = 0; j < 4; j++) {
1487                         if (mask & (0x1 << j))
1488                                 reta_conf->reta[i + j] =
1489                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1490                 }
1491         }
1492
1493         return 0;
1494 }
1495
1496 /**
1497  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1498  * @hw:   pointer to the HW structure
1499  * @mem:  pointer to mem struct to fill out
1500  * @size: size of memory requested
1501  * @alignment: what to align the allocation to
1502  **/
1503 enum i40e_status_code
1504 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1505                         struct i40e_dma_mem *mem,
1506                         u64 size,
1507                         u32 alignment)
1508 {
1509         static uint64_t id = 0;
1510         const struct rte_memzone *mz = NULL;
1511         char z_name[RTE_MEMZONE_NAMESIZE];
1512
1513         if (!mem)
1514                 return I40E_ERR_PARAM;
1515
1516         id++;
1517         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1518 #ifdef RTE_LIBRTE_XEN_DOM0
1519         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1520                                                         RTE_PGSIZE_2M);
1521 #else
1522         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1523 #endif
1524         if (!mz)
1525                 return I40E_ERR_NO_MEMORY;
1526
1527         mem->id = id;
1528         mem->size = size;
1529         mem->va = mz->addr;
1530 #ifdef RTE_LIBRTE_XEN_DOM0
1531         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1532 #else
1533         mem->pa = mz->phys_addr;
1534 #endif
1535
1536         return I40E_SUCCESS;
1537 }
1538
1539 /**
1540  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1541  * @hw:   pointer to the HW structure
1542  * @mem:  ptr to mem struct to free
1543  **/
1544 enum i40e_status_code
1545 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1546                     struct i40e_dma_mem *mem)
1547 {
1548         if (!mem || !mem->va)
1549                 return I40E_ERR_PARAM;
1550
1551         mem->va = NULL;
1552         mem->pa = (u64)0;
1553
1554         return I40E_SUCCESS;
1555 }
1556
1557 /**
1558  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1559  * @hw:   pointer to the HW structure
1560  * @mem:  pointer to mem struct to fill out
1561  * @size: size of memory requested
1562  **/
1563 enum i40e_status_code
1564 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1565                          struct i40e_virt_mem *mem,
1566                          u32 size)
1567 {
1568         if (!mem)
1569                 return I40E_ERR_PARAM;
1570
1571         mem->size = size;
1572         mem->va = rte_zmalloc("i40e", size, 0);
1573
1574         if (mem->va)
1575                 return I40E_SUCCESS;
1576         else
1577                 return I40E_ERR_NO_MEMORY;
1578 }
1579
1580 /**
1581  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1582  * @hw:   pointer to the HW structure
1583  * @mem:  pointer to mem struct to free
1584  **/
1585 enum i40e_status_code
1586 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1587                      struct i40e_virt_mem *mem)
1588 {
1589         if (!mem)
1590                 return I40E_ERR_PARAM;
1591
1592         rte_free(mem->va);
1593         mem->va = NULL;
1594
1595         return I40E_SUCCESS;
1596 }
1597
1598 void
1599 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1600 {
1601         rte_spinlock_init(&sp->spinlock);
1602 }
1603
1604 void
1605 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1606 {
1607         rte_spinlock_lock(&sp->spinlock);
1608 }
1609
1610 void
1611 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1612 {
1613         rte_spinlock_unlock(&sp->spinlock);
1614 }
1615
1616 void
1617 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1618 {
1619         return;
1620 }
1621
1622 /**
1623  * Get the hardware capabilities, which will be parsed
1624  * and saved into struct i40e_hw.
1625  */
1626 static int
1627 i40e_get_cap(struct i40e_hw *hw)
1628 {
1629         struct i40e_aqc_list_capabilities_element_resp *buf;
1630         uint16_t len, size = 0;
1631         int ret;
1632
1633         /* Calculate a huge enough buff for saving response data temporarily */
1634         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1635                                                 I40E_MAX_CAP_ELE_NUM;
1636         buf = rte_zmalloc("i40e", len, 0);
1637         if (!buf) {
1638                 PMD_DRV_LOG(ERR, "Failed to allocate memory\n");
1639                 return I40E_ERR_NO_MEMORY;
1640         }
1641
1642         /* Get, parse the capabilities and save it to hw */
1643         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1644                         i40e_aqc_opc_list_func_capabilities, NULL);
1645         if (ret != I40E_SUCCESS)
1646                 PMD_DRV_LOG(ERR, "Failed to discover capabilities\n");
1647
1648         /* Free the temporary buffer after being used */
1649         rte_free(buf);
1650
1651         return ret;
1652 }
1653
1654 static int
1655 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1656 {
1657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1658         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1659         uint16_t sum_queues = 0, sum_vsis;
1660
1661         /* First check if FW support SRIOV */
1662         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1663                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV\n");
1664                 return -EINVAL;
1665         }
1666
1667         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1668         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1669         PMD_INIT_LOG(INFO, "Max supported VSIs:%u\n", pf->max_num_vsi);
1670         /* Allocate queues for pf */
1671         if (hw->func_caps.rss) {
1672                 pf->flags |= I40E_FLAG_RSS;
1673                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1674                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1675                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1676         } else
1677                 pf->lan_nb_qps = 1;
1678         sum_queues = pf->lan_nb_qps;
1679         /* Default VSI is not counted in */
1680         sum_vsis = 0;
1681         PMD_INIT_LOG(INFO, "PF queue pairs:%u\n", pf->lan_nb_qps);
1682
1683         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1684                 pf->flags |= I40E_FLAG_SRIOV;
1685                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1686                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1687                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1688                                 "max supported %u.\n", dev->pci_dev->max_vfs,
1689                                                 hw->func_caps.num_vfs);
1690                         return -EINVAL;
1691                 }
1692                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1693                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1694                                 "max support %u queues.\n", pf->vf_nb_qps,
1695                                                 I40E_MAX_QP_NUM_PER_VF);
1696                         return -EINVAL;
1697                 }
1698                 pf->vf_num = dev->pci_dev->max_vfs;
1699                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1700                 sum_vsis   += pf->vf_num;
1701                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u\n",
1702                                                 pf->vf_num, pf->vf_nb_qps);
1703         } else
1704                 pf->vf_num = 0;
1705
1706         if (hw->func_caps.vmdq) {
1707                 pf->flags |= I40E_FLAG_VMDQ;
1708                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1709                 sum_queues += pf->vmdq_nb_qps;
1710                 sum_vsis += 1;
1711                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u\n", pf->vmdq_nb_qps);
1712         }
1713
1714         if (hw->func_caps.fd) {
1715                 pf->flags |= I40E_FLAG_FDIR;
1716                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1717                 /**
1718                  * Each flow director consumes one VSI and one queue,
1719                  * but can't calculate out predictably here.
1720                  */
1721         }
1722
1723         if (sum_vsis > pf->max_num_vsi ||
1724                 sum_queues > hw->func_caps.num_rx_qp) {
1725                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied\n");
1726                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u\n",
1727                                 pf->max_num_vsi, sum_vsis);
1728                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u\n",
1729                                 hw->func_caps.num_rx_qp, sum_queues);
1730                 return -EINVAL;
1731         }
1732
1733         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr cause */
1734         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1735                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough\n",
1736                                 sum_vsis, hw->func_caps.num_msix_vectors);
1737                 return -EINVAL;
1738         }
1739         return I40E_SUCCESS;
1740 }
1741
1742 static int
1743 i40e_pf_get_switch_config(struct i40e_pf *pf)
1744 {
1745         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1746         struct i40e_aqc_get_switch_config_resp *switch_config;
1747         struct i40e_aqc_switch_config_element_resp *element;
1748         uint16_t start_seid = 0, num_reported;
1749         int ret;
1750
1751         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1752                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1753         if (!switch_config) {
1754                 PMD_DRV_LOG(ERR, "Failed to allocated memory\n");
1755                 return -ENOMEM;
1756         }
1757
1758         /* Get the switch configurations */
1759         ret = i40e_aq_get_switch_config(hw, switch_config,
1760                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1761         if (ret != I40E_SUCCESS) {
1762                 PMD_DRV_LOG(ERR, "Failed to get switch configurations\n");
1763                 goto fail;
1764         }
1765         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1766         if (num_reported != 1) { /* The number should be 1 */
1767                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported\n");
1768                 goto fail;
1769         }
1770
1771         /* Parse the switch configuration elements */
1772         element = &(switch_config->element[0]);
1773         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1774                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1775                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1776         } else
1777                 PMD_DRV_LOG(INFO, "Unknown element type\n");
1778
1779 fail:
1780         rte_free(switch_config);
1781
1782         return ret;
1783 }
1784
1785 static int
1786 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1787                         uint32_t num)
1788 {
1789         struct pool_entry *entry;
1790
1791         if (pool == NULL || num == 0)
1792                 return -EINVAL;
1793
1794         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1795         if (entry == NULL) {
1796                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1797                                                 "resource pool\n");
1798                 return -ENOMEM;
1799         }
1800
1801         /* queue heap initialize */
1802         pool->num_free = num;
1803         pool->num_alloc = 0;
1804         pool->base = base;
1805         LIST_INIT(&pool->alloc_list);
1806         LIST_INIT(&pool->free_list);
1807
1808         /* Initialize element  */
1809         entry->base = 0;
1810         entry->len = num;
1811
1812         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1813         return 0;
1814 }
1815
1816 static void
1817 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1818 {
1819         struct pool_entry *entry;
1820
1821         if (pool == NULL)
1822                 return;
1823
1824         LIST_FOREACH(entry, &pool->alloc_list, next) {
1825                 LIST_REMOVE(entry, next);
1826                 rte_free(entry);
1827         }
1828
1829         LIST_FOREACH(entry, &pool->free_list, next) {
1830                 LIST_REMOVE(entry, next);
1831                 rte_free(entry);
1832         }
1833
1834         pool->num_free = 0;
1835         pool->num_alloc = 0;
1836         pool->base = 0;
1837         LIST_INIT(&pool->alloc_list);
1838         LIST_INIT(&pool->free_list);
1839 }
1840
1841 static int
1842 i40e_res_pool_free(struct i40e_res_pool_info *pool,
1843                        uint32_t base)
1844 {
1845         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
1846         uint32_t pool_offset;
1847         int insert;
1848
1849         if (pool == NULL) {
1850                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1851                 return -EINVAL;
1852         }
1853
1854         pool_offset = base - pool->base;
1855         /* Lookup in alloc list */
1856         LIST_FOREACH(entry, &pool->alloc_list, next) {
1857                 if (entry->base == pool_offset) {
1858                         valid_entry = entry;
1859                         LIST_REMOVE(entry, next);
1860                         break;
1861                 }
1862         }
1863
1864         /* Not find, return */
1865         if (valid_entry == NULL) {
1866                 PMD_DRV_LOG(ERR, "Failed to find entry\n");
1867                 return -EINVAL;
1868         }
1869
1870         /**
1871          * Found it, move it to free list  and try to merge.
1872          * In order to make merge easier, always sort it by qbase.
1873          * Find adjacent prev and last entries.
1874          */
1875         prev = next = NULL;
1876         LIST_FOREACH(entry, &pool->free_list, next) {
1877                 if (entry->base > valid_entry->base) {
1878                         next = entry;
1879                         break;
1880                 }
1881                 prev = entry;
1882         }
1883
1884         insert = 0;
1885         /* Try to merge with next one*/
1886         if (next != NULL) {
1887                 /* Merge with next one */
1888                 if (valid_entry->base + valid_entry->len == next->base) {
1889                         next->base = valid_entry->base;
1890                         next->len += valid_entry->len;
1891                         rte_free(valid_entry);
1892                         valid_entry = next;
1893                         insert = 1;
1894                 }
1895         }
1896
1897         if (prev != NULL) {
1898                 /* Merge with previous one */
1899                 if (prev->base + prev->len == valid_entry->base) {
1900                         prev->len += valid_entry->len;
1901                         /* If it merge with next one, remove next node */
1902                         if (insert == 1) {
1903                                 LIST_REMOVE(valid_entry, next);
1904                                 rte_free(valid_entry);
1905                         } else {
1906                                 rte_free(valid_entry);
1907                                 insert = 1;
1908                         }
1909                 }
1910         }
1911
1912         /* Not find any entry to merge, insert */
1913         if (insert == 0) {
1914                 if (prev != NULL)
1915                         LIST_INSERT_AFTER(prev, valid_entry, next);
1916                 else if (next != NULL)
1917                         LIST_INSERT_BEFORE(next, valid_entry, next);
1918                 else /* It's empty list, insert to head */
1919                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
1920         }
1921
1922         pool->num_free += valid_entry->len;
1923         pool->num_alloc -= valid_entry->len;
1924
1925         return 0;
1926 }
1927
1928 static int
1929 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
1930                        uint16_t num)
1931 {
1932         struct pool_entry *entry, *valid_entry;
1933
1934         if (pool == NULL || num == 0) {
1935                 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1936                 return -EINVAL;
1937         }
1938
1939         if (pool->num_free < num) {
1940                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u\n",
1941                                 num, pool->num_free);
1942                 return -ENOMEM;
1943         }
1944
1945         valid_entry = NULL;
1946         /* Lookup  in free list and find most fit one */
1947         LIST_FOREACH(entry, &pool->free_list, next) {
1948                 if (entry->len >= num) {
1949                         /* Find best one */
1950                         if (entry->len == num) {
1951                                 valid_entry = entry;
1952                                 break;
1953                         }
1954                         if (valid_entry == NULL || valid_entry->len > entry->len)
1955                                 valid_entry = entry;
1956                 }
1957         }
1958
1959         /* Not find one to satisfy the request, return */
1960         if (valid_entry == NULL) {
1961                 PMD_DRV_LOG(ERR, "No valid entry found\n");
1962                 return -ENOMEM;
1963         }
1964         /**
1965          * The entry have equal queue number as requested,
1966          * remove it from alloc_list.
1967          */
1968         if (valid_entry->len == num) {
1969                 LIST_REMOVE(valid_entry, next);
1970         } else {
1971                 /**
1972                  * The entry have more numbers than requested,
1973                  * create a new entry for alloc_list and minus its
1974                  * queue base and number in free_list.
1975                  */
1976                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
1977                 if (entry == NULL) {
1978                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1979                                         "resource pool\n");
1980                         return -ENOMEM;
1981                 }
1982                 entry->base = valid_entry->base;
1983                 entry->len = num;
1984                 valid_entry->base += num;
1985                 valid_entry->len -= num;
1986                 valid_entry = entry;
1987         }
1988
1989         /* Insert it into alloc list, not sorted */
1990         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
1991
1992         pool->num_free -= valid_entry->len;
1993         pool->num_alloc += valid_entry->len;
1994
1995         return (valid_entry->base + pool->base);
1996 }
1997
1998 /**
1999  * bitmap_is_subset - Check whether src2 is subset of src1
2000  **/
2001 static inline int
2002 bitmap_is_subset(uint8_t src1, uint8_t src2)
2003 {
2004         return !((src1 ^ src2) & src2);
2005 }
2006
2007 static int
2008 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2009 {
2010         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011
2012         /* If DCB is not supported, only default TC is supported */
2013         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2014                 PMD_DRV_LOG(ERR, "DCB is not enabled, "
2015                                 "only TC0 is supported\n");
2016                 return -EINVAL;
2017         }
2018
2019         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2020                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2021                         "HW support 0x%x\n", hw->func_caps.enabled_tcmap,
2022                                                         enabled_tcmap);
2023                 return -EINVAL;
2024         }
2025         return I40E_SUCCESS;
2026 }
2027
2028 int
2029 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2030                                 struct i40e_vsi_vlan_pvid_info *info)
2031 {
2032         struct i40e_hw *hw;
2033         struct i40e_vsi_context ctxt;
2034         uint8_t vlan_flags = 0;
2035         int ret;
2036
2037         if (vsi == NULL || info == NULL) {
2038                 PMD_DRV_LOG(ERR, "invalid parameters\n");
2039                 return I40E_ERR_PARAM;
2040         }
2041
2042         if (info->on) {
2043                 vsi->info.pvid = info->config.pvid;
2044                 /**
2045                  * If insert pvid is enabled, only tagged pkts are
2046                  * allowed to be sent out.
2047                  */
2048                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2049                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2050         } else {
2051                 vsi->info.pvid = 0;
2052                 if (info->config.reject.tagged == 0)
2053                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2054
2055                 if (info->config.reject.untagged == 0)
2056                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2057         }
2058         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2059                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2060         vsi->info.port_vlan_flags |= vlan_flags;
2061         vsi->info.valid_sections =
2062                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2063         memset(&ctxt, 0, sizeof(ctxt));
2064         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2065         ctxt.seid = vsi->seid;
2066
2067         hw = I40E_VSI_TO_HW(vsi);
2068         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2069         if (ret != I40E_SUCCESS)
2070                 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2071
2072         return ret;
2073 }
2074
2075 static int
2076 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2077 {
2078         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2079         int i, ret;
2080         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2081
2082         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2083         if (ret != I40E_SUCCESS)
2084                 return ret;
2085
2086         if (!vsi->seid) {
2087                 PMD_DRV_LOG(ERR, "seid not valid\n");
2088                 return -EINVAL;
2089         }
2090
2091         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2092         tc_bw_data.tc_valid_bits = enabled_tcmap;
2093         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2094                 tc_bw_data.tc_bw_credits[i] =
2095                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2096
2097         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2098         if (ret != I40E_SUCCESS) {
2099                 PMD_DRV_LOG(ERR, "Failed to configure TC BW\n");
2100                 return ret;
2101         }
2102
2103         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2104                                         sizeof(vsi->info.qs_handle));
2105         return I40E_SUCCESS;
2106 }
2107
2108 static int
2109 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2110                                  struct i40e_aqc_vsi_properties_data *info,
2111                                  uint8_t enabled_tcmap)
2112 {
2113         int ret, total_tc = 0, i;
2114         uint16_t qpnum_per_tc, bsf, qp_idx;
2115
2116         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2117         if (ret != I40E_SUCCESS)
2118                 return ret;
2119
2120         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2121                 if (enabled_tcmap & (1 << i))
2122                         total_tc++;
2123         vsi->enabled_tc = enabled_tcmap;
2124
2125         /* Number of queues per enabled TC */
2126         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2127         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2128         bsf = rte_bsf32(qpnum_per_tc);
2129
2130         /* Adjust the queue number to actual queues that can be applied */
2131         vsi->nb_qps = qpnum_per_tc * total_tc;
2132
2133         /**
2134          * Configure TC and queue mapping parameters, for enabled TC,
2135          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2136          * default queue will serve it.
2137          */
2138         qp_idx = 0;
2139         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2140                 if (vsi->enabled_tc & (1 << i)) {
2141                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2142                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2143                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2144                         qp_idx += qpnum_per_tc;
2145                 } else
2146                         info->tc_mapping[i] = 0;
2147         }
2148
2149         /* Associate queue number with VSI */
2150         if (vsi->type == I40E_VSI_SRIOV) {
2151                 info->mapping_flags |=
2152                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2153                 for (i = 0; i < vsi->nb_qps; i++)
2154                         info->queue_mapping[i] =
2155                                 rte_cpu_to_le_16(vsi->base_queue + i);
2156         } else {
2157                 info->mapping_flags |=
2158                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2159                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2160         }
2161         info->valid_sections =
2162                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2163
2164         return I40E_SUCCESS;
2165 }
2166
2167 static int
2168 i40e_veb_release(struct i40e_veb *veb)
2169 {
2170         struct i40e_vsi *vsi;
2171         struct i40e_hw *hw;
2172
2173         if (veb == NULL || veb->associate_vsi == NULL)
2174                 return -EINVAL;
2175
2176         if (!TAILQ_EMPTY(&veb->head)) {
2177                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove\n");
2178                 return -EACCES;
2179         }
2180
2181         vsi = veb->associate_vsi;
2182         hw = I40E_VSI_TO_HW(vsi);
2183
2184         vsi->uplink_seid = veb->uplink_seid;
2185         i40e_aq_delete_element(hw, veb->seid, NULL);
2186         rte_free(veb);
2187         vsi->veb = NULL;
2188         return I40E_SUCCESS;
2189 }
2190
2191 /* Setup a veb */
2192 static struct i40e_veb *
2193 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2194 {
2195         struct i40e_veb *veb;
2196         int ret;
2197         struct i40e_hw *hw;
2198
2199         if (NULL == pf || vsi == NULL) {
2200                 PMD_DRV_LOG(ERR, "veb setup failed, "
2201                         "associated VSI shouldn't null\n");
2202                 return NULL;
2203         }
2204         hw = I40E_PF_TO_HW(pf);
2205
2206         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2207         if (!veb) {
2208                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb\n");
2209                 goto fail;
2210         }
2211
2212         veb->associate_vsi = vsi;
2213         TAILQ_INIT(&veb->head);
2214         veb->uplink_seid = vsi->uplink_seid;
2215
2216         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2217                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2218
2219         if (ret != I40E_SUCCESS) {
2220                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d\n",
2221                                         hw->aq.asq_last_status);
2222                 goto fail;
2223         }
2224
2225         /* get statistics index */
2226         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2227                                 &veb->stats_idx, NULL, NULL, NULL);
2228         if (ret != I40E_SUCCESS) {
2229                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d\n",
2230                                                 hw->aq.asq_last_status);
2231                 goto fail;
2232         }
2233
2234         /* Get VEB bandwidth, to be implemented */
2235         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2236         vsi->uplink_seid = veb->seid;
2237
2238         return veb;
2239 fail:
2240         rte_free(veb);
2241         return NULL;
2242 }
2243
2244 int
2245 i40e_vsi_release(struct i40e_vsi *vsi)
2246 {
2247         struct i40e_pf *pf;
2248         struct i40e_hw *hw;
2249         struct i40e_vsi_list *vsi_list;
2250         int ret;
2251         struct i40e_mac_filter *f;
2252
2253         if (!vsi)
2254                 return I40E_SUCCESS;
2255
2256         pf = I40E_VSI_TO_PF(vsi);
2257         hw = I40E_VSI_TO_HW(vsi);
2258
2259         /* VSI has child to attach, release child first */
2260         if (vsi->veb) {
2261                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2262                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2263                                 return -1;
2264                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2265                 }
2266                 i40e_veb_release(vsi->veb);
2267         }
2268
2269         /* Remove all macvlan filters of the VSI */
2270         i40e_vsi_remove_all_macvlan_filter(vsi);
2271         TAILQ_FOREACH(f, &vsi->mac_list, next)
2272                 rte_free(f);
2273
2274         if (vsi->type != I40E_VSI_MAIN) {
2275                 /* Remove vsi from parent's sibling list */
2276                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2277                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL\n");
2278                         return I40E_ERR_PARAM;
2279                 }
2280                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2281                                 &vsi->sib_vsi_list, list);
2282
2283                 /* Remove all switch element of the VSI */
2284                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2285                 if (ret != I40E_SUCCESS)
2286                         PMD_DRV_LOG(ERR, "Failed to delete element\n");
2287         }
2288         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2289
2290         if (vsi->type != I40E_VSI_SRIOV)
2291                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2292         rte_free(vsi);
2293
2294         return I40E_SUCCESS;
2295 }
2296
2297 static int
2298 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2299 {
2300         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2301         struct i40e_aqc_remove_macvlan_element_data def_filter;
2302         int ret;
2303
2304         if (vsi->type != I40E_VSI_MAIN)
2305                 return I40E_ERR_CONFIG;
2306         memset(&def_filter, 0, sizeof(def_filter));
2307         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2308                                         ETH_ADDR_LEN);
2309         def_filter.vlan_tag = 0;
2310         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2311                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2312         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2313         if (ret != I40E_SUCCESS) {
2314                 struct i40e_mac_filter *f;
2315
2316                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2317                                                 "macvlan filter\n");
2318                 /* It needs to add the permanent mac into mac list */
2319                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2320                 if (f == NULL) {
2321                         PMD_DRV_LOG(ERR, "failed to allocate memory\n");
2322                         return I40E_ERR_NO_MEMORY;
2323                 }
2324                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2325                                 ETH_ADDR_LEN);
2326                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2327                 vsi->mac_num++;
2328
2329                 return ret;
2330         }
2331
2332         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2333 }
2334
2335 static int
2336 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2337 {
2338         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2339         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2340         struct i40e_hw *hw = &vsi->adapter->hw;
2341         i40e_status ret;
2342         int i;
2343
2344         memset(&bw_config, 0, sizeof(bw_config));
2345         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2346         if (ret != I40E_SUCCESS) {
2347                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth "
2348                         "configuration %u\n", hw->aq.asq_last_status);
2349                 return ret;
2350         }
2351
2352         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2353         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2354                                         &ets_sla_config, NULL);
2355         if (ret != I40E_SUCCESS) {
2356                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2357                         "configuration %u\n", hw->aq.asq_last_status);
2358                 return ret;
2359         }
2360
2361         /* Not store the info yet, just print out */
2362         PMD_DRV_LOG(INFO, "VSI bw limit:%u\n", bw_config.port_bw_limit);
2363         PMD_DRV_LOG(INFO, "VSI max_bw:%u\n", bw_config.max_bw);
2364         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2365                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u\n", i,
2366                                         ets_sla_config.share_credits[i]);
2367                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u\n", i,
2368                         rte_le_to_cpu_16(ets_sla_config.credits[i]));
2369                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2370                         rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2371                                                                 (i * 4));
2372         }
2373
2374         return 0;
2375 }
2376
2377 /* Setup a VSI */
2378 struct i40e_vsi *
2379 i40e_vsi_setup(struct i40e_pf *pf,
2380                enum i40e_vsi_type type,
2381                struct i40e_vsi *uplink_vsi,
2382                uint16_t user_param)
2383 {
2384         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2385         struct i40e_vsi *vsi;
2386         int ret;
2387         struct i40e_vsi_context ctxt;
2388         struct ether_addr broadcast =
2389                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2390
2391         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2392                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2393                         "VSI link shouldn't be NULL\n");
2394                 return NULL;
2395         }
2396
2397         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2398                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2399                                 "uplink VSI should be NULL\n");
2400                 return NULL;
2401         }
2402
2403         /* If uplink vsi didn't setup VEB, create one first */
2404         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2405                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2406
2407                 if (NULL == uplink_vsi->veb) {
2408                         PMD_DRV_LOG(ERR, "VEB setup failed\n");
2409                         return NULL;
2410                 }
2411         }
2412
2413         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2414         if (!vsi) {
2415                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi\n");
2416                 return NULL;
2417         }
2418         TAILQ_INIT(&vsi->mac_list);
2419         vsi->type = type;
2420         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2421         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2422         vsi->parent_vsi = uplink_vsi;
2423         vsi->user_param = user_param;
2424         /* Allocate queues */
2425         switch (vsi->type) {
2426         case I40E_VSI_MAIN  :
2427                 vsi->nb_qps = pf->lan_nb_qps;
2428                 break;
2429         case I40E_VSI_SRIOV :
2430                 vsi->nb_qps = pf->vf_nb_qps;
2431                 break;
2432         default:
2433                 goto fail_mem;
2434         }
2435         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2436         if (ret < 0) {
2437                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2438                                 vsi->seid, ret);
2439                 goto fail_mem;
2440         }
2441         vsi->base_queue = ret;
2442
2443         /* VF has MSIX interrupt in VF range, don't allocate here */
2444         if (type != I40E_VSI_SRIOV) {
2445                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2446                 if (ret < 0) {
2447                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2448                         goto fail_queue_alloc;
2449                 }
2450                 vsi->msix_intr = ret;
2451         } else
2452                 vsi->msix_intr = 0;
2453         /* Add VSI */
2454         if (type == I40E_VSI_MAIN) {
2455                 /* For main VSI, no need to add since it's default one */
2456                 vsi->uplink_seid = pf->mac_seid;
2457                 vsi->seid = pf->main_vsi_seid;
2458                 /* Bind queues with specific MSIX interrupt */
2459                 /**
2460                  * Needs 2 interrupt at least, one for misc cause which will
2461                  * enabled from OS side, Another for queues binding the
2462                  * interrupt from device side only.
2463                  */
2464
2465                 /* Get default VSI parameters from hardware */
2466                 memset(&ctxt, 0, sizeof(ctxt));
2467                 ctxt.seid = vsi->seid;
2468                 ctxt.pf_num = hw->pf_id;
2469                 ctxt.uplink_seid = vsi->uplink_seid;
2470                 ctxt.vf_num = 0;
2471                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2472                 if (ret != I40E_SUCCESS) {
2473                         PMD_DRV_LOG(ERR, "Failed to get VSI params\n");
2474                         goto fail_msix_alloc;
2475                 }
2476                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2477                         sizeof(struct i40e_aqc_vsi_properties_data));
2478                 vsi->vsi_id = ctxt.vsi_number;
2479                 vsi->info.valid_sections = 0;
2480
2481                 /* Configure tc, enabled TC0 only */
2482                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2483                         I40E_SUCCESS) {
2484                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth\n");
2485                         goto fail_msix_alloc;
2486                 }
2487
2488                 /* TC, queue mapping */
2489                 memset(&ctxt, 0, sizeof(ctxt));
2490                 vsi->info.valid_sections |=
2491                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2492                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2493                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2494                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2495                         sizeof(struct i40e_aqc_vsi_properties_data));
2496                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2497                                                 I40E_DEFAULT_TCMAP);
2498                 if (ret != I40E_SUCCESS) {
2499                         PMD_DRV_LOG(ERR, "Failed to configure "
2500                                         "TC queue mapping\n");
2501                         goto fail_msix_alloc;
2502                 }
2503                 ctxt.seid = vsi->seid;
2504                 ctxt.pf_num = hw->pf_id;
2505                 ctxt.uplink_seid = vsi->uplink_seid;
2506                 ctxt.vf_num = 0;
2507
2508                 /* Update VSI parameters */
2509                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2510                 if (ret != I40E_SUCCESS) {
2511                         PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2512                         goto fail_msix_alloc;
2513                 }
2514
2515                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2516                                                 sizeof(vsi->info.tc_mapping));
2517                 (void)rte_memcpy(&vsi->info.queue_mapping,
2518                                 &ctxt.info.queue_mapping,
2519                         sizeof(vsi->info.queue_mapping));
2520                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2521                 vsi->info.valid_sections = 0;
2522
2523                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2524                                 ETH_ADDR_LEN);
2525
2526                 /**
2527                  * Updating default filter settings are necessary to prevent
2528                  * reception of tagged packets.
2529                  * Some old firmware configurations load a default macvlan
2530                  * filter which accepts both tagged and untagged packets.
2531                  * The updating is to use a normal filter instead if needed.
2532                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2533                  * The firmware with correct configurations load the default
2534                  * macvlan filter which is expected and cannot be removed.
2535                  */
2536                 i40e_update_default_filter_setting(vsi);
2537         } else if (type == I40E_VSI_SRIOV) {
2538                 memset(&ctxt, 0, sizeof(ctxt));
2539                 /**
2540                  * For other VSI, the uplink_seid equals to uplink VSI's
2541                  * uplink_seid since they share same VEB
2542                  */
2543                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2544                 ctxt.pf_num = hw->pf_id;
2545                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2546                 ctxt.uplink_seid = vsi->uplink_seid;
2547                 ctxt.connection_type = 0x1;
2548                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2549
2550                 /* Configure switch ID */
2551                 ctxt.info.valid_sections |=
2552                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2553                 ctxt.info.switch_id =
2554                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2555                 /* Configure port/vlan */
2556                 ctxt.info.valid_sections |=
2557                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2558                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2559                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2560                                                 I40E_DEFAULT_TCMAP);
2561                 if (ret != I40E_SUCCESS) {
2562                         PMD_DRV_LOG(ERR, "Failed to configure "
2563                                         "TC queue mapping\n");
2564                         goto fail_msix_alloc;
2565                 }
2566                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2567                 ctxt.info.valid_sections |=
2568                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2569                 /**
2570                  * Since VSI is not created yet, only configure parameter,
2571                  * will add vsi below.
2572                  */
2573         }
2574         else {
2575                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet\n");
2576                 goto fail_msix_alloc;
2577         }
2578
2579         if (vsi->type != I40E_VSI_MAIN) {
2580                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2581                 if (ret) {
2582                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d\n",
2583                                  hw->aq.asq_last_status);
2584                         goto fail_msix_alloc;
2585                 }
2586                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2587                 vsi->info.valid_sections = 0;
2588                 vsi->seid = ctxt.seid;
2589                 vsi->vsi_id = ctxt.vsi_number;
2590                 vsi->sib_vsi_list.vsi = vsi;
2591                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2592                                 &vsi->sib_vsi_list, list);
2593         }
2594
2595         /* MAC/VLAN configuration */
2596         ret = i40e_vsi_add_mac(vsi, &broadcast);
2597         if (ret != I40E_SUCCESS) {
2598                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
2599                 goto fail_msix_alloc;
2600         }
2601
2602         /* Get VSI BW information */
2603         i40e_vsi_dump_bw_config(vsi);
2604         return vsi;
2605 fail_msix_alloc:
2606         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2607 fail_queue_alloc:
2608         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2609 fail_mem:
2610         rte_free(vsi);
2611         return NULL;
2612 }
2613
2614 /* Configure vlan stripping on or off */
2615 int
2616 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2617 {
2618         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2619         struct i40e_vsi_context ctxt;
2620         uint8_t vlan_flags;
2621         int ret = I40E_SUCCESS;
2622
2623         /* Check if it has been already on or off */
2624         if (vsi->info.valid_sections &
2625                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2626                 if (on) {
2627                         if ((vsi->info.port_vlan_flags &
2628                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2629                                 return 0; /* already on */
2630                 } else {
2631                         if ((vsi->info.port_vlan_flags &
2632                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2633                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2634                                 return 0; /* already off */
2635                 }
2636         }
2637
2638         if (on)
2639                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2640         else
2641                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2642         vsi->info.valid_sections =
2643                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2644         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2645         vsi->info.port_vlan_flags |= vlan_flags;
2646         ctxt.seid = vsi->seid;
2647         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2648         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2649         if (ret)
2650                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping\n",
2651                                                 on ? "enable" : "disable");
2652
2653         return ret;
2654 }
2655
2656 static int
2657 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2658 {
2659         struct rte_eth_dev_data *data = dev->data;
2660         int ret;
2661
2662         /* Apply vlan offload setting */
2663         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2664
2665         /* Apply double-vlan setting, not implemented yet */
2666
2667         /* Apply pvid setting */
2668         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2669                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2670         if (ret)
2671                 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
2672
2673         return ret;
2674 }
2675
2676 static int
2677 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2678 {
2679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2680
2681         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2682 }
2683
2684 static int
2685 i40e_update_flow_control(struct i40e_hw *hw)
2686 {
2687 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2688         struct i40e_link_status link_status;
2689         uint32_t rxfc = 0, txfc = 0, reg;
2690         uint8_t an_info;
2691         int ret;
2692
2693         memset(&link_status, 0, sizeof(link_status));
2694         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2695         if (ret != I40E_SUCCESS) {
2696                 PMD_DRV_LOG(ERR, "Failed to get link status information\n");
2697                 goto write_reg; /* Disable flow control */
2698         }
2699
2700         an_info = hw->phy.link_info.an_info;
2701         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2702                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed\n");
2703                 ret = I40E_ERR_NOT_READY;
2704                 goto write_reg; /* Disable flow control */
2705         }
2706         /**
2707          * If link auto negotiation is enabled, flow control needs to
2708          * be configured according to it
2709          */
2710         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2711         case I40E_LINK_PAUSE_RXTX:
2712                 rxfc = 1;
2713                 txfc = 1;
2714                 hw->fc.current_mode = I40E_FC_FULL;
2715                 break;
2716         case I40E_AQ_LINK_PAUSE_RX:
2717                 rxfc = 1;
2718                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2719                 break;
2720         case I40E_AQ_LINK_PAUSE_TX:
2721                 txfc = 1;
2722                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2723                 break;
2724         default:
2725                 hw->fc.current_mode = I40E_FC_NONE;
2726                 break;
2727         }
2728
2729 write_reg:
2730         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2731                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2732         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2733         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2734         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2735         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2736
2737         return ret;
2738 }
2739
2740 /* PF setup */
2741 static int
2742 i40e_pf_setup(struct i40e_pf *pf)
2743 {
2744         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2745         struct i40e_filter_control_settings settings;
2746         struct rte_eth_dev_data *dev_data = pf->dev_data;
2747         struct i40e_vsi *vsi;
2748         int ret;
2749
2750         /* Clear all stats counters */
2751         pf->offset_loaded = FALSE;
2752         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2753         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2754
2755         ret = i40e_pf_get_switch_config(pf);
2756         if (ret != I40E_SUCCESS) {
2757                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2758                 return ret;
2759         }
2760
2761         /* VSI setup */
2762         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2763         if (!vsi) {
2764                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2765                 return I40E_ERR_NOT_READY;
2766         }
2767         pf->main_vsi = vsi;
2768         dev_data->nb_rx_queues = vsi->nb_qps;
2769         dev_data->nb_tx_queues = vsi->nb_qps;
2770
2771         /* Configure filter control */
2772         memset(&settings, 0, sizeof(settings));
2773         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2774         /* Enable ethtype and macvlan filters */
2775         settings.enable_ethtype = TRUE;
2776         settings.enable_macvlan = TRUE;
2777         ret = i40e_set_filter_control(hw, &settings);
2778         if (ret)
2779                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2780                                                                 ret);
2781
2782         /* Update flow control according to the auto negotiation */
2783         i40e_update_flow_control(hw);
2784
2785         return I40E_SUCCESS;
2786 }
2787
2788 int
2789 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2790 {
2791         uint32_t reg;
2792         uint16_t j;
2793
2794         /**
2795          * Set or clear TX Queue Disable flags,
2796          * which is required by hardware.
2797          */
2798         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2799         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2800
2801         /* Wait until the request is finished */
2802         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2803                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2804                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2805                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2806                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2807                                                         & 0x1))) {
2808                         break;
2809                 }
2810         }
2811         if (on) {
2812                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2813                         return I40E_SUCCESS; /* already on, skip next steps */
2814
2815                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2816                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2817         } else {
2818                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2819                         return I40E_SUCCESS; /* already off, skip next steps */
2820                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2821         }
2822         /* Write the register */
2823         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
2824         /* Check the result */
2825         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2826                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2827                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2828                 if (on) {
2829                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2830                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
2831                                 break;
2832                 } else {
2833                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2834                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2835                                 break;
2836                 }
2837         }
2838         /* Check if it is timeout */
2839         if (j >= I40E_CHK_Q_ENA_COUNT) {
2840                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]\n",
2841                         (on ? "enable" : "disable"), q_idx);
2842                 return I40E_ERR_TIMEOUT;
2843         }
2844
2845         return I40E_SUCCESS;
2846 }
2847
2848 /* Swith on or off the tx queues */
2849 static int
2850 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
2851 {
2852         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2853         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2854         struct i40e_tx_queue *txq;
2855         uint16_t i, pf_q;
2856         int ret;
2857
2858         pf_q = vsi->base_queue;
2859         for (i = 0; i < dev_data->nb_tx_queues; i++, pf_q++) {
2860                 txq = dev_data->tx_queues[i];
2861                 if (!txq->q_set)
2862                         continue; /* Queue not configured */
2863                 ret = i40e_switch_tx_queue(hw, pf_q, on);
2864                 if ( ret != I40E_SUCCESS)
2865                         return ret;
2866         }
2867
2868         return I40E_SUCCESS;
2869 }
2870
2871 int
2872 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2873 {
2874         uint32_t reg;
2875         uint16_t j;
2876
2877         /* Wait until the request is finished */
2878         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2879                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2880                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2881                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2882                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
2883                         break;
2884         }
2885
2886         if (on) {
2887                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
2888                         return I40E_SUCCESS; /* Already on, skip next steps */
2889                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
2890         } else {
2891                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2892                         return I40E_SUCCESS; /* Already off, skip next steps */
2893                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
2894         }
2895
2896         /* Write the register */
2897         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
2898         /* Check the result */
2899         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2900                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2901                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
2902                 if (on) {
2903                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2904                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
2905                                 break;
2906                 } else {
2907                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
2908                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
2909                                 break;
2910                 }
2911         }
2912
2913         /* Check if it is timeout */
2914         if (j >= I40E_CHK_Q_ENA_COUNT) {
2915                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]\n",
2916                         (on ? "enable" : "disable"), q_idx);
2917                 return I40E_ERR_TIMEOUT;
2918         }
2919
2920         return I40E_SUCCESS;
2921 }
2922 /* Switch on or off the rx queues */
2923 static int
2924 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
2925 {
2926         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2927         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2928         struct i40e_rx_queue *rxq;
2929         uint16_t i, pf_q;
2930         int ret;
2931
2932         pf_q = vsi->base_queue;
2933         for (i = 0; i < dev_data->nb_rx_queues; i++, pf_q++) {
2934                 rxq = dev_data->rx_queues[i];
2935                 if (!rxq->q_set)
2936                         continue; /* Queue not configured */
2937                 ret = i40e_switch_rx_queue(hw, pf_q, on);
2938                 if ( ret != I40E_SUCCESS)
2939                         return ret;
2940         }
2941
2942         return I40E_SUCCESS;
2943 }
2944
2945 /* Switch on or off all the rx/tx queues */
2946 int
2947 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
2948 {
2949         int ret;
2950
2951         if (on) {
2952                 /* enable rx queues before enabling tx queues */
2953                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2954                 if (ret) {
2955                         PMD_DRV_LOG(ERR, "Failed to switch rx queues\n");
2956                         return ret;
2957                 }
2958                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2959         } else {
2960                 /* Stop tx queues before stopping rx queues */
2961                 ret = i40e_vsi_switch_tx_queues(vsi, on);
2962                 if (ret) {
2963                         PMD_DRV_LOG(ERR, "Failed to switch tx queues\n");
2964                         return ret;
2965                 }
2966                 ret = i40e_vsi_switch_rx_queues(vsi, on);
2967         }
2968
2969         return ret;
2970 }
2971
2972 /* Initialize VSI for TX */
2973 static int
2974 i40e_vsi_tx_init(struct i40e_vsi *vsi)
2975 {
2976         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2977         struct rte_eth_dev_data *data = pf->dev_data;
2978         uint16_t i;
2979         uint32_t ret = I40E_SUCCESS;
2980
2981         for (i = 0; i < data->nb_tx_queues; i++) {
2982                 ret = i40e_tx_queue_init(data->tx_queues[i]);
2983                 if (ret != I40E_SUCCESS)
2984                         break;
2985         }
2986
2987         return ret;
2988 }
2989
2990 /* Initialize VSI for RX */
2991 static int
2992 i40e_vsi_rx_init(struct i40e_vsi *vsi)
2993 {
2994         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2995         struct rte_eth_dev_data *data = pf->dev_data;
2996         int ret = I40E_SUCCESS;
2997         uint16_t i;
2998
2999         i40e_pf_config_mq_rx(pf);
3000         for (i = 0; i < data->nb_rx_queues; i++) {
3001                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3002                 if (ret != I40E_SUCCESS) {
3003                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3004                                         "initialization\n");
3005                         break;
3006                 }
3007         }
3008
3009         return ret;
3010 }
3011
3012 /* Initialize VSI */
3013 static int
3014 i40e_vsi_init(struct i40e_vsi *vsi)
3015 {
3016         int err;
3017
3018         err = i40e_vsi_tx_init(vsi);
3019         if (err) {
3020                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization\n");
3021                 return err;
3022         }
3023         err = i40e_vsi_rx_init(vsi);
3024         if (err) {
3025                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization\n");
3026                 return err;
3027         }
3028
3029         return err;
3030 }
3031
3032 static void
3033 i40e_stat_update_32(struct i40e_hw *hw,
3034                    uint32_t reg,
3035                    bool offset_loaded,
3036                    uint64_t *offset,
3037                    uint64_t *stat)
3038 {
3039         uint64_t new_data;
3040
3041         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3042         if (!offset_loaded)
3043                 *offset = new_data;
3044
3045         if (new_data >= *offset)
3046                 *stat = (uint64_t)(new_data - *offset);
3047         else
3048                 *stat = (uint64_t)((new_data +
3049                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3050 }
3051
3052 static void
3053 i40e_stat_update_48(struct i40e_hw *hw,
3054                    uint32_t hireg,
3055                    uint32_t loreg,
3056                    bool offset_loaded,
3057                    uint64_t *offset,
3058                    uint64_t *stat)
3059 {
3060         uint64_t new_data;
3061
3062         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3063         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3064                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3065
3066         if (!offset_loaded)
3067                 *offset = new_data;
3068
3069         if (new_data >= *offset)
3070                 *stat = new_data - *offset;
3071         else
3072                 *stat = (uint64_t)((new_data +
3073                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3074
3075         *stat &= I40E_48_BIT_MASK;
3076 }
3077
3078 /* Disable IRQ0 */
3079 void
3080 i40e_pf_disable_irq0(struct i40e_hw *hw)
3081 {
3082         /* Disable all interrupt types */
3083         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3084         I40E_WRITE_FLUSH(hw);
3085 }
3086
3087 /* Enable IRQ0 */
3088 void
3089 i40e_pf_enable_irq0(struct i40e_hw *hw)
3090 {
3091         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3092                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3093                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3094                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3095         I40E_WRITE_FLUSH(hw);
3096 }
3097
3098 static void
3099 i40e_pf_config_irq0(struct i40e_hw *hw)
3100 {
3101         uint32_t enable;
3102
3103         /* read pending request and disable first */
3104         i40e_pf_disable_irq0(hw);
3105         /**
3106          * Enable all interrupt error options to detect possible errors,
3107          * other informative int are ignored
3108          */
3109         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3110                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3111                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3112                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3113                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3114                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3115                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3116                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3117
3118         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3119         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3120                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3121
3122         /* Link no queues with irq0 */
3123         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3124                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3125 }
3126
3127 static void
3128 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3129 {
3130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132         int i;
3133         uint16_t abs_vf_id;
3134         uint32_t index, offset, val;
3135
3136         if (!pf->vfs)
3137                 return;
3138         /**
3139          * Try to find which VF trigger a reset, use absolute VF id to access
3140          * since the reg is global register.
3141          */
3142         for (i = 0; i < pf->vf_num; i++) {
3143                 abs_vf_id = hw->func_caps.vf_base_id + i;
3144                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3145                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3146                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3147                 /* VFR event occured */
3148                 if (val & (0x1 << offset)) {
3149                         int ret;
3150
3151                         /* Clear the event first */
3152                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3153                                                         (0x1 << offset));
3154                         PMD_DRV_LOG(INFO, "VF %u reset occured\n", abs_vf_id);
3155                         /**
3156                          * Only notify a VF reset event occured,
3157                          * don't trigger another SW reset
3158                          */
3159                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3160                         if (ret != I40E_SUCCESS)
3161                                 PMD_DRV_LOG(ERR, "Failed to do VF reset\n");
3162                 }
3163         }
3164 }
3165
3166 static void
3167 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3168 {
3169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3170         struct i40e_arq_event_info info;
3171         uint16_t pending, opcode;
3172         int ret;
3173
3174         info.msg_size = I40E_AQ_BUF_SZ;
3175         info.msg_buf = rte_zmalloc("msg_buffer", I40E_AQ_BUF_SZ, 0);
3176         if (!info.msg_buf) {
3177                 PMD_DRV_LOG(ERR, "Failed to allocate mem\n");
3178                 return;
3179         }
3180
3181         pending = 1;
3182         while (pending) {
3183                 ret = i40e_clean_arq_element(hw, &info, &pending);
3184
3185                 if (ret != I40E_SUCCESS) {
3186                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3187                                 "aq_err: %u\n", hw->aq.asq_last_status);
3188                         break;
3189                 }
3190                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3191
3192                 switch (opcode) {
3193                 case i40e_aqc_opc_send_msg_to_pf:
3194                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3195                         i40e_pf_host_handle_vf_msg(dev,
3196                                         rte_le_to_cpu_16(info.desc.retval),
3197                                         rte_le_to_cpu_32(info.desc.cookie_high),
3198                                         rte_le_to_cpu_32(info.desc.cookie_low),
3199                                         info.msg_buf,
3200                                         info.msg_size);
3201                         break;
3202                 default:
3203                         PMD_DRV_LOG(ERR, "Request %u is not supported yet\n",
3204                                 opcode);
3205                         break;
3206                 }
3207                 /* Reset the buffer after processing one */
3208                 info.msg_size = I40E_AQ_BUF_SZ;
3209         }
3210         rte_free(info.msg_buf);
3211 }
3212
3213 /**
3214  * Interrupt handler triggered by NIC  for handling
3215  * specific interrupt.
3216  *
3217  * @param handle
3218  *  Pointer to interrupt handle.
3219  * @param param
3220  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3221  *
3222  * @return
3223  *  void
3224  */
3225 static void
3226 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3227                            void *param)
3228 {
3229         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3230         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231         uint32_t cause, enable;
3232
3233         i40e_pf_disable_irq0(hw);
3234
3235         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3236         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3237
3238         /* Shared IRQ case, return */
3239         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3240                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3241                         "no INT event to process\n", hw->pf_id);
3242                 goto done;
3243         }
3244
3245         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3246                 PMD_DRV_LOG(INFO, "INT:Link status changed\n");
3247                 i40e_dev_link_update(dev, 0);
3248         }
3249
3250         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3251                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error\n");
3252
3253         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3254                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected\n");
3255
3256         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3257                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested\n");
3258
3259         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3260                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured\n");
3261
3262         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3263                 PMD_DRV_LOG(INFO, "INT:HMC error occured\n");
3264
3265         /* Add processing func to deal with VF reset vent */
3266         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3267                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3268                 i40e_dev_handle_vfr_event(dev);
3269         }
3270         /* Find admin queue event */
3271         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3272                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3273                 i40e_dev_handle_aq_msg(dev);
3274         }
3275
3276 done:
3277         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3278         /* Re-enable interrupt from device side */
3279         i40e_pf_enable_irq0(hw);
3280         /* Re-enable interrupt from host side */
3281         rte_intr_enable(&(dev->pci_dev->intr_handle));
3282 }
3283
3284 static int
3285 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3286                          struct i40e_macvlan_filter *filter,
3287                          int total)
3288 {
3289         int ele_num, ele_buff_size;
3290         int num, actual_num, i;
3291         int ret = I40E_SUCCESS;
3292         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3293         struct i40e_aqc_add_macvlan_element_data *req_list;
3294
3295         if (filter == NULL  || total == 0)
3296                 return I40E_ERR_PARAM;
3297         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3298         ele_buff_size = hw->aq.asq_buf_size;
3299
3300         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3301         if (req_list == NULL) {
3302                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3303                 return I40E_ERR_NO_MEMORY;
3304         }
3305
3306         num = 0;
3307         do {
3308                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3309                 memset(req_list, 0, ele_buff_size);
3310
3311                 for (i = 0; i < actual_num; i++) {
3312                         (void)rte_memcpy(req_list[i].mac_addr,
3313                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3314                         req_list[i].vlan_tag =
3315                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3316                         req_list[i].flags = rte_cpu_to_le_16(\
3317                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3318                         req_list[i].queue_number = 0;
3319                 }
3320
3321                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3322                                                 actual_num, NULL);
3323                 if (ret != I40E_SUCCESS) {
3324                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter\n");
3325                         goto DONE;
3326                 }
3327                 num += actual_num;
3328         } while (num < total);
3329
3330 DONE:
3331         rte_free(req_list);
3332         return ret;
3333 }
3334
3335 static int
3336 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3337                             struct i40e_macvlan_filter *filter,
3338                             int total)
3339 {
3340         int ele_num, ele_buff_size;
3341         int num, actual_num, i;
3342         int ret = I40E_SUCCESS;
3343         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3344         struct i40e_aqc_remove_macvlan_element_data *req_list;
3345
3346         if (filter == NULL  || total == 0)
3347                 return I40E_ERR_PARAM;
3348
3349         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3350         ele_buff_size = hw->aq.asq_buf_size;
3351
3352         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3353         if (req_list == NULL) {
3354                 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3355                 return I40E_ERR_NO_MEMORY;
3356         }
3357
3358         num = 0;
3359         do {
3360                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3361                 memset(req_list, 0, ele_buff_size);
3362
3363                 for (i = 0; i < actual_num; i++) {
3364                         (void)rte_memcpy(req_list[i].mac_addr,
3365                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3366                         req_list[i].vlan_tag =
3367                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3368                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3369                 }
3370
3371                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3372                                                 actual_num, NULL);
3373                 if (ret != I40E_SUCCESS) {
3374                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter\n");
3375                         goto DONE;
3376                 }
3377                 num += actual_num;
3378         } while (num < total);
3379
3380 DONE:
3381         rte_free(req_list);
3382         return ret;
3383 }
3384
3385 /* Find out specific MAC filter */
3386 static struct i40e_mac_filter *
3387 i40e_find_mac_filter(struct i40e_vsi *vsi,
3388                          struct ether_addr *macaddr)
3389 {
3390         struct i40e_mac_filter *f;
3391
3392         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3393                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3394                         return f;
3395         }
3396
3397         return NULL;
3398 }
3399
3400 static bool
3401 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3402                          uint16_t vlan_id)
3403 {
3404         uint32_t vid_idx, vid_bit;
3405
3406         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3407         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3408
3409         if (vsi->vfta[vid_idx] & vid_bit)
3410                 return 1;
3411         else
3412                 return 0;
3413 }
3414
3415 static void
3416 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3417                          uint16_t vlan_id, bool on)
3418 {
3419         uint32_t vid_idx, vid_bit;
3420
3421 #define UINT32_BIT_MASK      0x1F
3422 #define VALID_VLAN_BIT_MASK  0xFFF
3423         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3424          *  element first, then find the bits it belongs to
3425          */
3426         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3427                   sizeof(uint32_t));
3428         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3429
3430         if (on)
3431                 vsi->vfta[vid_idx] |= vid_bit;
3432         else
3433                 vsi->vfta[vid_idx] &= ~vid_bit;
3434 }
3435
3436 /**
3437  * Find all vlan options for specific mac addr,
3438  * return with actual vlan found.
3439  */
3440 static inline int
3441 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3442                            struct i40e_macvlan_filter *mv_f,
3443                            int num, struct ether_addr *addr)
3444 {
3445         int i;
3446         uint32_t j, k;
3447
3448         /**
3449          * Not to use i40e_find_vlan_filter to decrease the loop time,
3450          * although the code looks complex.
3451           */
3452         if (num < vsi->vlan_num)
3453                 return I40E_ERR_PARAM;
3454
3455         i = 0;
3456         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3457                 if (vsi->vfta[j]) {
3458                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3459                                 if (vsi->vfta[j] & (1 << k)) {
3460                                         if (i > num - 1) {
3461                                                 PMD_DRV_LOG(ERR, "vlan number "
3462                                                                 "not match\n");
3463                                                 return I40E_ERR_PARAM;
3464                                         }
3465                                         (void)rte_memcpy(&mv_f[i].macaddr,
3466                                                         addr, ETH_ADDR_LEN);
3467                                         mv_f[i].vlan_id =
3468                                                 j * I40E_UINT32_BIT_SIZE + k;
3469                                         i++;
3470                                 }
3471                         }
3472                 }
3473         }
3474         return I40E_SUCCESS;
3475 }
3476
3477 static inline int
3478 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3479                            struct i40e_macvlan_filter *mv_f,
3480                            int num,
3481                            uint16_t vlan)
3482 {
3483         int i = 0;
3484         struct i40e_mac_filter *f;
3485
3486         if (num < vsi->mac_num)
3487                 return I40E_ERR_PARAM;
3488
3489         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3490                 if (i > num - 1) {
3491                         PMD_DRV_LOG(ERR, "buffer number not match\n");
3492                         return I40E_ERR_PARAM;
3493                 }
3494                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3495                 mv_f[i].vlan_id = vlan;
3496                 i++;
3497         }
3498
3499         return I40E_SUCCESS;
3500 }
3501
3502 static int
3503 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3504 {
3505         int i, num;
3506         struct i40e_mac_filter *f;
3507         struct i40e_macvlan_filter *mv_f;
3508         int ret = I40E_SUCCESS;
3509
3510         if (vsi == NULL || vsi->mac_num == 0)
3511                 return I40E_ERR_PARAM;
3512
3513         /* Case that no vlan is set */
3514         if (vsi->vlan_num == 0)
3515                 num = vsi->mac_num;
3516         else
3517                 num = vsi->mac_num * vsi->vlan_num;
3518
3519         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3520         if (mv_f == NULL) {
3521                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3522                 return I40E_ERR_NO_MEMORY;
3523         }
3524
3525         i = 0;
3526         if (vsi->vlan_num == 0) {
3527                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3528                         (void)rte_memcpy(&mv_f[i].macaddr,
3529                                 &f->macaddr, ETH_ADDR_LEN);
3530                         mv_f[i].vlan_id = 0;
3531                         i++;
3532                 }
3533         } else {
3534                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3535                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3536                                         vsi->vlan_num, &f->macaddr);
3537                         if (ret != I40E_SUCCESS)
3538                                 goto DONE;
3539                         i += vsi->vlan_num;
3540                 }
3541         }
3542
3543         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3544 DONE:
3545         rte_free(mv_f);
3546
3547         return ret;
3548 }
3549
3550 int
3551 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3552 {
3553         struct i40e_macvlan_filter *mv_f;
3554         int mac_num;
3555         int ret = I40E_SUCCESS;
3556
3557         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3558                 return I40E_ERR_PARAM;
3559
3560         /* If it's already set, just return */
3561         if (i40e_find_vlan_filter(vsi,vlan))
3562                 return I40E_SUCCESS;
3563
3564         mac_num = vsi->mac_num;
3565
3566         if (mac_num == 0) {
3567                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3568                 return I40E_ERR_PARAM;
3569         }
3570
3571         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3572
3573         if (mv_f == NULL) {
3574                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3575                 return I40E_ERR_NO_MEMORY;
3576         }
3577
3578         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3579
3580         if (ret != I40E_SUCCESS)
3581                 goto DONE;
3582
3583         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3584
3585         if (ret != I40E_SUCCESS)
3586                 goto DONE;
3587
3588         i40e_set_vlan_filter(vsi, vlan, 1);
3589
3590         vsi->vlan_num++;
3591         ret = I40E_SUCCESS;
3592 DONE:
3593         rte_free(mv_f);
3594         return ret;
3595 }
3596
3597 int
3598 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3599 {
3600         struct i40e_macvlan_filter *mv_f;
3601         int mac_num;
3602         int ret = I40E_SUCCESS;
3603
3604         /**
3605          * Vlan 0 is the generic filter for untagged packets
3606          * and can't be removed.
3607          */
3608         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3609                 return I40E_ERR_PARAM;
3610
3611         /* If can't find it, just return */
3612         if (!i40e_find_vlan_filter(vsi, vlan))
3613                 return I40E_ERR_PARAM;
3614
3615         mac_num = vsi->mac_num;
3616
3617         if (mac_num == 0) {
3618                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3619                 return I40E_ERR_PARAM;
3620         }
3621
3622         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3623
3624         if (mv_f == NULL) {
3625                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3626                 return I40E_ERR_NO_MEMORY;
3627         }
3628
3629         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3630
3631         if (ret != I40E_SUCCESS)
3632                 goto DONE;
3633
3634         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3635
3636         if (ret != I40E_SUCCESS)
3637                 goto DONE;
3638
3639         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3640         if (vsi->vlan_num == 1) {
3641                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3642                 if (ret != I40E_SUCCESS)
3643                         goto DONE;
3644
3645                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3646                 if (ret != I40E_SUCCESS)
3647                         goto DONE;
3648         }
3649
3650         i40e_set_vlan_filter(vsi, vlan, 0);
3651
3652         vsi->vlan_num--;
3653         ret = I40E_SUCCESS;
3654 DONE:
3655         rte_free(mv_f);
3656         return ret;
3657 }
3658
3659 int
3660 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3661 {
3662         struct i40e_mac_filter *f;
3663         struct i40e_macvlan_filter *mv_f;
3664         int vlan_num;
3665         int ret = I40E_SUCCESS;
3666
3667         /* If it's add and we've config it, return */
3668         f = i40e_find_mac_filter(vsi, addr);
3669         if (f != NULL)
3670                 return I40E_SUCCESS;
3671
3672         /**
3673          * If vlan_num is 0, that's the first time to add mac,
3674          * set mask for vlan_id 0.
3675          */
3676         if (vsi->vlan_num == 0) {
3677                 i40e_set_vlan_filter(vsi, 0, 1);
3678                 vsi->vlan_num = 1;
3679         }
3680
3681         vlan_num = vsi->vlan_num;
3682
3683         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3684         if (mv_f == NULL) {
3685                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3686                 return I40E_ERR_NO_MEMORY;
3687         }
3688
3689         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3690         if (ret != I40E_SUCCESS)
3691                 goto DONE;
3692
3693         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3694         if (ret != I40E_SUCCESS)
3695                 goto DONE;
3696
3697         /* Add the mac addr into mac list */
3698         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3699         if (f == NULL) {
3700                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3701                 ret = I40E_ERR_NO_MEMORY;
3702                 goto DONE;
3703         }
3704         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3705         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3706         vsi->mac_num++;
3707
3708         ret = I40E_SUCCESS;
3709 DONE:
3710         rte_free(mv_f);
3711
3712         return ret;
3713 }
3714
3715 int
3716 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3717 {
3718         struct i40e_mac_filter *f;
3719         struct i40e_macvlan_filter *mv_f;
3720         int vlan_num;
3721         int ret = I40E_SUCCESS;
3722
3723         /* Can't find it, return an error */
3724         f = i40e_find_mac_filter(vsi, addr);
3725         if (f == NULL)
3726                 return I40E_ERR_PARAM;
3727
3728         vlan_num = vsi->vlan_num;
3729         if (vlan_num == 0) {
3730                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
3731                 return I40E_ERR_PARAM;
3732         }
3733         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3734         if (mv_f == NULL) {
3735                 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3736                 return I40E_ERR_NO_MEMORY;
3737         }
3738
3739         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3740         if (ret != I40E_SUCCESS)
3741                 goto DONE;
3742
3743         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3744         if (ret != I40E_SUCCESS)
3745                 goto DONE;
3746
3747         /* Remove the mac addr into mac list */
3748         TAILQ_REMOVE(&vsi->mac_list, f, next);
3749         rte_free(f);
3750         vsi->mac_num--;
3751
3752         ret = I40E_SUCCESS;
3753 DONE:
3754         rte_free(mv_f);
3755         return ret;
3756 }
3757
3758 /* Configure hash enable flags for RSS */
3759 static uint64_t
3760 i40e_config_hena(uint64_t flags)
3761 {
3762         uint64_t hena = 0;
3763
3764         if (!flags)
3765                 return hena;
3766
3767         if (flags & ETH_RSS_NONF_IPV4_UDP)
3768                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3769         if (flags & ETH_RSS_NONF_IPV4_TCP)
3770                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3771         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3772                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3773         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3774                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3775         if (flags & ETH_RSS_FRAG_IPV4)
3776                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3777         if (flags & ETH_RSS_NONF_IPV6_UDP)
3778                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3779         if (flags & ETH_RSS_NONF_IPV6_TCP)
3780                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3781         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3782                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3783         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3784                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3785         if (flags & ETH_RSS_FRAG_IPV6)
3786                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3787         if (flags & ETH_RSS_L2_PAYLOAD)
3788                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3789
3790         return hena;
3791 }
3792
3793 /* Parse the hash enable flags */
3794 static uint64_t
3795 i40e_parse_hena(uint64_t flags)
3796 {
3797         uint64_t rss_hf = 0;
3798
3799         if (!flags)
3800                 return rss_hf;
3801
3802         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3803                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3804         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3805                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3806         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3807                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3808         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3809                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3810         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3811                 rss_hf |= ETH_RSS_FRAG_IPV4;
3812         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3813                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3814         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
3815                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
3816         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
3817                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
3818         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
3819                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
3820         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
3821                 rss_hf |= ETH_RSS_FRAG_IPV6;
3822         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
3823                 rss_hf |= ETH_RSS_L2_PAYLOAD;
3824
3825         return rss_hf;
3826 }
3827
3828 /* Disable RSS */
3829 static void
3830 i40e_pf_disable_rss(struct i40e_pf *pf)
3831 {
3832         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3833         uint64_t hena;
3834
3835         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3836         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3837         hena &= ~I40E_RSS_HENA_ALL;
3838         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3839         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3840         I40E_WRITE_FLUSH(hw);
3841 }
3842
3843 static int
3844 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
3845 {
3846         uint32_t *hash_key;
3847         uint8_t hash_key_len;
3848         uint64_t rss_hf;
3849         uint16_t i;
3850         uint64_t hena;
3851
3852         hash_key = (uint32_t *)(rss_conf->rss_key);
3853         hash_key_len = rss_conf->rss_key_len;
3854         if (hash_key != NULL && hash_key_len >=
3855                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3856                 /* Fill in RSS hash key */
3857                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3858                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
3859         }
3860
3861         rss_hf = rss_conf->rss_hf;
3862         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3863         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3864         hena &= ~I40E_RSS_HENA_ALL;
3865         hena |= i40e_config_hena(rss_hf);
3866         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3867         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3868         I40E_WRITE_FLUSH(hw);
3869
3870         return 0;
3871 }
3872
3873 static int
3874 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
3875                          struct rte_eth_rss_conf *rss_conf)
3876 {
3877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3878         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
3879         uint64_t hena;
3880
3881         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3882         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3883         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
3884                 if (rss_hf != 0) /* Enable RSS */
3885                         return -EINVAL;
3886                 return 0; /* Nothing to do */
3887         }
3888         /* RSS enabled */
3889         if (rss_hf == 0) /* Disable RSS */
3890                 return -EINVAL;
3891
3892         return i40e_hw_rss_hash_set(hw, rss_conf);
3893 }
3894
3895 static int
3896 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3897                            struct rte_eth_rss_conf *rss_conf)
3898 {
3899         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
3901         uint64_t hena;
3902         uint16_t i;
3903
3904         if (hash_key != NULL) {
3905                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3906                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
3907                 rss_conf->rss_key_len = i * sizeof(uint32_t);
3908         }
3909         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3910         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3911         rss_conf->rss_hf = i40e_parse_hena(hena);
3912
3913         return 0;
3914 }
3915
3916 /* Configure RSS */
3917 static int
3918 i40e_pf_config_rss(struct i40e_pf *pf)
3919 {
3920         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3921         struct rte_eth_rss_conf rss_conf;
3922         uint32_t i, lut = 0;
3923         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
3924
3925         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
3926                 if (j == num)
3927                         j = 0;
3928                 lut = (lut << 8) | (j & ((0x1 <<
3929                         hw->func_caps.rss_table_entry_width) - 1));
3930                 if ((i & 3) == 3)
3931                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
3932         }
3933
3934         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
3935         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
3936                 i40e_pf_disable_rss(pf);
3937                 return 0;
3938         }
3939         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
3940                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3941                 /* Calculate the default hash key */
3942                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3943                         rss_key_default[i] = (uint32_t)rte_rand();
3944                 rss_conf.rss_key = (uint8_t *)rss_key_default;
3945                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3946                                                         sizeof(uint32_t);
3947         }
3948
3949         return i40e_hw_rss_hash_set(hw, &rss_conf);
3950 }
3951
3952 static int
3953 i40e_pf_config_mq_rx(struct i40e_pf *pf)
3954 {
3955         if (!pf->dev_data->sriov.active) {
3956                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
3957                 case ETH_MQ_RX_RSS:
3958                         i40e_pf_config_rss(pf);
3959                         break;
3960                 default:
3961                         i40e_pf_disable_rss(pf);
3962                         break;
3963                 }
3964         }
3965
3966         return 0;
3967 }