lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds*/
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 static int eth_i40e_dev_init(\
  97                         __attribute__((unused)) struct eth_driver *eth_drv,
  98                         struct rte_eth_dev *eth_dev);
  99 static int i40e_dev_configure(struct rte_eth_dev *dev);
 100 static int i40e_dev_start(struct rte_eth_dev *dev);
 101 static void i40e_dev_stop(struct rte_eth_dev *dev);
 102 static void i40e_dev_close(struct rte_eth_dev *dev);
 103 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 104 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 105 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 106 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 107 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 108 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 109 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 110                                struct rte_eth_stats *stats);
 111 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 112 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 113                                             uint16_t queue_id,
 114                                             uint8_t stat_idx,
 115                                             uint8_t is_rx);
 116 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_dev_info *dev_info);
 118 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 119                                 uint16_t vlan_id,
 120                                 int on);
 121 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 122 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 124                                       uint16_t queue,
 125                                       int on);
 126 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 127 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 128 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 129 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 130                               struct rte_eth_fc_conf *fc_conf);
 131 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 132                                        struct rte_eth_pfc_conf *pfc_conf);
 133 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 134                           struct ether_addr *mac_addr,
 135                           uint32_t index,
 136                           uint32_t pool);
 137 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 138 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 139                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 140                                     uint16_t reta_size);
 141 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 142                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 143                                    uint16_t reta_size);
 144
 145 static int i40e_get_cap(struct i40e_hw *hw);
 146 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 147 static int i40e_pf_setup(struct i40e_pf *pf);
 148 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 149 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 150 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 151                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 152 static void i40e_stat_update_48(struct i40e_hw *hw,
 153                                uint32_t hireg,
 154                                uint32_t loreg,
 155                                bool offset_loaded,
 156                                uint64_t *offset,
 157                                uint64_t *stat);
 158 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 159 static void i40e_dev_interrupt_handler(
 160                 __rte_unused struct rte_intr_handle *handle, void *param);
 161 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 162                                 uint32_t base, uint32_t num);
 163 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 164 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 165                         uint32_t base);
 166 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 167                         uint16_t num);
 168 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 169 static int i40e_veb_release(struct i40e_veb *veb);
 170 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 171                                                 struct i40e_vsi *vsi);
 172 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 173 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 174 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 175                                              struct i40e_macvlan_filter *mv_f,
 176                                              int num,
 177                                              struct ether_addr *addr);
 178 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 179                                              struct i40e_macvlan_filter *mv_f,
 180                                              int num,
 181                                              uint16_t vlan);
 182 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 183 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 184                                     struct rte_eth_rss_conf *rss_conf);
 185 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 186                                       struct rte_eth_rss_conf *rss_conf);
 187 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 188                                 struct rte_eth_udp_tunnel *udp_tunnel);
 189 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 190                                 struct rte_eth_udp_tunnel *udp_tunnel);
 191 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 192                         struct rte_eth_ethertype_filter *filter,
 193                         bool add);
 194 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 195                                 enum rte_filter_op filter_op,
 196                                 void *arg);
 197 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 198                                 enum rte_filter_type filter_type,
 199                                 enum rte_filter_op filter_op,
 200                                 void *arg);
 201 static void i40e_configure_registers(struct i40e_hw *hw);
 202
 203 /* Default hash key buffer for RSS */
 204 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 205
 206 static struct rte_pci_id pci_id_i40e_map[] = {
 207 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 208 #include "rte_pci_dev_ids.h"
 209 { .vendor_id = 0, /* sentinel */ },
 210 };
 211
 212 static struct eth_dev_ops i40e_eth_dev_ops = {
 213         .dev_configure                = i40e_dev_configure,
 214         .dev_start                    = i40e_dev_start,
 215         .dev_stop                     = i40e_dev_stop,
 216         .dev_close                    = i40e_dev_close,
 217         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 218         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 219         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 220         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 221         .dev_set_link_up              = i40e_dev_set_link_up,
 222         .dev_set_link_down            = i40e_dev_set_link_down,
 223         .link_update                  = i40e_dev_link_update,
 224         .stats_get                    = i40e_dev_stats_get,
 225         .stats_reset                  = i40e_dev_stats_reset,
 226         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 227         .dev_infos_get                = i40e_dev_info_get,
 228         .vlan_filter_set              = i40e_vlan_filter_set,
 229         .vlan_tpid_set                = i40e_vlan_tpid_set,
 230         .vlan_offload_set             = i40e_vlan_offload_set,
 231         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 232         .vlan_pvid_set                = i40e_vlan_pvid_set,
 233         .rx_queue_start               = i40e_dev_rx_queue_start,
 234         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 235         .tx_queue_start               = i40e_dev_tx_queue_start,
 236         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 237         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 238         .rx_queue_release             = i40e_dev_rx_queue_release,
 239         .rx_queue_count               = i40e_dev_rx_queue_count,
 240         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 241         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 242         .tx_queue_release             = i40e_dev_tx_queue_release,
 243         .dev_led_on                   = i40e_dev_led_on,
 244         .dev_led_off                  = i40e_dev_led_off,
 245         .flow_ctrl_set                = i40e_flow_ctrl_set,
 246         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 247         .mac_addr_add                 = i40e_macaddr_add,
 248         .mac_addr_remove              = i40e_macaddr_remove,
 249         .reta_update                  = i40e_dev_rss_reta_update,
 250         .reta_query                   = i40e_dev_rss_reta_query,
 251         .rss_hash_update              = i40e_dev_rss_hash_update,
 252         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 253         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 254         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 255         .filter_ctrl                  = i40e_dev_filter_ctrl,
 256 };
 257
 258 static struct eth_driver rte_i40e_pmd = {
 259         {
 260                 .name = "rte_i40e_pmd",
 261                 .id_table = pci_id_i40e_map,
 262                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 263         },
 264         .eth_dev_init = eth_i40e_dev_init,
 265         .dev_private_size = sizeof(struct i40e_adapter),
 266 };
 267
 268 static inline int
 269 i40e_align_floor(int n)
 270 {
 271         if (n == 0)
 272                 return 0;
 273         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 274 }
 275
 276 static inline int
 277 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 278                                      struct rte_eth_link *link)
 279 {
 280         struct rte_eth_link *dst = link;
 281         struct rte_eth_link *src = &(dev->data->dev_link);
 282
 283         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 284                                         *(uint64_t *)src) == 0)
 285                 return -1;
 286
 287         return 0;
 288 }
 289
 290 static inline int
 291 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 292                                       struct rte_eth_link *link)
 293 {
 294         struct rte_eth_link *dst = &(dev->data->dev_link);
 295         struct rte_eth_link *src = link;
 296
 297         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 298                                         *(uint64_t *)src) == 0)
 299                 return -1;
 300
 301         return 0;
 302 }
 303
 304 /*
 305  * Driver initialization routine.
 306  * Invoked once at EAL init time.
 307  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 308  */
 309 static int
 310 rte_i40e_pmd_init(const char *name __rte_unused,
 311                   const char *params __rte_unused)
 312 {
 313         PMD_INIT_FUNC_TRACE();
 314         rte_eth_driver_register(&rte_i40e_pmd);
 315
 316         return 0;
 317 }
 318
 319 static struct rte_driver rte_i40e_driver = {
 320         .type = PMD_PDEV,
 321         .init = rte_i40e_pmd_init,
 322 };
 323
 324 PMD_REGISTER_DRIVER(rte_i40e_driver);
 325
 326 /*
 327  * Initialize registers for flexible payload, which should be set by NVM.
 328  * This should be removed from code once it is fixed in NVM.
 329  */
 330 #ifndef I40E_GLQF_ORT
 331 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 332 #endif
 333 #ifndef I40E_GLQF_PIT
 334 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 335 #endif
 336
 337 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 338 {
 339         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 340         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 341         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 342         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 343         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 344         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 345         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 346         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 347         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 348         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 349
 350         /* GLQF_PIT Registers */
 351         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 352         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 353 }
 354
 355 static int
 356 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 357                   struct rte_eth_dev *dev)
 358 {
 359         struct rte_pci_device *pci_dev;
 360         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 361         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 362         struct i40e_vsi *vsi;
 363         int ret;
 364         uint32_t len;
 365         uint8_t aq_fail = 0;
 366
 367         PMD_INIT_FUNC_TRACE();
 368
 369         dev->dev_ops = &i40e_eth_dev_ops;
 370         dev->rx_pkt_burst = i40e_recv_pkts;
 371         dev->tx_pkt_burst = i40e_xmit_pkts;
 372
 373         /* for secondary processes, we don't initialise any further as primary
 374          * has already done this work. Only check we don't need a different
 375          * RX function */
 376         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 377                 if (dev->data->scattered_rx)
 378                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 379                 return 0;
 380         }
 381         pci_dev = dev->pci_dev;
 382         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 383         pf->adapter->eth_dev = dev;
 384         pf->dev_data = dev->data;
 385
 386         hw->back = I40E_PF_TO_ADAPTER(pf);
 387         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 388         if (!hw->hw_addr) {
 389                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 390                              "as address is NULL");
 391                 return -ENODEV;
 392         }
 393
 394         hw->vendor_id = pci_dev->id.vendor_id;
 395         hw->device_id = pci_dev->id.device_id;
 396         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 397         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 398         hw->bus.device = pci_dev->addr.devid;
 399         hw->bus.func = pci_dev->addr.function;
 400
 401         /* Make sure all is clean before doing PF reset */
 402         i40e_clear_hw(hw);
 403
 404         /* Reset here to make sure all is clean for each PF */
 405         ret = i40e_pf_reset(hw);
 406         if (ret) {
 407                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 408                 return ret;
 409         }
 410
 411         /* Initialize the shared code (base driver) */
 412         ret = i40e_init_shared_code(hw);
 413         if (ret) {
 414                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 415                 return ret;
 416         }
 417
 418         /*
 419          * To work around the NVM issue,initialize registers
 420          * for flexible payload by software.
 421          * It should be removed once issues are fixed in NVM.
 422          */
 423         i40e_flex_payload_reg_init(hw);
 424
 425         /* Initialize the parameters for adminq */
 426         i40e_init_adminq_parameter(hw);
 427         ret = i40e_init_adminq(hw);
 428         if (ret != I40E_SUCCESS) {
 429                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 430                 return -EIO;
 431         }
 432         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 433                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 434                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 435                      ((hw->nvm.version >> 12) & 0xf),
 436                      ((hw->nvm.version >> 4) & 0xff),
 437                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 438
 439         /* Disable LLDP */
 440         ret = i40e_aq_stop_lldp(hw, true, NULL);
 441         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 442                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 443
 444         /* Clear PXE mode */
 445         i40e_clear_pxe_mode(hw);
 446
 447         /*
 448          * On X710, performance number is far from the expectation on recent
 449          * firmware versions. The fix for this issue may not be integrated in
 450          * the following firmware version. So the workaround in software driver
 451          * is needed. It needs to modify the initial values of 3 internal only
 452          * registers. Note that the workaround can be removed when it is fixed
 453          * in firmware in the future.
 454          */
 455         i40e_configure_registers(hw);
 456
 457         /* Get hw capabilities */
 458         ret = i40e_get_cap(hw);
 459         if (ret != I40E_SUCCESS) {
 460                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 461                 goto err_get_capabilities;
 462         }
 463
 464         /* Initialize parameters for PF */
 465         ret = i40e_pf_parameter_init(dev);
 466         if (ret != 0) {
 467                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 468                 goto err_parameter_init;
 469         }
 470
 471         /* Initialize the queue management */
 472         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 473         if (ret < 0) {
 474                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 475                 goto err_qp_pool_init;
 476         }
 477         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 478                                 hw->func_caps.num_msix_vectors - 1);
 479         if (ret < 0) {
 480                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 481                 goto err_msix_pool_init;
 482         }
 483
 484         /* Initialize lan hmc */
 485         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 486                                 hw->func_caps.num_rx_qp, 0, 0);
 487         if (ret != I40E_SUCCESS) {
 488                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 489                 goto err_init_lan_hmc;
 490         }
 491
 492         /* Configure lan hmc */
 493         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 494         if (ret != I40E_SUCCESS) {
 495                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 496                 goto err_configure_lan_hmc;
 497         }
 498
 499         /* Get and check the mac address */
 500         i40e_get_mac_addr(hw, hw->mac.addr);
 501         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 502                 PMD_INIT_LOG(ERR, "mac address is not valid");
 503                 ret = -EIO;
 504                 goto err_get_mac_addr;
 505         }
 506         /* Copy the permanent MAC address */
 507         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 508                         (struct ether_addr *) hw->mac.perm_addr);
 509
 510         /* Disable flow control */
 511         hw->fc.requested_mode = I40E_FC_NONE;
 512         i40e_set_fc(hw, &aq_fail, TRUE);
 513
 514         /* PF setup, which includes VSI setup */
 515         ret = i40e_pf_setup(pf);
 516         if (ret) {
 517                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 518                 goto err_setup_pf_switch;
 519         }
 520
 521         vsi = pf->main_vsi;
 522
 523         /* Disable double vlan by default */
 524         i40e_vsi_config_double_vlan(vsi, FALSE);
 525
 526         if (!vsi->max_macaddrs)
 527                 len = ETHER_ADDR_LEN;
 528         else
 529                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 530
 531         /* Should be after VSI initialized */
 532         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 533         if (!dev->data->mac_addrs) {
 534                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 535                                         "for storing mac address");
 536                 goto err_mac_alloc;
 537         }
 538         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 539                                         &dev->data->mac_addrs[0]);
 540
 541         /* initialize pf host driver to setup SRIOV resource if applicable */
 542         i40e_pf_host_init(dev);
 543
 544         /* register callback func to eal lib */
 545         rte_intr_callback_register(&(pci_dev->intr_handle),
 546                 i40e_dev_interrupt_handler, (void *)dev);
 547
 548         /* configure and enable device interrupt */
 549         i40e_pf_config_irq0(hw);
 550         i40e_pf_enable_irq0(hw);
 551
 552         /* enable uio intr after callback register */
 553         rte_intr_enable(&(pci_dev->intr_handle));
 554
 555         return 0;
 556
 557 err_mac_alloc:
 558         i40e_vsi_release(pf->main_vsi);
 559 err_setup_pf_switch:
 560 err_get_mac_addr:
 561 err_configure_lan_hmc:
 562         (void)i40e_shutdown_lan_hmc(hw);
 563 err_init_lan_hmc:
 564         i40e_res_pool_destroy(&pf->msix_pool);
 565 err_msix_pool_init:
 566         i40e_res_pool_destroy(&pf->qp_pool);
 567 err_qp_pool_init:
 568 err_parameter_init:
 569 err_get_capabilities:
 570         (void)i40e_shutdown_adminq(hw);
 571
 572         return ret;
 573 }
 574
 575 static int
 576 i40e_dev_configure(struct rte_eth_dev *dev)
 577 {
 578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 579         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 580         int ret;
 581
 582         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 583                 ret = i40e_fdir_setup(pf);
 584                 if (ret != I40E_SUCCESS) {
 585                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 586                         return -ENOTSUP;
 587                 }
 588                 ret = i40e_fdir_configure(dev);
 589                 if (ret < 0) {
 590                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 591                         goto err;
 592                 }
 593         } else
 594                 i40e_fdir_teardown(pf);
 595
 596         ret = i40e_dev_init_vlan(dev);
 597         if (ret < 0)
 598                 goto err;
 599
 600         /* VMDQ setup.
 601          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 602          *  RSS setting have different requirements.
 603          *  General PMD driver call sequence are NIC init, configure,
 604          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 605          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 606          *  applicable. So, VMDQ setting has to be done before
 607          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 608          *  For RSS setting, it will try to calculate actual configured RX queue
 609          *  number, which will be available after rx_queue_setup(). dev_start()
 610          *  function is good to place RSS setup.
 611          */
 612         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 613                 ret = i40e_vmdq_setup(dev);
 614                 if (ret)
 615                         goto err;
 616         }
 617         return 0;
 618 err:
 619         i40e_fdir_teardown(pf);
 620         return ret;
 621 }
 622
 623 void
 624 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 625 {
 626         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 627         uint16_t msix_vect = vsi->msix_intr;
 628         uint16_t i;
 629
 630         for (i = 0; i < vsi->nb_qps; i++) {
 631                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 632                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 633                 rte_wmb();
 634         }
 635
 636         if (vsi->type != I40E_VSI_SRIOV) {
 637                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 638                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 639                                 msix_vect - 1), 0);
 640         } else {
 641                 uint32_t reg;
 642                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 643                         vsi->user_param + (msix_vect - 1);
 644
 645                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 646         }
 647         I40E_WRITE_FLUSH(hw);
 648 }
 649
 650 static inline uint16_t
 651 i40e_calc_itr_interval(int16_t interval)
 652 {
 653         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 654                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 655
 656         /* Convert to hardware count, as writing each 1 represents 2 us */
 657         return (interval/2);
 658 }
 659
 660 void
 661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 662 {
 663         uint32_t val;
 664         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 665         uint16_t msix_vect = vsi->msix_intr;
 666         int i;
 667
 668         for (i = 0; i < vsi->nb_qps; i++)
 669                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 670
 671         /* Bind all RX queues to allocated MSIX interrupt */
 672         for (i = 0; i < vsi->nb_qps; i++) {
 673                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 674                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 675                         ((vsi->base_queue + i + 1) <<
 676                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 677                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 678                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 679
 680                 if (i == vsi->nb_qps - 1)
 681                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 682                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 683         }
 684
 685         /* Write first RX queue to Link list register as the head element */
 686         if (vsi->type != I40E_VSI_SRIOV) {
 687                 uint16_t interval =
 688                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 689
 690                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 691                                                 (vsi->base_queue <<
 692                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 693                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 694
 695                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 696                                                 msix_vect - 1), interval);
 697
 698 #ifndef I40E_GLINT_CTL
 699 #define I40E_GLINT_CTL                     0x0003F800
 700 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 701 #endif
 702                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 703                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 704                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 705         } else {
 706                 uint32_t reg;
 707
 708                 /* num_msix_vectors_vf needs to minus irq0 */
 709                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 710                         vsi->user_param + (msix_vect - 1);
 711
 712                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 713                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 714                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 715         }
 716
 717         I40E_WRITE_FLUSH(hw);
 718 }
 719
 720 static void
 721 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 722 {
 723         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 724         uint16_t interval = i40e_calc_itr_interval(\
 725                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 726
 727         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 728                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 729                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 730                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 731                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 732 }
 733
 734 static void
 735 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 736 {
 737         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 738
 739         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 740 }
 741
 742 static inline uint8_t
 743 i40e_parse_link_speed(uint16_t eth_link_speed)
 744 {
 745         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 746
 747         switch (eth_link_speed) {
 748         case ETH_LINK_SPEED_40G:
 749                 link_speed = I40E_LINK_SPEED_40GB;
 750                 break;
 751         case ETH_LINK_SPEED_20G:
 752                 link_speed = I40E_LINK_SPEED_20GB;
 753                 break;
 754         case ETH_LINK_SPEED_10G:
 755                 link_speed = I40E_LINK_SPEED_10GB;
 756                 break;
 757         case ETH_LINK_SPEED_1000:
 758                 link_speed = I40E_LINK_SPEED_1GB;
 759                 break;
 760         case ETH_LINK_SPEED_100:
 761                 link_speed = I40E_LINK_SPEED_100MB;
 762                 break;
 763         }
 764
 765         return link_speed;
 766 }
 767
 768 static int
 769 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 770 {
 771         enum i40e_status_code status;
 772         struct i40e_aq_get_phy_abilities_resp phy_ab;
 773         struct i40e_aq_set_phy_config phy_conf;
 774         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 775                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 776                         I40E_AQ_PHY_FLAG_LOW_POWER;
 777         const uint8_t advt = I40E_LINK_SPEED_40GB |
 778                         I40E_LINK_SPEED_10GB |
 779                         I40E_LINK_SPEED_1GB |
 780                         I40E_LINK_SPEED_100MB;
 781         int ret = -ENOTSUP;
 782
 783         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 784                                               NULL);
 785         if (status)
 786                 return ret;
 787
 788         memset(&phy_conf, 0, sizeof(phy_conf));
 789
 790         /* bits 0-2 use the values from get_phy_abilities_resp */
 791         abilities &= ~mask;
 792         abilities |= phy_ab.abilities & mask;
 793
 794         /* update ablities and speed */
 795         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 796                 phy_conf.link_speed = advt;
 797         else
 798                 phy_conf.link_speed = force_speed;
 799
 800         phy_conf.abilities = abilities;
 801
 802         /* use get_phy_abilities_resp value for the rest */
 803         phy_conf.phy_type = phy_ab.phy_type;
 804         phy_conf.eee_capability = phy_ab.eee_capability;
 805         phy_conf.eeer = phy_ab.eeer_val;
 806         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 807
 808         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 809                     phy_ab.abilities, phy_ab.link_speed);
 810         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 811                     phy_conf.abilities, phy_conf.link_speed);
 812
 813         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 814         if (status)
 815                 return ret;
 816
 817         return I40E_SUCCESS;
 818 }
 819
 820 static int
 821 i40e_apply_link_speed(struct rte_eth_dev *dev)
 822 {
 823         uint8_t speed;
 824         uint8_t abilities = 0;
 825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 826         struct rte_eth_conf *conf = &dev->data->dev_conf;
 827
 828         speed = i40e_parse_link_speed(conf->link_speed);
 829         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 830         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 831                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 832         else
 833                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 834
 835         return i40e_phy_conf_link(hw, abilities, speed);
 836 }
 837
 838 static int
 839 i40e_dev_start(struct rte_eth_dev *dev)
 840 {
 841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 843         struct i40e_vsi *main_vsi = pf->main_vsi;
 844         int ret, i;
 845
 846         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 847                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 848                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 849                              dev->data->dev_conf.link_duplex,
 850                              dev->data->port_id);
 851                 return -EINVAL;
 852         }
 853
 854         /* Initialize VSI */
 855         ret = i40e_dev_rxtx_init(pf);
 856         if (ret != I40E_SUCCESS) {
 857                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 858                 goto err_up;
 859         }
 860
 861         /* Map queues with MSIX interrupt */
 862         i40e_vsi_queues_bind_intr(main_vsi);
 863         i40e_vsi_enable_queues_intr(main_vsi);
 864
 865         /* Map VMDQ VSI queues with MSIX interrupt */
 866         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 867                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 868                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 869         }
 870
 871         /* enable FDIR MSIX interrupt */
 872         if (pf->fdir.fdir_vsi) {
 873                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 874                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 875         }
 876
 877         /* Enable all queues which have been configured */
 878         ret = i40e_dev_switch_queues(pf, TRUE);
 879         if (ret != I40E_SUCCESS) {
 880                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 881                 goto err_up;
 882         }
 883
 884         /* Enable receiving broadcast packets */
 885         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 886         if (ret != I40E_SUCCESS)
 887                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 888
 889         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 890                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 891                                                 true, NULL);
 892                 if (ret != I40E_SUCCESS)
 893                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 894         }
 895
 896         /* Apply link configure */
 897         ret = i40e_apply_link_speed(dev);
 898         if (I40E_SUCCESS != ret) {
 899                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 900                 goto err_up;
 901         }
 902
 903         return I40E_SUCCESS;
 904
 905 err_up:
 906         i40e_dev_switch_queues(pf, FALSE);
 907         i40e_dev_clear_queues(dev);
 908
 909         return ret;
 910 }
 911
 912 static void
 913 i40e_dev_stop(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_vsi *main_vsi = pf->main_vsi;
 917         int i;
 918
 919         /* Disable all queues */
 920         i40e_dev_switch_queues(pf, FALSE);
 921
 922         /* un-map queues with interrupt registers */
 923         i40e_vsi_disable_queues_intr(main_vsi);
 924         i40e_vsi_queues_unbind_intr(main_vsi);
 925
 926         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 927                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 928                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 929         }
 930
 931         if (pf->fdir.fdir_vsi) {
 932                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 933                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 934         }
 935         /* Clear all queues and release memory */
 936         i40e_dev_clear_queues(dev);
 937
 938         /* Set link down */
 939         i40e_dev_set_link_down(dev);
 940
 941 }
 942
 943 static void
 944 i40e_dev_close(struct rte_eth_dev *dev)
 945 {
 946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 948         uint32_t reg;
 949
 950         PMD_INIT_FUNC_TRACE();
 951
 952         i40e_dev_stop(dev);
 953
 954         /* Disable interrupt */
 955         i40e_pf_disable_irq0(hw);
 956         rte_intr_disable(&(dev->pci_dev->intr_handle));
 957
 958         /* shutdown and destroy the HMC */
 959         i40e_shutdown_lan_hmc(hw);
 960
 961         /* release all the existing VSIs and VEBs */
 962         i40e_fdir_teardown(pf);
 963         i40e_vsi_release(pf->main_vsi);
 964
 965         /* shutdown the adminq */
 966         i40e_aq_queue_shutdown(hw, true);
 967         i40e_shutdown_adminq(hw);
 968
 969         i40e_res_pool_destroy(&pf->qp_pool);
 970         i40e_res_pool_destroy(&pf->msix_pool);
 971
 972         /* force a PF reset to clean anything leftover */
 973         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 974         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 975                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 976         I40E_WRITE_FLUSH(hw);
 977 }
 978
 979 static void
 980 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 981 {
 982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 984         struct i40e_vsi *vsi = pf->main_vsi;
 985         int status;
 986
 987         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 988                                                         true, NULL);
 989         if (status != I40E_SUCCESS)
 990                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 991
 992         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 993                                                         TRUE, NULL);
 994         if (status != I40E_SUCCESS)
 995                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 996
 997 }
 998
 999 static void
1000 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1001 {
1002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         struct i40e_vsi *vsi = pf->main_vsi;
1005         int status;
1006
1007         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1008                                                         false, NULL);
1009         if (status != I40E_SUCCESS)
1010                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1011
1012         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1013                                                         false, NULL);
1014         if (status != I40E_SUCCESS)
1015                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1016 }
1017
1018 static void
1019 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1020 {
1021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023         struct i40e_vsi *vsi = pf->main_vsi;
1024         int ret;
1025
1026         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1027         if (ret != I40E_SUCCESS)
1028                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1029 }
1030
1031 static void
1032 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1033 {
1034         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         struct i40e_vsi *vsi = pf->main_vsi;
1037         int ret;
1038
1039         if (dev->data->promiscuous == 1)
1040                 return; /* must remain in all_multicast mode */
1041
1042         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1043                                 vsi->seid, FALSE, NULL);
1044         if (ret != I40E_SUCCESS)
1045                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1046 }
1047
1048 /*
1049  * Set device link up.
1050  */
1051 static int
1052 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1053 {
1054         /* re-apply link speed setting */
1055         return i40e_apply_link_speed(dev);
1056 }
1057
1058 /*
1059  * Set device link down.
1060  */
1061 static int
1062 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1063 {
1064         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1065         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1067
1068         return i40e_phy_conf_link(hw, abilities, speed);
1069 }
1070
1071 int
1072 i40e_dev_link_update(struct rte_eth_dev *dev,
1073                      __rte_unused int wait_to_complete)
1074 {
1075         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1076         struct i40e_link_status link_status;
1077         struct rte_eth_link link, old;
1078         int status;
1079
1080         memset(&link, 0, sizeof(link));
1081         memset(&old, 0, sizeof(old));
1082         memset(&link_status, 0, sizeof(link_status));
1083         rte_i40e_dev_atomic_read_link_status(dev, &old);
1084
1085         /* Get link status information from hardware */
1086         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1087         if (status != I40E_SUCCESS) {
1088                 link.link_speed = ETH_LINK_SPEED_100;
1089                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1090                 PMD_DRV_LOG(ERR, "Failed to get link info");
1091                 goto out;
1092         }
1093
1094         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1095
1096         if (!link.link_status)
1097                 goto out;
1098
1099         /* i40e uses full duplex only */
1100         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1101
1102         /* Parse the link status */
1103         switch (link_status.link_speed) {
1104         case I40E_LINK_SPEED_100MB:
1105                 link.link_speed = ETH_LINK_SPEED_100;
1106                 break;
1107         case I40E_LINK_SPEED_1GB:
1108                 link.link_speed = ETH_LINK_SPEED_1000;
1109                 break;
1110         case I40E_LINK_SPEED_10GB:
1111                 link.link_speed = ETH_LINK_SPEED_10G;
1112                 break;
1113         case I40E_LINK_SPEED_20GB:
1114                 link.link_speed = ETH_LINK_SPEED_20G;
1115                 break;
1116         case I40E_LINK_SPEED_40GB:
1117                 link.link_speed = ETH_LINK_SPEED_40G;
1118                 break;
1119         default:
1120                 link.link_speed = ETH_LINK_SPEED_100;
1121                 break;
1122         }
1123
1124 out:
1125         rte_i40e_dev_atomic_write_link_status(dev, &link);
1126         if (link.link_status == old.link_status)
1127                 return -1;
1128
1129         return 0;
1130 }
1131
1132 /* Get all the statistics of a VSI */
1133 void
1134 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1135 {
1136         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1137         struct i40e_eth_stats *nes = &vsi->eth_stats;
1138         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1139         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1140
1141         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1142                             vsi->offset_loaded, &oes->rx_bytes,
1143                             &nes->rx_bytes);
1144         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1145                             vsi->offset_loaded, &oes->rx_unicast,
1146                             &nes->rx_unicast);
1147         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1148                             vsi->offset_loaded, &oes->rx_multicast,
1149                             &nes->rx_multicast);
1150         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1151                             vsi->offset_loaded, &oes->rx_broadcast,
1152                             &nes->rx_broadcast);
1153         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1154                             &oes->rx_discards, &nes->rx_discards);
1155         /* GLV_REPC not supported */
1156         /* GLV_RMPC not supported */
1157         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1158                             &oes->rx_unknown_protocol,
1159                             &nes->rx_unknown_protocol);
1160         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1161                             vsi->offset_loaded, &oes->tx_bytes,
1162                             &nes->tx_bytes);
1163         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1164                             vsi->offset_loaded, &oes->tx_unicast,
1165                             &nes->tx_unicast);
1166         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1167                             vsi->offset_loaded, &oes->tx_multicast,
1168                             &nes->tx_multicast);
1169         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1170                             vsi->offset_loaded,  &oes->tx_broadcast,
1171                             &nes->tx_broadcast);
1172         /* GLV_TDPC not supported */
1173         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1174                             &oes->tx_errors, &nes->tx_errors);
1175         vsi->offset_loaded = true;
1176
1177         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1178                     vsi->vsi_id);
1179         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1180         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1181         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1182         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1183         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1184         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1185                     nes->rx_unknown_protocol);
1186         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1187         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1188         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1189         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1190         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1191         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1192         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1193                     vsi->vsi_id);
1194 }
1195
1196 /* Get all statistics of a port */
1197 static void
1198 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1199 {
1200         uint32_t i;
1201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1202         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1204         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1205
1206         /* Get statistics of struct i40e_eth_stats */
1207         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1208                             I40E_GLPRT_GORCL(hw->port),
1209                             pf->offset_loaded, &os->eth.rx_bytes,
1210                             &ns->eth.rx_bytes);
1211         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1212                             I40E_GLPRT_UPRCL(hw->port),
1213                             pf->offset_loaded, &os->eth.rx_unicast,
1214                             &ns->eth.rx_unicast);
1215         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1216                             I40E_GLPRT_MPRCL(hw->port),
1217                             pf->offset_loaded, &os->eth.rx_multicast,
1218                             &ns->eth.rx_multicast);
1219         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1220                             I40E_GLPRT_BPRCL(hw->port),
1221                             pf->offset_loaded, &os->eth.rx_broadcast,
1222                             &ns->eth.rx_broadcast);
1223         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1224                             pf->offset_loaded, &os->eth.rx_discards,
1225                             &ns->eth.rx_discards);
1226         /* GLPRT_REPC not supported */
1227         /* GLPRT_RMPC not supported */
1228         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1229                             pf->offset_loaded,
1230                             &os->eth.rx_unknown_protocol,
1231                             &ns->eth.rx_unknown_protocol);
1232         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1233                             I40E_GLPRT_GOTCL(hw->port),
1234                             pf->offset_loaded, &os->eth.tx_bytes,
1235                             &ns->eth.tx_bytes);
1236         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1237                             I40E_GLPRT_UPTCL(hw->port),
1238                             pf->offset_loaded, &os->eth.tx_unicast,
1239                             &ns->eth.tx_unicast);
1240         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1241                             I40E_GLPRT_MPTCL(hw->port),
1242                             pf->offset_loaded, &os->eth.tx_multicast,
1243                             &ns->eth.tx_multicast);
1244         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1245                             I40E_GLPRT_BPTCL(hw->port),
1246                             pf->offset_loaded, &os->eth.tx_broadcast,
1247                             &ns->eth.tx_broadcast);
1248         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1249                             pf->offset_loaded, &os->eth.tx_discards,
1250                             &ns->eth.tx_discards);
1251         /* GLPRT_TEPC not supported */
1252
1253         /* additional port specific stats */
1254         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1255                             pf->offset_loaded, &os->tx_dropped_link_down,
1256                             &ns->tx_dropped_link_down);
1257         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1258                             pf->offset_loaded, &os->crc_errors,
1259                             &ns->crc_errors);
1260         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1261                             pf->offset_loaded, &os->illegal_bytes,
1262                             &ns->illegal_bytes);
1263         /* GLPRT_ERRBC not supported */
1264         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1265                             pf->offset_loaded, &os->mac_local_faults,
1266                             &ns->mac_local_faults);
1267         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1268                             pf->offset_loaded, &os->mac_remote_faults,
1269                             &ns->mac_remote_faults);
1270         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1271                             pf->offset_loaded, &os->rx_length_errors,
1272                             &ns->rx_length_errors);
1273         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1274                             pf->offset_loaded, &os->link_xon_rx,
1275                             &ns->link_xon_rx);
1276         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1277                             pf->offset_loaded, &os->link_xoff_rx,
1278                             &ns->link_xoff_rx);
1279         for (i = 0; i < 8; i++) {
1280                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1281                                     pf->offset_loaded,
1282                                     &os->priority_xon_rx[i],
1283                                     &ns->priority_xon_rx[i]);
1284                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1285                                     pf->offset_loaded,
1286                                     &os->priority_xoff_rx[i],
1287                                     &ns->priority_xoff_rx[i]);
1288         }
1289         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1290                             pf->offset_loaded, &os->link_xon_tx,
1291                             &ns->link_xon_tx);
1292         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1293                             pf->offset_loaded, &os->link_xoff_tx,
1294                             &ns->link_xoff_tx);
1295         for (i = 0; i < 8; i++) {
1296                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1297                                     pf->offset_loaded,
1298                                     &os->priority_xon_tx[i],
1299                                     &ns->priority_xon_tx[i]);
1300                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1301                                     pf->offset_loaded,
1302                                     &os->priority_xoff_tx[i],
1303                                     &ns->priority_xoff_tx[i]);
1304                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1305                                     pf->offset_loaded,
1306                                     &os->priority_xon_2_xoff[i],
1307                                     &ns->priority_xon_2_xoff[i]);
1308         }
1309         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1310                             I40E_GLPRT_PRC64L(hw->port),
1311                             pf->offset_loaded, &os->rx_size_64,
1312                             &ns->rx_size_64);
1313         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1314                             I40E_GLPRT_PRC127L(hw->port),
1315                             pf->offset_loaded, &os->rx_size_127,
1316                             &ns->rx_size_127);
1317         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1318                             I40E_GLPRT_PRC255L(hw->port),
1319                             pf->offset_loaded, &os->rx_size_255,
1320                             &ns->rx_size_255);
1321         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1322                             I40E_GLPRT_PRC511L(hw->port),
1323                             pf->offset_loaded, &os->rx_size_511,
1324                             &ns->rx_size_511);
1325         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1326                             I40E_GLPRT_PRC1023L(hw->port),
1327                             pf->offset_loaded, &os->rx_size_1023,
1328                             &ns->rx_size_1023);
1329         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1330                             I40E_GLPRT_PRC1522L(hw->port),
1331                             pf->offset_loaded, &os->rx_size_1522,
1332                             &ns->rx_size_1522);
1333         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1334                             I40E_GLPRT_PRC9522L(hw->port),
1335                             pf->offset_loaded, &os->rx_size_big,
1336                             &ns->rx_size_big);
1337         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1338                             pf->offset_loaded, &os->rx_undersize,
1339                             &ns->rx_undersize);
1340         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1341                             pf->offset_loaded, &os->rx_fragments,
1342                             &ns->rx_fragments);
1343         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1344                             pf->offset_loaded, &os->rx_oversize,
1345                             &ns->rx_oversize);
1346         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1347                             pf->offset_loaded, &os->rx_jabber,
1348                             &ns->rx_jabber);
1349         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1350                             I40E_GLPRT_PTC64L(hw->port),
1351                             pf->offset_loaded, &os->tx_size_64,
1352                             &ns->tx_size_64);
1353         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1354                             I40E_GLPRT_PTC127L(hw->port),
1355                             pf->offset_loaded, &os->tx_size_127,
1356                             &ns->tx_size_127);
1357         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1358                             I40E_GLPRT_PTC255L(hw->port),
1359                             pf->offset_loaded, &os->tx_size_255,
1360                             &ns->tx_size_255);
1361         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1362                             I40E_GLPRT_PTC511L(hw->port),
1363                             pf->offset_loaded, &os->tx_size_511,
1364                             &ns->tx_size_511);
1365         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1366                             I40E_GLPRT_PTC1023L(hw->port),
1367                             pf->offset_loaded, &os->tx_size_1023,
1368                             &ns->tx_size_1023);
1369         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1370                             I40E_GLPRT_PTC1522L(hw->port),
1371                             pf->offset_loaded, &os->tx_size_1522,
1372                             &ns->tx_size_1522);
1373         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1374                             I40E_GLPRT_PTC9522L(hw->port),
1375                             pf->offset_loaded, &os->tx_size_big,
1376                             &ns->tx_size_big);
1377         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1378                            pf->offset_loaded,
1379                            &os->fd_sb_match, &ns->fd_sb_match);
1380         /* GLPRT_MSPDC not supported */
1381         /* GLPRT_XEC not supported */
1382
1383         pf->offset_loaded = true;
1384
1385         if (pf->main_vsi)
1386                 i40e_update_vsi_stats(pf->main_vsi);
1387
1388         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1389                                                 ns->eth.rx_broadcast;
1390         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1391                                                 ns->eth.tx_broadcast;
1392         stats->ibytes   = ns->eth.rx_bytes;
1393         stats->obytes   = ns->eth.tx_bytes;
1394         stats->oerrors  = ns->eth.tx_errors;
1395         stats->imcasts  = ns->eth.rx_multicast;
1396         stats->fdirmatch = ns->fd_sb_match;
1397
1398         /* Rx Errors */
1399         stats->ibadcrc  = ns->crc_errors;
1400         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1401                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1402         stats->imissed  = ns->eth.rx_discards;
1403         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1404
1405         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1406         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1407         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1408         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1409         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1410         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1411         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1412                     ns->eth.rx_unknown_protocol);
1413         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1414         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1415         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1416         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1417         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1418         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1419
1420         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1421                     ns->tx_dropped_link_down);
1422         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1423         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1424                     ns->illegal_bytes);
1425         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1426         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1427                     ns->mac_local_faults);
1428         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1429                     ns->mac_remote_faults);
1430         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1431                     ns->rx_length_errors);
1432         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1433         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1434         for (i = 0; i < 8; i++) {
1435                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1436                                 i, ns->priority_xon_rx[i]);
1437                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1438                                 i, ns->priority_xoff_rx[i]);
1439         }
1440         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1441         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1442         for (i = 0; i < 8; i++) {
1443                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1444                                 i, ns->priority_xon_tx[i]);
1445                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1446                                 i, ns->priority_xoff_tx[i]);
1447                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1448                                 i, ns->priority_xon_2_xoff[i]);
1449         }
1450         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1451         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1452         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1453         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1454         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1455         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1456         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1457         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1458         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1459         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1460         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1461         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1462         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1463         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1464         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1465         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1466         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1467         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1468         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1469                         ns->mac_short_packet_dropped);
1470         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1471                     ns->checksum_error);
1472         PMD_DRV_LOG(DEBUG, "fdir_match:               %lu", ns->fd_sb_match);
1473         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1474 }
1475
1476 /* Reset the statistics */
1477 static void
1478 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1479 {
1480         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1481
1482         /* It results in reloading the start point of each counter */
1483         pf->offset_loaded = false;
1484 }
1485
1486 static int
1487 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1488                                  __rte_unused uint16_t queue_id,
1489                                  __rte_unused uint8_t stat_idx,
1490                                  __rte_unused uint8_t is_rx)
1491 {
1492         PMD_INIT_FUNC_TRACE();
1493
1494         return -ENOSYS;
1495 }
1496
1497 static void
1498 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1499 {
1500         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1501         struct i40e_vsi *vsi = pf->main_vsi;
1502
1503         dev_info->max_rx_queues = vsi->nb_qps;
1504         dev_info->max_tx_queues = vsi->nb_qps;
1505         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1506         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1507         dev_info->max_mac_addrs = vsi->max_macaddrs;
1508         dev_info->max_vfs = dev->pci_dev->max_vfs;
1509         dev_info->rx_offload_capa =
1510                 DEV_RX_OFFLOAD_VLAN_STRIP |
1511                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1512                 DEV_RX_OFFLOAD_UDP_CKSUM |
1513                 DEV_RX_OFFLOAD_TCP_CKSUM;
1514         dev_info->tx_offload_capa =
1515                 DEV_TX_OFFLOAD_VLAN_INSERT |
1516                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1517                 DEV_TX_OFFLOAD_UDP_CKSUM |
1518                 DEV_TX_OFFLOAD_TCP_CKSUM |
1519                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1520         dev_info->reta_size = pf->hash_lut_size;
1521
1522         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1523                 .rx_thresh = {
1524                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1525                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1526                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1527                 },
1528                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1529                 .rx_drop_en = 0,
1530         };
1531
1532         dev_info->default_txconf = (struct rte_eth_txconf) {
1533                 .tx_thresh = {
1534                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1535                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1536                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1537                 },
1538                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1539                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1540                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1541                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1542         };
1543
1544         if (pf->flags | I40E_FLAG_VMDQ) {
1545                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1546                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1547                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1548                                                 pf->max_nb_vmdq_vsi;
1549                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1550                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1551                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1552         }
1553 }
1554
1555 static int
1556 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1557 {
1558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1559         struct i40e_vsi *vsi = pf->main_vsi;
1560         PMD_INIT_FUNC_TRACE();
1561
1562         if (on)
1563                 return i40e_vsi_add_vlan(vsi, vlan_id);
1564         else
1565                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1566 }
1567
1568 static void
1569 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1570                    __rte_unused uint16_t tpid)
1571 {
1572         PMD_INIT_FUNC_TRACE();
1573 }
1574
1575 static void
1576 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1577 {
1578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1579         struct i40e_vsi *vsi = pf->main_vsi;
1580
1581         if (mask & ETH_VLAN_STRIP_MASK) {
1582                 /* Enable or disable VLAN stripping */
1583                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1584                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1585                 else
1586                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1587         }
1588
1589         if (mask & ETH_VLAN_EXTEND_MASK) {
1590                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1591                         i40e_vsi_config_double_vlan(vsi, TRUE);
1592                 else
1593                         i40e_vsi_config_double_vlan(vsi, FALSE);
1594         }
1595 }
1596
1597 static void
1598 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1599                           __rte_unused uint16_t queue,
1600                           __rte_unused int on)
1601 {
1602         PMD_INIT_FUNC_TRACE();
1603 }
1604
1605 static int
1606 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1607 {
1608         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1609         struct i40e_vsi *vsi = pf->main_vsi;
1610         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1611         struct i40e_vsi_vlan_pvid_info info;
1612
1613         memset(&info, 0, sizeof(info));
1614         info.on = on;
1615         if (info.on)
1616                 info.config.pvid = pvid;
1617         else {
1618                 info.config.reject.tagged =
1619                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1620                 info.config.reject.untagged =
1621                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1622         }
1623
1624         return i40e_vsi_vlan_pvid_set(vsi, &info);
1625 }
1626
1627 static int
1628 i40e_dev_led_on(struct rte_eth_dev *dev)
1629 {
1630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         uint32_t mode = i40e_led_get(hw);
1632
1633         if (mode == 0)
1634                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1635
1636         return 0;
1637 }
1638
1639 static int
1640 i40e_dev_led_off(struct rte_eth_dev *dev)
1641 {
1642         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643         uint32_t mode = i40e_led_get(hw);
1644
1645         if (mode != 0)
1646                 i40e_led_set(hw, 0, false);
1647
1648         return 0;
1649 }
1650
1651 static int
1652 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1653                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1654 {
1655         PMD_INIT_FUNC_TRACE();
1656
1657         return -ENOSYS;
1658 }
1659
1660 static int
1661 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1662                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1663 {
1664         PMD_INIT_FUNC_TRACE();
1665
1666         return -ENOSYS;
1667 }
1668
1669 /* Add a MAC address, and update filters */
1670 static void
1671 i40e_macaddr_add(struct rte_eth_dev *dev,
1672                  struct ether_addr *mac_addr,
1673                  __rte_unused uint32_t index,
1674                  uint32_t pool)
1675 {
1676         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1677         struct i40e_mac_filter_info mac_filter;
1678         struct i40e_vsi *vsi;
1679         int ret;
1680
1681         /* If VMDQ not enabled or configured, return */
1682         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1683                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1684                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1685                         pool);
1686                 return;
1687         }
1688
1689         if (pool > pf->nb_cfg_vmdq_vsi) {
1690                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1691                                 pool, pf->nb_cfg_vmdq_vsi);
1692                 return;
1693         }
1694
1695         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1696         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1697
1698         if (pool == 0)
1699                 vsi = pf->main_vsi;
1700         else
1701                 vsi = pf->vmdq[pool - 1].vsi;
1702
1703         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1704         if (ret != I40E_SUCCESS) {
1705                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1706                 return;
1707         }
1708 }
1709
1710 /* Remove a MAC address, and update filters */
1711 static void
1712 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1713 {
1714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1715         struct i40e_vsi *vsi;
1716         struct rte_eth_dev_data *data = dev->data;
1717         struct ether_addr *macaddr;
1718         int ret;
1719         uint32_t i;
1720         uint64_t pool_sel;
1721
1722         macaddr = &(data->mac_addrs[index]);
1723
1724         pool_sel = dev->data->mac_pool_sel[index];
1725
1726         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1727                 if (pool_sel & (1ULL << i)) {
1728                         if (i == 0)
1729                                 vsi = pf->main_vsi;
1730                         else {
1731                                 /* No VMDQ pool enabled or configured */
1732                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1733                                         (i > pf->nb_cfg_vmdq_vsi)) {
1734                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1735                                                         "/configured");
1736                                         return;
1737                                 }
1738                                 vsi = pf->vmdq[i - 1].vsi;
1739                         }
1740                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1741
1742                         if (ret) {
1743                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1744                                 return;
1745                         }
1746                 }
1747         }
1748 }
1749
1750 /* Set perfect match or hash match of MAC and VLAN for a VF */
1751 static int
1752 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1753                  struct rte_eth_mac_filter *filter,
1754                  bool add)
1755 {
1756         struct i40e_hw *hw;
1757         struct i40e_mac_filter_info mac_filter;
1758         struct ether_addr old_mac;
1759         struct ether_addr *new_mac;
1760         struct i40e_pf_vf *vf = NULL;
1761         uint16_t vf_id;
1762         int ret;
1763
1764         if (pf == NULL) {
1765                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1766                 return -EINVAL;
1767         }
1768         hw = I40E_PF_TO_HW(pf);
1769
1770         if (filter == NULL) {
1771                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1772                 return -EINVAL;
1773         }
1774
1775         new_mac = &filter->mac_addr;
1776
1777         if (is_zero_ether_addr(new_mac)) {
1778                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1779                 return -EINVAL;
1780         }
1781
1782         vf_id = filter->dst_id;
1783
1784         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1785                 PMD_DRV_LOG(ERR, "Invalid argument.");
1786                 return -EINVAL;
1787         }
1788         vf = &pf->vfs[vf_id];
1789
1790         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1791                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1792                 return -EINVAL;
1793         }
1794
1795         if (add) {
1796                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1797                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1798                                 ETHER_ADDR_LEN);
1799                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1800                                  ETHER_ADDR_LEN);
1801
1802                 mac_filter.filter_type = filter->filter_type;
1803                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1804                 if (ret != I40E_SUCCESS) {
1805                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1806                         return -1;
1807                 }
1808                 ether_addr_copy(new_mac, &pf->dev_addr);
1809         } else {
1810                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1811                                 ETHER_ADDR_LEN);
1812                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1813                 if (ret != I40E_SUCCESS) {
1814                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1815                         return -1;
1816                 }
1817
1818                 /* Clear device address as it has been removed */
1819                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1820                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1821         }
1822
1823         return 0;
1824 }
1825
1826 /* MAC filter handle */
1827 static int
1828 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1829                 void *arg)
1830 {
1831         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1832         struct rte_eth_mac_filter *filter;
1833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1834         int ret = I40E_NOT_SUPPORTED;
1835
1836         filter = (struct rte_eth_mac_filter *)(arg);
1837
1838         switch (filter_op) {
1839         case RTE_ETH_FILTER_NOP:
1840                 ret = I40E_SUCCESS;
1841                 break;
1842         case RTE_ETH_FILTER_ADD:
1843                 i40e_pf_disable_irq0(hw);
1844                 if (filter->is_vf)
1845                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1846                 i40e_pf_enable_irq0(hw);
1847                 break;
1848         case RTE_ETH_FILTER_DELETE:
1849                 i40e_pf_disable_irq0(hw);
1850                 if (filter->is_vf)
1851                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1852                 i40e_pf_enable_irq0(hw);
1853                 break;
1854         default:
1855                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1856                 ret = I40E_ERR_PARAM;
1857                 break;
1858         }
1859
1860         return ret;
1861 }
1862
1863 static int
1864 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1865                          struct rte_eth_rss_reta_entry64 *reta_conf,
1866                          uint16_t reta_size)
1867 {
1868         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         uint32_t lut, l;
1871         uint16_t i, j, lut_size = pf->hash_lut_size;
1872         uint16_t idx, shift;
1873         uint8_t mask;
1874
1875         if (reta_size != lut_size ||
1876                 reta_size > ETH_RSS_RETA_SIZE_512) {
1877                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1878                         "(%d) doesn't match the number hardware can supported "
1879                                         "(%d)\n", reta_size, lut_size);
1880                 return -EINVAL;
1881         }
1882
1883         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1884                 idx = i / RTE_RETA_GROUP_SIZE;
1885                 shift = i % RTE_RETA_GROUP_SIZE;
1886                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1887                                                 I40E_4_BIT_MASK);
1888                 if (!mask)
1889                         continue;
1890                 if (mask == I40E_4_BIT_MASK)
1891                         l = 0;
1892                 else
1893                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1894                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1895                         if (mask & (0x1 << j))
1896                                 lut |= reta_conf[idx].reta[shift + j] <<
1897                                                         (CHAR_BIT * j);
1898                         else
1899                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1900                 }
1901                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1902         }
1903
1904         return 0;
1905 }
1906
1907 static int
1908 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1909                         struct rte_eth_rss_reta_entry64 *reta_conf,
1910                         uint16_t reta_size)
1911 {
1912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914         uint32_t lut;
1915         uint16_t i, j, lut_size = pf->hash_lut_size;
1916         uint16_t idx, shift;
1917         uint8_t mask;
1918
1919         if (reta_size != lut_size ||
1920                 reta_size > ETH_RSS_RETA_SIZE_512) {
1921                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1922                         "(%d) doesn't match the number hardware can supported "
1923                                         "(%d)\n", reta_size, lut_size);
1924                 return -EINVAL;
1925         }
1926
1927         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1928                 idx = i / RTE_RETA_GROUP_SIZE;
1929                 shift = i % RTE_RETA_GROUP_SIZE;
1930                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1931                                                 I40E_4_BIT_MASK);
1932                 if (!mask)
1933                         continue;
1934
1935                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1936                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1937                         if (mask & (0x1 << j))
1938                                 reta_conf[idx].reta[shift + j] = ((lut >>
1939                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1940                 }
1941         }
1942
1943         return 0;
1944 }
1945
1946 /**
1947  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1948  * @hw:   pointer to the HW structure
1949  * @mem:  pointer to mem struct to fill out
1950  * @size: size of memory requested
1951  * @alignment: what to align the allocation to
1952  **/
1953 enum i40e_status_code
1954 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1955                         struct i40e_dma_mem *mem,
1956                         u64 size,
1957                         u32 alignment)
1958 {
1959         static uint64_t id = 0;
1960         const struct rte_memzone *mz = NULL;
1961         char z_name[RTE_MEMZONE_NAMESIZE];
1962
1963         if (!mem)
1964                 return I40E_ERR_PARAM;
1965
1966         id++;
1967         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1968 #ifdef RTE_LIBRTE_XEN_DOM0
1969         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1970                                                         RTE_PGSIZE_2M);
1971 #else
1972         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1973 #endif
1974         if (!mz)
1975                 return I40E_ERR_NO_MEMORY;
1976
1977         mem->id = id;
1978         mem->size = size;
1979         mem->va = mz->addr;
1980 #ifdef RTE_LIBRTE_XEN_DOM0
1981         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1982 #else
1983         mem->pa = mz->phys_addr;
1984 #endif
1985
1986         return I40E_SUCCESS;
1987 }
1988
1989 /**
1990  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1991  * @hw:   pointer to the HW structure
1992  * @mem:  ptr to mem struct to free
1993  **/
1994 enum i40e_status_code
1995 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1996                     struct i40e_dma_mem *mem)
1997 {
1998         if (!mem || !mem->va)
1999                 return I40E_ERR_PARAM;
2000
2001         mem->va = NULL;
2002         mem->pa = (u64)0;
2003
2004         return I40E_SUCCESS;
2005 }
2006
2007 /**
2008  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2009  * @hw:   pointer to the HW structure
2010  * @mem:  pointer to mem struct to fill out
2011  * @size: size of memory requested
2012  **/
2013 enum i40e_status_code
2014 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2015                          struct i40e_virt_mem *mem,
2016                          u32 size)
2017 {
2018         if (!mem)
2019                 return I40E_ERR_PARAM;
2020
2021         mem->size = size;
2022         mem->va = rte_zmalloc("i40e", size, 0);
2023
2024         if (mem->va)
2025                 return I40E_SUCCESS;
2026         else
2027                 return I40E_ERR_NO_MEMORY;
2028 }
2029
2030 /**
2031  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2032  * @hw:   pointer to the HW structure
2033  * @mem:  pointer to mem struct to free
2034  **/
2035 enum i40e_status_code
2036 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2037                      struct i40e_virt_mem *mem)
2038 {
2039         if (!mem)
2040                 return I40E_ERR_PARAM;
2041
2042         rte_free(mem->va);
2043         mem->va = NULL;
2044
2045         return I40E_SUCCESS;
2046 }
2047
2048 void
2049 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2050 {
2051         rte_spinlock_init(&sp->spinlock);
2052 }
2053
2054 void
2055 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2056 {
2057         rte_spinlock_lock(&sp->spinlock);
2058 }
2059
2060 void
2061 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2062 {
2063         rte_spinlock_unlock(&sp->spinlock);
2064 }
2065
2066 void
2067 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2068 {
2069         return;
2070 }
2071
2072 /**
2073  * Get the hardware capabilities, which will be parsed
2074  * and saved into struct i40e_hw.
2075  */
2076 static int
2077 i40e_get_cap(struct i40e_hw *hw)
2078 {
2079         struct i40e_aqc_list_capabilities_element_resp *buf;
2080         uint16_t len, size = 0;
2081         int ret;
2082
2083         /* Calculate a huge enough buff for saving response data temporarily */
2084         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2085                                                 I40E_MAX_CAP_ELE_NUM;
2086         buf = rte_zmalloc("i40e", len, 0);
2087         if (!buf) {
2088                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2089                 return I40E_ERR_NO_MEMORY;
2090         }
2091
2092         /* Get, parse the capabilities and save it to hw */
2093         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2094                         i40e_aqc_opc_list_func_capabilities, NULL);
2095         if (ret != I40E_SUCCESS)
2096                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2097
2098         /* Free the temporary buffer after being used */
2099         rte_free(buf);
2100
2101         return ret;
2102 }
2103
2104 static int
2105 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2106 {
2107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2108         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2109         uint16_t sum_queues = 0, sum_vsis, left_queues;
2110
2111         /* First check if FW support SRIOV */
2112         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2113                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2114                 return -EINVAL;
2115         }
2116
2117         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2118         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2119         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2120         /* Allocate queues for pf */
2121         if (hw->func_caps.rss) {
2122                 pf->flags |= I40E_FLAG_RSS;
2123                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2124                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2125                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2126         } else
2127                 pf->lan_nb_qps = 1;
2128         sum_queues = pf->lan_nb_qps;
2129         /* Default VSI is not counted in */
2130         sum_vsis = 0;
2131         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2132
2133         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2134                 pf->flags |= I40E_FLAG_SRIOV;
2135                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2136                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2137                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2138                                      "max supported %u.",
2139                                      dev->pci_dev->max_vfs,
2140                                      hw->func_caps.num_vfs);
2141                         return -EINVAL;
2142                 }
2143                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2144                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2145                                      "max support %u queues.",
2146                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2147                         return -EINVAL;
2148                 }
2149                 pf->vf_num = dev->pci_dev->max_vfs;
2150                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2151                 sum_vsis   += pf->vf_num;
2152                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2153                              pf->vf_num, pf->vf_nb_qps);
2154         } else
2155                 pf->vf_num = 0;
2156
2157         if (hw->func_caps.vmdq) {
2158                 pf->flags |= I40E_FLAG_VMDQ;
2159                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2160                 pf->max_nb_vmdq_vsi = 1;
2161                 /*
2162                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2163                  * later.
2164                  */
2165                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2166                 sum_vsis += pf->max_nb_vmdq_vsi;
2167         } else {
2168                 pf->vmdq_nb_qps = 0;
2169                 pf->max_nb_vmdq_vsi = 0;
2170         }
2171         pf->nb_cfg_vmdq_vsi = 0;
2172
2173         if (hw->func_caps.fd) {
2174                 pf->flags |= I40E_FLAG_FDIR;
2175                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2176                 /**
2177                  * Each flow director consumes one VSI and one queue,
2178                  * but can't calculate out predictably here.
2179                  */
2180         }
2181
2182         if (sum_vsis > pf->max_num_vsi ||
2183                 sum_queues > hw->func_caps.num_rx_qp) {
2184                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2185                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2186                              pf->max_num_vsi, sum_vsis);
2187                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2188                              hw->func_caps.num_rx_qp, sum_queues);
2189                 return -EINVAL;
2190         }
2191
2192         /* Adjust VMDQ setting to support as many VMs as possible */
2193         if (pf->flags & I40E_FLAG_VMDQ) {
2194                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2195
2196                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2197                                         pf->max_num_vsi - sum_vsis);
2198
2199                 /* Limit the max VMDQ number that rte_ether that can support  */
2200                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2201                                         ETH_64_POOLS - 1);
2202
2203                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2204                                 pf->max_nb_vmdq_vsi);
2205                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2206         }
2207
2208         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2209          * cause */
2210         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2211                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2212                              sum_vsis, hw->func_caps.num_msix_vectors);
2213                 return -EINVAL;
2214         }
2215         return I40E_SUCCESS;
2216 }
2217
2218 static int
2219 i40e_pf_get_switch_config(struct i40e_pf *pf)
2220 {
2221         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2222         struct i40e_aqc_get_switch_config_resp *switch_config;
2223         struct i40e_aqc_switch_config_element_resp *element;
2224         uint16_t start_seid = 0, num_reported;
2225         int ret;
2226
2227         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2228                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2229         if (!switch_config) {
2230                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2231                 return -ENOMEM;
2232         }
2233
2234         /* Get the switch configurations */
2235         ret = i40e_aq_get_switch_config(hw, switch_config,
2236                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2237         if (ret != I40E_SUCCESS) {
2238                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2239                 goto fail;
2240         }
2241         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2242         if (num_reported != 1) { /* The number should be 1 */
2243                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2244                 goto fail;
2245         }
2246
2247         /* Parse the switch configuration elements */
2248         element = &(switch_config->element[0]);
2249         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2250                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2251                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2252         } else
2253                 PMD_DRV_LOG(INFO, "Unknown element type");
2254
2255 fail:
2256         rte_free(switch_config);
2257
2258         return ret;
2259 }
2260
2261 static int
2262 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2263                         uint32_t num)
2264 {
2265         struct pool_entry *entry;
2266
2267         if (pool == NULL || num == 0)
2268                 return -EINVAL;
2269
2270         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2271         if (entry == NULL) {
2272                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2273                 return -ENOMEM;
2274         }
2275
2276         /* queue heap initialize */
2277         pool->num_free = num;
2278         pool->num_alloc = 0;
2279         pool->base = base;
2280         LIST_INIT(&pool->alloc_list);
2281         LIST_INIT(&pool->free_list);
2282
2283         /* Initialize element  */
2284         entry->base = 0;
2285         entry->len = num;
2286
2287         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2288         return 0;
2289 }
2290
2291 static void
2292 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2293 {
2294         struct pool_entry *entry;
2295
2296         if (pool == NULL)
2297                 return;
2298
2299         LIST_FOREACH(entry, &pool->alloc_list, next) {
2300                 LIST_REMOVE(entry, next);
2301                 rte_free(entry);
2302         }
2303
2304         LIST_FOREACH(entry, &pool->free_list, next) {
2305                 LIST_REMOVE(entry, next);
2306                 rte_free(entry);
2307         }
2308
2309         pool->num_free = 0;
2310         pool->num_alloc = 0;
2311         pool->base = 0;
2312         LIST_INIT(&pool->alloc_list);
2313         LIST_INIT(&pool->free_list);
2314 }
2315
2316 static int
2317 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2318                        uint32_t base)
2319 {
2320         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2321         uint32_t pool_offset;
2322         int insert;
2323
2324         if (pool == NULL) {
2325                 PMD_DRV_LOG(ERR, "Invalid parameter");
2326                 return -EINVAL;
2327         }
2328
2329         pool_offset = base - pool->base;
2330         /* Lookup in alloc list */
2331         LIST_FOREACH(entry, &pool->alloc_list, next) {
2332                 if (entry->base == pool_offset) {
2333                         valid_entry = entry;
2334                         LIST_REMOVE(entry, next);
2335                         break;
2336                 }
2337         }
2338
2339         /* Not find, return */
2340         if (valid_entry == NULL) {
2341                 PMD_DRV_LOG(ERR, "Failed to find entry");
2342                 return -EINVAL;
2343         }
2344
2345         /**
2346          * Found it, move it to free list  and try to merge.
2347          * In order to make merge easier, always sort it by qbase.
2348          * Find adjacent prev and last entries.
2349          */
2350         prev = next = NULL;
2351         LIST_FOREACH(entry, &pool->free_list, next) {
2352                 if (entry->base > valid_entry->base) {
2353                         next = entry;
2354                         break;
2355                 }
2356                 prev = entry;
2357         }
2358
2359         insert = 0;
2360         /* Try to merge with next one*/
2361         if (next != NULL) {
2362                 /* Merge with next one */
2363                 if (valid_entry->base + valid_entry->len == next->base) {
2364                         next->base = valid_entry->base;
2365                         next->len += valid_entry->len;
2366                         rte_free(valid_entry);
2367                         valid_entry = next;
2368                         insert = 1;
2369                 }
2370         }
2371
2372         if (prev != NULL) {
2373                 /* Merge with previous one */
2374                 if (prev->base + prev->len == valid_entry->base) {
2375                         prev->len += valid_entry->len;
2376                         /* If it merge with next one, remove next node */
2377                         if (insert == 1) {
2378                                 LIST_REMOVE(valid_entry, next);
2379                                 rte_free(valid_entry);
2380                         } else {
2381                                 rte_free(valid_entry);
2382                                 insert = 1;
2383                         }
2384                 }
2385         }
2386
2387         /* Not find any entry to merge, insert */
2388         if (insert == 0) {
2389                 if (prev != NULL)
2390                         LIST_INSERT_AFTER(prev, valid_entry, next);
2391                 else if (next != NULL)
2392                         LIST_INSERT_BEFORE(next, valid_entry, next);
2393                 else /* It's empty list, insert to head */
2394                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2395         }
2396
2397         pool->num_free += valid_entry->len;
2398         pool->num_alloc -= valid_entry->len;
2399
2400         return 0;
2401 }
2402
2403 static int
2404 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2405                        uint16_t num)
2406 {
2407         struct pool_entry *entry, *valid_entry;
2408
2409         if (pool == NULL || num == 0) {
2410                 PMD_DRV_LOG(ERR, "Invalid parameter");
2411                 return -EINVAL;
2412         }
2413
2414         if (pool->num_free < num) {
2415                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2416                             num, pool->num_free);
2417                 return -ENOMEM;
2418         }
2419
2420         valid_entry = NULL;
2421         /* Lookup  in free list and find most fit one */
2422         LIST_FOREACH(entry, &pool->free_list, next) {
2423                 if (entry->len >= num) {
2424                         /* Find best one */
2425                         if (entry->len == num) {
2426                                 valid_entry = entry;
2427                                 break;
2428                         }
2429                         if (valid_entry == NULL || valid_entry->len > entry->len)
2430                                 valid_entry = entry;
2431                 }
2432         }
2433
2434         /* Not find one to satisfy the request, return */
2435         if (valid_entry == NULL) {
2436                 PMD_DRV_LOG(ERR, "No valid entry found");
2437                 return -ENOMEM;
2438         }
2439         /**
2440          * The entry have equal queue number as requested,
2441          * remove it from alloc_list.
2442          */
2443         if (valid_entry->len == num) {
2444                 LIST_REMOVE(valid_entry, next);
2445         } else {
2446                 /**
2447                  * The entry have more numbers than requested,
2448                  * create a new entry for alloc_list and minus its
2449                  * queue base and number in free_list.
2450                  */
2451                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2452                 if (entry == NULL) {
2453                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2454                                     "resource pool");
2455                         return -ENOMEM;
2456                 }
2457                 entry->base = valid_entry->base;
2458                 entry->len = num;
2459                 valid_entry->base += num;
2460                 valid_entry->len -= num;
2461                 valid_entry = entry;
2462         }
2463
2464         /* Insert it into alloc list, not sorted */
2465         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2466
2467         pool->num_free -= valid_entry->len;
2468         pool->num_alloc += valid_entry->len;
2469
2470         return (valid_entry->base + pool->base);
2471 }
2472
2473 /**
2474  * bitmap_is_subset - Check whether src2 is subset of src1
2475  **/
2476 static inline int
2477 bitmap_is_subset(uint8_t src1, uint8_t src2)
2478 {
2479         return !((src1 ^ src2) & src2);
2480 }
2481
2482 static int
2483 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2484 {
2485         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2486
2487         /* If DCB is not supported, only default TC is supported */
2488         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2489                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2490                 return -EINVAL;
2491         }
2492
2493         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2494                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2495                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2496                             enabled_tcmap);
2497                 return -EINVAL;
2498         }
2499         return I40E_SUCCESS;
2500 }
2501
2502 int
2503 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2504                                 struct i40e_vsi_vlan_pvid_info *info)
2505 {
2506         struct i40e_hw *hw;
2507         struct i40e_vsi_context ctxt;
2508         uint8_t vlan_flags = 0;
2509         int ret;
2510
2511         if (vsi == NULL || info == NULL) {
2512                 PMD_DRV_LOG(ERR, "invalid parameters");
2513                 return I40E_ERR_PARAM;
2514         }
2515
2516         if (info->on) {
2517                 vsi->info.pvid = info->config.pvid;
2518                 /**
2519                  * If insert pvid is enabled, only tagged pkts are
2520                  * allowed to be sent out.
2521                  */
2522                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2523                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2524         } else {
2525                 vsi->info.pvid = 0;
2526                 if (info->config.reject.tagged == 0)
2527                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2528
2529                 if (info->config.reject.untagged == 0)
2530                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2531         }
2532         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2533                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2534         vsi->info.port_vlan_flags |= vlan_flags;
2535         vsi->info.valid_sections =
2536                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2537         memset(&ctxt, 0, sizeof(ctxt));
2538         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2539         ctxt.seid = vsi->seid;
2540
2541         hw = I40E_VSI_TO_HW(vsi);
2542         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2543         if (ret != I40E_SUCCESS)
2544                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2545
2546         return ret;
2547 }
2548
2549 static int
2550 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2551 {
2552         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2553         int i, ret;
2554         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2555
2556         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2557         if (ret != I40E_SUCCESS)
2558                 return ret;
2559
2560         if (!vsi->seid) {
2561                 PMD_DRV_LOG(ERR, "seid not valid");
2562                 return -EINVAL;
2563         }
2564
2565         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2566         tc_bw_data.tc_valid_bits = enabled_tcmap;
2567         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2568                 tc_bw_data.tc_bw_credits[i] =
2569                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2570
2571         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2572         if (ret != I40E_SUCCESS) {
2573                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2574                 return ret;
2575         }
2576
2577         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2578                                         sizeof(vsi->info.qs_handle));
2579         return I40E_SUCCESS;
2580 }
2581
2582 static int
2583 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2584                                  struct i40e_aqc_vsi_properties_data *info,
2585                                  uint8_t enabled_tcmap)
2586 {
2587         int ret, total_tc = 0, i;
2588         uint16_t qpnum_per_tc, bsf, qp_idx;
2589
2590         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2591         if (ret != I40E_SUCCESS)
2592                 return ret;
2593
2594         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2595                 if (enabled_tcmap & (1 << i))
2596                         total_tc++;
2597         vsi->enabled_tc = enabled_tcmap;
2598
2599         /* Number of queues per enabled TC */
2600         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2601         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2602         bsf = rte_bsf32(qpnum_per_tc);
2603
2604         /* Adjust the queue number to actual queues that can be applied */
2605         vsi->nb_qps = qpnum_per_tc * total_tc;
2606
2607         /**
2608          * Configure TC and queue mapping parameters, for enabled TC,
2609          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2610          * default queue will serve it.
2611          */
2612         qp_idx = 0;
2613         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2614                 if (vsi->enabled_tc & (1 << i)) {
2615                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2616                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2617                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2618                         qp_idx += qpnum_per_tc;
2619                 } else
2620                         info->tc_mapping[i] = 0;
2621         }
2622
2623         /* Associate queue number with VSI */
2624         if (vsi->type == I40E_VSI_SRIOV) {
2625                 info->mapping_flags |=
2626                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2627                 for (i = 0; i < vsi->nb_qps; i++)
2628                         info->queue_mapping[i] =
2629                                 rte_cpu_to_le_16(vsi->base_queue + i);
2630         } else {
2631                 info->mapping_flags |=
2632                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2633                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2634         }
2635         info->valid_sections =
2636                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2637
2638         return I40E_SUCCESS;
2639 }
2640
2641 static int
2642 i40e_veb_release(struct i40e_veb *veb)
2643 {
2644         struct i40e_vsi *vsi;
2645         struct i40e_hw *hw;
2646
2647         if (veb == NULL || veb->associate_vsi == NULL)
2648                 return -EINVAL;
2649
2650         if (!TAILQ_EMPTY(&veb->head)) {
2651                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2652                 return -EACCES;
2653         }
2654
2655         vsi = veb->associate_vsi;
2656         hw = I40E_VSI_TO_HW(vsi);
2657
2658         vsi->uplink_seid = veb->uplink_seid;
2659         i40e_aq_delete_element(hw, veb->seid, NULL);
2660         rte_free(veb);
2661         vsi->veb = NULL;
2662         return I40E_SUCCESS;
2663 }
2664
2665 /* Setup a veb */
2666 static struct i40e_veb *
2667 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2668 {
2669         struct i40e_veb *veb;
2670         int ret;
2671         struct i40e_hw *hw;
2672
2673         if (NULL == pf || vsi == NULL) {
2674                 PMD_DRV_LOG(ERR, "veb setup failed, "
2675                             "associated VSI shouldn't null");
2676                 return NULL;
2677         }
2678         hw = I40E_PF_TO_HW(pf);
2679
2680         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2681         if (!veb) {
2682                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2683                 goto fail;
2684         }
2685
2686         veb->associate_vsi = vsi;
2687         TAILQ_INIT(&veb->head);
2688         veb->uplink_seid = vsi->uplink_seid;
2689
2690         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2691                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2692
2693         if (ret != I40E_SUCCESS) {
2694                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2695                             hw->aq.asq_last_status);
2696                 goto fail;
2697         }
2698
2699         /* get statistics index */
2700         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2701                                 &veb->stats_idx, NULL, NULL, NULL);
2702         if (ret != I40E_SUCCESS) {
2703                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2704                             hw->aq.asq_last_status);
2705                 goto fail;
2706         }
2707
2708         /* Get VEB bandwidth, to be implemented */
2709         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2710         vsi->uplink_seid = veb->seid;
2711
2712         return veb;
2713 fail:
2714         rte_free(veb);
2715         return NULL;
2716 }
2717
2718 int
2719 i40e_vsi_release(struct i40e_vsi *vsi)
2720 {
2721         struct i40e_pf *pf;
2722         struct i40e_hw *hw;
2723         struct i40e_vsi_list *vsi_list;
2724         int ret;
2725         struct i40e_mac_filter *f;
2726
2727         if (!vsi)
2728                 return I40E_SUCCESS;
2729
2730         pf = I40E_VSI_TO_PF(vsi);
2731         hw = I40E_VSI_TO_HW(vsi);
2732
2733         /* VSI has child to attach, release child first */
2734         if (vsi->veb) {
2735                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2736                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2737                                 return -1;
2738                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2739                 }
2740                 i40e_veb_release(vsi->veb);
2741         }
2742
2743         /* Remove all macvlan filters of the VSI */
2744         i40e_vsi_remove_all_macvlan_filter(vsi);
2745         TAILQ_FOREACH(f, &vsi->mac_list, next)
2746                 rte_free(f);
2747
2748         if (vsi->type != I40E_VSI_MAIN) {
2749                 /* Remove vsi from parent's sibling list */
2750                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2751                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2752                         return I40E_ERR_PARAM;
2753                 }
2754                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2755                                 &vsi->sib_vsi_list, list);
2756
2757                 /* Remove all switch element of the VSI */
2758                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2759                 if (ret != I40E_SUCCESS)
2760                         PMD_DRV_LOG(ERR, "Failed to delete element");
2761         }
2762         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2763
2764         if (vsi->type != I40E_VSI_SRIOV)
2765                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2766         rte_free(vsi);
2767
2768         return I40E_SUCCESS;
2769 }
2770
2771 static int
2772 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2773 {
2774         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2775         struct i40e_aqc_remove_macvlan_element_data def_filter;
2776         struct i40e_mac_filter_info filter;
2777         int ret;
2778
2779         if (vsi->type != I40E_VSI_MAIN)
2780                 return I40E_ERR_CONFIG;
2781         memset(&def_filter, 0, sizeof(def_filter));
2782         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2783                                         ETH_ADDR_LEN);
2784         def_filter.vlan_tag = 0;
2785         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2786                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2787         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2788         if (ret != I40E_SUCCESS) {
2789                 struct i40e_mac_filter *f;
2790                 struct ether_addr *mac;
2791
2792                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2793                             "macvlan filter");
2794                 /* It needs to add the permanent mac into mac list */
2795                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2796                 if (f == NULL) {
2797                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2798                         return I40E_ERR_NO_MEMORY;
2799                 }
2800                 mac = &f->mac_info.mac_addr;
2801                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2802                                 ETH_ADDR_LEN);
2803                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2804                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2805                 vsi->mac_num++;
2806
2807                 return ret;
2808         }
2809         (void)rte_memcpy(&filter.mac_addr,
2810                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2811         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2812         return i40e_vsi_add_mac(vsi, &filter);
2813 }
2814
2815 static int
2816 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2817 {
2818         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2819         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2820         struct i40e_hw *hw = &vsi->adapter->hw;
2821         i40e_status ret;
2822         int i;
2823
2824         memset(&bw_config, 0, sizeof(bw_config));
2825         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2826         if (ret != I40E_SUCCESS) {
2827                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2828                             hw->aq.asq_last_status);
2829                 return ret;
2830         }
2831
2832         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2833         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2834                                         &ets_sla_config, NULL);
2835         if (ret != I40E_SUCCESS) {
2836                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2837                             "configuration %u", hw->aq.asq_last_status);
2838                 return ret;
2839         }
2840
2841         /* Not store the info yet, just print out */
2842         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2843         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2844         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2845                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2846                             ets_sla_config.share_credits[i]);
2847                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2848                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2849                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2850                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2851                             (i * 4));
2852         }
2853
2854         return 0;
2855 }
2856
2857 /* Setup a VSI */
2858 struct i40e_vsi *
2859 i40e_vsi_setup(struct i40e_pf *pf,
2860                enum i40e_vsi_type type,
2861                struct i40e_vsi *uplink_vsi,
2862                uint16_t user_param)
2863 {
2864         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2865         struct i40e_vsi *vsi;
2866         struct i40e_mac_filter_info filter;
2867         int ret;
2868         struct i40e_vsi_context ctxt;
2869         struct ether_addr broadcast =
2870                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2871
2872         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2873                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2874                             "VSI link shouldn't be NULL");
2875                 return NULL;
2876         }
2877
2878         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2879                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2880                             "uplink VSI should be NULL");
2881                 return NULL;
2882         }
2883
2884         /* If uplink vsi didn't setup VEB, create one first */
2885         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2886                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2887
2888                 if (NULL == uplink_vsi->veb) {
2889                         PMD_DRV_LOG(ERR, "VEB setup failed");
2890                         return NULL;
2891                 }
2892         }
2893
2894         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2895         if (!vsi) {
2896                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2897                 return NULL;
2898         }
2899         TAILQ_INIT(&vsi->mac_list);
2900         vsi->type = type;
2901         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2902         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2903         vsi->parent_vsi = uplink_vsi;
2904         vsi->user_param = user_param;
2905         /* Allocate queues */
2906         switch (vsi->type) {
2907         case I40E_VSI_MAIN  :
2908                 vsi->nb_qps = pf->lan_nb_qps;
2909                 break;
2910         case I40E_VSI_SRIOV :
2911                 vsi->nb_qps = pf->vf_nb_qps;
2912                 break;
2913         case I40E_VSI_VMDQ2:
2914                 vsi->nb_qps = pf->vmdq_nb_qps;
2915                 break;
2916         case I40E_VSI_FDIR:
2917                 vsi->nb_qps = pf->fdir_nb_qps;
2918                 break;
2919         default:
2920                 goto fail_mem;
2921         }
2922         /*
2923          * The filter status descriptor is reported in rx queue 0,
2924          * while the tx queue for fdir filter programming has no
2925          * such constraints, can be non-zero queues.
2926          * To simplify it, choose FDIR vsi use queue 0 pair.
2927          * To make sure it will use queue 0 pair, queue allocation
2928          * need be done before this function is called
2929          */
2930         if (type != I40E_VSI_FDIR) {
2931                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2932                         if (ret < 0) {
2933                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2934                                                 vsi->seid, ret);
2935                                 goto fail_mem;
2936                         }
2937                         vsi->base_queue = ret;
2938         } else
2939                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2940
2941         /* VF has MSIX interrupt in VF range, don't allocate here */
2942         if (type != I40E_VSI_SRIOV) {
2943                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2944                 if (ret < 0) {
2945                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2946                         goto fail_queue_alloc;
2947                 }
2948                 vsi->msix_intr = ret;
2949         } else
2950                 vsi->msix_intr = 0;
2951         /* Add VSI */
2952         if (type == I40E_VSI_MAIN) {
2953                 /* For main VSI, no need to add since it's default one */
2954                 vsi->uplink_seid = pf->mac_seid;
2955                 vsi->seid = pf->main_vsi_seid;
2956                 /* Bind queues with specific MSIX interrupt */
2957                 /**
2958                  * Needs 2 interrupt at least, one for misc cause which will
2959                  * enabled from OS side, Another for queues binding the
2960                  * interrupt from device side only.
2961                  */
2962
2963                 /* Get default VSI parameters from hardware */
2964                 memset(&ctxt, 0, sizeof(ctxt));
2965                 ctxt.seid = vsi->seid;
2966                 ctxt.pf_num = hw->pf_id;
2967                 ctxt.uplink_seid = vsi->uplink_seid;
2968                 ctxt.vf_num = 0;
2969                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2970                 if (ret != I40E_SUCCESS) {
2971                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2972                         goto fail_msix_alloc;
2973                 }
2974                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2975                         sizeof(struct i40e_aqc_vsi_properties_data));
2976                 vsi->vsi_id = ctxt.vsi_number;
2977                 vsi->info.valid_sections = 0;
2978
2979                 /* Configure tc, enabled TC0 only */
2980                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2981                         I40E_SUCCESS) {
2982                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2983                         goto fail_msix_alloc;
2984                 }
2985
2986                 /* TC, queue mapping */
2987                 memset(&ctxt, 0, sizeof(ctxt));
2988                 vsi->info.valid_sections |=
2989                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2990                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2991                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2992                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2993                         sizeof(struct i40e_aqc_vsi_properties_data));
2994                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2995                                                 I40E_DEFAULT_TCMAP);
2996                 if (ret != I40E_SUCCESS) {
2997                         PMD_DRV_LOG(ERR, "Failed to configure "
2998                                     "TC queue mapping");
2999                         goto fail_msix_alloc;
3000                 }
3001                 ctxt.seid = vsi->seid;
3002                 ctxt.pf_num = hw->pf_id;
3003                 ctxt.uplink_seid = vsi->uplink_seid;
3004                 ctxt.vf_num = 0;
3005
3006                 /* Update VSI parameters */
3007                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3008                 if (ret != I40E_SUCCESS) {
3009                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3010                         goto fail_msix_alloc;
3011                 }
3012
3013                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3014                                                 sizeof(vsi->info.tc_mapping));
3015                 (void)rte_memcpy(&vsi->info.queue_mapping,
3016                                 &ctxt.info.queue_mapping,
3017                         sizeof(vsi->info.queue_mapping));
3018                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3019                 vsi->info.valid_sections = 0;
3020
3021                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3022                                 ETH_ADDR_LEN);
3023
3024                 /**
3025                  * Updating default filter settings are necessary to prevent
3026                  * reception of tagged packets.
3027                  * Some old firmware configurations load a default macvlan
3028                  * filter which accepts both tagged and untagged packets.
3029                  * The updating is to use a normal filter instead if needed.
3030                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3031                  * The firmware with correct configurations load the default
3032                  * macvlan filter which is expected and cannot be removed.
3033                  */
3034                 i40e_update_default_filter_setting(vsi);
3035         } else if (type == I40E_VSI_SRIOV) {
3036                 memset(&ctxt, 0, sizeof(ctxt));
3037                 /**
3038                  * For other VSI, the uplink_seid equals to uplink VSI's
3039                  * uplink_seid since they share same VEB
3040                  */
3041                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3042                 ctxt.pf_num = hw->pf_id;
3043                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3044                 ctxt.uplink_seid = vsi->uplink_seid;
3045                 ctxt.connection_type = 0x1;
3046                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3047
3048                 /* Configure switch ID */
3049                 ctxt.info.valid_sections |=
3050                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3051                 ctxt.info.switch_id =
3052                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3053                 /* Configure port/vlan */
3054                 ctxt.info.valid_sections |=
3055                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3056                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3057                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3058                                                 I40E_DEFAULT_TCMAP);
3059                 if (ret != I40E_SUCCESS) {
3060                         PMD_DRV_LOG(ERR, "Failed to configure "
3061                                     "TC queue mapping");
3062                         goto fail_msix_alloc;
3063                 }
3064                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3065                 ctxt.info.valid_sections |=
3066                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3067                 /**
3068                  * Since VSI is not created yet, only configure parameter,
3069                  * will add vsi below.
3070                  */
3071         } else if (type == I40E_VSI_VMDQ2) {
3072                 memset(&ctxt, 0, sizeof(ctxt));
3073                 /*
3074                  * For other VSI, the uplink_seid equals to uplink VSI's
3075                  * uplink_seid since they share same VEB
3076                  */
3077                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3078                 ctxt.pf_num = hw->pf_id;
3079                 ctxt.vf_num = 0;
3080                 ctxt.uplink_seid = vsi->uplink_seid;
3081                 ctxt.connection_type = 0x1;
3082                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3083
3084                 ctxt.info.valid_sections |=
3085                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3086                 /* user_param carries flag to enable loop back */
3087                 if (user_param) {
3088                         ctxt.info.switch_id =
3089                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3090                         ctxt.info.switch_id |=
3091                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3092                 }
3093
3094                 /* Configure port/vlan */
3095                 ctxt.info.valid_sections |=
3096                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3097                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3098                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3099                                                 I40E_DEFAULT_TCMAP);
3100                 if (ret != I40E_SUCCESS) {
3101                         PMD_DRV_LOG(ERR, "Failed to configure "
3102                                         "TC queue mapping");
3103                         goto fail_msix_alloc;
3104                 }
3105                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3106                 ctxt.info.valid_sections |=
3107                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3108         } else if (type == I40E_VSI_FDIR) {
3109                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3110                 ctxt.pf_num = hw->pf_id;
3111                 ctxt.vf_num = 0;
3112                 ctxt.uplink_seid = vsi->uplink_seid;
3113                 ctxt.connection_type = 0x1;     /* regular data port */
3114                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3115                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3116                                                 I40E_DEFAULT_TCMAP);
3117                 if (ret != I40E_SUCCESS) {
3118                         PMD_DRV_LOG(ERR, "Failed to configure "
3119                                         "TC queue mapping.");
3120                         goto fail_msix_alloc;
3121                 }
3122                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3123                 ctxt.info.valid_sections |=
3124                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3125         } else {
3126                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3127                 goto fail_msix_alloc;
3128         }
3129
3130         if (vsi->type != I40E_VSI_MAIN) {
3131                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3132                 if (ret) {
3133                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3134                                     hw->aq.asq_last_status);
3135                         goto fail_msix_alloc;
3136                 }
3137                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3138                 vsi->info.valid_sections = 0;
3139                 vsi->seid = ctxt.seid;
3140                 vsi->vsi_id = ctxt.vsi_number;
3141                 vsi->sib_vsi_list.vsi = vsi;
3142                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3143                                 &vsi->sib_vsi_list, list);
3144         }
3145
3146         /* MAC/VLAN configuration */
3147         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3148         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3149
3150         ret = i40e_vsi_add_mac(vsi, &filter);
3151         if (ret != I40E_SUCCESS) {
3152                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3153                 goto fail_msix_alloc;
3154         }
3155
3156         /* Get VSI BW information */
3157         i40e_vsi_dump_bw_config(vsi);
3158         return vsi;
3159 fail_msix_alloc:
3160         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3161 fail_queue_alloc:
3162         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3163 fail_mem:
3164         rte_free(vsi);
3165         return NULL;
3166 }
3167
3168 /* Configure vlan stripping on or off */
3169 int
3170 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3171 {
3172         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3173         struct i40e_vsi_context ctxt;
3174         uint8_t vlan_flags;
3175         int ret = I40E_SUCCESS;
3176
3177         /* Check if it has been already on or off */
3178         if (vsi->info.valid_sections &
3179                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3180                 if (on) {
3181                         if ((vsi->info.port_vlan_flags &
3182                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3183                                 return 0; /* already on */
3184                 } else {
3185                         if ((vsi->info.port_vlan_flags &
3186                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3187                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3188                                 return 0; /* already off */
3189                 }
3190         }
3191
3192         if (on)
3193                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3194         else
3195                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3196         vsi->info.valid_sections =
3197                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3198         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3199         vsi->info.port_vlan_flags |= vlan_flags;
3200         ctxt.seid = vsi->seid;
3201         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3202         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3203         if (ret)
3204                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3205                             on ? "enable" : "disable");
3206
3207         return ret;
3208 }
3209
3210 static int
3211 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3212 {
3213         struct rte_eth_dev_data *data = dev->data;
3214         int ret;
3215
3216         /* Apply vlan offload setting */
3217         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3218
3219         /* Apply double-vlan setting, not implemented yet */
3220
3221         /* Apply pvid setting */
3222         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3223                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3224         if (ret)
3225                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3226
3227         return ret;
3228 }
3229
3230 static int
3231 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3232 {
3233         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3234
3235         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3236 }
3237
3238 static int
3239 i40e_update_flow_control(struct i40e_hw *hw)
3240 {
3241 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3242         struct i40e_link_status link_status;
3243         uint32_t rxfc = 0, txfc = 0, reg;
3244         uint8_t an_info;
3245         int ret;
3246
3247         memset(&link_status, 0, sizeof(link_status));
3248         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3249         if (ret != I40E_SUCCESS) {
3250                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3251                 goto write_reg; /* Disable flow control */
3252         }
3253
3254         an_info = hw->phy.link_info.an_info;
3255         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3256                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3257                 ret = I40E_ERR_NOT_READY;
3258                 goto write_reg; /* Disable flow control */
3259         }
3260         /**
3261          * If link auto negotiation is enabled, flow control needs to
3262          * be configured according to it
3263          */
3264         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3265         case I40E_LINK_PAUSE_RXTX:
3266                 rxfc = 1;
3267                 txfc = 1;
3268                 hw->fc.current_mode = I40E_FC_FULL;
3269                 break;
3270         case I40E_AQ_LINK_PAUSE_RX:
3271                 rxfc = 1;
3272                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3273                 break;
3274         case I40E_AQ_LINK_PAUSE_TX:
3275                 txfc = 1;
3276                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3277                 break;
3278         default:
3279                 hw->fc.current_mode = I40E_FC_NONE;
3280                 break;
3281         }
3282
3283 write_reg:
3284         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3285                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3286         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3287         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3288         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3289         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3290
3291         return ret;
3292 }
3293
3294 /* PF setup */
3295 static int
3296 i40e_pf_setup(struct i40e_pf *pf)
3297 {
3298         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3299         struct i40e_filter_control_settings settings;
3300         struct i40e_vsi *vsi;
3301         int ret;
3302
3303         /* Clear all stats counters */
3304         pf->offset_loaded = FALSE;
3305         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3306         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3307
3308         ret = i40e_pf_get_switch_config(pf);
3309         if (ret != I40E_SUCCESS) {
3310                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3311                 return ret;
3312         }
3313         if (pf->flags & I40E_FLAG_FDIR) {
3314                 /* make queue allocated first, let FDIR use queue pair 0*/
3315                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3316                 if (ret != I40E_FDIR_QUEUE_ID) {
3317                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3318                                     " ret =%d", ret);
3319                         pf->flags &= ~I40E_FLAG_FDIR;
3320                 }
3321         }
3322         /*  main VSI setup */
3323         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3324         if (!vsi) {
3325                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3326                 return I40E_ERR_NOT_READY;
3327         }
3328         pf->main_vsi = vsi;
3329
3330         /* Configure filter control */
3331         memset(&settings, 0, sizeof(settings));
3332         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3333                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3334         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3335                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3336         else {
3337                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3338                                                 hw->func_caps.rss_table_size);
3339                 return I40E_ERR_PARAM;
3340         }
3341         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3342                         "size: %u\n", hw->func_caps.rss_table_size);
3343         pf->hash_lut_size = hw->func_caps.rss_table_size;
3344
3345         /* Enable ethtype and macvlan filters */
3346         settings.enable_ethtype = TRUE;
3347         settings.enable_macvlan = TRUE;
3348         ret = i40e_set_filter_control(hw, &settings);
3349         if (ret)
3350                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3351                                                                 ret);
3352
3353         /* Update flow control according to the auto negotiation */
3354         i40e_update_flow_control(hw);
3355
3356         return I40E_SUCCESS;
3357 }
3358
3359 int
3360 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3361 {
3362         uint32_t reg;
3363         uint16_t j;
3364
3365         /**
3366          * Set or clear TX Queue Disable flags,
3367          * which is required by hardware.
3368          */
3369         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3370         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3371
3372         /* Wait until the request is finished */
3373         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3374                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3375                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3376                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3377                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3378                                                         & 0x1))) {
3379                         break;
3380                 }
3381         }
3382         if (on) {
3383                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3384                         return I40E_SUCCESS; /* already on, skip next steps */
3385
3386                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3387                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3388         } else {
3389                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3390                         return I40E_SUCCESS; /* already off, skip next steps */
3391                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3392         }
3393         /* Write the register */
3394         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3395         /* Check the result */
3396         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3397                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3398                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3399                 if (on) {
3400                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3401                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3402                                 break;
3403                 } else {
3404                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3405                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3406                                 break;
3407                 }
3408         }
3409         /* Check if it is timeout */
3410         if (j >= I40E_CHK_Q_ENA_COUNT) {
3411                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3412                             (on ? "enable" : "disable"), q_idx);
3413                 return I40E_ERR_TIMEOUT;
3414         }
3415
3416         return I40E_SUCCESS;
3417 }
3418
3419 /* Swith on or off the tx queues */
3420 static int
3421 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3422 {
3423         struct rte_eth_dev_data *dev_data = pf->dev_data;
3424         struct i40e_tx_queue *txq;
3425         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3426         uint16_t i;
3427         int ret;
3428
3429         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3430                 txq = dev_data->tx_queues[i];
3431                 /* Don't operate the queue if not configured or
3432                  * if starting only per queue */
3433                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3434                         continue;
3435                 if (on)
3436                         ret = i40e_dev_tx_queue_start(dev, i);
3437                 else
3438                         ret = i40e_dev_tx_queue_stop(dev, i);
3439                 if ( ret != I40E_SUCCESS)
3440                         return ret;
3441         }
3442
3443         return I40E_SUCCESS;
3444 }
3445
3446 int
3447 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3448 {
3449         uint32_t reg;
3450         uint16_t j;
3451
3452         /* Wait until the request is finished */
3453         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3454                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3455                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3456                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3457                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3458                         break;
3459         }
3460
3461         if (on) {
3462                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3463                         return I40E_SUCCESS; /* Already on, skip next steps */
3464                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3465         } else {
3466                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3467                         return I40E_SUCCESS; /* Already off, skip next steps */
3468                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3469         }
3470
3471         /* Write the register */
3472         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3473         /* Check the result */
3474         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3475                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3476                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3477                 if (on) {
3478                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3479                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3480                                 break;
3481                 } else {
3482                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3483                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3484                                 break;
3485                 }
3486         }
3487
3488         /* Check if it is timeout */
3489         if (j >= I40E_CHK_Q_ENA_COUNT) {
3490                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3491                             (on ? "enable" : "disable"), q_idx);
3492                 return I40E_ERR_TIMEOUT;
3493         }
3494
3495         return I40E_SUCCESS;
3496 }
3497 /* Switch on or off the rx queues */
3498 static int
3499 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3500 {
3501         struct rte_eth_dev_data *dev_data = pf->dev_data;
3502         struct i40e_rx_queue *rxq;
3503         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3504         uint16_t i;
3505         int ret;
3506
3507         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3508                 rxq = dev_data->rx_queues[i];
3509                 /* Don't operate the queue if not configured or
3510                  * if starting only per queue */
3511                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3512                         continue;
3513                 if (on)
3514                         ret = i40e_dev_rx_queue_start(dev, i);
3515                 else
3516                         ret = i40e_dev_rx_queue_stop(dev, i);
3517                 if (ret != I40E_SUCCESS)
3518                         return ret;
3519         }
3520
3521         return I40E_SUCCESS;
3522 }
3523
3524 /* Switch on or off all the rx/tx queues */
3525 int
3526 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3527 {
3528         int ret;
3529
3530         if (on) {
3531                 /* enable rx queues before enabling tx queues */
3532                 ret = i40e_dev_switch_rx_queues(pf, on);
3533                 if (ret) {
3534                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3535                         return ret;
3536                 }
3537                 ret = i40e_dev_switch_tx_queues(pf, on);
3538         } else {
3539                 /* Stop tx queues before stopping rx queues */
3540                 ret = i40e_dev_switch_tx_queues(pf, on);
3541                 if (ret) {
3542                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3543                         return ret;
3544                 }
3545                 ret = i40e_dev_switch_rx_queues(pf, on);
3546         }
3547
3548         return ret;
3549 }
3550
3551 /* Initialize VSI for TX */
3552 static int
3553 i40e_dev_tx_init(struct i40e_pf *pf)
3554 {
3555         struct rte_eth_dev_data *data = pf->dev_data;
3556         uint16_t i;
3557         uint32_t ret = I40E_SUCCESS;
3558         struct i40e_tx_queue *txq;
3559
3560         for (i = 0; i < data->nb_tx_queues; i++) {
3561                 txq = data->tx_queues[i];
3562                 if (!txq || !txq->q_set)
3563                         continue;
3564                 ret = i40e_tx_queue_init(txq);
3565                 if (ret != I40E_SUCCESS)
3566                         break;
3567         }
3568
3569         return ret;
3570 }
3571
3572 /* Initialize VSI for RX */
3573 static int
3574 i40e_dev_rx_init(struct i40e_pf *pf)
3575 {
3576         struct rte_eth_dev_data *data = pf->dev_data;
3577         int ret = I40E_SUCCESS;
3578         uint16_t i;
3579         struct i40e_rx_queue *rxq;
3580
3581         i40e_pf_config_mq_rx(pf);
3582         for (i = 0; i < data->nb_rx_queues; i++) {
3583                 rxq = data->rx_queues[i];
3584                 if (!rxq || !rxq->q_set)
3585                         continue;
3586
3587                 ret = i40e_rx_queue_init(rxq);
3588                 if (ret != I40E_SUCCESS) {
3589                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3590                                     "initialization");
3591                         break;
3592                 }
3593         }
3594
3595         return ret;
3596 }
3597
3598 static int
3599 i40e_dev_rxtx_init(struct i40e_pf *pf)
3600 {
3601         int err;
3602
3603         err = i40e_dev_tx_init(pf);
3604         if (err) {
3605                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3606                 return err;
3607         }
3608         err = i40e_dev_rx_init(pf);
3609         if (err) {
3610                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3611                 return err;
3612         }
3613
3614         return err;
3615 }
3616
3617 static int
3618 i40e_vmdq_setup(struct rte_eth_dev *dev)
3619 {
3620         struct rte_eth_conf *conf = &dev->data->dev_conf;
3621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3622         int i, err, conf_vsis, j, loop;
3623         struct i40e_vsi *vsi;
3624         struct i40e_vmdq_info *vmdq_info;
3625         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3626         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3627
3628         /*
3629          * Disable interrupt to avoid message from VF. Furthermore, it will
3630          * avoid race condition in VSI creation/destroy.
3631          */
3632         i40e_pf_disable_irq0(hw);
3633
3634         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3635                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3636                 return -ENOTSUP;
3637         }
3638
3639         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3640         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3641                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3642                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3643                         pf->max_nb_vmdq_vsi);
3644                 return -ENOTSUP;
3645         }
3646
3647         if (pf->vmdq != NULL) {
3648                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3649                 return 0;
3650         }
3651
3652         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3653                                 sizeof(*vmdq_info) * conf_vsis, 0);
3654
3655         if (pf->vmdq == NULL) {
3656                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3657                 return -ENOMEM;
3658         }
3659
3660         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3661
3662         /* Create VMDQ VSI */
3663         for (i = 0; i < conf_vsis; i++) {
3664                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3665                                 vmdq_conf->enable_loop_back);
3666                 if (vsi == NULL) {
3667                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3668                         err = -1;
3669                         goto err_vsi_setup;
3670                 }
3671                 vmdq_info = &pf->vmdq[i];
3672                 vmdq_info->pf = pf;
3673                 vmdq_info->vsi = vsi;
3674         }
3675         pf->nb_cfg_vmdq_vsi = conf_vsis;
3676
3677         /* Configure Vlan */
3678         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3679         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3680                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3681                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3682                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3683                                         vmdq_conf->pool_map[i].vlan_id, j);
3684
3685                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3686                                                 vmdq_conf->pool_map[i].vlan_id);
3687                                 if (err) {
3688                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3689                                         err = -1;
3690                                         goto err_vsi_setup;
3691                                 }
3692                         }
3693                 }
3694         }
3695
3696         i40e_pf_enable_irq0(hw);
3697
3698         return 0;
3699
3700 err_vsi_setup:
3701         for (i = 0; i < conf_vsis; i++)
3702                 if (pf->vmdq[i].vsi == NULL)
3703                         break;
3704                 else
3705                         i40e_vsi_release(pf->vmdq[i].vsi);
3706
3707         rte_free(pf->vmdq);
3708         pf->vmdq = NULL;
3709         i40e_pf_enable_irq0(hw);
3710         return err;
3711 }
3712
3713 static void
3714 i40e_stat_update_32(struct i40e_hw *hw,
3715                    uint32_t reg,
3716                    bool offset_loaded,
3717                    uint64_t *offset,
3718                    uint64_t *stat)
3719 {
3720         uint64_t new_data;
3721
3722         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3723         if (!offset_loaded)
3724                 *offset = new_data;
3725
3726         if (new_data >= *offset)
3727                 *stat = (uint64_t)(new_data - *offset);
3728         else
3729                 *stat = (uint64_t)((new_data +
3730                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3731 }
3732
3733 static void
3734 i40e_stat_update_48(struct i40e_hw *hw,
3735                    uint32_t hireg,
3736                    uint32_t loreg,
3737                    bool offset_loaded,
3738                    uint64_t *offset,
3739                    uint64_t *stat)
3740 {
3741         uint64_t new_data;
3742
3743         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3744         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3745                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3746
3747         if (!offset_loaded)
3748                 *offset = new_data;
3749
3750         if (new_data >= *offset)
3751                 *stat = new_data - *offset;
3752         else
3753                 *stat = (uint64_t)((new_data +
3754                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3755
3756         *stat &= I40E_48_BIT_MASK;
3757 }
3758
3759 /* Disable IRQ0 */
3760 void
3761 i40e_pf_disable_irq0(struct i40e_hw *hw)
3762 {
3763         /* Disable all interrupt types */
3764         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3765         I40E_WRITE_FLUSH(hw);
3766 }
3767
3768 /* Enable IRQ0 */
3769 void
3770 i40e_pf_enable_irq0(struct i40e_hw *hw)
3771 {
3772         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3773                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3774                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3775                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3776         I40E_WRITE_FLUSH(hw);
3777 }
3778
3779 static void
3780 i40e_pf_config_irq0(struct i40e_hw *hw)
3781 {
3782         /* read pending request and disable first */
3783         i40e_pf_disable_irq0(hw);
3784         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3785         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3786                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3787
3788         /* Link no queues with irq0 */
3789         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3790                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3791 }
3792
3793 static void
3794 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3795 {
3796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3797         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3798         int i;
3799         uint16_t abs_vf_id;
3800         uint32_t index, offset, val;
3801
3802         if (!pf->vfs)
3803                 return;
3804         /**
3805          * Try to find which VF trigger a reset, use absolute VF id to access
3806          * since the reg is global register.
3807          */
3808         for (i = 0; i < pf->vf_num; i++) {
3809                 abs_vf_id = hw->func_caps.vf_base_id + i;
3810                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3811                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3812                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3813                 /* VFR event occured */
3814                 if (val & (0x1 << offset)) {
3815                         int ret;
3816
3817                         /* Clear the event first */
3818                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3819                                                         (0x1 << offset));
3820                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3821                         /**
3822                          * Only notify a VF reset event occured,
3823                          * don't trigger another SW reset
3824                          */
3825                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3826                         if (ret != I40E_SUCCESS)
3827                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3828                 }
3829         }
3830 }
3831
3832 static void
3833 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3834 {
3835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3836         struct i40e_arq_event_info info;
3837         uint16_t pending, opcode;
3838         int ret;
3839
3840         info.buf_len = I40E_AQ_BUF_SZ;
3841         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3842         if (!info.msg_buf) {
3843                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3844                 return;
3845         }
3846
3847         pending = 1;
3848         while (pending) {
3849                 ret = i40e_clean_arq_element(hw, &info, &pending);
3850
3851                 if (ret != I40E_SUCCESS) {
3852                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3853                                     "aq_err: %u", hw->aq.asq_last_status);
3854                         break;
3855                 }
3856                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3857
3858                 switch (opcode) {
3859                 case i40e_aqc_opc_send_msg_to_pf:
3860                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3861                         i40e_pf_host_handle_vf_msg(dev,
3862                                         rte_le_to_cpu_16(info.desc.retval),
3863                                         rte_le_to_cpu_32(info.desc.cookie_high),
3864                                         rte_le_to_cpu_32(info.desc.cookie_low),
3865                                         info.msg_buf,
3866                                         info.msg_len);
3867                         break;
3868                 default:
3869                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3870                                     opcode);
3871                         break;
3872                 }
3873         }
3874         rte_free(info.msg_buf);
3875 }
3876
3877 /*
3878  * Interrupt handler is registered as the alarm callback for handling LSC
3879  * interrupt in a definite of time, in order to wait the NIC into a stable
3880  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3881  * no need for link down interrupt.
3882  */
3883 static void
3884 i40e_dev_interrupt_delayed_handler(void *param)
3885 {
3886         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888         uint32_t icr0;
3889
3890         /* read interrupt causes again */
3891         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3892
3893 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3894         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3895                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3896         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3897                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3898         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3899                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3900         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3901                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3902         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3903                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3904                                                                 "state\n");
3905         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3906                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3907         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3908                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3909 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3910
3911         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3912                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3913                 i40e_dev_handle_vfr_event(dev);
3914         }
3915         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3916                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3917                 i40e_dev_handle_aq_msg(dev);
3918         }
3919
3920         /* handle the link up interrupt in an alarm callback */
3921         i40e_dev_link_update(dev, 0);
3922         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3923
3924         i40e_pf_enable_irq0(hw);
3925         rte_intr_enable(&(dev->pci_dev->intr_handle));
3926 }
3927
3928 /**
3929  * Interrupt handler triggered by NIC  for handling
3930  * specific interrupt.
3931  *
3932  * @param handle
3933  *  Pointer to interrupt handle.
3934  * @param param
3935  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3936  *
3937  * @return
3938  *  void
3939  */
3940 static void
3941 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3942                            void *param)
3943 {
3944         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3945         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946         uint32_t icr0;
3947
3948         /* Disable interrupt */
3949         i40e_pf_disable_irq0(hw);
3950
3951         /* read out interrupt causes */
3952         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3953
3954         /* No interrupt event indicated */
3955         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3956                 PMD_DRV_LOG(INFO, "No interrupt event");
3957                 goto done;
3958         }
3959 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3960         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3961                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3962         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3963                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3964         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3965                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3966         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3967                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3968         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3969                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3970         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3971                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3972         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3973                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3974 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3975
3976         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3977                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3978                 i40e_dev_handle_vfr_event(dev);
3979         }
3980         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3981                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3982                 i40e_dev_handle_aq_msg(dev);
3983         }
3984
3985         /* Link Status Change interrupt */
3986         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3987 #define I40E_US_PER_SECOND 1000000
3988                 struct rte_eth_link link;
3989
3990                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3991                 memset(&link, 0, sizeof(link));
3992                 rte_i40e_dev_atomic_read_link_status(dev, &link);
3993                 i40e_dev_link_update(dev, 0);
3994
3995                 /*
3996                  * For link up interrupt, it needs to wait 1 second to let the
3997                  * hardware be a stable state. Otherwise several consecutive
3998                  * interrupts can be observed.
3999                  * For link down interrupt, no need to wait.
4000                  */
4001                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4002                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4003                         return;
4004                 else
4005                         _rte_eth_dev_callback_process(dev,
4006                                 RTE_ETH_EVENT_INTR_LSC);
4007         }
4008
4009 done:
4010         /* Enable interrupt */
4011         i40e_pf_enable_irq0(hw);
4012         rte_intr_enable(&(dev->pci_dev->intr_handle));
4013 }
4014
4015 static int
4016 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4017                          struct i40e_macvlan_filter *filter,
4018                          int total)
4019 {
4020         int ele_num, ele_buff_size;
4021         int num, actual_num, i;
4022         uint16_t flags;
4023         int ret = I40E_SUCCESS;
4024         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4025         struct i40e_aqc_add_macvlan_element_data *req_list;
4026
4027         if (filter == NULL  || total == 0)
4028                 return I40E_ERR_PARAM;
4029         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4030         ele_buff_size = hw->aq.asq_buf_size;
4031
4032         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4033         if (req_list == NULL) {
4034                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4035                 return I40E_ERR_NO_MEMORY;
4036         }
4037
4038         num = 0;
4039         do {
4040                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4041                 memset(req_list, 0, ele_buff_size);
4042
4043                 for (i = 0; i < actual_num; i++) {
4044                         (void)rte_memcpy(req_list[i].mac_addr,
4045                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4046                         req_list[i].vlan_tag =
4047                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4048
4049                         switch (filter[num + i].filter_type) {
4050                         case RTE_MAC_PERFECT_MATCH:
4051                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4052                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4053                                 break;
4054                         case RTE_MACVLAN_PERFECT_MATCH:
4055                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4056                                 break;
4057                         case RTE_MAC_HASH_MATCH:
4058                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4059                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4060                                 break;
4061                         case RTE_MACVLAN_HASH_MATCH:
4062                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4063                                 break;
4064                         default:
4065                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4066                                 ret = I40E_ERR_PARAM;
4067                                 goto DONE;
4068                         }
4069
4070                         req_list[i].queue_number = 0;
4071
4072                         req_list[i].flags = rte_cpu_to_le_16(flags);
4073                 }
4074
4075                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4076                                                 actual_num, NULL);
4077                 if (ret != I40E_SUCCESS) {
4078                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4079                         goto DONE;
4080                 }
4081                 num += actual_num;
4082         } while (num < total);
4083
4084 DONE:
4085         rte_free(req_list);
4086         return ret;
4087 }
4088
4089 static int
4090 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4091                             struct i40e_macvlan_filter *filter,
4092                             int total)
4093 {
4094         int ele_num, ele_buff_size;
4095         int num, actual_num, i;
4096         uint16_t flags;
4097         int ret = I40E_SUCCESS;
4098         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4099         struct i40e_aqc_remove_macvlan_element_data *req_list;
4100
4101         if (filter == NULL  || total == 0)
4102                 return I40E_ERR_PARAM;
4103
4104         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4105         ele_buff_size = hw->aq.asq_buf_size;
4106
4107         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4108         if (req_list == NULL) {
4109                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4110                 return I40E_ERR_NO_MEMORY;
4111         }
4112
4113         num = 0;
4114         do {
4115                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4116                 memset(req_list, 0, ele_buff_size);
4117
4118                 for (i = 0; i < actual_num; i++) {
4119                         (void)rte_memcpy(req_list[i].mac_addr,
4120                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4121                         req_list[i].vlan_tag =
4122                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4123
4124                         switch (filter[num + i].filter_type) {
4125                         case RTE_MAC_PERFECT_MATCH:
4126                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4127                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4128                                 break;
4129                         case RTE_MACVLAN_PERFECT_MATCH:
4130                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4131                                 break;
4132                         case RTE_MAC_HASH_MATCH:
4133                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4134                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4135                                 break;
4136                         case RTE_MACVLAN_HASH_MATCH:
4137                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4138                                 break;
4139                         default:
4140                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4141                                 ret = I40E_ERR_PARAM;
4142                                 goto DONE;
4143                         }
4144                         req_list[i].flags = rte_cpu_to_le_16(flags);
4145                 }
4146
4147                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4148                                                 actual_num, NULL);
4149                 if (ret != I40E_SUCCESS) {
4150                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4151                         goto DONE;
4152                 }
4153                 num += actual_num;
4154         } while (num < total);
4155
4156 DONE:
4157         rte_free(req_list);
4158         return ret;
4159 }
4160
4161 /* Find out specific MAC filter */
4162 static struct i40e_mac_filter *
4163 i40e_find_mac_filter(struct i40e_vsi *vsi,
4164                          struct ether_addr *macaddr)
4165 {
4166         struct i40e_mac_filter *f;
4167
4168         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4169                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4170                         return f;
4171         }
4172
4173         return NULL;
4174 }
4175
4176 static bool
4177 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4178                          uint16_t vlan_id)
4179 {
4180         uint32_t vid_idx, vid_bit;
4181
4182         if (vlan_id > ETH_VLAN_ID_MAX)
4183                 return 0;
4184
4185         vid_idx = I40E_VFTA_IDX(vlan_id);
4186         vid_bit = I40E_VFTA_BIT(vlan_id);
4187
4188         if (vsi->vfta[vid_idx] & vid_bit)
4189                 return 1;
4190         else
4191                 return 0;
4192 }
4193
4194 static void
4195 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4196                          uint16_t vlan_id, bool on)
4197 {
4198         uint32_t vid_idx, vid_bit;
4199
4200         if (vlan_id > ETH_VLAN_ID_MAX)
4201                 return;
4202
4203         vid_idx = I40E_VFTA_IDX(vlan_id);
4204         vid_bit = I40E_VFTA_BIT(vlan_id);
4205
4206         if (on)
4207                 vsi->vfta[vid_idx] |= vid_bit;
4208         else
4209                 vsi->vfta[vid_idx] &= ~vid_bit;
4210 }
4211
4212 /**
4213  * Find all vlan options for specific mac addr,
4214  * return with actual vlan found.
4215  */
4216 static inline int
4217 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4218                            struct i40e_macvlan_filter *mv_f,
4219                            int num, struct ether_addr *addr)
4220 {
4221         int i;
4222         uint32_t j, k;
4223
4224         /**
4225          * Not to use i40e_find_vlan_filter to decrease the loop time,
4226          * although the code looks complex.
4227           */
4228         if (num < vsi->vlan_num)
4229                 return I40E_ERR_PARAM;
4230
4231         i = 0;
4232         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4233                 if (vsi->vfta[j]) {
4234                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4235                                 if (vsi->vfta[j] & (1 << k)) {
4236                                         if (i > num - 1) {
4237                                                 PMD_DRV_LOG(ERR, "vlan number "
4238                                                             "not match");
4239                                                 return I40E_ERR_PARAM;
4240                                         }
4241                                         (void)rte_memcpy(&mv_f[i].macaddr,
4242                                                         addr, ETH_ADDR_LEN);
4243                                         mv_f[i].vlan_id =
4244                                                 j * I40E_UINT32_BIT_SIZE + k;
4245                                         i++;
4246                                 }
4247                         }
4248                 }
4249         }
4250         return I40E_SUCCESS;
4251 }
4252
4253 static inline int
4254 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4255                            struct i40e_macvlan_filter *mv_f,
4256                            int num,
4257                            uint16_t vlan)
4258 {
4259         int i = 0;
4260         struct i40e_mac_filter *f;
4261
4262         if (num < vsi->mac_num)
4263                 return I40E_ERR_PARAM;
4264
4265         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4266                 if (i > num - 1) {
4267                         PMD_DRV_LOG(ERR, "buffer number not match");
4268                         return I40E_ERR_PARAM;
4269                 }
4270                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4271                                 ETH_ADDR_LEN);
4272                 mv_f[i].vlan_id = vlan;
4273                 mv_f[i].filter_type = f->mac_info.filter_type;
4274                 i++;
4275         }
4276
4277         return I40E_SUCCESS;
4278 }
4279
4280 static int
4281 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4282 {
4283         int i, num;
4284         struct i40e_mac_filter *f;
4285         struct i40e_macvlan_filter *mv_f;
4286         int ret = I40E_SUCCESS;
4287
4288         if (vsi == NULL || vsi->mac_num == 0)
4289                 return I40E_ERR_PARAM;
4290
4291         /* Case that no vlan is set */
4292         if (vsi->vlan_num == 0)
4293                 num = vsi->mac_num;
4294         else
4295                 num = vsi->mac_num * vsi->vlan_num;
4296
4297         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4298         if (mv_f == NULL) {
4299                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4300                 return I40E_ERR_NO_MEMORY;
4301         }
4302
4303         i = 0;
4304         if (vsi->vlan_num == 0) {
4305                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4306                         (void)rte_memcpy(&mv_f[i].macaddr,
4307                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4308                         mv_f[i].vlan_id = 0;
4309                         i++;
4310                 }
4311         } else {
4312                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4313                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4314                                         vsi->vlan_num, &f->mac_info.mac_addr);
4315                         if (ret != I40E_SUCCESS)
4316                                 goto DONE;
4317                         i += vsi->vlan_num;
4318                 }
4319         }
4320
4321         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4322 DONE:
4323         rte_free(mv_f);
4324
4325         return ret;
4326 }
4327
4328 int
4329 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4330 {
4331         struct i40e_macvlan_filter *mv_f;
4332         int mac_num;
4333         int ret = I40E_SUCCESS;
4334
4335         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4336                 return I40E_ERR_PARAM;
4337
4338         /* If it's already set, just return */
4339         if (i40e_find_vlan_filter(vsi,vlan))
4340                 return I40E_SUCCESS;
4341
4342         mac_num = vsi->mac_num;
4343
4344         if (mac_num == 0) {
4345                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4346                 return I40E_ERR_PARAM;
4347         }
4348
4349         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4350
4351         if (mv_f == NULL) {
4352                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4353                 return I40E_ERR_NO_MEMORY;
4354         }
4355
4356         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4357
4358         if (ret != I40E_SUCCESS)
4359                 goto DONE;
4360
4361         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4362
4363         if (ret != I40E_SUCCESS)
4364                 goto DONE;
4365
4366         i40e_set_vlan_filter(vsi, vlan, 1);
4367
4368         vsi->vlan_num++;
4369         ret = I40E_SUCCESS;
4370 DONE:
4371         rte_free(mv_f);
4372         return ret;
4373 }
4374
4375 int
4376 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4377 {
4378         struct i40e_macvlan_filter *mv_f;
4379         int mac_num;
4380         int ret = I40E_SUCCESS;
4381
4382         /**
4383          * Vlan 0 is the generic filter for untagged packets
4384          * and can't be removed.
4385          */
4386         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4387                 return I40E_ERR_PARAM;
4388
4389         /* If can't find it, just return */
4390         if (!i40e_find_vlan_filter(vsi, vlan))
4391                 return I40E_ERR_PARAM;
4392
4393         mac_num = vsi->mac_num;
4394
4395         if (mac_num == 0) {
4396                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4397                 return I40E_ERR_PARAM;
4398         }
4399
4400         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4401
4402         if (mv_f == NULL) {
4403                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4404                 return I40E_ERR_NO_MEMORY;
4405         }
4406
4407         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4408
4409         if (ret != I40E_SUCCESS)
4410                 goto DONE;
4411
4412         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4413
4414         if (ret != I40E_SUCCESS)
4415                 goto DONE;
4416
4417         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4418         if (vsi->vlan_num == 1) {
4419                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4420                 if (ret != I40E_SUCCESS)
4421                         goto DONE;
4422
4423                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4424                 if (ret != I40E_SUCCESS)
4425                         goto DONE;
4426         }
4427
4428         i40e_set_vlan_filter(vsi, vlan, 0);
4429
4430         vsi->vlan_num--;
4431         ret = I40E_SUCCESS;
4432 DONE:
4433         rte_free(mv_f);
4434         return ret;
4435 }
4436
4437 int
4438 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4439 {
4440         struct i40e_mac_filter *f;
4441         struct i40e_macvlan_filter *mv_f;
4442         int i, vlan_num = 0;
4443         int ret = I40E_SUCCESS;
4444
4445         /* If it's add and we've config it, return */
4446         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4447         if (f != NULL)
4448                 return I40E_SUCCESS;
4449         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4450                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4451
4452                 /**
4453                  * If vlan_num is 0, that's the first time to add mac,
4454                  * set mask for vlan_id 0.
4455                  */
4456                 if (vsi->vlan_num == 0) {
4457                         i40e_set_vlan_filter(vsi, 0, 1);
4458                         vsi->vlan_num = 1;
4459                 }
4460                 vlan_num = vsi->vlan_num;
4461         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4462                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4463                 vlan_num = 1;
4464
4465         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4466         if (mv_f == NULL) {
4467                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4468                 return I40E_ERR_NO_MEMORY;
4469         }
4470
4471         for (i = 0; i < vlan_num; i++) {
4472                 mv_f[i].filter_type = mac_filter->filter_type;
4473                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4474                                 ETH_ADDR_LEN);
4475         }
4476
4477         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4478                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4479                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4480                                         &mac_filter->mac_addr);
4481                 if (ret != I40E_SUCCESS)
4482                         goto DONE;
4483         }
4484
4485         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4486         if (ret != I40E_SUCCESS)
4487                 goto DONE;
4488
4489         /* Add the mac addr into mac list */
4490         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4491         if (f == NULL) {
4492                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4493                 ret = I40E_ERR_NO_MEMORY;
4494                 goto DONE;
4495         }
4496         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4497                         ETH_ADDR_LEN);
4498         f->mac_info.filter_type = mac_filter->filter_type;
4499         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4500         vsi->mac_num++;
4501
4502         ret = I40E_SUCCESS;
4503 DONE:
4504         rte_free(mv_f);
4505
4506         return ret;
4507 }
4508
4509 int
4510 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4511 {
4512         struct i40e_mac_filter *f;
4513         struct i40e_macvlan_filter *mv_f;
4514         int i, vlan_num;
4515         enum rte_mac_filter_type filter_type;
4516         int ret = I40E_SUCCESS;
4517
4518         /* Can't find it, return an error */
4519         f = i40e_find_mac_filter(vsi, addr);
4520         if (f == NULL)
4521                 return I40E_ERR_PARAM;
4522
4523         vlan_num = vsi->vlan_num;
4524         filter_type = f->mac_info.filter_type;
4525         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4526                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4527                 if (vlan_num == 0) {
4528                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4529                         return I40E_ERR_PARAM;
4530                 }
4531         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4532                         filter_type == RTE_MAC_HASH_MATCH)
4533                 vlan_num = 1;
4534
4535         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4536         if (mv_f == NULL) {
4537                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4538                 return I40E_ERR_NO_MEMORY;
4539         }
4540
4541         for (i = 0; i < vlan_num; i++) {
4542                 mv_f[i].filter_type = filter_type;
4543                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4544                                 ETH_ADDR_LEN);
4545         }
4546         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4547                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4548                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4549                 if (ret != I40E_SUCCESS)
4550                         goto DONE;
4551         }
4552
4553         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4554         if (ret != I40E_SUCCESS)
4555                 goto DONE;
4556
4557         /* Remove the mac addr into mac list */
4558         TAILQ_REMOVE(&vsi->mac_list, f, next);
4559         rte_free(f);
4560         vsi->mac_num--;
4561
4562         ret = I40E_SUCCESS;
4563 DONE:
4564         rte_free(mv_f);
4565         return ret;
4566 }
4567
4568 /* Configure hash enable flags for RSS */
4569 uint64_t
4570 i40e_config_hena(uint64_t flags)
4571 {
4572         uint64_t hena = 0;
4573
4574         if (!flags)
4575                 return hena;
4576
4577         if (flags & ETH_RSS_NONF_IPV4_UDP)
4578                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4579         if (flags & ETH_RSS_NONF_IPV4_TCP)
4580                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4581         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4582                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4583         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4584                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4585         if (flags & ETH_RSS_FRAG_IPV4)
4586                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4587         if (flags & ETH_RSS_NONF_IPV6_UDP)
4588                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4589         if (flags & ETH_RSS_NONF_IPV6_TCP)
4590                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4591         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4592                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4593         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4594                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4595         if (flags & ETH_RSS_FRAG_IPV6)
4596                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4597         if (flags & ETH_RSS_L2_PAYLOAD)
4598                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4599
4600         return hena;
4601 }
4602
4603 /* Parse the hash enable flags */
4604 uint64_t
4605 i40e_parse_hena(uint64_t flags)
4606 {
4607         uint64_t rss_hf = 0;
4608
4609         if (!flags)
4610                 return rss_hf;
4611
4612         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4613                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4614         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4615                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4616         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4617                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4618         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4619                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4620         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4621                 rss_hf |= ETH_RSS_FRAG_IPV4;
4622         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4623                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4624         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4625                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4626         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4627                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4628         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4629                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4630         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4631                 rss_hf |= ETH_RSS_FRAG_IPV6;
4632         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4633                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4634
4635         return rss_hf;
4636 }
4637
4638 /* Disable RSS */
4639 static void
4640 i40e_pf_disable_rss(struct i40e_pf *pf)
4641 {
4642         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4643         uint64_t hena;
4644
4645         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4646         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4647         hena &= ~I40E_RSS_HENA_ALL;
4648         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4649         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4650         I40E_WRITE_FLUSH(hw);
4651 }
4652
4653 static int
4654 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4655 {
4656         uint32_t *hash_key;
4657         uint8_t hash_key_len;
4658         uint64_t rss_hf;
4659         uint16_t i;
4660         uint64_t hena;
4661
4662         hash_key = (uint32_t *)(rss_conf->rss_key);
4663         hash_key_len = rss_conf->rss_key_len;
4664         if (hash_key != NULL && hash_key_len >=
4665                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4666                 /* Fill in RSS hash key */
4667                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4668                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4669         }
4670
4671         rss_hf = rss_conf->rss_hf;
4672         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4673         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4674         hena &= ~I40E_RSS_HENA_ALL;
4675         hena |= i40e_config_hena(rss_hf);
4676         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4677         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4678         I40E_WRITE_FLUSH(hw);
4679
4680         return 0;
4681 }
4682
4683 static int
4684 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4685                          struct rte_eth_rss_conf *rss_conf)
4686 {
4687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4689         uint64_t hena;
4690
4691         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4692         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4693         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4694                 if (rss_hf != 0) /* Enable RSS */
4695                         return -EINVAL;
4696                 return 0; /* Nothing to do */
4697         }
4698         /* RSS enabled */
4699         if (rss_hf == 0) /* Disable RSS */
4700                 return -EINVAL;
4701
4702         return i40e_hw_rss_hash_set(hw, rss_conf);
4703 }
4704
4705 static int
4706 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4707                            struct rte_eth_rss_conf *rss_conf)
4708 {
4709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4711         uint64_t hena;
4712         uint16_t i;
4713
4714         if (hash_key != NULL) {
4715                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4716                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4717                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4718         }
4719         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4720         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4721         rss_conf->rss_hf = i40e_parse_hena(hena);
4722
4723         return 0;
4724 }
4725
4726 static int
4727 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4728 {
4729         switch (filter_type) {
4730         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4731                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4732                 break;
4733         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4734                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4735                 break;
4736         case RTE_TUNNEL_FILTER_IMAC_TENID:
4737                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4738                 break;
4739         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4740                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4741                 break;
4742         case ETH_TUNNEL_FILTER_IMAC:
4743                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4744                 break;
4745         default:
4746                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4747                 return -EINVAL;
4748         }
4749
4750         return 0;
4751 }
4752
4753 static int
4754 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4755                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4756                         uint8_t add)
4757 {
4758         uint16_t ip_type;
4759         uint8_t tun_type = 0;
4760         int val, ret = 0;
4761         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4762         struct i40e_vsi *vsi = pf->main_vsi;
4763         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4764         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4765
4766         cld_filter = rte_zmalloc("tunnel_filter",
4767                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4768                 0);
4769
4770         if (NULL == cld_filter) {
4771                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4772                 return -EINVAL;
4773         }
4774         pfilter = cld_filter;
4775
4776         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4777                         sizeof(struct ether_addr));
4778         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4779                         sizeof(struct ether_addr));
4780
4781         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4782         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4783                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4784                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4785                                 &tunnel_filter->ip_addr,
4786                                 sizeof(pfilter->ipaddr.v4.data));
4787         } else {
4788                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4789                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4790                                 &tunnel_filter->ip_addr,
4791                                 sizeof(pfilter->ipaddr.v6.data));
4792         }
4793
4794         /* check tunneled type */
4795         switch (tunnel_filter->tunnel_type) {
4796         case RTE_TUNNEL_TYPE_VXLAN:
4797                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4798                 break;
4799         default:
4800                 /* Other tunnel types is not supported. */
4801                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4802                 rte_free(cld_filter);
4803                 return -EINVAL;
4804         }
4805
4806         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4807                                                 &pfilter->flags);
4808         if (val < 0) {
4809                 rte_free(cld_filter);
4810                 return -EINVAL;
4811         }
4812
4813         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4814                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4815         pfilter->tenant_id = tunnel_filter->tenant_id;
4816         pfilter->queue_number = tunnel_filter->queue_id;
4817
4818         if (add)
4819                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4820         else
4821                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4822                                                 cld_filter, 1);
4823
4824         rte_free(cld_filter);
4825         return ret;
4826 }
4827
4828 static int
4829 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4830 {
4831         uint8_t i;
4832
4833         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4834                 if (pf->vxlan_ports[i] == port)
4835                         return i;
4836         }
4837
4838         return -1;
4839 }
4840
4841 static int
4842 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4843 {
4844         int  idx, ret;
4845         uint8_t filter_idx;
4846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4847
4848         idx = i40e_get_vxlan_port_idx(pf, port);
4849
4850         /* Check if port already exists */
4851         if (idx >= 0) {
4852                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4853                 return -EINVAL;
4854         }
4855
4856         /* Now check if there is space to add the new port */
4857         idx = i40e_get_vxlan_port_idx(pf, 0);
4858         if (idx < 0) {
4859                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4860                         "not adding port %d", port);
4861                 return -ENOSPC;
4862         }
4863
4864         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4865                                         &filter_idx, NULL);
4866         if (ret < 0) {
4867                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4868                 return -1;
4869         }
4870
4871         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4872                          port,  filter_idx);
4873
4874         /* New port: add it and mark its index in the bitmap */
4875         pf->vxlan_ports[idx] = port;
4876         pf->vxlan_bitmap |= (1 << idx);
4877
4878         if (!(pf->flags & I40E_FLAG_VXLAN))
4879                 pf->flags |= I40E_FLAG_VXLAN;
4880
4881         return 0;
4882 }
4883
4884 static int
4885 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4886 {
4887         int idx;
4888         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4889
4890         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4891                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4892                 return -EINVAL;
4893         }
4894
4895         idx = i40e_get_vxlan_port_idx(pf, port);
4896
4897         if (idx < 0) {
4898                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4899                 return -EINVAL;
4900         }
4901
4902         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4903                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4904                 return -1;
4905         }
4906
4907         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4908                         port, idx);
4909
4910         pf->vxlan_ports[idx] = 0;
4911         pf->vxlan_bitmap &= ~(1 << idx);
4912
4913         if (!pf->vxlan_bitmap)
4914                 pf->flags &= ~I40E_FLAG_VXLAN;
4915
4916         return 0;
4917 }
4918
4919 /* Add UDP tunneling port */
4920 static int
4921 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4922                         struct rte_eth_udp_tunnel *udp_tunnel)
4923 {
4924         int ret = 0;
4925         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4926
4927         if (udp_tunnel == NULL)
4928                 return -EINVAL;
4929
4930         switch (udp_tunnel->prot_type) {
4931         case RTE_TUNNEL_TYPE_VXLAN:
4932                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4933                 break;
4934
4935         case RTE_TUNNEL_TYPE_GENEVE:
4936         case RTE_TUNNEL_TYPE_TEREDO:
4937                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4938                 ret = -1;
4939                 break;
4940
4941         default:
4942                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4943                 ret = -1;
4944                 break;
4945         }
4946
4947         return ret;
4948 }
4949
4950 /* Remove UDP tunneling port */
4951 static int
4952 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4953                         struct rte_eth_udp_tunnel *udp_tunnel)
4954 {
4955         int ret = 0;
4956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4957
4958         if (udp_tunnel == NULL)
4959                 return -EINVAL;
4960
4961         switch (udp_tunnel->prot_type) {
4962         case RTE_TUNNEL_TYPE_VXLAN:
4963                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4964                 break;
4965         case RTE_TUNNEL_TYPE_GENEVE:
4966         case RTE_TUNNEL_TYPE_TEREDO:
4967                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4968                 ret = -1;
4969                 break;
4970         default:
4971                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4972                 ret = -1;
4973                 break;
4974         }
4975
4976         return ret;
4977 }
4978
4979 /* Calculate the maximum number of contiguous PF queues that are configured */
4980 static int
4981 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4982 {
4983         struct rte_eth_dev_data *data = pf->dev_data;
4984         int i, num;
4985         struct i40e_rx_queue *rxq;
4986
4987         num = 0;
4988         for (i = 0; i < pf->lan_nb_qps; i++) {
4989                 rxq = data->rx_queues[i];
4990                 if (rxq && rxq->q_set)
4991                         num++;
4992                 else
4993                         break;
4994         }
4995
4996         return num;
4997 }
4998
4999 /* Configure RSS */
5000 static int
5001 i40e_pf_config_rss(struct i40e_pf *pf)
5002 {
5003         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5004         struct rte_eth_rss_conf rss_conf;
5005         uint32_t i, lut = 0;
5006         uint16_t j, num;
5007
5008         /*
5009          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5010          * It's necessary to calulate the actual PF queues that are configured.
5011          */
5012         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5013                 num = i40e_pf_calc_configured_queues_num(pf);
5014                 num = i40e_align_floor(num);
5015         } else
5016                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5017
5018         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5019                         num);
5020
5021         if (num == 0) {
5022                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5023                 return -ENOTSUP;
5024         }
5025
5026         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5027                 if (j == num)
5028                         j = 0;
5029                 lut = (lut << 8) | (j & ((0x1 <<
5030                         hw->func_caps.rss_table_entry_width) - 1));
5031                 if ((i & 3) == 3)
5032                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5033         }
5034
5035         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5036         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5037                 i40e_pf_disable_rss(pf);
5038                 return 0;
5039         }
5040         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5041                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5042                 /* Calculate the default hash key */
5043                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5044                         rss_key_default[i] = (uint32_t)rte_rand();
5045                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5046                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5047                                                         sizeof(uint32_t);
5048         }
5049
5050         return i40e_hw_rss_hash_set(hw, &rss_conf);
5051 }
5052
5053 static int
5054 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5055                         struct rte_eth_tunnel_filter_conf *filter)
5056 {
5057         if (pf == NULL || filter == NULL) {
5058                 PMD_DRV_LOG(ERR, "Invalid parameter");
5059                 return -EINVAL;
5060         }
5061
5062         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5063                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5064                 return -EINVAL;
5065         }
5066
5067         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5068                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5069                 return -EINVAL;
5070         }
5071
5072         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5073                 (is_zero_ether_addr(filter->outer_mac))) {
5074                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5075                 return -EINVAL;
5076         }
5077
5078         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5079                 (is_zero_ether_addr(filter->inner_mac))) {
5080                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5081                 return -EINVAL;
5082         }
5083
5084         return 0;
5085 }
5086
5087 static int
5088 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5089                         void *arg)
5090 {
5091         struct rte_eth_tunnel_filter_conf *filter;
5092         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5093         int ret = I40E_SUCCESS;
5094
5095         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5096
5097         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5098                 return I40E_ERR_PARAM;
5099
5100         switch (filter_op) {
5101         case RTE_ETH_FILTER_NOP:
5102                 if (!(pf->flags & I40E_FLAG_VXLAN))
5103                         ret = I40E_NOT_SUPPORTED;
5104         case RTE_ETH_FILTER_ADD:
5105                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5106                 break;
5107         case RTE_ETH_FILTER_DELETE:
5108                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5109                 break;
5110         default:
5111                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5112                 ret = I40E_ERR_PARAM;
5113                 break;
5114         }
5115
5116         return ret;
5117 }
5118
5119 static int
5120 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5121 {
5122         int ret = 0;
5123         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5124
5125         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5126                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5127                 return -ENOTSUP;
5128         }
5129
5130         /* RSS setup */
5131         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5132                 ret = i40e_pf_config_rss(pf);
5133         else
5134                 i40e_pf_disable_rss(pf);
5135
5136         return ret;
5137 }
5138
5139 /*
5140  * Configure ethertype filter, which can director packet by filtering
5141  * with mac address and ether_type or only ether_type
5142  */
5143 static int
5144 i40e_ethertype_filter_set(struct i40e_pf *pf,
5145                         struct rte_eth_ethertype_filter *filter,
5146                         bool add)
5147 {
5148         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5149         struct i40e_control_filter_stats stats;
5150         uint16_t flags = 0;
5151         int ret;
5152
5153         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5154                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5155                 return -EINVAL;
5156         }
5157         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5158                 filter->ether_type == ETHER_TYPE_IPv6) {
5159                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5160                         " control packet filter.", filter->ether_type);
5161                 return -EINVAL;
5162         }
5163         if (filter->ether_type == ETHER_TYPE_VLAN)
5164                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5165                         " not supported.");
5166
5167         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5168                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5169         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5170                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5171         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5172
5173         memset(&stats, 0, sizeof(stats));
5174         ret = i40e_aq_add_rem_control_packet_filter(hw,
5175                         filter->mac_addr.addr_bytes,
5176                         filter->ether_type, flags,
5177                         pf->main_vsi->seid,
5178                         filter->queue, add, &stats, NULL);
5179
5180         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5181                          " mac_etype_used = %u, etype_used = %u,"
5182                          " mac_etype_free = %u, etype_free = %u\n",
5183                          ret, stats.mac_etype_used, stats.etype_used,
5184                          stats.mac_etype_free, stats.etype_free);
5185         if (ret < 0)
5186                 return -ENOSYS;
5187         return 0;
5188 }
5189
5190 /*
5191  * Handle operations for ethertype filter.
5192  */
5193 static int
5194 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5195                                 enum rte_filter_op filter_op,
5196                                 void *arg)
5197 {
5198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5199         int ret = 0;
5200
5201         if (filter_op == RTE_ETH_FILTER_NOP)
5202                 return ret;
5203
5204         if (arg == NULL) {
5205                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5206                             filter_op);
5207                 return -EINVAL;
5208         }
5209
5210         switch (filter_op) {
5211         case RTE_ETH_FILTER_ADD:
5212                 ret = i40e_ethertype_filter_set(pf,
5213                         (struct rte_eth_ethertype_filter *)arg,
5214                         TRUE);
5215                 break;
5216         case RTE_ETH_FILTER_DELETE:
5217                 ret = i40e_ethertype_filter_set(pf,
5218                         (struct rte_eth_ethertype_filter *)arg,
5219                         FALSE);
5220                 break;
5221         default:
5222                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5223                 ret = -ENOSYS;
5224                 break;
5225         }
5226         return ret;
5227 }
5228
5229 static int
5230 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5231                      enum rte_filter_type filter_type,
5232                      enum rte_filter_op filter_op,
5233                      void *arg)
5234 {
5235         int ret = 0;
5236
5237         if (dev == NULL)
5238                 return -EINVAL;
5239
5240         switch (filter_type) {
5241         case RTE_ETH_FILTER_MACVLAN:
5242                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5243                 break;
5244         case RTE_ETH_FILTER_ETHERTYPE:
5245                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5246                 break;
5247         case RTE_ETH_FILTER_TUNNEL:
5248                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5249                 break;
5250         case RTE_ETH_FILTER_FDIR:
5251                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5252                 break;
5253         default:
5254                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5255                                                         filter_type);
5256                 ret = -EINVAL;
5257                 break;
5258         }
5259
5260         return ret;
5261 }
5262
5263 enum i40e_filter_pctype
5264 i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
5265 {
5266         static const enum i40e_filter_pctype pctype_table[] = {
5267                 [RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5268                 [RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5269                 [RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5270                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] =
5271                                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5272                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] =
5273                                         I40E_FILTER_PCTYPE_FRAG_IPV4,
5274                 [RTE_ETH_FLOW_TYPE_UDPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5275                 [RTE_ETH_FLOW_TYPE_TCPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5276                 [RTE_ETH_FLOW_TYPE_SCTPV6] = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5277                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] =
5278                                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5279                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] =
5280                                         I40E_FILTER_PCTYPE_FRAG_IPV6,
5281         };
5282
5283         return pctype_table[flow_type];
5284 }
5285
5286 enum rte_eth_flow_type
5287 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5288 {
5289         static const enum rte_eth_flow_type flowtype_table[] = {
5290                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
5291                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
5292                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
5293                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5294                                         RTE_ETH_FLOW_TYPE_IPV4_OTHER,
5295                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
5296                                         RTE_ETH_FLOW_TYPE_FRAG_IPV4,
5297                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = RTE_ETH_FLOW_TYPE_UDPV6,
5298                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = RTE_ETH_FLOW_TYPE_TCPV6,
5299                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV6,
5300                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5301                                         RTE_ETH_FLOW_TYPE_IPV6_OTHER,
5302                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
5303                                         RTE_ETH_FLOW_TYPE_FRAG_IPV6,
5304         };
5305
5306         return flowtype_table[pctype];
5307 }
5308
5309 static int
5310 i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
5311 {
5312         struct i40e_aq_desc desc;
5313         enum i40e_status_code status;
5314
5315         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
5316         desc.params.internal.param1 = rte_cpu_to_le_32(addr);
5317         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5318         if (status < 0)
5319                 return status;
5320
5321         *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
5322                                         (CHAR_BIT * sizeof(uint32_t))) +
5323                                 rte_le_to_cpu_32(desc.params.internal.param3);
5324
5325         return status;
5326 }
5327
5328 /*
5329  * On X710, performance number is far from the expectation on recent firmware
5330  * versions. The fix for this issue may not be integrated in the following
5331  * firmware version. So the workaround in software driver is needed. It needs
5332  * to modify the initial values of 3 internal only registers. Note that the
5333  * workaround can be removed when it is fixed in firmware in the future.
5334  */
5335 static void
5336 i40e_configure_registers(struct i40e_hw *hw)
5337 {
5338 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5339 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5340 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5341 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5342 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5343 #define I40E_GL_SWR_PM_UP_THR_VALUE      0x03030303
5344
5345         static const struct {
5346                 uint32_t addr;
5347                 uint64_t val;
5348         } reg_table[] = {
5349                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5350                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5351                 {I40E_GL_SWR_PM_UP_THR, I40E_GL_SWR_PM_UP_THR_VALUE},
5352         };
5353         uint64_t reg;
5354         uint32_t i;
5355         int ret;
5356
5357         /* Below fix is for X710 only */
5358         if (i40e_is_40G_device(hw->device_id))
5359                 return;
5360
5361         for (i = 0; i < RTE_DIM(reg_table); i++) {
5362                 ret = i40e_debug_read_register(hw, reg_table[i].addr, &reg);
5363                 if (ret < 0) {
5364                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5365                                                         reg_table[i].addr);
5366                         break;
5367                 }
5368                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5369                                                 reg_table[i].addr, reg);
5370                 if (reg == reg_table[i].val)
5371                         continue;
5372
5373                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5374                                                 reg_table[i].val, NULL);
5375                 if (ret < 0) {
5376                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5377                                 "address of 0x%"PRIx32, reg_table[i].val,
5378                                                         reg_table[i].addr);
5379                         break;
5380                 }
5381                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5382                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5383         }
5384 }