lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 #define I40E_DEFAULT_RX_FREE_THRESH  32
  63 #define I40E_DEFAULT_RX_PTHRESH      8
  64 #define I40E_DEFAULT_RX_HTHRESH      8
  65 #define I40E_DEFAULT_RX_WTHRESH      0
  66
  67 #define I40E_DEFAULT_TX_FREE_THRESH  32
  68 #define I40E_DEFAULT_TX_PTHRESH      32
  69 #define I40E_DEFAULT_TX_HTHRESH      0
  70 #define I40E_DEFAULT_TX_WTHRESH      0
  71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  72
  73 /* Maximun number of MAC addresses */
  74 #define I40E_NUM_MACADDR_MAX       64
  75 #define I40E_CLEAR_PXE_WAIT_MS     200
  76
  77 /* Maximun number of capability elements */
  78 #define I40E_MAX_CAP_ELE_NUM       128
  79
  80 /* Wait count and inteval */
  81 #define I40E_CHK_Q_ENA_COUNT       1000
  82 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  83
  84 /* Maximun number of VSI */
  85 #define I40E_MAX_NUM_VSIS          (384UL)
  86
  87 /* Bit shift and mask */
  88 #define I40E_16_BIT_SHIFT 16
  89 #define I40E_16_BIT_MASK  0xFFFF
  90 #define I40E_32_BIT_SHIFT 32
  91 #define I40E_32_BIT_MASK  0xFFFFFFFF
  92 #define I40E_48_BIT_SHIFT 48
  93 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  94
  95 /* Default queue interrupt throttling time in microseconds*/
  96 #define I40E_ITR_INDEX_DEFAULT          0
  97 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  98 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  99
 100 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 static int eth_i40e_dev_init(\
 116                         __attribute__((unused)) struct eth_driver *eth_drv,
 117                         struct rte_eth_dev *eth_dev);
 118 static int i40e_dev_configure(struct rte_eth_dev *dev);
 119 static int i40e_dev_start(struct rte_eth_dev *dev);
 120 static void i40e_dev_stop(struct rte_eth_dev *dev);
 121 static void i40e_dev_close(struct rte_eth_dev *dev);
 122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 129                                struct rte_eth_stats *stats);
 130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 132                                             uint16_t queue_id,
 133                                             uint8_t stat_idx,
 134                                             uint8_t is_rx);
 135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 136                               struct rte_eth_dev_info *dev_info);
 137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 138                                 uint16_t vlan_id,
 139                                 int on);
 140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 143                                       uint16_t queue,
 144                                       int on);
 145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 149                               struct rte_eth_fc_conf *fc_conf);
 150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 151                                        struct rte_eth_pfc_conf *pfc_conf);
 152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 153                           struct ether_addr *mac_addr,
 154                           uint32_t index,
 155                           uint32_t pool);
 156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 158                                     struct rte_eth_rss_reta *reta_conf);
 159 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 160                                    struct rte_eth_rss_reta *reta_conf);
 161
 162 static int i40e_get_cap(struct i40e_hw *hw);
 163 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 164 static int i40e_pf_setup(struct i40e_pf *pf);
 165 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 166 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 167 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 168                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 169 static void i40e_stat_update_48(struct i40e_hw *hw,
 170                                uint32_t hireg,
 171                                uint32_t loreg,
 172                                bool offset_loaded,
 173                                uint64_t *offset,
 174                                uint64_t *stat);
 175 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 176 static void i40e_dev_interrupt_handler(
 177                 __rte_unused struct rte_intr_handle *handle, void *param);
 178 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 179                                 uint32_t base, uint32_t num);
 180 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 181 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 182                         uint32_t base);
 183 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 184                         uint16_t num);
 185 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 186 static int i40e_veb_release(struct i40e_veb *veb);
 187 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 188                                                 struct i40e_vsi *vsi);
 189 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 190 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 191 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 192                                              struct i40e_macvlan_filter *mv_f,
 193                                              int num,
 194                                              struct ether_addr *addr);
 195 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 196                                              struct i40e_macvlan_filter *mv_f,
 197                                              int num,
 198                                              uint16_t vlan);
 199 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 200 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 201                                     struct rte_eth_rss_conf *rss_conf);
 202 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 203                                       struct rte_eth_rss_conf *rss_conf);
 204 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 205                                 struct rte_eth_udp_tunnel *udp_tunnel);
 206 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 207                                 struct rte_eth_udp_tunnel *udp_tunnel);
 208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 209                                 enum rte_filter_type filter_type,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212
 213 /* Default hash key buffer for RSS */
 214 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 215
 216 static struct rte_pci_id pci_id_i40e_map[] = {
 217 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 218 #include "rte_pci_dev_ids.h"
 219 { .vendor_id = 0, /* sentinel */ },
 220 };
 221
 222 static struct eth_dev_ops i40e_eth_dev_ops = {
 223         .dev_configure                = i40e_dev_configure,
 224         .dev_start                    = i40e_dev_start,
 225         .dev_stop                     = i40e_dev_stop,
 226         .dev_close                    = i40e_dev_close,
 227         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 228         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 229         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 230         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 231         .dev_set_link_up              = i40e_dev_set_link_up,
 232         .dev_set_link_down            = i40e_dev_set_link_down,
 233         .link_update                  = i40e_dev_link_update,
 234         .stats_get                    = i40e_dev_stats_get,
 235         .stats_reset                  = i40e_dev_stats_reset,
 236         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 237         .dev_infos_get                = i40e_dev_info_get,
 238         .vlan_filter_set              = i40e_vlan_filter_set,
 239         .vlan_tpid_set                = i40e_vlan_tpid_set,
 240         .vlan_offload_set             = i40e_vlan_offload_set,
 241         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 242         .vlan_pvid_set                = i40e_vlan_pvid_set,
 243         .rx_queue_start               = i40e_dev_rx_queue_start,
 244         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 245         .tx_queue_start               = i40e_dev_tx_queue_start,
 246         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 247         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 248         .rx_queue_release             = i40e_dev_rx_queue_release,
 249         .rx_queue_count               = i40e_dev_rx_queue_count,
 250         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 251         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 252         .tx_queue_release             = i40e_dev_tx_queue_release,
 253         .dev_led_on                   = i40e_dev_led_on,
 254         .dev_led_off                  = i40e_dev_led_off,
 255         .flow_ctrl_set                = i40e_flow_ctrl_set,
 256         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 257         .mac_addr_add                 = i40e_macaddr_add,
 258         .mac_addr_remove              = i40e_macaddr_remove,
 259         .reta_update                  = i40e_dev_rss_reta_update,
 260         .reta_query                   = i40e_dev_rss_reta_query,
 261         .rss_hash_update              = i40e_dev_rss_hash_update,
 262         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 263         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 264         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 265         .filter_ctrl                  = i40e_dev_filter_ctrl,
 266 };
 267
 268 static struct eth_driver rte_i40e_pmd = {
 269         {
 270                 .name = "rte_i40e_pmd",
 271                 .id_table = pci_id_i40e_map,
 272                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 273         },
 274         .eth_dev_init = eth_i40e_dev_init,
 275         .dev_private_size = sizeof(struct i40e_adapter),
 276 };
 277
 278 static inline int
 279 i40e_align_floor(int n)
 280 {
 281         if (n == 0)
 282                 return 0;
 283         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 284 }
 285
 286 static inline int
 287 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 288                                      struct rte_eth_link *link)
 289 {
 290         struct rte_eth_link *dst = link;
 291         struct rte_eth_link *src = &(dev->data->dev_link);
 292
 293         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 294                                         *(uint64_t *)src) == 0)
 295                 return -1;
 296
 297         return 0;
 298 }
 299
 300 static inline int
 301 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 302                                       struct rte_eth_link *link)
 303 {
 304         struct rte_eth_link *dst = &(dev->data->dev_link);
 305         struct rte_eth_link *src = link;
 306
 307         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 308                                         *(uint64_t *)src) == 0)
 309                 return -1;
 310
 311         return 0;
 312 }
 313
 314 /*
 315  * Driver initialization routine.
 316  * Invoked once at EAL init time.
 317  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 318  */
 319 static int
 320 rte_i40e_pmd_init(const char *name __rte_unused,
 321                   const char *params __rte_unused)
 322 {
 323         PMD_INIT_FUNC_TRACE();
 324         rte_eth_driver_register(&rte_i40e_pmd);
 325
 326         return 0;
 327 }
 328
 329 static struct rte_driver rte_i40e_driver = {
 330         .type = PMD_PDEV,
 331         .init = rte_i40e_pmd_init,
 332 };
 333
 334 PMD_REGISTER_DRIVER(rte_i40e_driver);
 335
 336 static int
 337 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 338                   struct rte_eth_dev *dev)
 339 {
 340         struct rte_pci_device *pci_dev;
 341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 343         struct i40e_vsi *vsi;
 344         int ret;
 345         uint32_t len;
 346         uint8_t aq_fail = 0;
 347
 348         PMD_INIT_FUNC_TRACE();
 349
 350         dev->dev_ops = &i40e_eth_dev_ops;
 351         dev->rx_pkt_burst = i40e_recv_pkts;
 352         dev->tx_pkt_burst = i40e_xmit_pkts;
 353
 354         /* for secondary processes, we don't initialise any further as primary
 355          * has already done this work. Only check we don't need a different
 356          * RX function */
 357         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 358                 if (dev->data->scattered_rx)
 359                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 360                 return 0;
 361         }
 362         pci_dev = dev->pci_dev;
 363         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 364         pf->adapter->eth_dev = dev;
 365         pf->dev_data = dev->data;
 366
 367         hw->back = I40E_PF_TO_ADAPTER(pf);
 368         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 369         if (!hw->hw_addr) {
 370                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 371                              "as address is NULL");
 372                 return -ENODEV;
 373         }
 374
 375         hw->vendor_id = pci_dev->id.vendor_id;
 376         hw->device_id = pci_dev->id.device_id;
 377         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 378         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 379         hw->bus.device = pci_dev->addr.devid;
 380         hw->bus.func = pci_dev->addr.function;
 381
 382         /* Make sure all is clean before doing PF reset */
 383         i40e_clear_hw(hw);
 384
 385         /* Reset here to make sure all is clean for each PF */
 386         ret = i40e_pf_reset(hw);
 387         if (ret) {
 388                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 389                 return ret;
 390         }
 391
 392         /* Initialize the shared code (base driver) */
 393         ret = i40e_init_shared_code(hw);
 394         if (ret) {
 395                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 396                 return ret;
 397         }
 398
 399         /* Initialize the parameters for adminq */
 400         i40e_init_adminq_parameter(hw);
 401         ret = i40e_init_adminq(hw);
 402         if (ret != I40E_SUCCESS) {
 403                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 404                 return -EIO;
 405         }
 406         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 407                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 408                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 409                      ((hw->nvm.version >> 12) & 0xf),
 410                      ((hw->nvm.version >> 4) & 0xff),
 411                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 412
 413         /* Disable LLDP */
 414         ret = i40e_aq_stop_lldp(hw, true, NULL);
 415         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 416                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 417
 418         /* Clear PXE mode */
 419         i40e_clear_pxe_mode(hw);
 420
 421         /* Get hw capabilities */
 422         ret = i40e_get_cap(hw);
 423         if (ret != I40E_SUCCESS) {
 424                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 425                 goto err_get_capabilities;
 426         }
 427
 428         /* Initialize parameters for PF */
 429         ret = i40e_pf_parameter_init(dev);
 430         if (ret != 0) {
 431                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 432                 goto err_parameter_init;
 433         }
 434
 435         /* Initialize the queue management */
 436         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 437         if (ret < 0) {
 438                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 439                 goto err_qp_pool_init;
 440         }
 441         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 442                                 hw->func_caps.num_msix_vectors - 1);
 443         if (ret < 0) {
 444                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 445                 goto err_msix_pool_init;
 446         }
 447
 448         /* Initialize lan hmc */
 449         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 450                                 hw->func_caps.num_rx_qp, 0, 0);
 451         if (ret != I40E_SUCCESS) {
 452                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 453                 goto err_init_lan_hmc;
 454         }
 455
 456         /* Configure lan hmc */
 457         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 458         if (ret != I40E_SUCCESS) {
 459                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 460                 goto err_configure_lan_hmc;
 461         }
 462
 463         /* Get and check the mac address */
 464         i40e_get_mac_addr(hw, hw->mac.addr);
 465         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 466                 PMD_INIT_LOG(ERR, "mac address is not valid");
 467                 ret = -EIO;
 468                 goto err_get_mac_addr;
 469         }
 470         /* Copy the permanent MAC address */
 471         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 472                         (struct ether_addr *) hw->mac.perm_addr);
 473
 474         /* Disable flow control */
 475         hw->fc.requested_mode = I40E_FC_NONE;
 476         i40e_set_fc(hw, &aq_fail, TRUE);
 477
 478         /* PF setup, which includes VSI setup */
 479         ret = i40e_pf_setup(pf);
 480         if (ret) {
 481                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 482                 goto err_setup_pf_switch;
 483         }
 484
 485         vsi = pf->main_vsi;
 486
 487         /* Disable double vlan by default */
 488         i40e_vsi_config_double_vlan(vsi, FALSE);
 489
 490         if (!vsi->max_macaddrs)
 491                 len = ETHER_ADDR_LEN;
 492         else
 493                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 494
 495         /* Should be after VSI initialized */
 496         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 497         if (!dev->data->mac_addrs) {
 498                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 499                                         "for storing mac address");
 500                 goto err_mac_alloc;
 501         }
 502         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 503                                         &dev->data->mac_addrs[0]);
 504
 505         /* initialize pf host driver to setup SRIOV resource if applicable */
 506         i40e_pf_host_init(dev);
 507
 508         /* register callback func to eal lib */
 509         rte_intr_callback_register(&(pci_dev->intr_handle),
 510                 i40e_dev_interrupt_handler, (void *)dev);
 511
 512         /* configure and enable device interrupt */
 513         i40e_pf_config_irq0(hw);
 514         i40e_pf_enable_irq0(hw);
 515
 516         /* enable uio intr after callback register */
 517         rte_intr_enable(&(pci_dev->intr_handle));
 518
 519         return 0;
 520
 521 err_mac_alloc:
 522         i40e_vsi_release(pf->main_vsi);
 523 err_setup_pf_switch:
 524 err_get_mac_addr:
 525 err_configure_lan_hmc:
 526         (void)i40e_shutdown_lan_hmc(hw);
 527 err_init_lan_hmc:
 528         i40e_res_pool_destroy(&pf->msix_pool);
 529 err_msix_pool_init:
 530         i40e_res_pool_destroy(&pf->qp_pool);
 531 err_qp_pool_init:
 532 err_parameter_init:
 533 err_get_capabilities:
 534         (void)i40e_shutdown_adminq(hw);
 535
 536         return ret;
 537 }
 538
 539 static int
 540 i40e_dev_configure(struct rte_eth_dev *dev)
 541 {
 542         int ret;
 543         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 544
 545         /* VMDQ setup.
 546          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 547          *  RSS setting have different requirements.
 548          *  General PMD driver call sequence are NIC init, configure,
 549          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 550          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 551          *  applicable. So, VMDQ setting has to be done before
 552          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 553          *  For RSS setting, it will try to calculate actual configured RX queue
 554          *  number, which will be available after rx_queue_setup(). dev_start()
 555          *  function is good to place RSS setup.
 556          */
 557         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 558                 ret = i40e_vmdq_setup(dev);
 559                 if (ret)
 560                         return ret;
 561         }
 562
 563         return i40e_dev_init_vlan(dev);
 564 }
 565
 566 void
 567 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 568 {
 569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 570         uint16_t msix_vect = vsi->msix_intr;
 571         uint16_t i;
 572
 573         for (i = 0; i < vsi->nb_qps; i++) {
 574                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 575                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 576                 rte_wmb();
 577         }
 578
 579         if (vsi->type != I40E_VSI_SRIOV) {
 580                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 581                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 582                                 msix_vect - 1), 0);
 583         } else {
 584                 uint32_t reg;
 585                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 586                         vsi->user_param + (msix_vect - 1);
 587
 588                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 589         }
 590         I40E_WRITE_FLUSH(hw);
 591 }
 592
 593 static inline uint16_t
 594 i40e_calc_itr_interval(int16_t interval)
 595 {
 596         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 597                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 598
 599         /* Convert to hardware count, as writing each 1 represents 2 us */
 600         return (interval/2);
 601 }
 602
 603 void
 604 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 605 {
 606         uint32_t val;
 607         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 608         uint16_t msix_vect = vsi->msix_intr;
 609         int i;
 610
 611         for (i = 0; i < vsi->nb_qps; i++)
 612                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 613
 614         /* Bind all RX queues to allocated MSIX interrupt */
 615         for (i = 0; i < vsi->nb_qps; i++) {
 616                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 617                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 618                         ((vsi->base_queue + i + 1) <<
 619                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 620                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 621                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 622
 623                 if (i == vsi->nb_qps - 1)
 624                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 625                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 626         }
 627
 628         /* Write first RX queue to Link list register as the head element */
 629         if (vsi->type != I40E_VSI_SRIOV) {
 630                 uint16_t interval =
 631                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 632
 633                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 634                                                 (vsi->base_queue <<
 635                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 636                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 637
 638                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 639                                                 msix_vect - 1), interval);
 640
 641 #ifndef I40E_GLINT_CTL
 642 #define I40E_GLINT_CTL                     0x0003F800
 643 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 644 #endif
 645                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 646                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 647                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 648         } else {
 649                 uint32_t reg;
 650
 651                 /* num_msix_vectors_vf needs to minus irq0 */
 652                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 653                         vsi->user_param + (msix_vect - 1);
 654
 655                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 656                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 657                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 658         }
 659
 660         I40E_WRITE_FLUSH(hw);
 661 }
 662
 663 static void
 664 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 665 {
 666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 667         uint16_t interval = i40e_calc_itr_interval(\
 668                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 669
 670         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 671                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 672                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 673                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 674                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 675 }
 676
 677 static void
 678 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 679 {
 680         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 681
 682         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 683 }
 684
 685 static inline uint8_t
 686 i40e_parse_link_speed(uint16_t eth_link_speed)
 687 {
 688         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 689
 690         switch (eth_link_speed) {
 691         case ETH_LINK_SPEED_40G:
 692                 link_speed = I40E_LINK_SPEED_40GB;
 693                 break;
 694         case ETH_LINK_SPEED_20G:
 695                 link_speed = I40E_LINK_SPEED_20GB;
 696                 break;
 697         case ETH_LINK_SPEED_10G:
 698                 link_speed = I40E_LINK_SPEED_10GB;
 699                 break;
 700         case ETH_LINK_SPEED_1000:
 701                 link_speed = I40E_LINK_SPEED_1GB;
 702                 break;
 703         case ETH_LINK_SPEED_100:
 704                 link_speed = I40E_LINK_SPEED_100MB;
 705                 break;
 706         }
 707
 708         return link_speed;
 709 }
 710
 711 static int
 712 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 713 {
 714         enum i40e_status_code status;
 715         struct i40e_aq_get_phy_abilities_resp phy_ab;
 716         struct i40e_aq_set_phy_config phy_conf;
 717         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 718                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 719                         I40E_AQ_PHY_FLAG_LOW_POWER;
 720         const uint8_t advt = I40E_LINK_SPEED_40GB |
 721                         I40E_LINK_SPEED_10GB |
 722                         I40E_LINK_SPEED_1GB |
 723                         I40E_LINK_SPEED_100MB;
 724         int ret = -ENOTSUP;
 725
 726         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 727                                               NULL);
 728         if (status)
 729                 return ret;
 730
 731         memset(&phy_conf, 0, sizeof(phy_conf));
 732
 733         /* bits 0-2 use the values from get_phy_abilities_resp */
 734         abilities &= ~mask;
 735         abilities |= phy_ab.abilities & mask;
 736
 737         /* update ablities and speed */
 738         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 739                 phy_conf.link_speed = advt;
 740         else
 741                 phy_conf.link_speed = force_speed;
 742
 743         phy_conf.abilities = abilities;
 744
 745         /* use get_phy_abilities_resp value for the rest */
 746         phy_conf.phy_type = phy_ab.phy_type;
 747         phy_conf.eee_capability = phy_ab.eee_capability;
 748         phy_conf.eeer = phy_ab.eeer_val;
 749         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 750
 751         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 752                     phy_ab.abilities, phy_ab.link_speed);
 753         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 754                     phy_conf.abilities, phy_conf.link_speed);
 755
 756         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 757         if (status)
 758                 return ret;
 759
 760         return I40E_SUCCESS;
 761 }
 762
 763 static int
 764 i40e_apply_link_speed(struct rte_eth_dev *dev)
 765 {
 766         uint8_t speed;
 767         uint8_t abilities = 0;
 768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 769         struct rte_eth_conf *conf = &dev->data->dev_conf;
 770
 771         speed = i40e_parse_link_speed(conf->link_speed);
 772         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 773         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 774                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 775         else
 776                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 777
 778         return i40e_phy_conf_link(hw, abilities, speed);
 779 }
 780
 781 static int
 782 i40e_dev_start(struct rte_eth_dev *dev)
 783 {
 784         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 786         struct i40e_vsi *main_vsi = pf->main_vsi;
 787         int ret, i;
 788
 789         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 790                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 791                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 792                              dev->data->dev_conf.link_duplex,
 793                              dev->data->port_id);
 794                 return -EINVAL;
 795         }
 796
 797         /* Initialize VSI */
 798         ret = i40e_dev_rxtx_init(pf);
 799         if (ret != I40E_SUCCESS) {
 800                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 801                 goto err_up;
 802         }
 803
 804         /* Map queues with MSIX interrupt */
 805         i40e_vsi_queues_bind_intr(main_vsi);
 806         i40e_vsi_enable_queues_intr(main_vsi);
 807
 808         /* Map VMDQ VSI queues with MSIX interrupt */
 809         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 810                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 811                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 812         }
 813
 814         /* Enable all queues which have been configured */
 815         ret = i40e_dev_switch_queues(pf, TRUE);
 816         if (ret != I40E_SUCCESS) {
 817                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 818                 goto err_up;
 819         }
 820
 821         /* Enable receiving broadcast packets */
 822         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 823         if (ret != I40E_SUCCESS)
 824                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 825
 826         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 827                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 828                                                 true, NULL);
 829                 if (ret != I40E_SUCCESS)
 830                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 831         }
 832
 833         /* Apply link configure */
 834         ret = i40e_apply_link_speed(dev);
 835         if (I40E_SUCCESS != ret) {
 836                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 837                 goto err_up;
 838         }
 839
 840         return I40E_SUCCESS;
 841
 842 err_up:
 843         i40e_dev_switch_queues(pf, FALSE);
 844         i40e_dev_clear_queues(dev);
 845
 846         return ret;
 847 }
 848
 849 static void
 850 i40e_dev_stop(struct rte_eth_dev *dev)
 851 {
 852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 853         struct i40e_vsi *main_vsi = pf->main_vsi;
 854         int i;
 855
 856         /* Disable all queues */
 857         i40e_dev_switch_queues(pf, FALSE);
 858
 859         /* un-map queues with interrupt registers */
 860         i40e_vsi_disable_queues_intr(main_vsi);
 861         i40e_vsi_queues_unbind_intr(main_vsi);
 862
 863         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 864                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 865                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 866         }
 867
 868         /* Clear all queues and release memory */
 869         i40e_dev_clear_queues(dev);
 870
 871         /* Set link down */
 872         i40e_dev_set_link_down(dev);
 873 }
 874
 875 static void
 876 i40e_dev_close(struct rte_eth_dev *dev)
 877 {
 878         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 880         uint32_t reg;
 881
 882         PMD_INIT_FUNC_TRACE();
 883
 884         i40e_dev_stop(dev);
 885
 886         /* Disable interrupt */
 887         i40e_pf_disable_irq0(hw);
 888         rte_intr_disable(&(dev->pci_dev->intr_handle));
 889
 890         /* shutdown and destroy the HMC */
 891         i40e_shutdown_lan_hmc(hw);
 892
 893         /* release all the existing VSIs and VEBs */
 894         i40e_vsi_release(pf->main_vsi);
 895
 896         /* shutdown the adminq */
 897         i40e_aq_queue_shutdown(hw, true);
 898         i40e_shutdown_adminq(hw);
 899
 900         i40e_res_pool_destroy(&pf->qp_pool);
 901         i40e_res_pool_destroy(&pf->msix_pool);
 902
 903         /* force a PF reset to clean anything leftover */
 904         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 905         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 906                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 907         I40E_WRITE_FLUSH(hw);
 908 }
 909
 910 static void
 911 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 912 {
 913         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 914         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 915         struct i40e_vsi *vsi = pf->main_vsi;
 916         int status;
 917
 918         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 919                                                         true, NULL);
 920         if (status != I40E_SUCCESS)
 921                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 922
 923         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 924                                                         TRUE, NULL);
 925         if (status != I40E_SUCCESS)
 926                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 927
 928 }
 929
 930 static void
 931 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 932 {
 933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935         struct i40e_vsi *vsi = pf->main_vsi;
 936         int status;
 937
 938         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 939                                                         false, NULL);
 940         if (status != I40E_SUCCESS)
 941                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 942
 943         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 944                                                         false, NULL);
 945         if (status != I40E_SUCCESS)
 946                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 947 }
 948
 949 static void
 950 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 951 {
 952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 954         struct i40e_vsi *vsi = pf->main_vsi;
 955         int ret;
 956
 957         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 958         if (ret != I40E_SUCCESS)
 959                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 960 }
 961
 962 static void
 963 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 964 {
 965         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 966         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 967         struct i40e_vsi *vsi = pf->main_vsi;
 968         int ret;
 969
 970         if (dev->data->promiscuous == 1)
 971                 return; /* must remain in all_multicast mode */
 972
 973         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 974                                 vsi->seid, FALSE, NULL);
 975         if (ret != I40E_SUCCESS)
 976                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 977 }
 978
 979 /*
 980  * Set device link up.
 981  */
 982 static int
 983 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 984 {
 985         /* re-apply link speed setting */
 986         return i40e_apply_link_speed(dev);
 987 }
 988
 989 /*
 990  * Set device link down.
 991  */
 992 static int
 993 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 994 {
 995         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 996         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998
 999         return i40e_phy_conf_link(hw, abilities, speed);
1000 }
1001
1002 int
1003 i40e_dev_link_update(struct rte_eth_dev *dev,
1004                      __rte_unused int wait_to_complete)
1005 {
1006         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1007         struct i40e_link_status link_status;
1008         struct rte_eth_link link, old;
1009         int status;
1010
1011         memset(&link, 0, sizeof(link));
1012         memset(&old, 0, sizeof(old));
1013         memset(&link_status, 0, sizeof(link_status));
1014         rte_i40e_dev_atomic_read_link_status(dev, &old);
1015
1016         /* Get link status information from hardware */
1017         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1018         if (status != I40E_SUCCESS) {
1019                 link.link_speed = ETH_LINK_SPEED_100;
1020                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1021                 PMD_DRV_LOG(ERR, "Failed to get link info");
1022                 goto out;
1023         }
1024
1025         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1026
1027         if (!link.link_status)
1028                 goto out;
1029
1030         /* i40e uses full duplex only */
1031         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1032
1033         /* Parse the link status */
1034         switch (link_status.link_speed) {
1035         case I40E_LINK_SPEED_100MB:
1036                 link.link_speed = ETH_LINK_SPEED_100;
1037                 break;
1038         case I40E_LINK_SPEED_1GB:
1039                 link.link_speed = ETH_LINK_SPEED_1000;
1040                 break;
1041         case I40E_LINK_SPEED_10GB:
1042                 link.link_speed = ETH_LINK_SPEED_10G;
1043                 break;
1044         case I40E_LINK_SPEED_20GB:
1045                 link.link_speed = ETH_LINK_SPEED_20G;
1046                 break;
1047         case I40E_LINK_SPEED_40GB:
1048                 link.link_speed = ETH_LINK_SPEED_40G;
1049                 break;
1050         default:
1051                 link.link_speed = ETH_LINK_SPEED_100;
1052                 break;
1053         }
1054
1055 out:
1056         rte_i40e_dev_atomic_write_link_status(dev, &link);
1057         if (link.link_status == old.link_status)
1058                 return -1;
1059
1060         return 0;
1061 }
1062
1063 /* Get all the statistics of a VSI */
1064 void
1065 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1066 {
1067         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1068         struct i40e_eth_stats *nes = &vsi->eth_stats;
1069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1070         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1071
1072         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1073                             vsi->offset_loaded, &oes->rx_bytes,
1074                             &nes->rx_bytes);
1075         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1076                             vsi->offset_loaded, &oes->rx_unicast,
1077                             &nes->rx_unicast);
1078         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1079                             vsi->offset_loaded, &oes->rx_multicast,
1080                             &nes->rx_multicast);
1081         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1082                             vsi->offset_loaded, &oes->rx_broadcast,
1083                             &nes->rx_broadcast);
1084         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1085                             &oes->rx_discards, &nes->rx_discards);
1086         /* GLV_REPC not supported */
1087         /* GLV_RMPC not supported */
1088         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1089                             &oes->rx_unknown_protocol,
1090                             &nes->rx_unknown_protocol);
1091         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1092                             vsi->offset_loaded, &oes->tx_bytes,
1093                             &nes->tx_bytes);
1094         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1095                             vsi->offset_loaded, &oes->tx_unicast,
1096                             &nes->tx_unicast);
1097         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1098                             vsi->offset_loaded, &oes->tx_multicast,
1099                             &nes->tx_multicast);
1100         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1101                             vsi->offset_loaded,  &oes->tx_broadcast,
1102                             &nes->tx_broadcast);
1103         /* GLV_TDPC not supported */
1104         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1105                             &oes->tx_errors, &nes->tx_errors);
1106         vsi->offset_loaded = true;
1107
1108         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1109                     vsi->vsi_id);
1110         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1111         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1112         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1113         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1114         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1115         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1116                     nes->rx_unknown_protocol);
1117         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1118         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1119         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1120         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1121         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1122         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1123         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1124                     vsi->vsi_id);
1125 }
1126
1127 /* Get all statistics of a port */
1128 static void
1129 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1130 {
1131         uint32_t i;
1132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1134         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1135         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1136
1137         /* Get statistics of struct i40e_eth_stats */
1138         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1139                             I40E_GLPRT_GORCL(hw->port),
1140                             pf->offset_loaded, &os->eth.rx_bytes,
1141                             &ns->eth.rx_bytes);
1142         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1143                             I40E_GLPRT_UPRCL(hw->port),
1144                             pf->offset_loaded, &os->eth.rx_unicast,
1145                             &ns->eth.rx_unicast);
1146         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1147                             I40E_GLPRT_MPRCL(hw->port),
1148                             pf->offset_loaded, &os->eth.rx_multicast,
1149                             &ns->eth.rx_multicast);
1150         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1151                             I40E_GLPRT_BPRCL(hw->port),
1152                             pf->offset_loaded, &os->eth.rx_broadcast,
1153                             &ns->eth.rx_broadcast);
1154         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1155                             pf->offset_loaded, &os->eth.rx_discards,
1156                             &ns->eth.rx_discards);
1157         /* GLPRT_REPC not supported */
1158         /* GLPRT_RMPC not supported */
1159         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1160                             pf->offset_loaded,
1161                             &os->eth.rx_unknown_protocol,
1162                             &ns->eth.rx_unknown_protocol);
1163         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1164                             I40E_GLPRT_GOTCL(hw->port),
1165                             pf->offset_loaded, &os->eth.tx_bytes,
1166                             &ns->eth.tx_bytes);
1167         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1168                             I40E_GLPRT_UPTCL(hw->port),
1169                             pf->offset_loaded, &os->eth.tx_unicast,
1170                             &ns->eth.tx_unicast);
1171         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1172                             I40E_GLPRT_MPTCL(hw->port),
1173                             pf->offset_loaded, &os->eth.tx_multicast,
1174                             &ns->eth.tx_multicast);
1175         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1176                             I40E_GLPRT_BPTCL(hw->port),
1177                             pf->offset_loaded, &os->eth.tx_broadcast,
1178                             &ns->eth.tx_broadcast);
1179         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1180                             pf->offset_loaded, &os->eth.tx_discards,
1181                             &ns->eth.tx_discards);
1182         /* GLPRT_TEPC not supported */
1183
1184         /* additional port specific stats */
1185         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1186                             pf->offset_loaded, &os->tx_dropped_link_down,
1187                             &ns->tx_dropped_link_down);
1188         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1189                             pf->offset_loaded, &os->crc_errors,
1190                             &ns->crc_errors);
1191         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1192                             pf->offset_loaded, &os->illegal_bytes,
1193                             &ns->illegal_bytes);
1194         /* GLPRT_ERRBC not supported */
1195         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1196                             pf->offset_loaded, &os->mac_local_faults,
1197                             &ns->mac_local_faults);
1198         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1199                             pf->offset_loaded, &os->mac_remote_faults,
1200                             &ns->mac_remote_faults);
1201         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1202                             pf->offset_loaded, &os->rx_length_errors,
1203                             &ns->rx_length_errors);
1204         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1205                             pf->offset_loaded, &os->link_xon_rx,
1206                             &ns->link_xon_rx);
1207         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1208                             pf->offset_loaded, &os->link_xoff_rx,
1209                             &ns->link_xoff_rx);
1210         for (i = 0; i < 8; i++) {
1211                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1212                                     pf->offset_loaded,
1213                                     &os->priority_xon_rx[i],
1214                                     &ns->priority_xon_rx[i]);
1215                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1216                                     pf->offset_loaded,
1217                                     &os->priority_xoff_rx[i],
1218                                     &ns->priority_xoff_rx[i]);
1219         }
1220         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1221                             pf->offset_loaded, &os->link_xon_tx,
1222                             &ns->link_xon_tx);
1223         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1224                             pf->offset_loaded, &os->link_xoff_tx,
1225                             &ns->link_xoff_tx);
1226         for (i = 0; i < 8; i++) {
1227                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1228                                     pf->offset_loaded,
1229                                     &os->priority_xon_tx[i],
1230                                     &ns->priority_xon_tx[i]);
1231                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1232                                     pf->offset_loaded,
1233                                     &os->priority_xoff_tx[i],
1234                                     &ns->priority_xoff_tx[i]);
1235                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1236                                     pf->offset_loaded,
1237                                     &os->priority_xon_2_xoff[i],
1238                                     &ns->priority_xon_2_xoff[i]);
1239         }
1240         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1241                             I40E_GLPRT_PRC64L(hw->port),
1242                             pf->offset_loaded, &os->rx_size_64,
1243                             &ns->rx_size_64);
1244         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1245                             I40E_GLPRT_PRC127L(hw->port),
1246                             pf->offset_loaded, &os->rx_size_127,
1247                             &ns->rx_size_127);
1248         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1249                             I40E_GLPRT_PRC255L(hw->port),
1250                             pf->offset_loaded, &os->rx_size_255,
1251                             &ns->rx_size_255);
1252         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1253                             I40E_GLPRT_PRC511L(hw->port),
1254                             pf->offset_loaded, &os->rx_size_511,
1255                             &ns->rx_size_511);
1256         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1257                             I40E_GLPRT_PRC1023L(hw->port),
1258                             pf->offset_loaded, &os->rx_size_1023,
1259                             &ns->rx_size_1023);
1260         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1261                             I40E_GLPRT_PRC1522L(hw->port),
1262                             pf->offset_loaded, &os->rx_size_1522,
1263                             &ns->rx_size_1522);
1264         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1265                             I40E_GLPRT_PRC9522L(hw->port),
1266                             pf->offset_loaded, &os->rx_size_big,
1267                             &ns->rx_size_big);
1268         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1269                             pf->offset_loaded, &os->rx_undersize,
1270                             &ns->rx_undersize);
1271         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1272                             pf->offset_loaded, &os->rx_fragments,
1273                             &ns->rx_fragments);
1274         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1275                             pf->offset_loaded, &os->rx_oversize,
1276                             &ns->rx_oversize);
1277         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1278                             pf->offset_loaded, &os->rx_jabber,
1279                             &ns->rx_jabber);
1280         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1281                             I40E_GLPRT_PTC64L(hw->port),
1282                             pf->offset_loaded, &os->tx_size_64,
1283                             &ns->tx_size_64);
1284         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1285                             I40E_GLPRT_PTC127L(hw->port),
1286                             pf->offset_loaded, &os->tx_size_127,
1287                             &ns->tx_size_127);
1288         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1289                             I40E_GLPRT_PTC255L(hw->port),
1290                             pf->offset_loaded, &os->tx_size_255,
1291                             &ns->tx_size_255);
1292         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1293                             I40E_GLPRT_PTC511L(hw->port),
1294                             pf->offset_loaded, &os->tx_size_511,
1295                             &ns->tx_size_511);
1296         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1297                             I40E_GLPRT_PTC1023L(hw->port),
1298                             pf->offset_loaded, &os->tx_size_1023,
1299                             &ns->tx_size_1023);
1300         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1301                             I40E_GLPRT_PTC1522L(hw->port),
1302                             pf->offset_loaded, &os->tx_size_1522,
1303                             &ns->tx_size_1522);
1304         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1305                             I40E_GLPRT_PTC9522L(hw->port),
1306                             pf->offset_loaded, &os->tx_size_big,
1307                             &ns->tx_size_big);
1308         /* GLPRT_MSPDC not supported */
1309         /* GLPRT_XEC not supported */
1310
1311         pf->offset_loaded = true;
1312
1313         if (pf->main_vsi)
1314                 i40e_update_vsi_stats(pf->main_vsi);
1315
1316         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1317                                                 ns->eth.rx_broadcast;
1318         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1319                                                 ns->eth.tx_broadcast;
1320         stats->ibytes   = ns->eth.rx_bytes;
1321         stats->obytes   = ns->eth.tx_bytes;
1322         stats->oerrors  = ns->eth.tx_errors;
1323         stats->imcasts  = ns->eth.rx_multicast;
1324
1325         /* Rx Errors */
1326         stats->ibadcrc  = ns->crc_errors;
1327         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1328                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1329         stats->imissed  = ns->eth.rx_discards;
1330         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1331
1332         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1333         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1334         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1335         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1336         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1337         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1338         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1339                     ns->eth.rx_unknown_protocol);
1340         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1341         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1342         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1343         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1344         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1345         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1346
1347         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1348                     ns->tx_dropped_link_down);
1349         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1350         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1351                     ns->illegal_bytes);
1352         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1353         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1354                     ns->mac_local_faults);
1355         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1356                     ns->mac_remote_faults);
1357         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1358                     ns->rx_length_errors);
1359         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1360         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1361         for (i = 0; i < 8; i++) {
1362                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1363                                 i, ns->priority_xon_rx[i]);
1364                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1365                                 i, ns->priority_xoff_rx[i]);
1366         }
1367         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1368         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1369         for (i = 0; i < 8; i++) {
1370                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1371                                 i, ns->priority_xon_tx[i]);
1372                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1373                                 i, ns->priority_xoff_tx[i]);
1374                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1375                                 i, ns->priority_xon_2_xoff[i]);
1376         }
1377         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1378         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1379         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1380         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1381         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1382         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1383         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1384         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1385         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1386         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1387         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1388         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1389         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1390         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1391         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1392         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1393         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1394         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1395         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1396                         ns->mac_short_packet_dropped);
1397         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1398                     ns->checksum_error);
1399         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1400 }
1401
1402 /* Reset the statistics */
1403 static void
1404 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1405 {
1406         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1407
1408         /* It results in reloading the start point of each counter */
1409         pf->offset_loaded = false;
1410 }
1411
1412 static int
1413 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1414                                  __rte_unused uint16_t queue_id,
1415                                  __rte_unused uint8_t stat_idx,
1416                                  __rte_unused uint8_t is_rx)
1417 {
1418         PMD_INIT_FUNC_TRACE();
1419
1420         return -ENOSYS;
1421 }
1422
1423 static void
1424 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1425 {
1426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         struct i40e_vsi *vsi = pf->main_vsi;
1428
1429         dev_info->max_rx_queues = vsi->nb_qps;
1430         dev_info->max_tx_queues = vsi->nb_qps;
1431         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1432         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1433         dev_info->max_mac_addrs = vsi->max_macaddrs;
1434         dev_info->max_vfs = dev->pci_dev->max_vfs;
1435         dev_info->rx_offload_capa =
1436                 DEV_RX_OFFLOAD_VLAN_STRIP |
1437                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1438                 DEV_RX_OFFLOAD_UDP_CKSUM |
1439                 DEV_RX_OFFLOAD_TCP_CKSUM;
1440         dev_info->tx_offload_capa =
1441                 DEV_TX_OFFLOAD_VLAN_INSERT |
1442                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1443                 DEV_TX_OFFLOAD_UDP_CKSUM |
1444                 DEV_TX_OFFLOAD_TCP_CKSUM |
1445                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1446
1447         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1448                 .rx_thresh = {
1449                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1450                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1451                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1452                 },
1453                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1454                 .rx_drop_en = 0,
1455         };
1456
1457         dev_info->default_txconf = (struct rte_eth_txconf) {
1458                 .tx_thresh = {
1459                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1460                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1461                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1462                 },
1463                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1464                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1465                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1466         };
1467
1468         if (pf->flags | I40E_FLAG_VMDQ) {
1469                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1470                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1471                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1472                                                 pf->max_nb_vmdq_vsi;
1473                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1474                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1475                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1476         }
1477 }
1478
1479 static int
1480 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1481 {
1482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1483         struct i40e_vsi *vsi = pf->main_vsi;
1484         PMD_INIT_FUNC_TRACE();
1485
1486         if (on)
1487                 return i40e_vsi_add_vlan(vsi, vlan_id);
1488         else
1489                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1490 }
1491
1492 static void
1493 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1494                    __rte_unused uint16_t tpid)
1495 {
1496         PMD_INIT_FUNC_TRACE();
1497 }
1498
1499 static void
1500 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1501 {
1502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1503         struct i40e_vsi *vsi = pf->main_vsi;
1504
1505         if (mask & ETH_VLAN_STRIP_MASK) {
1506                 /* Enable or disable VLAN stripping */
1507                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1508                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1509                 else
1510                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1511         }
1512
1513         if (mask & ETH_VLAN_EXTEND_MASK) {
1514                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1515                         i40e_vsi_config_double_vlan(vsi, TRUE);
1516                 else
1517                         i40e_vsi_config_double_vlan(vsi, FALSE);
1518         }
1519 }
1520
1521 static void
1522 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1523                           __rte_unused uint16_t queue,
1524                           __rte_unused int on)
1525 {
1526         PMD_INIT_FUNC_TRACE();
1527 }
1528
1529 static int
1530 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1531 {
1532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1533         struct i40e_vsi *vsi = pf->main_vsi;
1534         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1535         struct i40e_vsi_vlan_pvid_info info;
1536
1537         memset(&info, 0, sizeof(info));
1538         info.on = on;
1539         if (info.on)
1540                 info.config.pvid = pvid;
1541         else {
1542                 info.config.reject.tagged =
1543                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1544                 info.config.reject.untagged =
1545                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1546         }
1547
1548         return i40e_vsi_vlan_pvid_set(vsi, &info);
1549 }
1550
1551 static int
1552 i40e_dev_led_on(struct rte_eth_dev *dev)
1553 {
1554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555         uint32_t mode = i40e_led_get(hw);
1556
1557         if (mode == 0)
1558                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1559
1560         return 0;
1561 }
1562
1563 static int
1564 i40e_dev_led_off(struct rte_eth_dev *dev)
1565 {
1566         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567         uint32_t mode = i40e_led_get(hw);
1568
1569         if (mode != 0)
1570                 i40e_led_set(hw, 0, false);
1571
1572         return 0;
1573 }
1574
1575 static int
1576 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1577                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1578 {
1579         PMD_INIT_FUNC_TRACE();
1580
1581         return -ENOSYS;
1582 }
1583
1584 static int
1585 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1586                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1587 {
1588         PMD_INIT_FUNC_TRACE();
1589
1590         return -ENOSYS;
1591 }
1592
1593 /* Add a MAC address, and update filters */
1594 static void
1595 i40e_macaddr_add(struct rte_eth_dev *dev,
1596                  struct ether_addr *mac_addr,
1597                  __rte_unused uint32_t index,
1598                  uint32_t pool)
1599 {
1600         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1601         struct i40e_mac_filter_info mac_filter;
1602         struct i40e_vsi *vsi;
1603         int ret;
1604
1605         /* If VMDQ not enabled or configured, return */
1606         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1607                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1608                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1609                         pool);
1610                 return;
1611         }
1612
1613         if (pool > pf->nb_cfg_vmdq_vsi) {
1614                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1615                                 pool, pf->nb_cfg_vmdq_vsi);
1616                 return;
1617         }
1618
1619         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1620         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1621
1622         if (pool == 0)
1623                 vsi = pf->main_vsi;
1624         else
1625                 vsi = pf->vmdq[pool - 1].vsi;
1626
1627         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1628         if (ret != I40E_SUCCESS) {
1629                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1630                 return;
1631         }
1632 }
1633
1634 /* Remove a MAC address, and update filters */
1635 static void
1636 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1637 {
1638         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1639         struct i40e_vsi *vsi;
1640         struct rte_eth_dev_data *data = dev->data;
1641         struct ether_addr *macaddr;
1642         int ret;
1643         uint32_t i;
1644         uint64_t pool_sel;
1645
1646         macaddr = &(data->mac_addrs[index]);
1647
1648         pool_sel = dev->data->mac_pool_sel[index];
1649
1650         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1651                 if (pool_sel & (1ULL << i)) {
1652                         if (i == 0)
1653                                 vsi = pf->main_vsi;
1654                         else {
1655                                 /* No VMDQ pool enabled or configured */
1656                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1657                                         (i > pf->nb_cfg_vmdq_vsi)) {
1658                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1659                                                         "/configured");
1660                                         return;
1661                                 }
1662                                 vsi = pf->vmdq[i - 1].vsi;
1663                         }
1664                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1665
1666                         if (ret) {
1667                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1668                                 return;
1669                         }
1670                 }
1671         }
1672 }
1673
1674 /* Set perfect match or hash match of MAC and VLAN for a VF */
1675 static int
1676 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1677                  struct rte_eth_mac_filter *filter,
1678                  bool add)
1679 {
1680         struct i40e_hw *hw;
1681         struct i40e_mac_filter_info mac_filter;
1682         struct ether_addr old_mac;
1683         struct ether_addr *new_mac;
1684         struct i40e_pf_vf *vf = NULL;
1685         uint16_t vf_id;
1686         int ret;
1687
1688         if (pf == NULL) {
1689                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1690                 return -EINVAL;
1691         }
1692         hw = I40E_PF_TO_HW(pf);
1693
1694         if (filter == NULL) {
1695                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1696                 return -EINVAL;
1697         }
1698
1699         new_mac = &filter->mac_addr;
1700
1701         if (is_zero_ether_addr(new_mac)) {
1702                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1703                 return -EINVAL;
1704         }
1705
1706         vf_id = filter->dst_id;
1707
1708         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1709                 PMD_DRV_LOG(ERR, "Invalid argument.");
1710                 return -EINVAL;
1711         }
1712         vf = &pf->vfs[vf_id];
1713
1714         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1715                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1716                 return -EINVAL;
1717         }
1718
1719         if (add) {
1720                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1721                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1722                                 ETHER_ADDR_LEN);
1723                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1724                                  ETHER_ADDR_LEN);
1725
1726                 mac_filter.filter_type = filter->filter_type;
1727                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1728                 if (ret != I40E_SUCCESS) {
1729                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1730                         return -1;
1731                 }
1732                 ether_addr_copy(new_mac, &pf->dev_addr);
1733         } else {
1734                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1735                                 ETHER_ADDR_LEN);
1736                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1737                 if (ret != I40E_SUCCESS) {
1738                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1739                         return -1;
1740                 }
1741
1742                 /* Clear device address as it has been removed */
1743                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1744                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1745         }
1746
1747         return 0;
1748 }
1749
1750 /* MAC filter handle */
1751 static int
1752 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1753                 void *arg)
1754 {
1755         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1756         struct rte_eth_mac_filter *filter;
1757         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1758         int ret = I40E_NOT_SUPPORTED;
1759
1760         filter = (struct rte_eth_mac_filter *)(arg);
1761
1762         switch (filter_op) {
1763         case RTE_ETH_FILTER_NOP:
1764                 ret = I40E_SUCCESS;
1765                 break;
1766         case RTE_ETH_FILTER_ADD:
1767                 i40e_pf_disable_irq0(hw);
1768                 if (filter->is_vf)
1769                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1770                 i40e_pf_enable_irq0(hw);
1771                 break;
1772         case RTE_ETH_FILTER_DELETE:
1773                 i40e_pf_disable_irq0(hw);
1774                 if (filter->is_vf)
1775                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1776                 i40e_pf_enable_irq0(hw);
1777                 break;
1778         default:
1779                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1780                 ret = I40E_ERR_PARAM;
1781                 break;
1782         }
1783
1784         return ret;
1785 }
1786
1787 static int
1788 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1789                          struct rte_eth_rss_reta *reta_conf)
1790 {
1791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1792         uint32_t lut, l;
1793         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1794
1795         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1796                 if (i < max)
1797                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1798                 else
1799                         mask = (uint8_t)((reta_conf->mask_hi >>
1800                                                 (i - max)) & 0xF);
1801
1802                 if (!mask)
1803                         continue;
1804
1805                 if (mask == 0xF)
1806                         l = 0;
1807                 else
1808                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1809
1810                 for (j = 0, lut = 0; j < 4; j++) {
1811                         if (mask & (0x1 << j))
1812                                 lut |= reta_conf->reta[i + j] << (8 * j);
1813                         else
1814                                 lut |= l & (0xFF << (8 * j));
1815                 }
1816                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int
1823 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1824                         struct rte_eth_rss_reta *reta_conf)
1825 {
1826         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         uint32_t lut;
1828         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1829
1830         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1831                 if (i < max)
1832                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1833                 else
1834                         mask = (uint8_t)((reta_conf->mask_hi >>
1835                                                 (i - max)) & 0xF);
1836
1837                 if (!mask)
1838                         continue;
1839
1840                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1841                 for (j = 0; j < 4; j++) {
1842                         if (mask & (0x1 << j))
1843                                 reta_conf->reta[i + j] =
1844                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1845                 }
1846         }
1847
1848         return 0;
1849 }
1850
1851 /**
1852  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1853  * @hw:   pointer to the HW structure
1854  * @mem:  pointer to mem struct to fill out
1855  * @size: size of memory requested
1856  * @alignment: what to align the allocation to
1857  **/
1858 enum i40e_status_code
1859 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1860                         struct i40e_dma_mem *mem,
1861                         u64 size,
1862                         u32 alignment)
1863 {
1864         static uint64_t id = 0;
1865         const struct rte_memzone *mz = NULL;
1866         char z_name[RTE_MEMZONE_NAMESIZE];
1867
1868         if (!mem)
1869                 return I40E_ERR_PARAM;
1870
1871         id++;
1872         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1873 #ifdef RTE_LIBRTE_XEN_DOM0
1874         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1875                                                         RTE_PGSIZE_2M);
1876 #else
1877         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1878 #endif
1879         if (!mz)
1880                 return I40E_ERR_NO_MEMORY;
1881
1882         mem->id = id;
1883         mem->size = size;
1884         mem->va = mz->addr;
1885 #ifdef RTE_LIBRTE_XEN_DOM0
1886         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1887 #else
1888         mem->pa = mz->phys_addr;
1889 #endif
1890
1891         return I40E_SUCCESS;
1892 }
1893
1894 /**
1895  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1896  * @hw:   pointer to the HW structure
1897  * @mem:  ptr to mem struct to free
1898  **/
1899 enum i40e_status_code
1900 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1901                     struct i40e_dma_mem *mem)
1902 {
1903         if (!mem || !mem->va)
1904                 return I40E_ERR_PARAM;
1905
1906         mem->va = NULL;
1907         mem->pa = (u64)0;
1908
1909         return I40E_SUCCESS;
1910 }
1911
1912 /**
1913  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1914  * @hw:   pointer to the HW structure
1915  * @mem:  pointer to mem struct to fill out
1916  * @size: size of memory requested
1917  **/
1918 enum i40e_status_code
1919 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1920                          struct i40e_virt_mem *mem,
1921                          u32 size)
1922 {
1923         if (!mem)
1924                 return I40E_ERR_PARAM;
1925
1926         mem->size = size;
1927         mem->va = rte_zmalloc("i40e", size, 0);
1928
1929         if (mem->va)
1930                 return I40E_SUCCESS;
1931         else
1932                 return I40E_ERR_NO_MEMORY;
1933 }
1934
1935 /**
1936  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1937  * @hw:   pointer to the HW structure
1938  * @mem:  pointer to mem struct to free
1939  **/
1940 enum i40e_status_code
1941 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1942                      struct i40e_virt_mem *mem)
1943 {
1944         if (!mem)
1945                 return I40E_ERR_PARAM;
1946
1947         rte_free(mem->va);
1948         mem->va = NULL;
1949
1950         return I40E_SUCCESS;
1951 }
1952
1953 void
1954 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1955 {
1956         rte_spinlock_init(&sp->spinlock);
1957 }
1958
1959 void
1960 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1961 {
1962         rte_spinlock_lock(&sp->spinlock);
1963 }
1964
1965 void
1966 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1967 {
1968         rte_spinlock_unlock(&sp->spinlock);
1969 }
1970
1971 void
1972 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1973 {
1974         return;
1975 }
1976
1977 /**
1978  * Get the hardware capabilities, which will be parsed
1979  * and saved into struct i40e_hw.
1980  */
1981 static int
1982 i40e_get_cap(struct i40e_hw *hw)
1983 {
1984         struct i40e_aqc_list_capabilities_element_resp *buf;
1985         uint16_t len, size = 0;
1986         int ret;
1987
1988         /* Calculate a huge enough buff for saving response data temporarily */
1989         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1990                                                 I40E_MAX_CAP_ELE_NUM;
1991         buf = rte_zmalloc("i40e", len, 0);
1992         if (!buf) {
1993                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1994                 return I40E_ERR_NO_MEMORY;
1995         }
1996
1997         /* Get, parse the capabilities and save it to hw */
1998         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1999                         i40e_aqc_opc_list_func_capabilities, NULL);
2000         if (ret != I40E_SUCCESS)
2001                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2002
2003         /* Free the temporary buffer after being used */
2004         rte_free(buf);
2005
2006         return ret;
2007 }
2008
2009 static int
2010 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2011 {
2012         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2013         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2014         uint16_t sum_queues = 0, sum_vsis, left_queues;
2015
2016         /* First check if FW support SRIOV */
2017         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2018                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2019                 return -EINVAL;
2020         }
2021
2022         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2023         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2024         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2025         /* Allocate queues for pf */
2026         if (hw->func_caps.rss) {
2027                 pf->flags |= I40E_FLAG_RSS;
2028                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2029                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2030                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2031         } else
2032                 pf->lan_nb_qps = 1;
2033         sum_queues = pf->lan_nb_qps;
2034         /* Default VSI is not counted in */
2035         sum_vsis = 0;
2036         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2037
2038         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2039                 pf->flags |= I40E_FLAG_SRIOV;
2040                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2041                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2042                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2043                                      "max supported %u.",
2044                                      dev->pci_dev->max_vfs,
2045                                      hw->func_caps.num_vfs);
2046                         return -EINVAL;
2047                 }
2048                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2049                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2050                                      "max support %u queues.",
2051                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2052                         return -EINVAL;
2053                 }
2054                 pf->vf_num = dev->pci_dev->max_vfs;
2055                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2056                 sum_vsis   += pf->vf_num;
2057                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2058                              pf->vf_num, pf->vf_nb_qps);
2059         } else
2060                 pf->vf_num = 0;
2061
2062         if (hw->func_caps.vmdq) {
2063                 pf->flags |= I40E_FLAG_VMDQ;
2064                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2065                 pf->max_nb_vmdq_vsi = 1;
2066                 /*
2067                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2068                  * later.
2069                  */
2070                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2071                 sum_vsis += pf->max_nb_vmdq_vsi;
2072         } else {
2073                 pf->vmdq_nb_qps = 0;
2074                 pf->max_nb_vmdq_vsi = 0;
2075         }
2076         pf->nb_cfg_vmdq_vsi = 0;
2077
2078         if (hw->func_caps.fd) {
2079                 pf->flags |= I40E_FLAG_FDIR;
2080                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2081                 /**
2082                  * Each flow director consumes one VSI and one queue,
2083                  * but can't calculate out predictably here.
2084                  */
2085         }
2086
2087         if (sum_vsis > pf->max_num_vsi ||
2088                 sum_queues > hw->func_caps.num_rx_qp) {
2089                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2090                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2091                              pf->max_num_vsi, sum_vsis);
2092                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2093                              hw->func_caps.num_rx_qp, sum_queues);
2094                 return -EINVAL;
2095         }
2096
2097         /* Adjust VMDQ setting to support as many VMs as possible */
2098         if (pf->flags & I40E_FLAG_VMDQ) {
2099                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2100
2101                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2102                                         pf->max_num_vsi - sum_vsis);
2103
2104                 /* Limit the max VMDQ number that rte_ether that can support  */
2105                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2106                                         ETH_64_POOLS - 1);
2107
2108                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2109                                 pf->max_nb_vmdq_vsi);
2110                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2111         }
2112
2113         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2114          * cause */
2115         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2116                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2117                              sum_vsis, hw->func_caps.num_msix_vectors);
2118                 return -EINVAL;
2119         }
2120         return I40E_SUCCESS;
2121 }
2122
2123 static int
2124 i40e_pf_get_switch_config(struct i40e_pf *pf)
2125 {
2126         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2127         struct i40e_aqc_get_switch_config_resp *switch_config;
2128         struct i40e_aqc_switch_config_element_resp *element;
2129         uint16_t start_seid = 0, num_reported;
2130         int ret;
2131
2132         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2133                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2134         if (!switch_config) {
2135                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2136                 return -ENOMEM;
2137         }
2138
2139         /* Get the switch configurations */
2140         ret = i40e_aq_get_switch_config(hw, switch_config,
2141                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2142         if (ret != I40E_SUCCESS) {
2143                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2144                 goto fail;
2145         }
2146         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2147         if (num_reported != 1) { /* The number should be 1 */
2148                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2149                 goto fail;
2150         }
2151
2152         /* Parse the switch configuration elements */
2153         element = &(switch_config->element[0]);
2154         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2155                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2156                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2157         } else
2158                 PMD_DRV_LOG(INFO, "Unknown element type");
2159
2160 fail:
2161         rte_free(switch_config);
2162
2163         return ret;
2164 }
2165
2166 static int
2167 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2168                         uint32_t num)
2169 {
2170         struct pool_entry *entry;
2171
2172         if (pool == NULL || num == 0)
2173                 return -EINVAL;
2174
2175         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2176         if (entry == NULL) {
2177                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2178                 return -ENOMEM;
2179         }
2180
2181         /* queue heap initialize */
2182         pool->num_free = num;
2183         pool->num_alloc = 0;
2184         pool->base = base;
2185         LIST_INIT(&pool->alloc_list);
2186         LIST_INIT(&pool->free_list);
2187
2188         /* Initialize element  */
2189         entry->base = 0;
2190         entry->len = num;
2191
2192         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2193         return 0;
2194 }
2195
2196 static void
2197 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2198 {
2199         struct pool_entry *entry;
2200
2201         if (pool == NULL)
2202                 return;
2203
2204         LIST_FOREACH(entry, &pool->alloc_list, next) {
2205                 LIST_REMOVE(entry, next);
2206                 rte_free(entry);
2207         }
2208
2209         LIST_FOREACH(entry, &pool->free_list, next) {
2210                 LIST_REMOVE(entry, next);
2211                 rte_free(entry);
2212         }
2213
2214         pool->num_free = 0;
2215         pool->num_alloc = 0;
2216         pool->base = 0;
2217         LIST_INIT(&pool->alloc_list);
2218         LIST_INIT(&pool->free_list);
2219 }
2220
2221 static int
2222 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2223                        uint32_t base)
2224 {
2225         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2226         uint32_t pool_offset;
2227         int insert;
2228
2229         if (pool == NULL) {
2230                 PMD_DRV_LOG(ERR, "Invalid parameter");
2231                 return -EINVAL;
2232         }
2233
2234         pool_offset = base - pool->base;
2235         /* Lookup in alloc list */
2236         LIST_FOREACH(entry, &pool->alloc_list, next) {
2237                 if (entry->base == pool_offset) {
2238                         valid_entry = entry;
2239                         LIST_REMOVE(entry, next);
2240                         break;
2241                 }
2242         }
2243
2244         /* Not find, return */
2245         if (valid_entry == NULL) {
2246                 PMD_DRV_LOG(ERR, "Failed to find entry");
2247                 return -EINVAL;
2248         }
2249
2250         /**
2251          * Found it, move it to free list  and try to merge.
2252          * In order to make merge easier, always sort it by qbase.
2253          * Find adjacent prev and last entries.
2254          */
2255         prev = next = NULL;
2256         LIST_FOREACH(entry, &pool->free_list, next) {
2257                 if (entry->base > valid_entry->base) {
2258                         next = entry;
2259                         break;
2260                 }
2261                 prev = entry;
2262         }
2263
2264         insert = 0;
2265         /* Try to merge with next one*/
2266         if (next != NULL) {
2267                 /* Merge with next one */
2268                 if (valid_entry->base + valid_entry->len == next->base) {
2269                         next->base = valid_entry->base;
2270                         next->len += valid_entry->len;
2271                         rte_free(valid_entry);
2272                         valid_entry = next;
2273                         insert = 1;
2274                 }
2275         }
2276
2277         if (prev != NULL) {
2278                 /* Merge with previous one */
2279                 if (prev->base + prev->len == valid_entry->base) {
2280                         prev->len += valid_entry->len;
2281                         /* If it merge with next one, remove next node */
2282                         if (insert == 1) {
2283                                 LIST_REMOVE(valid_entry, next);
2284                                 rte_free(valid_entry);
2285                         } else {
2286                                 rte_free(valid_entry);
2287                                 insert = 1;
2288                         }
2289                 }
2290         }
2291
2292         /* Not find any entry to merge, insert */
2293         if (insert == 0) {
2294                 if (prev != NULL)
2295                         LIST_INSERT_AFTER(prev, valid_entry, next);
2296                 else if (next != NULL)
2297                         LIST_INSERT_BEFORE(next, valid_entry, next);
2298                 else /* It's empty list, insert to head */
2299                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2300         }
2301
2302         pool->num_free += valid_entry->len;
2303         pool->num_alloc -= valid_entry->len;
2304
2305         return 0;
2306 }
2307
2308 static int
2309 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2310                        uint16_t num)
2311 {
2312         struct pool_entry *entry, *valid_entry;
2313
2314         if (pool == NULL || num == 0) {
2315                 PMD_DRV_LOG(ERR, "Invalid parameter");
2316                 return -EINVAL;
2317         }
2318
2319         if (pool->num_free < num) {
2320                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2321                             num, pool->num_free);
2322                 return -ENOMEM;
2323         }
2324
2325         valid_entry = NULL;
2326         /* Lookup  in free list and find most fit one */
2327         LIST_FOREACH(entry, &pool->free_list, next) {
2328                 if (entry->len >= num) {
2329                         /* Find best one */
2330                         if (entry->len == num) {
2331                                 valid_entry = entry;
2332                                 break;
2333                         }
2334                         if (valid_entry == NULL || valid_entry->len > entry->len)
2335                                 valid_entry = entry;
2336                 }
2337         }
2338
2339         /* Not find one to satisfy the request, return */
2340         if (valid_entry == NULL) {
2341                 PMD_DRV_LOG(ERR, "No valid entry found");
2342                 return -ENOMEM;
2343         }
2344         /**
2345          * The entry have equal queue number as requested,
2346          * remove it from alloc_list.
2347          */
2348         if (valid_entry->len == num) {
2349                 LIST_REMOVE(valid_entry, next);
2350         } else {
2351                 /**
2352                  * The entry have more numbers than requested,
2353                  * create a new entry for alloc_list and minus its
2354                  * queue base and number in free_list.
2355                  */
2356                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2357                 if (entry == NULL) {
2358                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2359                                     "resource pool");
2360                         return -ENOMEM;
2361                 }
2362                 entry->base = valid_entry->base;
2363                 entry->len = num;
2364                 valid_entry->base += num;
2365                 valid_entry->len -= num;
2366                 valid_entry = entry;
2367         }
2368
2369         /* Insert it into alloc list, not sorted */
2370         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2371
2372         pool->num_free -= valid_entry->len;
2373         pool->num_alloc += valid_entry->len;
2374
2375         return (valid_entry->base + pool->base);
2376 }
2377
2378 /**
2379  * bitmap_is_subset - Check whether src2 is subset of src1
2380  **/
2381 static inline int
2382 bitmap_is_subset(uint8_t src1, uint8_t src2)
2383 {
2384         return !((src1 ^ src2) & src2);
2385 }
2386
2387 static int
2388 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2389 {
2390         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2391
2392         /* If DCB is not supported, only default TC is supported */
2393         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2394                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2395                 return -EINVAL;
2396         }
2397
2398         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2399                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2400                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2401                             enabled_tcmap);
2402                 return -EINVAL;
2403         }
2404         return I40E_SUCCESS;
2405 }
2406
2407 int
2408 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2409                                 struct i40e_vsi_vlan_pvid_info *info)
2410 {
2411         struct i40e_hw *hw;
2412         struct i40e_vsi_context ctxt;
2413         uint8_t vlan_flags = 0;
2414         int ret;
2415
2416         if (vsi == NULL || info == NULL) {
2417                 PMD_DRV_LOG(ERR, "invalid parameters");
2418                 return I40E_ERR_PARAM;
2419         }
2420
2421         if (info->on) {
2422                 vsi->info.pvid = info->config.pvid;
2423                 /**
2424                  * If insert pvid is enabled, only tagged pkts are
2425                  * allowed to be sent out.
2426                  */
2427                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2428                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2429         } else {
2430                 vsi->info.pvid = 0;
2431                 if (info->config.reject.tagged == 0)
2432                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2433
2434                 if (info->config.reject.untagged == 0)
2435                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2436         }
2437         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2438                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2439         vsi->info.port_vlan_flags |= vlan_flags;
2440         vsi->info.valid_sections =
2441                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2442         memset(&ctxt, 0, sizeof(ctxt));
2443         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2444         ctxt.seid = vsi->seid;
2445
2446         hw = I40E_VSI_TO_HW(vsi);
2447         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2448         if (ret != I40E_SUCCESS)
2449                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2450
2451         return ret;
2452 }
2453
2454 static int
2455 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2456 {
2457         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2458         int i, ret;
2459         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2460
2461         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2462         if (ret != I40E_SUCCESS)
2463                 return ret;
2464
2465         if (!vsi->seid) {
2466                 PMD_DRV_LOG(ERR, "seid not valid");
2467                 return -EINVAL;
2468         }
2469
2470         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2471         tc_bw_data.tc_valid_bits = enabled_tcmap;
2472         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2473                 tc_bw_data.tc_bw_credits[i] =
2474                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2475
2476         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2477         if (ret != I40E_SUCCESS) {
2478                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2479                 return ret;
2480         }
2481
2482         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2483                                         sizeof(vsi->info.qs_handle));
2484         return I40E_SUCCESS;
2485 }
2486
2487 static int
2488 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2489                                  struct i40e_aqc_vsi_properties_data *info,
2490                                  uint8_t enabled_tcmap)
2491 {
2492         int ret, total_tc = 0, i;
2493         uint16_t qpnum_per_tc, bsf, qp_idx;
2494
2495         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2496         if (ret != I40E_SUCCESS)
2497                 return ret;
2498
2499         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2500                 if (enabled_tcmap & (1 << i))
2501                         total_tc++;
2502         vsi->enabled_tc = enabled_tcmap;
2503
2504         /* Number of queues per enabled TC */
2505         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2506         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2507         bsf = rte_bsf32(qpnum_per_tc);
2508
2509         /* Adjust the queue number to actual queues that can be applied */
2510         vsi->nb_qps = qpnum_per_tc * total_tc;
2511
2512         /**
2513          * Configure TC and queue mapping parameters, for enabled TC,
2514          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2515          * default queue will serve it.
2516          */
2517         qp_idx = 0;
2518         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2519                 if (vsi->enabled_tc & (1 << i)) {
2520                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2521                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2522                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2523                         qp_idx += qpnum_per_tc;
2524                 } else
2525                         info->tc_mapping[i] = 0;
2526         }
2527
2528         /* Associate queue number with VSI */
2529         if (vsi->type == I40E_VSI_SRIOV) {
2530                 info->mapping_flags |=
2531                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2532                 for (i = 0; i < vsi->nb_qps; i++)
2533                         info->queue_mapping[i] =
2534                                 rte_cpu_to_le_16(vsi->base_queue + i);
2535         } else {
2536                 info->mapping_flags |=
2537                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2538                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2539         }
2540         info->valid_sections =
2541                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2542
2543         return I40E_SUCCESS;
2544 }
2545
2546 static int
2547 i40e_veb_release(struct i40e_veb *veb)
2548 {
2549         struct i40e_vsi *vsi;
2550         struct i40e_hw *hw;
2551
2552         if (veb == NULL || veb->associate_vsi == NULL)
2553                 return -EINVAL;
2554
2555         if (!TAILQ_EMPTY(&veb->head)) {
2556                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2557                 return -EACCES;
2558         }
2559
2560         vsi = veb->associate_vsi;
2561         hw = I40E_VSI_TO_HW(vsi);
2562
2563         vsi->uplink_seid = veb->uplink_seid;
2564         i40e_aq_delete_element(hw, veb->seid, NULL);
2565         rte_free(veb);
2566         vsi->veb = NULL;
2567         return I40E_SUCCESS;
2568 }
2569
2570 /* Setup a veb */
2571 static struct i40e_veb *
2572 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2573 {
2574         struct i40e_veb *veb;
2575         int ret;
2576         struct i40e_hw *hw;
2577
2578         if (NULL == pf || vsi == NULL) {
2579                 PMD_DRV_LOG(ERR, "veb setup failed, "
2580                             "associated VSI shouldn't null");
2581                 return NULL;
2582         }
2583         hw = I40E_PF_TO_HW(pf);
2584
2585         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2586         if (!veb) {
2587                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2588                 goto fail;
2589         }
2590
2591         veb->associate_vsi = vsi;
2592         TAILQ_INIT(&veb->head);
2593         veb->uplink_seid = vsi->uplink_seid;
2594
2595         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2596                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2597
2598         if (ret != I40E_SUCCESS) {
2599                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2600                             hw->aq.asq_last_status);
2601                 goto fail;
2602         }
2603
2604         /* get statistics index */
2605         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2606                                 &veb->stats_idx, NULL, NULL, NULL);
2607         if (ret != I40E_SUCCESS) {
2608                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2609                             hw->aq.asq_last_status);
2610                 goto fail;
2611         }
2612
2613         /* Get VEB bandwidth, to be implemented */
2614         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2615         vsi->uplink_seid = veb->seid;
2616
2617         return veb;
2618 fail:
2619         rte_free(veb);
2620         return NULL;
2621 }
2622
2623 int
2624 i40e_vsi_release(struct i40e_vsi *vsi)
2625 {
2626         struct i40e_pf *pf;
2627         struct i40e_hw *hw;
2628         struct i40e_vsi_list *vsi_list;
2629         int ret;
2630         struct i40e_mac_filter *f;
2631
2632         if (!vsi)
2633                 return I40E_SUCCESS;
2634
2635         pf = I40E_VSI_TO_PF(vsi);
2636         hw = I40E_VSI_TO_HW(vsi);
2637
2638         /* VSI has child to attach, release child first */
2639         if (vsi->veb) {
2640                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2641                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2642                                 return -1;
2643                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2644                 }
2645                 i40e_veb_release(vsi->veb);
2646         }
2647
2648         /* Remove all macvlan filters of the VSI */
2649         i40e_vsi_remove_all_macvlan_filter(vsi);
2650         TAILQ_FOREACH(f, &vsi->mac_list, next)
2651                 rte_free(f);
2652
2653         if (vsi->type != I40E_VSI_MAIN) {
2654                 /* Remove vsi from parent's sibling list */
2655                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2656                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2657                         return I40E_ERR_PARAM;
2658                 }
2659                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2660                                 &vsi->sib_vsi_list, list);
2661
2662                 /* Remove all switch element of the VSI */
2663                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2664                 if (ret != I40E_SUCCESS)
2665                         PMD_DRV_LOG(ERR, "Failed to delete element");
2666         }
2667         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2668
2669         if (vsi->type != I40E_VSI_SRIOV)
2670                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2671         rte_free(vsi);
2672
2673         return I40E_SUCCESS;
2674 }
2675
2676 static int
2677 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2678 {
2679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2680         struct i40e_aqc_remove_macvlan_element_data def_filter;
2681         struct i40e_mac_filter_info filter;
2682         int ret;
2683
2684         if (vsi->type != I40E_VSI_MAIN)
2685                 return I40E_ERR_CONFIG;
2686         memset(&def_filter, 0, sizeof(def_filter));
2687         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2688                                         ETH_ADDR_LEN);
2689         def_filter.vlan_tag = 0;
2690         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2691                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2692         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2693         if (ret != I40E_SUCCESS) {
2694                 struct i40e_mac_filter *f;
2695                 struct ether_addr *mac;
2696
2697                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2698                             "macvlan filter");
2699                 /* It needs to add the permanent mac into mac list */
2700                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2701                 if (f == NULL) {
2702                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2703                         return I40E_ERR_NO_MEMORY;
2704                 }
2705                 mac = &f->mac_info.mac_addr;
2706                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2707                                 ETH_ADDR_LEN);
2708                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2709                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2710                 vsi->mac_num++;
2711
2712                 return ret;
2713         }
2714         (void)rte_memcpy(&filter.mac_addr,
2715                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2716         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2717         return i40e_vsi_add_mac(vsi, &filter);
2718 }
2719
2720 static int
2721 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2722 {
2723         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2724         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2725         struct i40e_hw *hw = &vsi->adapter->hw;
2726         i40e_status ret;
2727         int i;
2728
2729         memset(&bw_config, 0, sizeof(bw_config));
2730         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2731         if (ret != I40E_SUCCESS) {
2732                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2733                             hw->aq.asq_last_status);
2734                 return ret;
2735         }
2736
2737         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2738         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2739                                         &ets_sla_config, NULL);
2740         if (ret != I40E_SUCCESS) {
2741                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2742                             "configuration %u", hw->aq.asq_last_status);
2743                 return ret;
2744         }
2745
2746         /* Not store the info yet, just print out */
2747         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2748         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2749         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2750                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2751                             ets_sla_config.share_credits[i]);
2752                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2753                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2754                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2755                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2756                             (i * 4));
2757         }
2758
2759         return 0;
2760 }
2761
2762 /* Setup a VSI */
2763 struct i40e_vsi *
2764 i40e_vsi_setup(struct i40e_pf *pf,
2765                enum i40e_vsi_type type,
2766                struct i40e_vsi *uplink_vsi,
2767                uint16_t user_param)
2768 {
2769         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2770         struct i40e_vsi *vsi;
2771         struct i40e_mac_filter_info filter;
2772         int ret;
2773         struct i40e_vsi_context ctxt;
2774         struct ether_addr broadcast =
2775                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2776
2777         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2778                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2779                             "VSI link shouldn't be NULL");
2780                 return NULL;
2781         }
2782
2783         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2784                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2785                             "uplink VSI should be NULL");
2786                 return NULL;
2787         }
2788
2789         /* If uplink vsi didn't setup VEB, create one first */
2790         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2791                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2792
2793                 if (NULL == uplink_vsi->veb) {
2794                         PMD_DRV_LOG(ERR, "VEB setup failed");
2795                         return NULL;
2796                 }
2797         }
2798
2799         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2800         if (!vsi) {
2801                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2802                 return NULL;
2803         }
2804         TAILQ_INIT(&vsi->mac_list);
2805         vsi->type = type;
2806         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2807         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2808         vsi->parent_vsi = uplink_vsi;
2809         vsi->user_param = user_param;
2810         /* Allocate queues */
2811         switch (vsi->type) {
2812         case I40E_VSI_MAIN  :
2813                 vsi->nb_qps = pf->lan_nb_qps;
2814                 break;
2815         case I40E_VSI_SRIOV :
2816                 vsi->nb_qps = pf->vf_nb_qps;
2817                 break;
2818         case I40E_VSI_VMDQ2:
2819                 vsi->nb_qps = pf->vmdq_nb_qps;
2820                 break;
2821         default:
2822                 goto fail_mem;
2823         }
2824         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2825         if (ret < 0) {
2826                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2827                                 vsi->seid, ret);
2828                 goto fail_mem;
2829         }
2830         vsi->base_queue = ret;
2831
2832         /* VF has MSIX interrupt in VF range, don't allocate here */
2833         if (type != I40E_VSI_SRIOV) {
2834                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2835                 if (ret < 0) {
2836                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2837                         goto fail_queue_alloc;
2838                 }
2839                 vsi->msix_intr = ret;
2840         } else
2841                 vsi->msix_intr = 0;
2842         /* Add VSI */
2843         if (type == I40E_VSI_MAIN) {
2844                 /* For main VSI, no need to add since it's default one */
2845                 vsi->uplink_seid = pf->mac_seid;
2846                 vsi->seid = pf->main_vsi_seid;
2847                 /* Bind queues with specific MSIX interrupt */
2848                 /**
2849                  * Needs 2 interrupt at least, one for misc cause which will
2850                  * enabled from OS side, Another for queues binding the
2851                  * interrupt from device side only.
2852                  */
2853
2854                 /* Get default VSI parameters from hardware */
2855                 memset(&ctxt, 0, sizeof(ctxt));
2856                 ctxt.seid = vsi->seid;
2857                 ctxt.pf_num = hw->pf_id;
2858                 ctxt.uplink_seid = vsi->uplink_seid;
2859                 ctxt.vf_num = 0;
2860                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2861                 if (ret != I40E_SUCCESS) {
2862                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2863                         goto fail_msix_alloc;
2864                 }
2865                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2866                         sizeof(struct i40e_aqc_vsi_properties_data));
2867                 vsi->vsi_id = ctxt.vsi_number;
2868                 vsi->info.valid_sections = 0;
2869
2870                 /* Configure tc, enabled TC0 only */
2871                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2872                         I40E_SUCCESS) {
2873                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2874                         goto fail_msix_alloc;
2875                 }
2876
2877                 /* TC, queue mapping */
2878                 memset(&ctxt, 0, sizeof(ctxt));
2879                 vsi->info.valid_sections |=
2880                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2881                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2882                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2883                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2884                         sizeof(struct i40e_aqc_vsi_properties_data));
2885                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2886                                                 I40E_DEFAULT_TCMAP);
2887                 if (ret != I40E_SUCCESS) {
2888                         PMD_DRV_LOG(ERR, "Failed to configure "
2889                                     "TC queue mapping");
2890                         goto fail_msix_alloc;
2891                 }
2892                 ctxt.seid = vsi->seid;
2893                 ctxt.pf_num = hw->pf_id;
2894                 ctxt.uplink_seid = vsi->uplink_seid;
2895                 ctxt.vf_num = 0;
2896
2897                 /* Update VSI parameters */
2898                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2899                 if (ret != I40E_SUCCESS) {
2900                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2901                         goto fail_msix_alloc;
2902                 }
2903
2904                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2905                                                 sizeof(vsi->info.tc_mapping));
2906                 (void)rte_memcpy(&vsi->info.queue_mapping,
2907                                 &ctxt.info.queue_mapping,
2908                         sizeof(vsi->info.queue_mapping));
2909                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2910                 vsi->info.valid_sections = 0;
2911
2912                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2913                                 ETH_ADDR_LEN);
2914
2915                 /**
2916                  * Updating default filter settings are necessary to prevent
2917                  * reception of tagged packets.
2918                  * Some old firmware configurations load a default macvlan
2919                  * filter which accepts both tagged and untagged packets.
2920                  * The updating is to use a normal filter instead if needed.
2921                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2922                  * The firmware with correct configurations load the default
2923                  * macvlan filter which is expected and cannot be removed.
2924                  */
2925                 i40e_update_default_filter_setting(vsi);
2926         } else if (type == I40E_VSI_SRIOV) {
2927                 memset(&ctxt, 0, sizeof(ctxt));
2928                 /**
2929                  * For other VSI, the uplink_seid equals to uplink VSI's
2930                  * uplink_seid since they share same VEB
2931                  */
2932                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2933                 ctxt.pf_num = hw->pf_id;
2934                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2935                 ctxt.uplink_seid = vsi->uplink_seid;
2936                 ctxt.connection_type = 0x1;
2937                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2938
2939                 /* Configure switch ID */
2940                 ctxt.info.valid_sections |=
2941                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2942                 ctxt.info.switch_id =
2943                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2944                 /* Configure port/vlan */
2945                 ctxt.info.valid_sections |=
2946                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2947                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2948                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2949                                                 I40E_DEFAULT_TCMAP);
2950                 if (ret != I40E_SUCCESS) {
2951                         PMD_DRV_LOG(ERR, "Failed to configure "
2952                                     "TC queue mapping");
2953                         goto fail_msix_alloc;
2954                 }
2955                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2956                 ctxt.info.valid_sections |=
2957                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2958                 /**
2959                  * Since VSI is not created yet, only configure parameter,
2960                  * will add vsi below.
2961                  */
2962         } else if (type == I40E_VSI_VMDQ2) {
2963                 memset(&ctxt, 0, sizeof(ctxt));
2964                 /*
2965                  * For other VSI, the uplink_seid equals to uplink VSI's
2966                  * uplink_seid since they share same VEB
2967                  */
2968                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2969                 ctxt.pf_num = hw->pf_id;
2970                 ctxt.vf_num = 0;
2971                 ctxt.uplink_seid = vsi->uplink_seid;
2972                 ctxt.connection_type = 0x1;
2973                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
2974
2975                 ctxt.info.valid_sections |=
2976                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2977                 /* user_param carries flag to enable loop back */
2978                 if (user_param) {
2979                         ctxt.info.switch_id =
2980                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
2981                         ctxt.info.switch_id |=
2982                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2983                 }
2984
2985                 /* Configure port/vlan */
2986                 ctxt.info.valid_sections |=
2987                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2988                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2989                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2990                                                 I40E_DEFAULT_TCMAP);
2991                 if (ret != I40E_SUCCESS) {
2992                         PMD_DRV_LOG(ERR, "Failed to configure "
2993                                         "TC queue mapping");
2994                         goto fail_msix_alloc;
2995                 }
2996                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2997                 ctxt.info.valid_sections |=
2998                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2999         } else {
3000                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3001                 goto fail_msix_alloc;
3002         }
3003
3004         if (vsi->type != I40E_VSI_MAIN) {
3005                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3006                 if (ret) {
3007                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3008                                     hw->aq.asq_last_status);
3009                         goto fail_msix_alloc;
3010                 }
3011                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3012                 vsi->info.valid_sections = 0;
3013                 vsi->seid = ctxt.seid;
3014                 vsi->vsi_id = ctxt.vsi_number;
3015                 vsi->sib_vsi_list.vsi = vsi;
3016                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3017                                 &vsi->sib_vsi_list, list);
3018         }
3019
3020         /* MAC/VLAN configuration */
3021         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3022         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3023
3024         ret = i40e_vsi_add_mac(vsi, &filter);
3025         if (ret != I40E_SUCCESS) {
3026                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3027                 goto fail_msix_alloc;
3028         }
3029
3030         /* Get VSI BW information */
3031         i40e_vsi_dump_bw_config(vsi);
3032         return vsi;
3033 fail_msix_alloc:
3034         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3035 fail_queue_alloc:
3036         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3037 fail_mem:
3038         rte_free(vsi);
3039         return NULL;
3040 }
3041
3042 /* Configure vlan stripping on or off */
3043 int
3044 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3045 {
3046         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3047         struct i40e_vsi_context ctxt;
3048         uint8_t vlan_flags;
3049         int ret = I40E_SUCCESS;
3050
3051         /* Check if it has been already on or off */
3052         if (vsi->info.valid_sections &
3053                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3054                 if (on) {
3055                         if ((vsi->info.port_vlan_flags &
3056                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3057                                 return 0; /* already on */
3058                 } else {
3059                         if ((vsi->info.port_vlan_flags &
3060                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3061                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3062                                 return 0; /* already off */
3063                 }
3064         }
3065
3066         if (on)
3067                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3068         else
3069                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3070         vsi->info.valid_sections =
3071                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3072         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3073         vsi->info.port_vlan_flags |= vlan_flags;
3074         ctxt.seid = vsi->seid;
3075         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3076         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3077         if (ret)
3078                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3079                             on ? "enable" : "disable");
3080
3081         return ret;
3082 }
3083
3084 static int
3085 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3086 {
3087         struct rte_eth_dev_data *data = dev->data;
3088         int ret;
3089
3090         /* Apply vlan offload setting */
3091         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3092
3093         /* Apply double-vlan setting, not implemented yet */
3094
3095         /* Apply pvid setting */
3096         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3097                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3098         if (ret)
3099                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3100
3101         return ret;
3102 }
3103
3104 static int
3105 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3106 {
3107         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3108
3109         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3110 }
3111
3112 static int
3113 i40e_update_flow_control(struct i40e_hw *hw)
3114 {
3115 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3116         struct i40e_link_status link_status;
3117         uint32_t rxfc = 0, txfc = 0, reg;
3118         uint8_t an_info;
3119         int ret;
3120
3121         memset(&link_status, 0, sizeof(link_status));
3122         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3123         if (ret != I40E_SUCCESS) {
3124                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3125                 goto write_reg; /* Disable flow control */
3126         }
3127
3128         an_info = hw->phy.link_info.an_info;
3129         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3130                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3131                 ret = I40E_ERR_NOT_READY;
3132                 goto write_reg; /* Disable flow control */
3133         }
3134         /**
3135          * If link auto negotiation is enabled, flow control needs to
3136          * be configured according to it
3137          */
3138         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3139         case I40E_LINK_PAUSE_RXTX:
3140                 rxfc = 1;
3141                 txfc = 1;
3142                 hw->fc.current_mode = I40E_FC_FULL;
3143                 break;
3144         case I40E_AQ_LINK_PAUSE_RX:
3145                 rxfc = 1;
3146                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3147                 break;
3148         case I40E_AQ_LINK_PAUSE_TX:
3149                 txfc = 1;
3150                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3151                 break;
3152         default:
3153                 hw->fc.current_mode = I40E_FC_NONE;
3154                 break;
3155         }
3156
3157 write_reg:
3158         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3159                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3160         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3161         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3162         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3163         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3164
3165         return ret;
3166 }
3167
3168 /* PF setup */
3169 static int
3170 i40e_pf_setup(struct i40e_pf *pf)
3171 {
3172         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3173         struct i40e_filter_control_settings settings;
3174         struct i40e_vsi *vsi;
3175         int ret;
3176
3177         /* Clear all stats counters */
3178         pf->offset_loaded = FALSE;
3179         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3180         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3181
3182         ret = i40e_pf_get_switch_config(pf);
3183         if (ret != I40E_SUCCESS) {
3184                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3185                 return ret;
3186         }
3187
3188         /* VSI setup */
3189         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3190         if (!vsi) {
3191                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3192                 return I40E_ERR_NOT_READY;
3193         }
3194         pf->main_vsi = vsi;
3195
3196         /* Configure filter control */
3197         memset(&settings, 0, sizeof(settings));
3198         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3199                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3200         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3201                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3202         else {
3203                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3204                                                 hw->func_caps.rss_table_size);
3205                 return I40E_ERR_PARAM;
3206         }
3207         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3208                         "size: %u\n", hw->func_caps.rss_table_size);
3209         pf->hash_lut_size = hw->func_caps.rss_table_size;
3210
3211         /* Enable ethtype and macvlan filters */
3212         settings.enable_ethtype = TRUE;
3213         settings.enable_macvlan = TRUE;
3214         ret = i40e_set_filter_control(hw, &settings);
3215         if (ret)
3216                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3217                                                                 ret);
3218
3219         /* Update flow control according to the auto negotiation */
3220         i40e_update_flow_control(hw);
3221
3222         return I40E_SUCCESS;
3223 }
3224
3225 int
3226 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3227 {
3228         uint32_t reg;
3229         uint16_t j;
3230
3231         /**
3232          * Set or clear TX Queue Disable flags,
3233          * which is required by hardware.
3234          */
3235         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3236         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3237
3238         /* Wait until the request is finished */
3239         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3240                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3241                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3242                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3243                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3244                                                         & 0x1))) {
3245                         break;
3246                 }
3247         }
3248         if (on) {
3249                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3250                         return I40E_SUCCESS; /* already on, skip next steps */
3251
3252                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3253                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3254         } else {
3255                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3256                         return I40E_SUCCESS; /* already off, skip next steps */
3257                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3258         }
3259         /* Write the register */
3260         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3261         /* Check the result */
3262         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3263                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3264                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3265                 if (on) {
3266                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3267                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3268                                 break;
3269                 } else {
3270                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3271                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3272                                 break;
3273                 }
3274         }
3275         /* Check if it is timeout */
3276         if (j >= I40E_CHK_Q_ENA_COUNT) {
3277                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3278                             (on ? "enable" : "disable"), q_idx);
3279                 return I40E_ERR_TIMEOUT;
3280         }
3281
3282         return I40E_SUCCESS;
3283 }
3284
3285 /* Swith on or off the tx queues */
3286 static int
3287 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3288 {
3289         struct rte_eth_dev_data *dev_data = pf->dev_data;
3290         struct i40e_tx_queue *txq;
3291         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3292         uint16_t i;
3293         int ret;
3294
3295         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3296                 txq = dev_data->tx_queues[i];
3297                 /* Don't operate the queue if not configured or
3298                  * if starting only per queue */
3299                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3300                         continue;
3301                 if (on)
3302                         ret = i40e_dev_tx_queue_start(dev, i);
3303                 else
3304                         ret = i40e_dev_tx_queue_stop(dev, i);
3305                 if ( ret != I40E_SUCCESS)
3306                         return ret;
3307         }
3308
3309         return I40E_SUCCESS;
3310 }
3311
3312 int
3313 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3314 {
3315         uint32_t reg;
3316         uint16_t j;
3317
3318         /* Wait until the request is finished */
3319         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3320                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3321                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3322                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3323                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3324                         break;
3325         }
3326
3327         if (on) {
3328                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3329                         return I40E_SUCCESS; /* Already on, skip next steps */
3330                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3331         } else {
3332                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3333                         return I40E_SUCCESS; /* Already off, skip next steps */
3334                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3335         }
3336
3337         /* Write the register */
3338         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3339         /* Check the result */
3340         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3341                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3342                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3343                 if (on) {
3344                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3345                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3346                                 break;
3347                 } else {
3348                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3349                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3350                                 break;
3351                 }
3352         }
3353
3354         /* Check if it is timeout */
3355         if (j >= I40E_CHK_Q_ENA_COUNT) {
3356                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3357                             (on ? "enable" : "disable"), q_idx);
3358                 return I40E_ERR_TIMEOUT;
3359         }
3360
3361         return I40E_SUCCESS;
3362 }
3363 /* Switch on or off the rx queues */
3364 static int
3365 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3366 {
3367         struct rte_eth_dev_data *dev_data = pf->dev_data;
3368         struct i40e_rx_queue *rxq;
3369         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3370         uint16_t i;
3371         int ret;
3372
3373         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3374                 rxq = dev_data->rx_queues[i];
3375                 /* Don't operate the queue if not configured or
3376                  * if starting only per queue */
3377                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3378                         continue;
3379                 if (on)
3380                         ret = i40e_dev_rx_queue_start(dev, i);
3381                 else
3382                         ret = i40e_dev_rx_queue_stop(dev, i);
3383                 if (ret != I40E_SUCCESS)
3384                         return ret;
3385         }
3386
3387         return I40E_SUCCESS;
3388 }
3389
3390 /* Switch on or off all the rx/tx queues */
3391 int
3392 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3393 {
3394         int ret;
3395
3396         if (on) {
3397                 /* enable rx queues before enabling tx queues */
3398                 ret = i40e_dev_switch_rx_queues(pf, on);
3399                 if (ret) {
3400                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3401                         return ret;
3402                 }
3403                 ret = i40e_dev_switch_tx_queues(pf, on);
3404         } else {
3405                 /* Stop tx queues before stopping rx queues */
3406                 ret = i40e_dev_switch_tx_queues(pf, on);
3407                 if (ret) {
3408                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3409                         return ret;
3410                 }
3411                 ret = i40e_dev_switch_rx_queues(pf, on);
3412         }
3413
3414         return ret;
3415 }
3416
3417 /* Initialize VSI for TX */
3418 static int
3419 i40e_dev_tx_init(struct i40e_pf *pf)
3420 {
3421         struct rte_eth_dev_data *data = pf->dev_data;
3422         uint16_t i;
3423         uint32_t ret = I40E_SUCCESS;
3424         struct i40e_tx_queue *txq;
3425
3426         for (i = 0; i < data->nb_tx_queues; i++) {
3427                 txq = data->tx_queues[i];
3428                 if (!txq || !txq->q_set)
3429                         continue;
3430                 ret = i40e_tx_queue_init(txq);
3431                 if (ret != I40E_SUCCESS)
3432                         break;
3433         }
3434
3435         return ret;
3436 }
3437
3438 /* Initialize VSI for RX */
3439 static int
3440 i40e_dev_rx_init(struct i40e_pf *pf)
3441 {
3442         struct rte_eth_dev_data *data = pf->dev_data;
3443         int ret = I40E_SUCCESS;
3444         uint16_t i;
3445         struct i40e_rx_queue *rxq;
3446
3447         i40e_pf_config_mq_rx(pf);
3448         for (i = 0; i < data->nb_rx_queues; i++) {
3449                 rxq = data->rx_queues[i];
3450                 if (!rxq || !rxq->q_set)
3451                         continue;
3452
3453                 ret = i40e_rx_queue_init(rxq);
3454                 if (ret != I40E_SUCCESS) {
3455                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3456                                     "initialization");
3457                         break;
3458                 }
3459         }
3460
3461         return ret;
3462 }
3463
3464 static int
3465 i40e_dev_rxtx_init(struct i40e_pf *pf)
3466 {
3467         int err;
3468
3469         err = i40e_dev_tx_init(pf);
3470         if (err) {
3471                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3472                 return err;
3473         }
3474         err = i40e_dev_rx_init(pf);
3475         if (err) {
3476                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3477                 return err;
3478         }
3479
3480         return err;
3481 }
3482
3483 static int
3484 i40e_vmdq_setup(struct rte_eth_dev *dev)
3485 {
3486         struct rte_eth_conf *conf = &dev->data->dev_conf;
3487         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3488         int i, err, conf_vsis, j, loop;
3489         struct i40e_vsi *vsi;
3490         struct i40e_vmdq_info *vmdq_info;
3491         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3492         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3493
3494         /*
3495          * Disable interrupt to avoid message from VF. Furthermore, it will
3496          * avoid race condition in VSI creation/destroy.
3497          */
3498         i40e_pf_disable_irq0(hw);
3499
3500         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3501                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3502                 return -ENOTSUP;
3503         }
3504
3505         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3506         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3507                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3508                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3509                         pf->max_nb_vmdq_vsi);
3510                 return -ENOTSUP;
3511         }
3512
3513         if (pf->vmdq != NULL) {
3514                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3515                 return 0;
3516         }
3517
3518         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3519                                 sizeof(*vmdq_info) * conf_vsis, 0);
3520
3521         if (pf->vmdq == NULL) {
3522                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3523                 return -ENOMEM;
3524         }
3525
3526         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3527
3528         /* Create VMDQ VSI */
3529         for (i = 0; i < conf_vsis; i++) {
3530                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3531                                 vmdq_conf->enable_loop_back);
3532                 if (vsi == NULL) {
3533                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3534                         err = -1;
3535                         goto err_vsi_setup;
3536                 }
3537                 vmdq_info = &pf->vmdq[i];
3538                 vmdq_info->pf = pf;
3539                 vmdq_info->vsi = vsi;
3540         }
3541         pf->nb_cfg_vmdq_vsi = conf_vsis;
3542
3543         /* Configure Vlan */
3544         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3545         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3546                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3547                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3548                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3549                                         vmdq_conf->pool_map[i].vlan_id, j);
3550
3551                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3552                                                 vmdq_conf->pool_map[i].vlan_id);
3553                                 if (err) {
3554                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3555                                         err = -1;
3556                                         goto err_vsi_setup;
3557                                 }
3558                         }
3559                 }
3560         }
3561
3562         i40e_pf_enable_irq0(hw);
3563
3564         return 0;
3565
3566 err_vsi_setup:
3567         for (i = 0; i < conf_vsis; i++)
3568                 if (pf->vmdq[i].vsi == NULL)
3569                         break;
3570                 else
3571                         i40e_vsi_release(pf->vmdq[i].vsi);
3572
3573         rte_free(pf->vmdq);
3574         pf->vmdq = NULL;
3575         i40e_pf_enable_irq0(hw);
3576         return err;
3577 }
3578
3579 static void
3580 i40e_stat_update_32(struct i40e_hw *hw,
3581                    uint32_t reg,
3582                    bool offset_loaded,
3583                    uint64_t *offset,
3584                    uint64_t *stat)
3585 {
3586         uint64_t new_data;
3587
3588         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3589         if (!offset_loaded)
3590                 *offset = new_data;
3591
3592         if (new_data >= *offset)
3593                 *stat = (uint64_t)(new_data - *offset);
3594         else
3595                 *stat = (uint64_t)((new_data +
3596                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3597 }
3598
3599 static void
3600 i40e_stat_update_48(struct i40e_hw *hw,
3601                    uint32_t hireg,
3602                    uint32_t loreg,
3603                    bool offset_loaded,
3604                    uint64_t *offset,
3605                    uint64_t *stat)
3606 {
3607         uint64_t new_data;
3608
3609         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3610         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3611                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3612
3613         if (!offset_loaded)
3614                 *offset = new_data;
3615
3616         if (new_data >= *offset)
3617                 *stat = new_data - *offset;
3618         else
3619                 *stat = (uint64_t)((new_data +
3620                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3621
3622         *stat &= I40E_48_BIT_MASK;
3623 }
3624
3625 /* Disable IRQ0 */
3626 void
3627 i40e_pf_disable_irq0(struct i40e_hw *hw)
3628 {
3629         /* Disable all interrupt types */
3630         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3631         I40E_WRITE_FLUSH(hw);
3632 }
3633
3634 /* Enable IRQ0 */
3635 void
3636 i40e_pf_enable_irq0(struct i40e_hw *hw)
3637 {
3638         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3639                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3640                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3641                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3642         I40E_WRITE_FLUSH(hw);
3643 }
3644
3645 static void
3646 i40e_pf_config_irq0(struct i40e_hw *hw)
3647 {
3648         /* read pending request and disable first */
3649         i40e_pf_disable_irq0(hw);
3650         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3651         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3652                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3653
3654         /* Link no queues with irq0 */
3655         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3656                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3657 }
3658
3659 static void
3660 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3661 {
3662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3663         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3664         int i;
3665         uint16_t abs_vf_id;
3666         uint32_t index, offset, val;
3667
3668         if (!pf->vfs)
3669                 return;
3670         /**
3671          * Try to find which VF trigger a reset, use absolute VF id to access
3672          * since the reg is global register.
3673          */
3674         for (i = 0; i < pf->vf_num; i++) {
3675                 abs_vf_id = hw->func_caps.vf_base_id + i;
3676                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3677                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3678                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3679                 /* VFR event occured */
3680                 if (val & (0x1 << offset)) {
3681                         int ret;
3682
3683                         /* Clear the event first */
3684                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3685                                                         (0x1 << offset));
3686                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3687                         /**
3688                          * Only notify a VF reset event occured,
3689                          * don't trigger another SW reset
3690                          */
3691                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3692                         if (ret != I40E_SUCCESS)
3693                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3694                 }
3695         }
3696 }
3697
3698 static void
3699 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3700 {
3701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702         struct i40e_arq_event_info info;
3703         uint16_t pending, opcode;
3704         int ret;
3705
3706         info.buf_len = I40E_AQ_BUF_SZ;
3707         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3708         if (!info.msg_buf) {
3709                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3710                 return;
3711         }
3712
3713         pending = 1;
3714         while (pending) {
3715                 ret = i40e_clean_arq_element(hw, &info, &pending);
3716
3717                 if (ret != I40E_SUCCESS) {
3718                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3719                                     "aq_err: %u", hw->aq.asq_last_status);
3720                         break;
3721                 }
3722                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3723
3724                 switch (opcode) {
3725                 case i40e_aqc_opc_send_msg_to_pf:
3726                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3727                         i40e_pf_host_handle_vf_msg(dev,
3728                                         rte_le_to_cpu_16(info.desc.retval),
3729                                         rte_le_to_cpu_32(info.desc.cookie_high),
3730                                         rte_le_to_cpu_32(info.desc.cookie_low),
3731                                         info.msg_buf,
3732                                         info.msg_len);
3733                         break;
3734                 default:
3735                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3736                                     opcode);
3737                         break;
3738                 }
3739         }
3740         rte_free(info.msg_buf);
3741 }
3742
3743 /*
3744  * Interrupt handler is registered as the alarm callback for handling LSC
3745  * interrupt in a definite of time, in order to wait the NIC into a stable
3746  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3747  * no need for link down interrupt.
3748  */
3749 static void
3750 i40e_dev_interrupt_delayed_handler(void *param)
3751 {
3752         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3753         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3754         uint32_t icr0;
3755
3756         /* read interrupt causes again */
3757         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3758
3759 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3760         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3761                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3762         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3763                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3764         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3765                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3766         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3767                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3768         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3769                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3770                                                                 "state\n");
3771         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3772                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3773         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3774                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3775 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3776
3777         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3778                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3779                 i40e_dev_handle_vfr_event(dev);
3780         }
3781         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3782                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3783                 i40e_dev_handle_aq_msg(dev);
3784         }
3785
3786         /* handle the link up interrupt in an alarm callback */
3787         i40e_dev_link_update(dev, 0);
3788         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3789
3790         i40e_pf_enable_irq0(hw);
3791         rte_intr_enable(&(dev->pci_dev->intr_handle));
3792 }
3793
3794 /**
3795  * Interrupt handler triggered by NIC  for handling
3796  * specific interrupt.
3797  *
3798  * @param handle
3799  *  Pointer to interrupt handle.
3800  * @param param
3801  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3802  *
3803  * @return
3804  *  void
3805  */
3806 static void
3807 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3808                            void *param)
3809 {
3810         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812         uint32_t icr0;
3813
3814         /* Disable interrupt */
3815         i40e_pf_disable_irq0(hw);
3816
3817         /* read out interrupt causes */
3818         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3819
3820         /* No interrupt event indicated */
3821         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3822                 PMD_DRV_LOG(INFO, "No interrupt event");
3823                 goto done;
3824         }
3825 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3826         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3827                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3828         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3829                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3830         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3831                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
3832         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3833                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
3834         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3835                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
3836         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3837                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
3838         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3839                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
3840 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3841
3842         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3843                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
3844                 i40e_dev_handle_vfr_event(dev);
3845         }
3846         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3847                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
3848                 i40e_dev_handle_aq_msg(dev);
3849         }
3850
3851         /* Link Status Change interrupt */
3852         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3853 #define I40E_US_PER_SECOND 1000000
3854                 struct rte_eth_link link;
3855
3856                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
3857                 memset(&link, 0, sizeof(link));
3858                 rte_i40e_dev_atomic_read_link_status(dev, &link);
3859                 i40e_dev_link_update(dev, 0);
3860
3861                 /*
3862                  * For link up interrupt, it needs to wait 1 second to let the
3863                  * hardware be a stable state. Otherwise several consecutive
3864                  * interrupts can be observed.
3865                  * For link down interrupt, no need to wait.
3866                  */
3867                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
3868                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
3869                         return;
3870                 else
3871                         _rte_eth_dev_callback_process(dev,
3872                                 RTE_ETH_EVENT_INTR_LSC);
3873         }
3874
3875 done:
3876         /* Enable interrupt */
3877         i40e_pf_enable_irq0(hw);
3878         rte_intr_enable(&(dev->pci_dev->intr_handle));
3879 }
3880
3881 static int
3882 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3883                          struct i40e_macvlan_filter *filter,
3884                          int total)
3885 {
3886         int ele_num, ele_buff_size;
3887         int num, actual_num, i;
3888         uint16_t flags;
3889         int ret = I40E_SUCCESS;
3890         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3891         struct i40e_aqc_add_macvlan_element_data *req_list;
3892
3893         if (filter == NULL  || total == 0)
3894                 return I40E_ERR_PARAM;
3895         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3896         ele_buff_size = hw->aq.asq_buf_size;
3897
3898         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3899         if (req_list == NULL) {
3900                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3901                 return I40E_ERR_NO_MEMORY;
3902         }
3903
3904         num = 0;
3905         do {
3906                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3907                 memset(req_list, 0, ele_buff_size);
3908
3909                 for (i = 0; i < actual_num; i++) {
3910                         (void)rte_memcpy(req_list[i].mac_addr,
3911                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3912                         req_list[i].vlan_tag =
3913                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3914
3915                         switch (filter[num + i].filter_type) {
3916                         case RTE_MAC_PERFECT_MATCH:
3917                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
3918                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3919                                 break;
3920                         case RTE_MACVLAN_PERFECT_MATCH:
3921                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
3922                                 break;
3923                         case RTE_MAC_HASH_MATCH:
3924                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
3925                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
3926                                 break;
3927                         case RTE_MACVLAN_HASH_MATCH:
3928                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
3929                                 break;
3930                         default:
3931                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
3932                                 ret = I40E_ERR_PARAM;
3933                                 goto DONE;
3934                         }
3935
3936                         req_list[i].queue_number = 0;
3937
3938                         req_list[i].flags = rte_cpu_to_le_16(flags);
3939                 }
3940
3941                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3942                                                 actual_num, NULL);
3943                 if (ret != I40E_SUCCESS) {
3944                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3945                         goto DONE;
3946                 }
3947                 num += actual_num;
3948         } while (num < total);
3949
3950 DONE:
3951         rte_free(req_list);
3952         return ret;
3953 }
3954
3955 static int
3956 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3957                             struct i40e_macvlan_filter *filter,
3958                             int total)
3959 {
3960         int ele_num, ele_buff_size;
3961         int num, actual_num, i;
3962         uint16_t flags;
3963         int ret = I40E_SUCCESS;
3964         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3965         struct i40e_aqc_remove_macvlan_element_data *req_list;
3966
3967         if (filter == NULL  || total == 0)
3968                 return I40E_ERR_PARAM;
3969
3970         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3971         ele_buff_size = hw->aq.asq_buf_size;
3972
3973         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3974         if (req_list == NULL) {
3975                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3976                 return I40E_ERR_NO_MEMORY;
3977         }
3978
3979         num = 0;
3980         do {
3981                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3982                 memset(req_list, 0, ele_buff_size);
3983
3984                 for (i = 0; i < actual_num; i++) {
3985                         (void)rte_memcpy(req_list[i].mac_addr,
3986                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3987                         req_list[i].vlan_tag =
3988                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3989
3990                         switch (filter[num + i].filter_type) {
3991                         case RTE_MAC_PERFECT_MATCH:
3992                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3993                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3994                                 break;
3995                         case RTE_MACVLAN_PERFECT_MATCH:
3996                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3997                                 break;
3998                         case RTE_MAC_HASH_MATCH:
3999                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4000                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4001                                 break;
4002                         case RTE_MACVLAN_HASH_MATCH:
4003                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4004                                 break;
4005                         default:
4006                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4007                                 ret = I40E_ERR_PARAM;
4008                                 goto DONE;
4009                         }
4010                         req_list[i].flags = rte_cpu_to_le_16(flags);
4011                 }
4012
4013                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4014                                                 actual_num, NULL);
4015                 if (ret != I40E_SUCCESS) {
4016                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4017                         goto DONE;
4018                 }
4019                 num += actual_num;
4020         } while (num < total);
4021
4022 DONE:
4023         rte_free(req_list);
4024         return ret;
4025 }
4026
4027 /* Find out specific MAC filter */
4028 static struct i40e_mac_filter *
4029 i40e_find_mac_filter(struct i40e_vsi *vsi,
4030                          struct ether_addr *macaddr)
4031 {
4032         struct i40e_mac_filter *f;
4033
4034         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4035                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4036                         return f;
4037         }
4038
4039         return NULL;
4040 }
4041
4042 static bool
4043 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4044                          uint16_t vlan_id)
4045 {
4046         uint32_t vid_idx, vid_bit;
4047
4048         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4049         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4050
4051         if (vsi->vfta[vid_idx] & vid_bit)
4052                 return 1;
4053         else
4054                 return 0;
4055 }
4056
4057 static void
4058 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4059                          uint16_t vlan_id, bool on)
4060 {
4061         uint32_t vid_idx, vid_bit;
4062
4063 #define UINT32_BIT_MASK      0x1F
4064 #define VALID_VLAN_BIT_MASK  0xFFF
4065         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
4066          *  element first, then find the bits it belongs to
4067          */
4068         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
4069                   sizeof(uint32_t));
4070         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
4071
4072         if (on)
4073                 vsi->vfta[vid_idx] |= vid_bit;
4074         else
4075                 vsi->vfta[vid_idx] &= ~vid_bit;
4076 }
4077
4078 /**
4079  * Find all vlan options for specific mac addr,
4080  * return with actual vlan found.
4081  */
4082 static inline int
4083 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4084                            struct i40e_macvlan_filter *mv_f,
4085                            int num, struct ether_addr *addr)
4086 {
4087         int i;
4088         uint32_t j, k;
4089
4090         /**
4091          * Not to use i40e_find_vlan_filter to decrease the loop time,
4092          * although the code looks complex.
4093           */
4094         if (num < vsi->vlan_num)
4095                 return I40E_ERR_PARAM;
4096
4097         i = 0;
4098         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4099                 if (vsi->vfta[j]) {
4100                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4101                                 if (vsi->vfta[j] & (1 << k)) {
4102                                         if (i > num - 1) {
4103                                                 PMD_DRV_LOG(ERR, "vlan number "
4104                                                             "not match");
4105                                                 return I40E_ERR_PARAM;
4106                                         }
4107                                         (void)rte_memcpy(&mv_f[i].macaddr,
4108                                                         addr, ETH_ADDR_LEN);
4109                                         mv_f[i].vlan_id =
4110                                                 j * I40E_UINT32_BIT_SIZE + k;
4111                                         i++;
4112                                 }
4113                         }
4114                 }
4115         }
4116         return I40E_SUCCESS;
4117 }
4118
4119 static inline int
4120 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4121                            struct i40e_macvlan_filter *mv_f,
4122                            int num,
4123                            uint16_t vlan)
4124 {
4125         int i = 0;
4126         struct i40e_mac_filter *f;
4127
4128         if (num < vsi->mac_num)
4129                 return I40E_ERR_PARAM;
4130
4131         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4132                 if (i > num - 1) {
4133                         PMD_DRV_LOG(ERR, "buffer number not match");
4134                         return I40E_ERR_PARAM;
4135                 }
4136                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4137                                 ETH_ADDR_LEN);
4138                 mv_f[i].vlan_id = vlan;
4139                 mv_f[i].filter_type = f->mac_info.filter_type;
4140                 i++;
4141         }
4142
4143         return I40E_SUCCESS;
4144 }
4145
4146 static int
4147 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4148 {
4149         int i, num;
4150         struct i40e_mac_filter *f;
4151         struct i40e_macvlan_filter *mv_f;
4152         int ret = I40E_SUCCESS;
4153
4154         if (vsi == NULL || vsi->mac_num == 0)
4155                 return I40E_ERR_PARAM;
4156
4157         /* Case that no vlan is set */
4158         if (vsi->vlan_num == 0)
4159                 num = vsi->mac_num;
4160         else
4161                 num = vsi->mac_num * vsi->vlan_num;
4162
4163         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4164         if (mv_f == NULL) {
4165                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4166                 return I40E_ERR_NO_MEMORY;
4167         }
4168
4169         i = 0;
4170         if (vsi->vlan_num == 0) {
4171                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4172                         (void)rte_memcpy(&mv_f[i].macaddr,
4173                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4174                         mv_f[i].vlan_id = 0;
4175                         i++;
4176                 }
4177         } else {
4178                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4179                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4180                                         vsi->vlan_num, &f->mac_info.mac_addr);
4181                         if (ret != I40E_SUCCESS)
4182                                 goto DONE;
4183                         i += vsi->vlan_num;
4184                 }
4185         }
4186
4187         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4188 DONE:
4189         rte_free(mv_f);
4190
4191         return ret;
4192 }
4193
4194 int
4195 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4196 {
4197         struct i40e_macvlan_filter *mv_f;
4198         int mac_num;
4199         int ret = I40E_SUCCESS;
4200
4201         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4202                 return I40E_ERR_PARAM;
4203
4204         /* If it's already set, just return */
4205         if (i40e_find_vlan_filter(vsi,vlan))
4206                 return I40E_SUCCESS;
4207
4208         mac_num = vsi->mac_num;
4209
4210         if (mac_num == 0) {
4211                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4212                 return I40E_ERR_PARAM;
4213         }
4214
4215         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4216
4217         if (mv_f == NULL) {
4218                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4219                 return I40E_ERR_NO_MEMORY;
4220         }
4221
4222         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4223
4224         if (ret != I40E_SUCCESS)
4225                 goto DONE;
4226
4227         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4228
4229         if (ret != I40E_SUCCESS)
4230                 goto DONE;
4231
4232         i40e_set_vlan_filter(vsi, vlan, 1);
4233
4234         vsi->vlan_num++;
4235         ret = I40E_SUCCESS;
4236 DONE:
4237         rte_free(mv_f);
4238         return ret;
4239 }
4240
4241 int
4242 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4243 {
4244         struct i40e_macvlan_filter *mv_f;
4245         int mac_num;
4246         int ret = I40E_SUCCESS;
4247
4248         /**
4249          * Vlan 0 is the generic filter for untagged packets
4250          * and can't be removed.
4251          */
4252         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4253                 return I40E_ERR_PARAM;
4254
4255         /* If can't find it, just return */
4256         if (!i40e_find_vlan_filter(vsi, vlan))
4257                 return I40E_ERR_PARAM;
4258
4259         mac_num = vsi->mac_num;
4260
4261         if (mac_num == 0) {
4262                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4263                 return I40E_ERR_PARAM;
4264         }
4265
4266         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4267
4268         if (mv_f == NULL) {
4269                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4270                 return I40E_ERR_NO_MEMORY;
4271         }
4272
4273         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4274
4275         if (ret != I40E_SUCCESS)
4276                 goto DONE;
4277
4278         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4279
4280         if (ret != I40E_SUCCESS)
4281                 goto DONE;
4282
4283         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4284         if (vsi->vlan_num == 1) {
4285                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4286                 if (ret != I40E_SUCCESS)
4287                         goto DONE;
4288
4289                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4290                 if (ret != I40E_SUCCESS)
4291                         goto DONE;
4292         }
4293
4294         i40e_set_vlan_filter(vsi, vlan, 0);
4295
4296         vsi->vlan_num--;
4297         ret = I40E_SUCCESS;
4298 DONE:
4299         rte_free(mv_f);
4300         return ret;
4301 }
4302
4303 int
4304 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4305 {
4306         struct i40e_mac_filter *f;
4307         struct i40e_macvlan_filter *mv_f;
4308         int i, vlan_num = 0;
4309         int ret = I40E_SUCCESS;
4310
4311         /* If it's add and we've config it, return */
4312         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4313         if (f != NULL)
4314                 return I40E_SUCCESS;
4315         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4316                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4317
4318                 /**
4319                  * If vlan_num is 0, that's the first time to add mac,
4320                  * set mask for vlan_id 0.
4321                  */
4322                 if (vsi->vlan_num == 0) {
4323                         i40e_set_vlan_filter(vsi, 0, 1);
4324                         vsi->vlan_num = 1;
4325                 }
4326                 vlan_num = vsi->vlan_num;
4327         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4328                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4329                 vlan_num = 1;
4330
4331         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4332         if (mv_f == NULL) {
4333                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4334                 return I40E_ERR_NO_MEMORY;
4335         }
4336
4337         for (i = 0; i < vlan_num; i++) {
4338                 mv_f[i].filter_type = mac_filter->filter_type;
4339                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4340                                 ETH_ADDR_LEN);
4341         }
4342
4343         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4344                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4345                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4346                                         &mac_filter->mac_addr);
4347                 if (ret != I40E_SUCCESS)
4348                         goto DONE;
4349         }
4350
4351         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4352         if (ret != I40E_SUCCESS)
4353                 goto DONE;
4354
4355         /* Add the mac addr into mac list */
4356         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4357         if (f == NULL) {
4358                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4359                 ret = I40E_ERR_NO_MEMORY;
4360                 goto DONE;
4361         }
4362         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4363                         ETH_ADDR_LEN);
4364         f->mac_info.filter_type = mac_filter->filter_type;
4365         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4366         vsi->mac_num++;
4367
4368         ret = I40E_SUCCESS;
4369 DONE:
4370         rte_free(mv_f);
4371
4372         return ret;
4373 }
4374
4375 int
4376 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4377 {
4378         struct i40e_mac_filter *f;
4379         struct i40e_macvlan_filter *mv_f;
4380         int i, vlan_num;
4381         enum rte_mac_filter_type filter_type;
4382         int ret = I40E_SUCCESS;
4383
4384         /* Can't find it, return an error */
4385         f = i40e_find_mac_filter(vsi, addr);
4386         if (f == NULL)
4387                 return I40E_ERR_PARAM;
4388
4389         vlan_num = vsi->vlan_num;
4390         filter_type = f->mac_info.filter_type;
4391         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4392                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4393                 if (vlan_num == 0) {
4394                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4395                         return I40E_ERR_PARAM;
4396                 }
4397         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4398                         filter_type == RTE_MAC_HASH_MATCH)
4399                 vlan_num = 1;
4400
4401         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4402         if (mv_f == NULL) {
4403                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4404                 return I40E_ERR_NO_MEMORY;
4405         }
4406
4407         for (i = 0; i < vlan_num; i++) {
4408                 mv_f[i].filter_type = filter_type;
4409                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4410                                 ETH_ADDR_LEN);
4411         }
4412         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4413                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4414                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4415                 if (ret != I40E_SUCCESS)
4416                         goto DONE;
4417         }
4418
4419         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4420         if (ret != I40E_SUCCESS)
4421                 goto DONE;
4422
4423         /* Remove the mac addr into mac list */
4424         TAILQ_REMOVE(&vsi->mac_list, f, next);
4425         rte_free(f);
4426         vsi->mac_num--;
4427
4428         ret = I40E_SUCCESS;
4429 DONE:
4430         rte_free(mv_f);
4431         return ret;
4432 }
4433
4434 /* Configure hash enable flags for RSS */
4435 uint64_t
4436 i40e_config_hena(uint64_t flags)
4437 {
4438         uint64_t hena = 0;
4439
4440         if (!flags)
4441                 return hena;
4442
4443         if (flags & ETH_RSS_NONF_IPV4_UDP)
4444                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4445         if (flags & ETH_RSS_NONF_IPV4_TCP)
4446                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4447         if (flags & ETH_RSS_NONF_IPV4_SCTP)
4448                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4449         if (flags & ETH_RSS_NONF_IPV4_OTHER)
4450                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4451         if (flags & ETH_RSS_FRAG_IPV4)
4452                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4453         if (flags & ETH_RSS_NONF_IPV6_UDP)
4454                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4455         if (flags & ETH_RSS_NONF_IPV6_TCP)
4456                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4457         if (flags & ETH_RSS_NONF_IPV6_SCTP)
4458                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4459         if (flags & ETH_RSS_NONF_IPV6_OTHER)
4460                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4461         if (flags & ETH_RSS_FRAG_IPV6)
4462                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4463         if (flags & ETH_RSS_L2_PAYLOAD)
4464                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4465
4466         return hena;
4467 }
4468
4469 /* Parse the hash enable flags */
4470 uint64_t
4471 i40e_parse_hena(uint64_t flags)
4472 {
4473         uint64_t rss_hf = 0;
4474
4475         if (!flags)
4476                 return rss_hf;
4477
4478         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4479                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
4480         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4481                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
4482         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4483                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
4484         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4485                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
4486         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4487                 rss_hf |= ETH_RSS_FRAG_IPV4;
4488         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4489                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4490         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4491                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4492         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4493                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4494         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4495                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4496         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4497                 rss_hf |= ETH_RSS_FRAG_IPV6;
4498         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4499                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4500
4501         return rss_hf;
4502 }
4503
4504 /* Disable RSS */
4505 static void
4506 i40e_pf_disable_rss(struct i40e_pf *pf)
4507 {
4508         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4509         uint64_t hena;
4510
4511         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4512         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4513         hena &= ~I40E_RSS_HENA_ALL;
4514         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4515         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4516         I40E_WRITE_FLUSH(hw);
4517 }
4518
4519 static int
4520 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4521 {
4522         uint32_t *hash_key;
4523         uint8_t hash_key_len;
4524         uint64_t rss_hf;
4525         uint16_t i;
4526         uint64_t hena;
4527
4528         hash_key = (uint32_t *)(rss_conf->rss_key);
4529         hash_key_len = rss_conf->rss_key_len;
4530         if (hash_key != NULL && hash_key_len >=
4531                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4532                 /* Fill in RSS hash key */
4533                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4534                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4535         }
4536
4537         rss_hf = rss_conf->rss_hf;
4538         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4539         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4540         hena &= ~I40E_RSS_HENA_ALL;
4541         hena |= i40e_config_hena(rss_hf);
4542         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4543         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4544         I40E_WRITE_FLUSH(hw);
4545
4546         return 0;
4547 }
4548
4549 static int
4550 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4551                          struct rte_eth_rss_conf *rss_conf)
4552 {
4553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4555         uint64_t hena;
4556
4557         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4558         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4559         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4560                 if (rss_hf != 0) /* Enable RSS */
4561                         return -EINVAL;
4562                 return 0; /* Nothing to do */
4563         }
4564         /* RSS enabled */
4565         if (rss_hf == 0) /* Disable RSS */
4566                 return -EINVAL;
4567
4568         return i40e_hw_rss_hash_set(hw, rss_conf);
4569 }
4570
4571 static int
4572 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4573                            struct rte_eth_rss_conf *rss_conf)
4574 {
4575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4576         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4577         uint64_t hena;
4578         uint16_t i;
4579
4580         if (hash_key != NULL) {
4581                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4582                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4583                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4584         }
4585         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4586         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4587         rss_conf->rss_hf = i40e_parse_hena(hena);
4588
4589         return 0;
4590 }
4591
4592 static int
4593 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4594 {
4595         switch (filter_type) {
4596         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4597                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4598                 break;
4599         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4600                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4601                 break;
4602         case RTE_TUNNEL_FILTER_IMAC_TENID:
4603                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4604                 break;
4605         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4606                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4607                 break;
4608         case ETH_TUNNEL_FILTER_IMAC:
4609                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4610                 break;
4611         default:
4612                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4613                 return -EINVAL;
4614         }
4615
4616         return 0;
4617 }
4618
4619 static int
4620 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4621                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4622                         uint8_t add)
4623 {
4624         uint16_t ip_type;
4625         uint8_t tun_type = 0;
4626         int val, ret = 0;
4627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4628         struct i40e_vsi *vsi = pf->main_vsi;
4629         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4630         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4631
4632         cld_filter = rte_zmalloc("tunnel_filter",
4633                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4634                 0);
4635
4636         if (NULL == cld_filter) {
4637                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4638                 return -EINVAL;
4639         }
4640         pfilter = cld_filter;
4641
4642         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4643                         sizeof(struct ether_addr));
4644         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4645                         sizeof(struct ether_addr));
4646
4647         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4648         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4649                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4650                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4651                                 &tunnel_filter->ip_addr,
4652                                 sizeof(pfilter->ipaddr.v4.data));
4653         } else {
4654                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4655                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4656                                 &tunnel_filter->ip_addr,
4657                                 sizeof(pfilter->ipaddr.v6.data));
4658         }
4659
4660         /* check tunneled type */
4661         switch (tunnel_filter->tunnel_type) {
4662         case RTE_TUNNEL_TYPE_VXLAN:
4663                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4664                 break;
4665         default:
4666                 /* Other tunnel types is not supported. */
4667                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4668                 rte_free(cld_filter);
4669                 return -EINVAL;
4670         }
4671
4672         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4673                                                 &pfilter->flags);
4674         if (val < 0) {
4675                 rte_free(cld_filter);
4676                 return -EINVAL;
4677         }
4678
4679         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4680                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4681         pfilter->tenant_id = tunnel_filter->tenant_id;
4682         pfilter->queue_number = tunnel_filter->queue_id;
4683
4684         if (add)
4685                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4686         else
4687                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4688                                                 cld_filter, 1);
4689
4690         rte_free(cld_filter);
4691         return ret;
4692 }
4693
4694 static int
4695 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4696 {
4697         uint8_t i;
4698
4699         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4700                 if (pf->vxlan_ports[i] == port)
4701                         return i;
4702         }
4703
4704         return -1;
4705 }
4706
4707 static int
4708 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4709 {
4710         int  idx, ret;
4711         uint8_t filter_idx;
4712         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4713
4714         idx = i40e_get_vxlan_port_idx(pf, port);
4715
4716         /* Check if port already exists */
4717         if (idx >= 0) {
4718                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4719                 return -EINVAL;
4720         }
4721
4722         /* Now check if there is space to add the new port */
4723         idx = i40e_get_vxlan_port_idx(pf, 0);
4724         if (idx < 0) {
4725                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4726                         "not adding port %d", port);
4727                 return -ENOSPC;
4728         }
4729
4730         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4731                                         &filter_idx, NULL);
4732         if (ret < 0) {
4733                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4734                 return -1;
4735         }
4736
4737         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4738                          port,  filter_idx);
4739
4740         /* New port: add it and mark its index in the bitmap */
4741         pf->vxlan_ports[idx] = port;
4742         pf->vxlan_bitmap |= (1 << idx);
4743
4744         if (!(pf->flags & I40E_FLAG_VXLAN))
4745                 pf->flags |= I40E_FLAG_VXLAN;
4746
4747         return 0;
4748 }
4749
4750 static int
4751 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4752 {
4753         int idx;
4754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4755
4756         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4757                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4758                 return -EINVAL;
4759         }
4760
4761         idx = i40e_get_vxlan_port_idx(pf, port);
4762
4763         if (idx < 0) {
4764                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4765                 return -EINVAL;
4766         }
4767
4768         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4769                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4770                 return -1;
4771         }
4772
4773         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4774                         port, idx);
4775
4776         pf->vxlan_ports[idx] = 0;
4777         pf->vxlan_bitmap &= ~(1 << idx);
4778
4779         if (!pf->vxlan_bitmap)
4780                 pf->flags &= ~I40E_FLAG_VXLAN;
4781
4782         return 0;
4783 }
4784
4785 /* Add UDP tunneling port */
4786 static int
4787 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4788                         struct rte_eth_udp_tunnel *udp_tunnel)
4789 {
4790         int ret = 0;
4791         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4792
4793         if (udp_tunnel == NULL)
4794                 return -EINVAL;
4795
4796         switch (udp_tunnel->prot_type) {
4797         case RTE_TUNNEL_TYPE_VXLAN:
4798                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4799                 break;
4800
4801         case RTE_TUNNEL_TYPE_GENEVE:
4802         case RTE_TUNNEL_TYPE_TEREDO:
4803                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4804                 ret = -1;
4805                 break;
4806
4807         default:
4808                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4809                 ret = -1;
4810                 break;
4811         }
4812
4813         return ret;
4814 }
4815
4816 /* Remove UDP tunneling port */
4817 static int
4818 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4819                         struct rte_eth_udp_tunnel *udp_tunnel)
4820 {
4821         int ret = 0;
4822         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4823
4824         if (udp_tunnel == NULL)
4825                 return -EINVAL;
4826
4827         switch (udp_tunnel->prot_type) {
4828         case RTE_TUNNEL_TYPE_VXLAN:
4829                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4830                 break;
4831         case RTE_TUNNEL_TYPE_GENEVE:
4832         case RTE_TUNNEL_TYPE_TEREDO:
4833                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4834                 ret = -1;
4835                 break;
4836         default:
4837                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4838                 ret = -1;
4839                 break;
4840         }
4841
4842         return ret;
4843 }
4844
4845 /* Calculate the maximum number of contiguous PF queues that are configured */
4846 static int
4847 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
4848 {
4849         struct rte_eth_dev_data *data = pf->dev_data;
4850         int i, num;
4851         struct i40e_rx_queue *rxq;
4852
4853         num = 0;
4854         for (i = 0; i < pf->lan_nb_qps; i++) {
4855                 rxq = data->rx_queues[i];
4856                 if (rxq && rxq->q_set)
4857                         num++;
4858                 else
4859                         break;
4860         }
4861
4862         return num;
4863 }
4864
4865 /* Configure RSS */
4866 static int
4867 i40e_pf_config_rss(struct i40e_pf *pf)
4868 {
4869         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4870         struct rte_eth_rss_conf rss_conf;
4871         uint32_t i, lut = 0;
4872         uint16_t j, num;
4873
4874         /*
4875          * If both VMDQ and RSS enabled, not all of PF queues are configured.
4876          * It's necessary to calulate the actual PF queues that are configured.
4877          */
4878         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
4879                 num = i40e_pf_calc_configured_queues_num(pf);
4880                 num = i40e_align_floor(num);
4881         } else
4882                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
4883
4884         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
4885                         num);
4886
4887         if (num == 0) {
4888                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
4889                 return -ENOTSUP;
4890         }
4891
4892         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4893                 if (j == num)
4894                         j = 0;
4895                 lut = (lut << 8) | (j & ((0x1 <<
4896                         hw->func_caps.rss_table_entry_width) - 1));
4897                 if ((i & 3) == 3)
4898                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4899         }
4900
4901         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4902         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4903                 i40e_pf_disable_rss(pf);
4904                 return 0;
4905         }
4906         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4907                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4908                 /* Calculate the default hash key */
4909                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4910                         rss_key_default[i] = (uint32_t)rte_rand();
4911                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4912                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4913                                                         sizeof(uint32_t);
4914         }
4915
4916         return i40e_hw_rss_hash_set(hw, &rss_conf);
4917 }
4918
4919 static int
4920 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4921                         struct rte_eth_tunnel_filter_conf *filter)
4922 {
4923         if (pf == NULL || filter == NULL) {
4924                 PMD_DRV_LOG(ERR, "Invalid parameter");
4925                 return -EINVAL;
4926         }
4927
4928         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4929                 PMD_DRV_LOG(ERR, "Invalid queue ID");
4930                 return -EINVAL;
4931         }
4932
4933         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4934                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4935                 return -EINVAL;
4936         }
4937
4938         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4939                 (is_zero_ether_addr(filter->outer_mac))) {
4940                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4941                 return -EINVAL;
4942         }
4943
4944         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4945                 (is_zero_ether_addr(filter->inner_mac))) {
4946                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4947                 return -EINVAL;
4948         }
4949
4950         return 0;
4951 }
4952
4953 static int
4954 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4955                         void *arg)
4956 {
4957         struct rte_eth_tunnel_filter_conf *filter;
4958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4959         int ret = I40E_SUCCESS;
4960
4961         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4962
4963         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4964                 return I40E_ERR_PARAM;
4965
4966         switch (filter_op) {
4967         case RTE_ETH_FILTER_NOP:
4968                 if (!(pf->flags & I40E_FLAG_VXLAN))
4969                         ret = I40E_NOT_SUPPORTED;
4970         case RTE_ETH_FILTER_ADD:
4971                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4972                 break;
4973         case RTE_ETH_FILTER_DELETE:
4974                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4975                 break;
4976         default:
4977                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4978                 ret = I40E_ERR_PARAM;
4979                 break;
4980         }
4981
4982         return ret;
4983 }
4984
4985 static int
4986 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4987 {
4988         int ret = 0;
4989         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
4990
4991         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
4992                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
4993                 return -ENOTSUP;
4994         }
4995
4996         /* RSS setup */
4997         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
4998                 ret = i40e_pf_config_rss(pf);
4999         else
5000                 i40e_pf_disable_rss(pf);
5001
5002         return ret;
5003 }
5004
5005 static int
5006 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5007                      enum rte_filter_type filter_type,
5008                      enum rte_filter_op filter_op,
5009                      void *arg)
5010 {
5011         int ret = 0;
5012
5013         if (dev == NULL)
5014                 return -EINVAL;
5015
5016         switch (filter_type) {
5017         case RTE_ETH_FILTER_MACVLAN:
5018                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5019                 break;
5020         case RTE_ETH_FILTER_TUNNEL:
5021                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5022                 break;
5023         default:
5024                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5025                                                         filter_type);
5026                 ret = -EINVAL;
5027                 break;
5028         }
5029
5030         return ret;
5031 }