lib/librte_pmd_i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_dev.h>
  51 #include <rte_eth_ctrl.h>
  52
  53 #include "i40e_logs.h"
  54 #include "i40e/i40e_register_x710_int.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_adminq_cmd.h"
  57 #include "i40e/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 #define I40E_DEFAULT_RX_FREE_THRESH  32
  63 #define I40E_DEFAULT_RX_PTHRESH      8
  64 #define I40E_DEFAULT_RX_HTHRESH      8
  65 #define I40E_DEFAULT_RX_WTHRESH      0
  66
  67 #define I40E_DEFAULT_TX_FREE_THRESH  32
  68 #define I40E_DEFAULT_TX_PTHRESH      32
  69 #define I40E_DEFAULT_TX_HTHRESH      0
  70 #define I40E_DEFAULT_TX_WTHRESH      0
  71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
  72
  73 /* Maximun number of MAC addresses */
  74 #define I40E_NUM_MACADDR_MAX       64
  75 #define I40E_CLEAR_PXE_WAIT_MS     200
  76
  77 /* Maximun number of capability elements */
  78 #define I40E_MAX_CAP_ELE_NUM       128
  79
  80 /* Wait count and inteval */
  81 #define I40E_CHK_Q_ENA_COUNT       1000
  82 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  83
  84 /* Maximun number of VSI */
  85 #define I40E_MAX_NUM_VSIS          (384UL)
  86
  87 /* Bit shift and mask */
  88 #define I40E_16_BIT_SHIFT 16
  89 #define I40E_16_BIT_MASK  0xFFFF
  90 #define I40E_32_BIT_SHIFT 32
  91 #define I40E_32_BIT_MASK  0xFFFFFFFF
  92 #define I40E_48_BIT_SHIFT 48
  93 #define I40E_48_BIT_MASK  0xFFFFFFFFFFFFULL
  94
  95 /* Default queue interrupt throttling time in microseconds*/
  96 #define I40E_ITR_INDEX_DEFAULT          0
  97 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  98 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  99
 100 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
 101
 102 static int eth_i40e_dev_init(\
 103                         __attribute__((unused)) struct eth_driver *eth_drv,
 104                         struct rte_eth_dev *eth_dev);
 105 static int i40e_dev_configure(struct rte_eth_dev *dev);
 106 static int i40e_dev_start(struct rte_eth_dev *dev);
 107 static void i40e_dev_stop(struct rte_eth_dev *dev);
 108 static void i40e_dev_close(struct rte_eth_dev *dev);
 109 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 114 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 115 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 116                                struct rte_eth_stats *stats);
 117 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 118 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 119                                             uint16_t queue_id,
 120                                             uint8_t stat_idx,
 121                                             uint8_t is_rx);
 122 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 123                               struct rte_eth_dev_info *dev_info);
 124 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 125                                 uint16_t vlan_id,
 126                                 int on);
 127 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 128 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 130                                       uint16_t queue,
 131                                       int on);
 132 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 133 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 134 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 135 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 136                               struct rte_eth_fc_conf *fc_conf);
 137 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 138                                        struct rte_eth_pfc_conf *pfc_conf);
 139 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 140                           struct ether_addr *mac_addr,
 141                           uint32_t index,
 142                           uint32_t pool);
 143 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 144 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 145                                     struct rte_eth_rss_reta *reta_conf);
 146 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 147                                    struct rte_eth_rss_reta *reta_conf);
 148
 149 static int i40e_get_cap(struct i40e_hw *hw);
 150 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 151 static int i40e_pf_setup(struct i40e_pf *pf);
 152 static int i40e_vsi_init(struct i40e_vsi *vsi);
 153 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 154                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 155 static void i40e_stat_update_48(struct i40e_hw *hw,
 156                                uint32_t hireg,
 157                                uint32_t loreg,
 158                                bool offset_loaded,
 159                                uint64_t *offset,
 160                                uint64_t *stat);
 161 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 162 static void i40e_dev_interrupt_handler(
 163                 __rte_unused struct rte_intr_handle *handle, void *param);
 164 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 165                                 uint32_t base, uint32_t num);
 166 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 167 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 168                         uint32_t base);
 169 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 170                         uint16_t num);
 171 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 172 static int i40e_veb_release(struct i40e_veb *veb);
 173 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 174                                                 struct i40e_vsi *vsi);
 175 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 176 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 177 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 178                                              struct i40e_macvlan_filter *mv_f,
 179                                              int num,
 180                                              struct ether_addr *addr);
 181 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 182                                              struct i40e_macvlan_filter *mv_f,
 183                                              int num,
 184                                              uint16_t vlan);
 185 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 186 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 187                                     struct rte_eth_rss_conf *rss_conf);
 188 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 189                                       struct rte_eth_rss_conf *rss_conf);
 190 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 191                                 struct rte_eth_udp_tunnel *udp_tunnel);
 192 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 193                                 struct rte_eth_udp_tunnel *udp_tunnel);
 194 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 195                                 enum rte_filter_type filter_type,
 196                                 enum rte_filter_op filter_op,
 197                                 void *arg);
 198
 199 /* Default hash key buffer for RSS */
 200 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
 201
 202 static struct rte_pci_id pci_id_i40e_map[] = {
 203 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 204 #include "rte_pci_dev_ids.h"
 205 { .vendor_id = 0, /* sentinel */ },
 206 };
 207
 208 static struct eth_dev_ops i40e_eth_dev_ops = {
 209         .dev_configure                = i40e_dev_configure,
 210         .dev_start                    = i40e_dev_start,
 211         .dev_stop                     = i40e_dev_stop,
 212         .dev_close                    = i40e_dev_close,
 213         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 214         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 215         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 216         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 217         .dev_set_link_up              = i40e_dev_set_link_up,
 218         .dev_set_link_down            = i40e_dev_set_link_down,
 219         .link_update                  = i40e_dev_link_update,
 220         .stats_get                    = i40e_dev_stats_get,
 221         .stats_reset                  = i40e_dev_stats_reset,
 222         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 223         .dev_infos_get                = i40e_dev_info_get,
 224         .vlan_filter_set              = i40e_vlan_filter_set,
 225         .vlan_tpid_set                = i40e_vlan_tpid_set,
 226         .vlan_offload_set             = i40e_vlan_offload_set,
 227         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 228         .vlan_pvid_set                = i40e_vlan_pvid_set,
 229         .rx_queue_start               = i40e_dev_rx_queue_start,
 230         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 231         .tx_queue_start               = i40e_dev_tx_queue_start,
 232         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 233         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 234         .rx_queue_release             = i40e_dev_rx_queue_release,
 235         .rx_queue_count               = i40e_dev_rx_queue_count,
 236         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 237         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 238         .tx_queue_release             = i40e_dev_tx_queue_release,
 239         .dev_led_on                   = i40e_dev_led_on,
 240         .dev_led_off                  = i40e_dev_led_off,
 241         .flow_ctrl_set                = i40e_flow_ctrl_set,
 242         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 243         .mac_addr_add                 = i40e_macaddr_add,
 244         .mac_addr_remove              = i40e_macaddr_remove,
 245         .reta_update                  = i40e_dev_rss_reta_update,
 246         .reta_query                   = i40e_dev_rss_reta_query,
 247         .rss_hash_update              = i40e_dev_rss_hash_update,
 248         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 249         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 250         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 251         .filter_ctrl                  = i40e_dev_filter_ctrl,
 252 };
 253
 254 static struct eth_driver rte_i40e_pmd = {
 255         {
 256                 .name = "rte_i40e_pmd",
 257                 .id_table = pci_id_i40e_map,
 258                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 259         },
 260         .eth_dev_init = eth_i40e_dev_init,
 261         .dev_private_size = sizeof(struct i40e_adapter),
 262 };
 263
 264 static inline int
 265 i40e_prev_power_of_2(int n)
 266 {
 267        int p = n;
 268
 269        --p;
 270        p |= p >> 1;
 271        p |= p >> 2;
 272        p |= p >> 4;
 273        p |= p >> 8;
 274        p |= p >> 16;
 275        if (p == (n - 1))
 276                return n;
 277        p >>= 1;
 278
 279        return ++p;
 280 }
 281
 282 static inline int
 283 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 284                                      struct rte_eth_link *link)
 285 {
 286         struct rte_eth_link *dst = link;
 287         struct rte_eth_link *src = &(dev->data->dev_link);
 288
 289         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 290                                         *(uint64_t *)src) == 0)
 291                 return -1;
 292
 293         return 0;
 294 }
 295
 296 static inline int
 297 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 298                                       struct rte_eth_link *link)
 299 {
 300         struct rte_eth_link *dst = &(dev->data->dev_link);
 301         struct rte_eth_link *src = link;
 302
 303         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 304                                         *(uint64_t *)src) == 0)
 305                 return -1;
 306
 307         return 0;
 308 }
 309
 310 /*
 311  * Driver initialization routine.
 312  * Invoked once at EAL init time.
 313  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 314  */
 315 static int
 316 rte_i40e_pmd_init(const char *name __rte_unused,
 317                   const char *params __rte_unused)
 318 {
 319         PMD_INIT_FUNC_TRACE();
 320         rte_eth_driver_register(&rte_i40e_pmd);
 321
 322         return 0;
 323 }
 324
 325 static struct rte_driver rte_i40e_driver = {
 326         .type = PMD_PDEV,
 327         .init = rte_i40e_pmd_init,
 328 };
 329
 330 PMD_REGISTER_DRIVER(rte_i40e_driver);
 331
 332 static int
 333 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 334                   struct rte_eth_dev *dev)
 335 {
 336         struct rte_pci_device *pci_dev;
 337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339         struct i40e_vsi *vsi;
 340         int ret;
 341         uint32_t len;
 342         uint8_t aq_fail = 0;
 343
 344         PMD_INIT_FUNC_TRACE();
 345
 346         dev->dev_ops = &i40e_eth_dev_ops;
 347         dev->rx_pkt_burst = i40e_recv_pkts;
 348         dev->tx_pkt_burst = i40e_xmit_pkts;
 349
 350         /* for secondary processes, we don't initialise any further as primary
 351          * has already done this work. Only check we don't need a different
 352          * RX function */
 353         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 354                 if (dev->data->scattered_rx)
 355                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 356                 return 0;
 357         }
 358         pci_dev = dev->pci_dev;
 359         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 360         pf->adapter->eth_dev = dev;
 361         pf->dev_data = dev->data;
 362
 363         hw->back = I40E_PF_TO_ADAPTER(pf);
 364         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 365         if (!hw->hw_addr) {
 366                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 367                              "as address is NULL");
 368                 return -ENODEV;
 369         }
 370
 371         hw->vendor_id = pci_dev->id.vendor_id;
 372         hw->device_id = pci_dev->id.device_id;
 373         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 374         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 375         hw->bus.device = pci_dev->addr.devid;
 376         hw->bus.func = pci_dev->addr.function;
 377
 378         /* Make sure all is clean before doing PF reset */
 379         i40e_clear_hw(hw);
 380
 381         /* Reset here to make sure all is clean for each PF */
 382         ret = i40e_pf_reset(hw);
 383         if (ret) {
 384                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 385                 return ret;
 386         }
 387
 388         /* Initialize the shared code (base driver) */
 389         ret = i40e_init_shared_code(hw);
 390         if (ret) {
 391                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 392                 return ret;
 393         }
 394
 395         /* Initialize the parameters for adminq */
 396         i40e_init_adminq_parameter(hw);
 397         ret = i40e_init_adminq(hw);
 398         if (ret != I40E_SUCCESS) {
 399                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 400                 return -EIO;
 401         }
 402         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 403                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 404                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 405                      ((hw->nvm.version >> 12) & 0xf),
 406                      ((hw->nvm.version >> 4) & 0xff),
 407                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 408
 409         /* Disable LLDP */
 410         ret = i40e_aq_stop_lldp(hw, true, NULL);
 411         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 412                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 413
 414         /* Clear PXE mode */
 415         i40e_clear_pxe_mode(hw);
 416
 417         /* Get hw capabilities */
 418         ret = i40e_get_cap(hw);
 419         if (ret != I40E_SUCCESS) {
 420                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 421                 goto err_get_capabilities;
 422         }
 423
 424         /* Initialize parameters for PF */
 425         ret = i40e_pf_parameter_init(dev);
 426         if (ret != 0) {
 427                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 428                 goto err_parameter_init;
 429         }
 430
 431         /* Initialize the queue management */
 432         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 433         if (ret < 0) {
 434                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 435                 goto err_qp_pool_init;
 436         }
 437         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 438                                 hw->func_caps.num_msix_vectors - 1);
 439         if (ret < 0) {
 440                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 441                 goto err_msix_pool_init;
 442         }
 443
 444         /* Initialize lan hmc */
 445         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 446                                 hw->func_caps.num_rx_qp, 0, 0);
 447         if (ret != I40E_SUCCESS) {
 448                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 449                 goto err_init_lan_hmc;
 450         }
 451
 452         /* Configure lan hmc */
 453         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 454         if (ret != I40E_SUCCESS) {
 455                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 456                 goto err_configure_lan_hmc;
 457         }
 458
 459         /* Get and check the mac address */
 460         i40e_get_mac_addr(hw, hw->mac.addr);
 461         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 462                 PMD_INIT_LOG(ERR, "mac address is not valid");
 463                 ret = -EIO;
 464                 goto err_get_mac_addr;
 465         }
 466         /* Copy the permanent MAC address */
 467         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 468                         (struct ether_addr *) hw->mac.perm_addr);
 469
 470         /* Disable flow control */
 471         hw->fc.requested_mode = I40E_FC_NONE;
 472         i40e_set_fc(hw, &aq_fail, TRUE);
 473
 474         /* PF setup, which includes VSI setup */
 475         ret = i40e_pf_setup(pf);
 476         if (ret) {
 477                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 478                 goto err_setup_pf_switch;
 479         }
 480
 481         vsi = pf->main_vsi;
 482
 483         /* Disable double vlan by default */
 484         i40e_vsi_config_double_vlan(vsi, FALSE);
 485
 486         if (!vsi->max_macaddrs)
 487                 len = ETHER_ADDR_LEN;
 488         else
 489                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 490
 491         /* Should be after VSI initialized */
 492         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 493         if (!dev->data->mac_addrs) {
 494                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 495                                         "for storing mac address");
 496                 goto err_get_mac_addr;
 497         }
 498         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 499                                         &dev->data->mac_addrs[0]);
 500
 501         /* initialize pf host driver to setup SRIOV resource if applicable */
 502         i40e_pf_host_init(dev);
 503
 504         /* register callback func to eal lib */
 505         rte_intr_callback_register(&(pci_dev->intr_handle),
 506                 i40e_dev_interrupt_handler, (void *)dev);
 507
 508         /* configure and enable device interrupt */
 509         i40e_pf_config_irq0(hw);
 510         i40e_pf_enable_irq0(hw);
 511
 512         /* enable uio intr after callback register */
 513         rte_intr_enable(&(pci_dev->intr_handle));
 514
 515         return 0;
 516
 517 err_setup_pf_switch:
 518         rte_free(pf->main_vsi);
 519 err_get_mac_addr:
 520 err_configure_lan_hmc:
 521         (void)i40e_shutdown_lan_hmc(hw);
 522 err_init_lan_hmc:
 523         i40e_res_pool_destroy(&pf->msix_pool);
 524 err_msix_pool_init:
 525         i40e_res_pool_destroy(&pf->qp_pool);
 526 err_qp_pool_init:
 527 err_parameter_init:
 528 err_get_capabilities:
 529         (void)i40e_shutdown_adminq(hw);
 530
 531         return ret;
 532 }
 533
 534 static int
 535 i40e_dev_configure(struct rte_eth_dev *dev)
 536 {
 537         return i40e_dev_init_vlan(dev);
 538 }
 539
 540 void
 541 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 542 {
 543         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 544         uint16_t msix_vect = vsi->msix_intr;
 545         uint16_t i;
 546
 547         for (i = 0; i < vsi->nb_qps; i++) {
 548                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 549                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 550                 rte_wmb();
 551         }
 552
 553         if (vsi->type != I40E_VSI_SRIOV) {
 554                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 555                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 556                                 msix_vect - 1), 0);
 557         } else {
 558                 uint32_t reg;
 559                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 560                         vsi->user_param + (msix_vect - 1);
 561
 562                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 563         }
 564         I40E_WRITE_FLUSH(hw);
 565 }
 566
 567 static inline uint16_t
 568 i40e_calc_itr_interval(int16_t interval)
 569 {
 570         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 571                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 572
 573         /* Convert to hardware count, as writing each 1 represents 2 us */
 574         return (interval/2);
 575 }
 576
 577 void
 578 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 579 {
 580         uint32_t val;
 581         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 582         uint16_t msix_vect = vsi->msix_intr;
 583         uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 584         int i;
 585
 586         for (i = 0; i < vsi->nb_qps; i++)
 587                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 588
 589         /* Bind all RX queues to allocated MSIX interrupt */
 590         for (i = 0; i < vsi->nb_qps; i++) {
 591                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 592                         (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 593                         ((vsi->base_queue + i + 1) <<
 594                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 595                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 596                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 597
 598                 if (i == vsi->nb_qps - 1)
 599                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 600                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 601         }
 602
 603         /* Write first RX queue to Link list register as the head element */
 604         if (vsi->type != I40E_VSI_SRIOV) {
 605                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 606                         (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 607                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 608
 609                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 610                                 msix_vect - 1), interval);
 611
 612                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 613                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 614                                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 615         }
 616         else {
 617                 uint32_t reg;
 618                 /* num_msix_vectors_vf needs to minus irq0 */
 619                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 620                         vsi->user_param + (msix_vect - 1);
 621
 622                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
 623                         (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 624                         (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 625         }
 626
 627         I40E_WRITE_FLUSH(hw);
 628 }
 629
 630 static void
 631 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 632 {
 633         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 634         uint16_t interval = i40e_calc_itr_interval(\
 635                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 636
 637         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 638                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 639                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 640                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 641                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 642 }
 643
 644 static void
 645 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 646 {
 647         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 648
 649         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 650 }
 651
 652 static inline uint8_t
 653 i40e_parse_link_speed(uint16_t eth_link_speed)
 654 {
 655         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 656
 657         switch (eth_link_speed) {
 658         case ETH_LINK_SPEED_40G:
 659                 link_speed = I40E_LINK_SPEED_40GB;
 660                 break;
 661         case ETH_LINK_SPEED_20G:
 662                 link_speed = I40E_LINK_SPEED_20GB;
 663                 break;
 664         case ETH_LINK_SPEED_10G:
 665                 link_speed = I40E_LINK_SPEED_10GB;
 666                 break;
 667         case ETH_LINK_SPEED_1000:
 668                 link_speed = I40E_LINK_SPEED_1GB;
 669                 break;
 670         case ETH_LINK_SPEED_100:
 671                 link_speed = I40E_LINK_SPEED_100MB;
 672                 break;
 673         }
 674
 675         return link_speed;
 676 }
 677
 678 static int
 679 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 680 {
 681         enum i40e_status_code status;
 682         struct i40e_aq_get_phy_abilities_resp phy_ab;
 683         struct i40e_aq_set_phy_config phy_conf;
 684         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 685                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 686                         I40E_AQ_PHY_FLAG_LOW_POWER;
 687         const uint8_t advt = I40E_LINK_SPEED_40GB |
 688                         I40E_LINK_SPEED_10GB |
 689                         I40E_LINK_SPEED_1GB |
 690                         I40E_LINK_SPEED_100MB;
 691         int ret = -ENOTSUP;
 692
 693         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 694                                               NULL);
 695         if (status)
 696                 return ret;
 697
 698         memset(&phy_conf, 0, sizeof(phy_conf));
 699
 700         /* bits 0-2 use the values from get_phy_abilities_resp */
 701         abilities &= ~mask;
 702         abilities |= phy_ab.abilities & mask;
 703
 704         /* update ablities and speed */
 705         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 706                 phy_conf.link_speed = advt;
 707         else
 708                 phy_conf.link_speed = force_speed;
 709
 710         phy_conf.abilities = abilities;
 711
 712         /* use get_phy_abilities_resp value for the rest */
 713         phy_conf.phy_type = phy_ab.phy_type;
 714         phy_conf.eee_capability = phy_ab.eee_capability;
 715         phy_conf.eeer = phy_ab.eeer_val;
 716         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 717
 718         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 719                     phy_ab.abilities, phy_ab.link_speed);
 720         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 721                     phy_conf.abilities, phy_conf.link_speed);
 722
 723         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 724         if (status)
 725                 return ret;
 726
 727         return I40E_SUCCESS;
 728 }
 729
 730 static int
 731 i40e_apply_link_speed(struct rte_eth_dev *dev)
 732 {
 733         uint8_t speed;
 734         uint8_t abilities = 0;
 735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 736         struct rte_eth_conf *conf = &dev->data->dev_conf;
 737
 738         speed = i40e_parse_link_speed(conf->link_speed);
 739         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 740         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 741                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 742         else
 743                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 744
 745         return i40e_phy_conf_link(hw, abilities, speed);
 746 }
 747
 748 static int
 749 i40e_dev_start(struct rte_eth_dev *dev)
 750 {
 751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct i40e_vsi *vsi = pf->main_vsi;
 754         int ret;
 755
 756         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 757                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 758                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 759                              dev->data->dev_conf.link_duplex,
 760                              dev->data->port_id);
 761                 return -EINVAL;
 762         }
 763
 764         /* Initialize VSI */
 765         ret = i40e_vsi_init(vsi);
 766         if (ret != I40E_SUCCESS) {
 767                 PMD_DRV_LOG(ERR, "Failed to init VSI");
 768                 goto err_up;
 769         }
 770
 771         /* Map queues with MSIX interrupt */
 772         i40e_vsi_queues_bind_intr(vsi);
 773         i40e_vsi_enable_queues_intr(vsi);
 774
 775         /* Enable all queues which have been configured */
 776         ret = i40e_vsi_switch_queues(vsi, TRUE);
 777         if (ret != I40E_SUCCESS) {
 778                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 779                 goto err_up;
 780         }
 781
 782         /* Enable receiving broadcast packets */
 783         if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
 784                 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
 785                 if (ret != I40E_SUCCESS)
 786                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 787         }
 788
 789         /* Apply link configure */
 790         ret = i40e_apply_link_speed(dev);
 791         if (I40E_SUCCESS != ret) {
 792                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 793                 goto err_up;
 794         }
 795
 796         return I40E_SUCCESS;
 797
 798 err_up:
 799         i40e_vsi_switch_queues(vsi, FALSE);
 800
 801         return ret;
 802 }
 803
 804 static void
 805 i40e_dev_stop(struct rte_eth_dev *dev)
 806 {
 807         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 808         struct i40e_vsi *vsi = pf->main_vsi;
 809
 810         /* Disable all queues */
 811         i40e_vsi_switch_queues(vsi, FALSE);
 812
 813         /* Set link down */
 814         i40e_dev_set_link_down(dev);
 815
 816         /* un-map queues with interrupt registers */
 817         i40e_vsi_disable_queues_intr(vsi);
 818         i40e_vsi_queues_unbind_intr(vsi);
 819 }
 820
 821 static void
 822 i40e_dev_close(struct rte_eth_dev *dev)
 823 {
 824         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 826         uint32_t reg;
 827
 828         PMD_INIT_FUNC_TRACE();
 829
 830         i40e_dev_stop(dev);
 831
 832         /* Disable interrupt */
 833         i40e_pf_disable_irq0(hw);
 834         rte_intr_disable(&(dev->pci_dev->intr_handle));
 835
 836         /* shutdown and destroy the HMC */
 837         i40e_shutdown_lan_hmc(hw);
 838
 839         /* release all the existing VSIs and VEBs */
 840         i40e_vsi_release(pf->main_vsi);
 841
 842         /* shutdown the adminq */
 843         i40e_aq_queue_shutdown(hw, true);
 844         i40e_shutdown_adminq(hw);
 845
 846         i40e_res_pool_destroy(&pf->qp_pool);
 847         i40e_res_pool_destroy(&pf->msix_pool);
 848
 849         /* force a PF reset to clean anything leftover */
 850         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
 851         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
 852                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
 853         I40E_WRITE_FLUSH(hw);
 854 }
 855
 856 static void
 857 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
 858 {
 859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 861         struct i40e_vsi *vsi = pf->main_vsi;
 862         int status;
 863
 864         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 865                                                         true, NULL);
 866         if (status != I40E_SUCCESS)
 867                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
 868
 869         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 870                                                         TRUE, NULL);
 871         if (status != I40E_SUCCESS)
 872                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 873
 874 }
 875
 876 static void
 877 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
 878 {
 879         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 880         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 881         struct i40e_vsi *vsi = pf->main_vsi;
 882         int status;
 883
 884         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
 885                                                         false, NULL);
 886         if (status != I40E_SUCCESS)
 887                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
 888
 889         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
 890                                                         false, NULL);
 891         if (status != I40E_SUCCESS)
 892                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 893 }
 894
 895 static void
 896 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
 897 {
 898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 899         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 900         struct i40e_vsi *vsi = pf->main_vsi;
 901         int ret;
 902
 903         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
 904         if (ret != I40E_SUCCESS)
 905                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
 906 }
 907
 908 static void
 909 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
 910 {
 911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913         struct i40e_vsi *vsi = pf->main_vsi;
 914         int ret;
 915
 916         if (dev->data->promiscuous == 1)
 917                 return; /* must remain in all_multicast mode */
 918
 919         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
 920                                 vsi->seid, FALSE, NULL);
 921         if (ret != I40E_SUCCESS)
 922                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
 923 }
 924
 925 /*
 926  * Set device link up.
 927  */
 928 static int
 929 i40e_dev_set_link_up(struct rte_eth_dev *dev)
 930 {
 931         /* re-apply link speed setting */
 932         return i40e_apply_link_speed(dev);
 933 }
 934
 935 /*
 936  * Set device link down.
 937  */
 938 static int
 939 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
 940 {
 941         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
 942         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 944
 945         return i40e_phy_conf_link(hw, abilities, speed);
 946 }
 947
 948 int
 949 i40e_dev_link_update(struct rte_eth_dev *dev,
 950                      __rte_unused int wait_to_complete)
 951 {
 952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 953         struct i40e_link_status link_status;
 954         struct rte_eth_link link, old;
 955         int status;
 956
 957         memset(&link, 0, sizeof(link));
 958         memset(&old, 0, sizeof(old));
 959         memset(&link_status, 0, sizeof(link_status));
 960         rte_i40e_dev_atomic_read_link_status(dev, &old);
 961
 962         /* Get link status information from hardware */
 963         status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
 964         if (status != I40E_SUCCESS) {
 965                 link.link_speed = ETH_LINK_SPEED_100;
 966                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 967                 PMD_DRV_LOG(ERR, "Failed to get link info");
 968                 goto out;
 969         }
 970
 971         link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
 972
 973         if (!link.link_status)
 974                 goto out;
 975
 976         /* i40e uses full duplex only */
 977         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 978
 979         /* Parse the link status */
 980         switch (link_status.link_speed) {
 981         case I40E_LINK_SPEED_100MB:
 982                 link.link_speed = ETH_LINK_SPEED_100;
 983                 break;
 984         case I40E_LINK_SPEED_1GB:
 985                 link.link_speed = ETH_LINK_SPEED_1000;
 986                 break;
 987         case I40E_LINK_SPEED_10GB:
 988                 link.link_speed = ETH_LINK_SPEED_10G;
 989                 break;
 990         case I40E_LINK_SPEED_20GB:
 991                 link.link_speed = ETH_LINK_SPEED_20G;
 992                 break;
 993         case I40E_LINK_SPEED_40GB:
 994                 link.link_speed = ETH_LINK_SPEED_40G;
 995                 break;
 996         default:
 997                 link.link_speed = ETH_LINK_SPEED_100;
 998                 break;
 999         }
1000
1001 out:
1002         rte_i40e_dev_atomic_write_link_status(dev, &link);
1003         if (link.link_status == old.link_status)
1004                 return -1;
1005
1006         return 0;
1007 }
1008
1009 /* Get all the statistics of a VSI */
1010 void
1011 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1012 {
1013         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1014         struct i40e_eth_stats *nes = &vsi->eth_stats;
1015         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1016         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1017
1018         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1019                             vsi->offset_loaded, &oes->rx_bytes,
1020                             &nes->rx_bytes);
1021         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1022                             vsi->offset_loaded, &oes->rx_unicast,
1023                             &nes->rx_unicast);
1024         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1025                             vsi->offset_loaded, &oes->rx_multicast,
1026                             &nes->rx_multicast);
1027         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1028                             vsi->offset_loaded, &oes->rx_broadcast,
1029                             &nes->rx_broadcast);
1030         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1031                             &oes->rx_discards, &nes->rx_discards);
1032         /* GLV_REPC not supported */
1033         /* GLV_RMPC not supported */
1034         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1035                             &oes->rx_unknown_protocol,
1036                             &nes->rx_unknown_protocol);
1037         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1038                             vsi->offset_loaded, &oes->tx_bytes,
1039                             &nes->tx_bytes);
1040         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1041                             vsi->offset_loaded, &oes->tx_unicast,
1042                             &nes->tx_unicast);
1043         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1044                             vsi->offset_loaded, &oes->tx_multicast,
1045                             &nes->tx_multicast);
1046         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1047                             vsi->offset_loaded,  &oes->tx_broadcast,
1048                             &nes->tx_broadcast);
1049         /* GLV_TDPC not supported */
1050         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1051                             &oes->tx_errors, &nes->tx_errors);
1052         vsi->offset_loaded = true;
1053
1054         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1055                     vsi->vsi_id);
1056         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", nes->rx_bytes);
1057         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", nes->rx_unicast);
1058         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", nes->rx_multicast);
1059         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", nes->rx_broadcast);
1060         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", nes->rx_discards);
1061         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1062                     nes->rx_unknown_protocol);
1063         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", nes->tx_bytes);
1064         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", nes->tx_unicast);
1065         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", nes->tx_multicast);
1066         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", nes->tx_broadcast);
1067         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", nes->tx_discards);
1068         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", nes->tx_errors);
1069         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1070                     vsi->vsi_id);
1071 }
1072
1073 /* Get all statistics of a port */
1074 static void
1075 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1076 {
1077         uint32_t i;
1078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1080         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1081         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1082
1083         /* Get statistics of struct i40e_eth_stats */
1084         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1085                             I40E_GLPRT_GORCL(hw->port),
1086                             pf->offset_loaded, &os->eth.rx_bytes,
1087                             &ns->eth.rx_bytes);
1088         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1089                             I40E_GLPRT_UPRCL(hw->port),
1090                             pf->offset_loaded, &os->eth.rx_unicast,
1091                             &ns->eth.rx_unicast);
1092         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1093                             I40E_GLPRT_MPRCL(hw->port),
1094                             pf->offset_loaded, &os->eth.rx_multicast,
1095                             &ns->eth.rx_multicast);
1096         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1097                             I40E_GLPRT_BPRCL(hw->port),
1098                             pf->offset_loaded, &os->eth.rx_broadcast,
1099                             &ns->eth.rx_broadcast);
1100         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1101                             pf->offset_loaded, &os->eth.rx_discards,
1102                             &ns->eth.rx_discards);
1103         /* GLPRT_REPC not supported */
1104         /* GLPRT_RMPC not supported */
1105         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1106                             pf->offset_loaded,
1107                             &os->eth.rx_unknown_protocol,
1108                             &ns->eth.rx_unknown_protocol);
1109         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1110                             I40E_GLPRT_GOTCL(hw->port),
1111                             pf->offset_loaded, &os->eth.tx_bytes,
1112                             &ns->eth.tx_bytes);
1113         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1114                             I40E_GLPRT_UPTCL(hw->port),
1115                             pf->offset_loaded, &os->eth.tx_unicast,
1116                             &ns->eth.tx_unicast);
1117         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1118                             I40E_GLPRT_MPTCL(hw->port),
1119                             pf->offset_loaded, &os->eth.tx_multicast,
1120                             &ns->eth.tx_multicast);
1121         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1122                             I40E_GLPRT_BPTCL(hw->port),
1123                             pf->offset_loaded, &os->eth.tx_broadcast,
1124                             &ns->eth.tx_broadcast);
1125         i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1126                             pf->offset_loaded, &os->eth.tx_discards,
1127                             &ns->eth.tx_discards);
1128         /* GLPRT_TEPC not supported */
1129
1130         /* additional port specific stats */
1131         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1132                             pf->offset_loaded, &os->tx_dropped_link_down,
1133                             &ns->tx_dropped_link_down);
1134         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1135                             pf->offset_loaded, &os->crc_errors,
1136                             &ns->crc_errors);
1137         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1138                             pf->offset_loaded, &os->illegal_bytes,
1139                             &ns->illegal_bytes);
1140         /* GLPRT_ERRBC not supported */
1141         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1142                             pf->offset_loaded, &os->mac_local_faults,
1143                             &ns->mac_local_faults);
1144         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1145                             pf->offset_loaded, &os->mac_remote_faults,
1146                             &ns->mac_remote_faults);
1147         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1148                             pf->offset_loaded, &os->rx_length_errors,
1149                             &ns->rx_length_errors);
1150         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1151                             pf->offset_loaded, &os->link_xon_rx,
1152                             &ns->link_xon_rx);
1153         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1154                             pf->offset_loaded, &os->link_xoff_rx,
1155                             &ns->link_xoff_rx);
1156         for (i = 0; i < 8; i++) {
1157                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1158                                     pf->offset_loaded,
1159                                     &os->priority_xon_rx[i],
1160                                     &ns->priority_xon_rx[i]);
1161                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1162                                     pf->offset_loaded,
1163                                     &os->priority_xoff_rx[i],
1164                                     &ns->priority_xoff_rx[i]);
1165         }
1166         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1167                             pf->offset_loaded, &os->link_xon_tx,
1168                             &ns->link_xon_tx);
1169         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1170                             pf->offset_loaded, &os->link_xoff_tx,
1171                             &ns->link_xoff_tx);
1172         for (i = 0; i < 8; i++) {
1173                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1174                                     pf->offset_loaded,
1175                                     &os->priority_xon_tx[i],
1176                                     &ns->priority_xon_tx[i]);
1177                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1178                                     pf->offset_loaded,
1179                                     &os->priority_xoff_tx[i],
1180                                     &ns->priority_xoff_tx[i]);
1181                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1182                                     pf->offset_loaded,
1183                                     &os->priority_xon_2_xoff[i],
1184                                     &ns->priority_xon_2_xoff[i]);
1185         }
1186         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1187                             I40E_GLPRT_PRC64L(hw->port),
1188                             pf->offset_loaded, &os->rx_size_64,
1189                             &ns->rx_size_64);
1190         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1191                             I40E_GLPRT_PRC127L(hw->port),
1192                             pf->offset_loaded, &os->rx_size_127,
1193                             &ns->rx_size_127);
1194         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1195                             I40E_GLPRT_PRC255L(hw->port),
1196                             pf->offset_loaded, &os->rx_size_255,
1197                             &ns->rx_size_255);
1198         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1199                             I40E_GLPRT_PRC511L(hw->port),
1200                             pf->offset_loaded, &os->rx_size_511,
1201                             &ns->rx_size_511);
1202         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1203                             I40E_GLPRT_PRC1023L(hw->port),
1204                             pf->offset_loaded, &os->rx_size_1023,
1205                             &ns->rx_size_1023);
1206         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1207                             I40E_GLPRT_PRC1522L(hw->port),
1208                             pf->offset_loaded, &os->rx_size_1522,
1209                             &ns->rx_size_1522);
1210         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1211                             I40E_GLPRT_PRC9522L(hw->port),
1212                             pf->offset_loaded, &os->rx_size_big,
1213                             &ns->rx_size_big);
1214         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1215                             pf->offset_loaded, &os->rx_undersize,
1216                             &ns->rx_undersize);
1217         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1218                             pf->offset_loaded, &os->rx_fragments,
1219                             &ns->rx_fragments);
1220         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1221                             pf->offset_loaded, &os->rx_oversize,
1222                             &ns->rx_oversize);
1223         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1224                             pf->offset_loaded, &os->rx_jabber,
1225                             &ns->rx_jabber);
1226         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1227                             I40E_GLPRT_PTC64L(hw->port),
1228                             pf->offset_loaded, &os->tx_size_64,
1229                             &ns->tx_size_64);
1230         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1231                             I40E_GLPRT_PTC127L(hw->port),
1232                             pf->offset_loaded, &os->tx_size_127,
1233                             &ns->tx_size_127);
1234         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1235                             I40E_GLPRT_PTC255L(hw->port),
1236                             pf->offset_loaded, &os->tx_size_255,
1237                             &ns->tx_size_255);
1238         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1239                             I40E_GLPRT_PTC511L(hw->port),
1240                             pf->offset_loaded, &os->tx_size_511,
1241                             &ns->tx_size_511);
1242         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1243                             I40E_GLPRT_PTC1023L(hw->port),
1244                             pf->offset_loaded, &os->tx_size_1023,
1245                             &ns->tx_size_1023);
1246         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1247                             I40E_GLPRT_PTC1522L(hw->port),
1248                             pf->offset_loaded, &os->tx_size_1522,
1249                             &ns->tx_size_1522);
1250         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1251                             I40E_GLPRT_PTC9522L(hw->port),
1252                             pf->offset_loaded, &os->tx_size_big,
1253                             &ns->tx_size_big);
1254         /* GLPRT_MSPDC not supported */
1255         /* GLPRT_XEC not supported */
1256
1257         pf->offset_loaded = true;
1258
1259         if (pf->main_vsi)
1260                 i40e_update_vsi_stats(pf->main_vsi);
1261
1262         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1263                                                 ns->eth.rx_broadcast;
1264         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1265                                                 ns->eth.tx_broadcast;
1266         stats->ibytes   = ns->eth.rx_bytes;
1267         stats->obytes   = ns->eth.tx_bytes;
1268         stats->oerrors  = ns->eth.tx_errors;
1269         stats->imcasts  = ns->eth.rx_multicast;
1270
1271         /* Rx Errors */
1272         stats->ibadcrc  = ns->crc_errors;
1273         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1274                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1275         stats->imissed  = ns->eth.rx_discards;
1276         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1277
1278         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1279         PMD_DRV_LOG(DEBUG, "rx_bytes:            %lu", ns->eth.rx_bytes);
1280         PMD_DRV_LOG(DEBUG, "rx_unicast:          %lu", ns->eth.rx_unicast);
1281         PMD_DRV_LOG(DEBUG, "rx_multicast:        %lu", ns->eth.rx_multicast);
1282         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %lu", ns->eth.rx_broadcast);
1283         PMD_DRV_LOG(DEBUG, "rx_discards:         %lu", ns->eth.rx_discards);
1284         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %lu",
1285                     ns->eth.rx_unknown_protocol);
1286         PMD_DRV_LOG(DEBUG, "tx_bytes:            %lu", ns->eth.tx_bytes);
1287         PMD_DRV_LOG(DEBUG, "tx_unicast:          %lu", ns->eth.tx_unicast);
1288         PMD_DRV_LOG(DEBUG, "tx_multicast:        %lu", ns->eth.tx_multicast);
1289         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %lu", ns->eth.tx_broadcast);
1290         PMD_DRV_LOG(DEBUG, "tx_discards:         %lu", ns->eth.tx_discards);
1291         PMD_DRV_LOG(DEBUG, "tx_errors:           %lu", ns->eth.tx_errors);
1292
1293         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %lu",
1294                     ns->tx_dropped_link_down);
1295         PMD_DRV_LOG(DEBUG, "crc_errors:               %lu", ns->crc_errors);
1296         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %lu",
1297                     ns->illegal_bytes);
1298         PMD_DRV_LOG(DEBUG, "error_bytes:              %lu", ns->error_bytes);
1299         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %lu",
1300                     ns->mac_local_faults);
1301         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %lu",
1302                     ns->mac_remote_faults);
1303         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %lu",
1304                     ns->rx_length_errors);
1305         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %lu", ns->link_xon_rx);
1306         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %lu", ns->link_xoff_rx);
1307         for (i = 0; i < 8; i++) {
1308                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %lu",
1309                                 i, ns->priority_xon_rx[i]);
1310                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %lu",
1311                                 i, ns->priority_xoff_rx[i]);
1312         }
1313         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %lu", ns->link_xon_tx);
1314         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %lu", ns->link_xoff_tx);
1315         for (i = 0; i < 8; i++) {
1316                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %lu",
1317                                 i, ns->priority_xon_tx[i]);
1318                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %lu",
1319                                 i, ns->priority_xoff_tx[i]);
1320                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %lu",
1321                                 i, ns->priority_xon_2_xoff[i]);
1322         }
1323         PMD_DRV_LOG(DEBUG, "rx_size_64:               %lu", ns->rx_size_64);
1324         PMD_DRV_LOG(DEBUG, "rx_size_127:              %lu", ns->rx_size_127);
1325         PMD_DRV_LOG(DEBUG, "rx_size_255:              %lu", ns->rx_size_255);
1326         PMD_DRV_LOG(DEBUG, "rx_size_511:              %lu", ns->rx_size_511);
1327         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %lu", ns->rx_size_1023);
1328         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %lu", ns->rx_size_1522);
1329         PMD_DRV_LOG(DEBUG, "rx_size_big:              %lu", ns->rx_size_big);
1330         PMD_DRV_LOG(DEBUG, "rx_undersize:             %lu", ns->rx_undersize);
1331         PMD_DRV_LOG(DEBUG, "rx_fragments:             %lu", ns->rx_fragments);
1332         PMD_DRV_LOG(DEBUG, "rx_oversize:              %lu", ns->rx_oversize);
1333         PMD_DRV_LOG(DEBUG, "rx_jabber:                %lu", ns->rx_jabber);
1334         PMD_DRV_LOG(DEBUG, "tx_size_64:               %lu", ns->tx_size_64);
1335         PMD_DRV_LOG(DEBUG, "tx_size_127:              %lu", ns->tx_size_127);
1336         PMD_DRV_LOG(DEBUG, "tx_size_255:              %lu", ns->tx_size_255);
1337         PMD_DRV_LOG(DEBUG, "tx_size_511:              %lu", ns->tx_size_511);
1338         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %lu", ns->tx_size_1023);
1339         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %lu", ns->tx_size_1522);
1340         PMD_DRV_LOG(DEBUG, "tx_size_big:              %lu", ns->tx_size_big);
1341         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %lu",
1342                         ns->mac_short_packet_dropped);
1343         PMD_DRV_LOG(DEBUG, "checksum_error:           %lu",
1344                     ns->checksum_error);
1345         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1346 }
1347
1348 /* Reset the statistics */
1349 static void
1350 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1351 {
1352         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1353
1354         /* It results in reloading the start point of each counter */
1355         pf->offset_loaded = false;
1356 }
1357
1358 static int
1359 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1360                                  __rte_unused uint16_t queue_id,
1361                                  __rte_unused uint8_t stat_idx,
1362                                  __rte_unused uint8_t is_rx)
1363 {
1364         PMD_INIT_FUNC_TRACE();
1365
1366         return -ENOSYS;
1367 }
1368
1369 static void
1370 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1371 {
1372         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1373         struct i40e_vsi *vsi = pf->main_vsi;
1374
1375         dev_info->max_rx_queues = vsi->nb_qps;
1376         dev_info->max_tx_queues = vsi->nb_qps;
1377         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1378         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1379         dev_info->max_mac_addrs = vsi->max_macaddrs;
1380         dev_info->max_vfs = dev->pci_dev->max_vfs;
1381         dev_info->rx_offload_capa =
1382                 DEV_RX_OFFLOAD_VLAN_STRIP |
1383                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1384                 DEV_RX_OFFLOAD_UDP_CKSUM |
1385                 DEV_RX_OFFLOAD_TCP_CKSUM;
1386         dev_info->tx_offload_capa =
1387                 DEV_TX_OFFLOAD_VLAN_INSERT |
1388                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1389                 DEV_TX_OFFLOAD_UDP_CKSUM |
1390                 DEV_TX_OFFLOAD_TCP_CKSUM |
1391                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1392
1393         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1394                 .rx_thresh = {
1395                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1396                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1397                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1398                 },
1399                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1400                 .rx_drop_en = 0,
1401         };
1402
1403         dev_info->default_txconf = (struct rte_eth_txconf) {
1404                 .tx_thresh = {
1405                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1406                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1407                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1408                 },
1409                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1410                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1411                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1412         };
1413
1414 }
1415
1416 static int
1417 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1418 {
1419         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1420         struct i40e_vsi *vsi = pf->main_vsi;
1421         PMD_INIT_FUNC_TRACE();
1422
1423         if (on)
1424                 return i40e_vsi_add_vlan(vsi, vlan_id);
1425         else
1426                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1427 }
1428
1429 static void
1430 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1431                    __rte_unused uint16_t tpid)
1432 {
1433         PMD_INIT_FUNC_TRACE();
1434 }
1435
1436 static void
1437 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1438 {
1439         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440         struct i40e_vsi *vsi = pf->main_vsi;
1441
1442         if (mask & ETH_VLAN_STRIP_MASK) {
1443                 /* Enable or disable VLAN stripping */
1444                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1445                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1446                 else
1447                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1448         }
1449
1450         if (mask & ETH_VLAN_EXTEND_MASK) {
1451                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1452                         i40e_vsi_config_double_vlan(vsi, TRUE);
1453                 else
1454                         i40e_vsi_config_double_vlan(vsi, FALSE);
1455         }
1456 }
1457
1458 static void
1459 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1460                           __rte_unused uint16_t queue,
1461                           __rte_unused int on)
1462 {
1463         PMD_INIT_FUNC_TRACE();
1464 }
1465
1466 static int
1467 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1468 {
1469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1470         struct i40e_vsi *vsi = pf->main_vsi;
1471         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1472         struct i40e_vsi_vlan_pvid_info info;
1473
1474         memset(&info, 0, sizeof(info));
1475         info.on = on;
1476         if (info.on)
1477                 info.config.pvid = pvid;
1478         else {
1479                 info.config.reject.tagged =
1480                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1481                 info.config.reject.untagged =
1482                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1483         }
1484
1485         return i40e_vsi_vlan_pvid_set(vsi, &info);
1486 }
1487
1488 static int
1489 i40e_dev_led_on(struct rte_eth_dev *dev)
1490 {
1491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492         uint32_t mode = i40e_led_get(hw);
1493
1494         if (mode == 0)
1495                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1496
1497         return 0;
1498 }
1499
1500 static int
1501 i40e_dev_led_off(struct rte_eth_dev *dev)
1502 {
1503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504         uint32_t mode = i40e_led_get(hw);
1505
1506         if (mode != 0)
1507                 i40e_led_set(hw, 0, false);
1508
1509         return 0;
1510 }
1511
1512 static int
1513 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1514                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1515 {
1516         PMD_INIT_FUNC_TRACE();
1517
1518         return -ENOSYS;
1519 }
1520
1521 static int
1522 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1523                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1524 {
1525         PMD_INIT_FUNC_TRACE();
1526
1527         return -ENOSYS;
1528 }
1529
1530 /* Add a MAC address, and update filters */
1531 static void
1532 i40e_macaddr_add(struct rte_eth_dev *dev,
1533                  struct ether_addr *mac_addr,
1534                  __attribute__((unused)) uint32_t index,
1535                  __attribute__((unused)) uint32_t pool)
1536 {
1537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         struct i40e_vsi *vsi = pf->main_vsi;
1540         struct ether_addr old_mac;
1541         int ret;
1542
1543         if (!is_valid_assigned_ether_addr(mac_addr)) {
1544                 PMD_DRV_LOG(ERR, "Invalid ethernet address");
1545                 return;
1546         }
1547
1548         if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1549                 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address");
1550                 return;
1551         }
1552
1553         /* Write mac address */
1554         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1555                                         mac_addr->addr_bytes, NULL);
1556         if (ret != I40E_SUCCESS) {
1557                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1558                 return;
1559         }
1560
1561         (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1562         (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1563                         ETHER_ADDR_LEN);
1564
1565         ret = i40e_vsi_add_mac(vsi, mac_addr);
1566         if (ret != I40E_SUCCESS) {
1567                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1568                 return;
1569         }
1570
1571         ether_addr_copy(mac_addr, &pf->dev_addr);
1572         i40e_vsi_delete_mac(vsi, &old_mac);
1573 }
1574
1575 /* Remove a MAC address, and update filters */
1576 static void
1577 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1578 {
1579         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1580         struct i40e_vsi *vsi = pf->main_vsi;
1581         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1582         struct ether_addr *macaddr;
1583         int ret;
1584         struct i40e_hw *hw =
1585                 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586
1587         if (index >= vsi->max_macaddrs)
1588                 return;
1589
1590         macaddr = &(data->mac_addrs[index]);
1591         if (!is_valid_assigned_ether_addr(macaddr))
1592                 return;
1593
1594         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1595                                         hw->mac.perm_addr, NULL);
1596         if (ret != I40E_SUCCESS) {
1597                 PMD_DRV_LOG(ERR, "Failed to write mac address");
1598                 return;
1599         }
1600
1601         (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1602
1603         ret = i40e_vsi_delete_mac(vsi, macaddr);
1604         if (ret != I40E_SUCCESS)
1605                 return;
1606
1607         /* Clear device address as it has been removed */
1608         if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1609                 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1610 }
1611
1612 static int
1613 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1614                          struct rte_eth_rss_reta *reta_conf)
1615 {
1616         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         uint32_t lut, l;
1618         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1619
1620         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1621                 if (i < max)
1622                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1623                 else
1624                         mask = (uint8_t)((reta_conf->mask_hi >>
1625                                                 (i - max)) & 0xF);
1626
1627                 if (!mask)
1628                         continue;
1629
1630                 if (mask == 0xF)
1631                         l = 0;
1632                 else
1633                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1634
1635                 for (j = 0, lut = 0; j < 4; j++) {
1636                         if (mask & (0x1 << j))
1637                                 lut |= reta_conf->reta[i + j] << (8 * j);
1638                         else
1639                                 lut |= l & (0xFF << (8 * j));
1640                 }
1641                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1642         }
1643
1644         return 0;
1645 }
1646
1647 static int
1648 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1649                         struct rte_eth_rss_reta *reta_conf)
1650 {
1651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652         uint32_t lut;
1653         uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1654
1655         for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1656                 if (i < max)
1657                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1658                 else
1659                         mask = (uint8_t)((reta_conf->mask_hi >>
1660                                                 (i - max)) & 0xF);
1661
1662                 if (!mask)
1663                         continue;
1664
1665                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1666                 for (j = 0; j < 4; j++) {
1667                         if (mask & (0x1 << j))
1668                                 reta_conf->reta[i + j] =
1669                                         (uint8_t)((lut >> (8 * j)) & 0xFF);
1670                 }
1671         }
1672
1673         return 0;
1674 }
1675
1676 /**
1677  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1678  * @hw:   pointer to the HW structure
1679  * @mem:  pointer to mem struct to fill out
1680  * @size: size of memory requested
1681  * @alignment: what to align the allocation to
1682  **/
1683 enum i40e_status_code
1684 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1685                         struct i40e_dma_mem *mem,
1686                         u64 size,
1687                         u32 alignment)
1688 {
1689         static uint64_t id = 0;
1690         const struct rte_memzone *mz = NULL;
1691         char z_name[RTE_MEMZONE_NAMESIZE];
1692
1693         if (!mem)
1694                 return I40E_ERR_PARAM;
1695
1696         id++;
1697         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1698 #ifdef RTE_LIBRTE_XEN_DOM0
1699         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1700                                                         RTE_PGSIZE_2M);
1701 #else
1702         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1703 #endif
1704         if (!mz)
1705                 return I40E_ERR_NO_MEMORY;
1706
1707         mem->id = id;
1708         mem->size = size;
1709         mem->va = mz->addr;
1710 #ifdef RTE_LIBRTE_XEN_DOM0
1711         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1712 #else
1713         mem->pa = mz->phys_addr;
1714 #endif
1715
1716         return I40E_SUCCESS;
1717 }
1718
1719 /**
1720  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1721  * @hw:   pointer to the HW structure
1722  * @mem:  ptr to mem struct to free
1723  **/
1724 enum i40e_status_code
1725 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1726                     struct i40e_dma_mem *mem)
1727 {
1728         if (!mem || !mem->va)
1729                 return I40E_ERR_PARAM;
1730
1731         mem->va = NULL;
1732         mem->pa = (u64)0;
1733
1734         return I40E_SUCCESS;
1735 }
1736
1737 /**
1738  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1739  * @hw:   pointer to the HW structure
1740  * @mem:  pointer to mem struct to fill out
1741  * @size: size of memory requested
1742  **/
1743 enum i40e_status_code
1744 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1745                          struct i40e_virt_mem *mem,
1746                          u32 size)
1747 {
1748         if (!mem)
1749                 return I40E_ERR_PARAM;
1750
1751         mem->size = size;
1752         mem->va = rte_zmalloc("i40e", size, 0);
1753
1754         if (mem->va)
1755                 return I40E_SUCCESS;
1756         else
1757                 return I40E_ERR_NO_MEMORY;
1758 }
1759
1760 /**
1761  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1762  * @hw:   pointer to the HW structure
1763  * @mem:  pointer to mem struct to free
1764  **/
1765 enum i40e_status_code
1766 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1767                      struct i40e_virt_mem *mem)
1768 {
1769         if (!mem)
1770                 return I40E_ERR_PARAM;
1771
1772         rte_free(mem->va);
1773         mem->va = NULL;
1774
1775         return I40E_SUCCESS;
1776 }
1777
1778 void
1779 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1780 {
1781         rte_spinlock_init(&sp->spinlock);
1782 }
1783
1784 void
1785 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1786 {
1787         rte_spinlock_lock(&sp->spinlock);
1788 }
1789
1790 void
1791 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1792 {
1793         rte_spinlock_unlock(&sp->spinlock);
1794 }
1795
1796 void
1797 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1798 {
1799         return;
1800 }
1801
1802 /**
1803  * Get the hardware capabilities, which will be parsed
1804  * and saved into struct i40e_hw.
1805  */
1806 static int
1807 i40e_get_cap(struct i40e_hw *hw)
1808 {
1809         struct i40e_aqc_list_capabilities_element_resp *buf;
1810         uint16_t len, size = 0;
1811         int ret;
1812
1813         /* Calculate a huge enough buff for saving response data temporarily */
1814         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1815                                                 I40E_MAX_CAP_ELE_NUM;
1816         buf = rte_zmalloc("i40e", len, 0);
1817         if (!buf) {
1818                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1819                 return I40E_ERR_NO_MEMORY;
1820         }
1821
1822         /* Get, parse the capabilities and save it to hw */
1823         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1824                         i40e_aqc_opc_list_func_capabilities, NULL);
1825         if (ret != I40E_SUCCESS)
1826                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
1827
1828         /* Free the temporary buffer after being used */
1829         rte_free(buf);
1830
1831         return ret;
1832 }
1833
1834 static int
1835 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1836 {
1837         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1838         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1839         uint16_t sum_queues = 0, sum_vsis;
1840
1841         /* First check if FW support SRIOV */
1842         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1843                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
1844                 return -EINVAL;
1845         }
1846
1847         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1848         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1849         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
1850         /* Allocate queues for pf */
1851         if (hw->func_caps.rss) {
1852                 pf->flags |= I40E_FLAG_RSS;
1853                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1854                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1855                 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1856         } else
1857                 pf->lan_nb_qps = 1;
1858         sum_queues = pf->lan_nb_qps;
1859         /* Default VSI is not counted in */
1860         sum_vsis = 0;
1861         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
1862
1863         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1864                 pf->flags |= I40E_FLAG_SRIOV;
1865                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1866                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1867                         PMD_INIT_LOG(ERR, "Config VF number %u, "
1868                                      "max supported %u.",
1869                                      dev->pci_dev->max_vfs,
1870                                      hw->func_caps.num_vfs);
1871                         return -EINVAL;
1872                 }
1873                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1874                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1875                                      "max support %u queues.",
1876                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
1877                         return -EINVAL;
1878                 }
1879                 pf->vf_num = dev->pci_dev->max_vfs;
1880                 sum_queues += pf->vf_nb_qps * pf->vf_num;
1881                 sum_vsis   += pf->vf_num;
1882                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
1883                              pf->vf_num, pf->vf_nb_qps);
1884         } else
1885                 pf->vf_num = 0;
1886
1887         if (hw->func_caps.vmdq) {
1888                 pf->flags |= I40E_FLAG_VMDQ;
1889                 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1890                 sum_queues += pf->vmdq_nb_qps;
1891                 sum_vsis += 1;
1892                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
1893         }
1894
1895         if (hw->func_caps.fd) {
1896                 pf->flags |= I40E_FLAG_FDIR;
1897                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1898                 /**
1899                  * Each flow director consumes one VSI and one queue,
1900                  * but can't calculate out predictably here.
1901                  */
1902         }
1903
1904         if (sum_vsis > pf->max_num_vsi ||
1905                 sum_queues > hw->func_caps.num_rx_qp) {
1906                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
1907                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
1908                              pf->max_num_vsi, sum_vsis);
1909                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
1910                              hw->func_caps.num_rx_qp, sum_queues);
1911                 return -EINVAL;
1912         }
1913
1914         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
1915          * cause */
1916         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1917                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
1918                              sum_vsis, hw->func_caps.num_msix_vectors);
1919                 return -EINVAL;
1920         }
1921         return I40E_SUCCESS;
1922 }
1923
1924 static int
1925 i40e_pf_get_switch_config(struct i40e_pf *pf)
1926 {
1927         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1928         struct i40e_aqc_get_switch_config_resp *switch_config;
1929         struct i40e_aqc_switch_config_element_resp *element;
1930         uint16_t start_seid = 0, num_reported;
1931         int ret;
1932
1933         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1934                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1935         if (!switch_config) {
1936                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
1937                 return -ENOMEM;
1938         }
1939
1940         /* Get the switch configurations */
1941         ret = i40e_aq_get_switch_config(hw, switch_config,
1942                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1943         if (ret != I40E_SUCCESS) {
1944                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
1945                 goto fail;
1946         }
1947         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1948         if (num_reported != 1) { /* The number should be 1 */
1949                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
1950                 goto fail;
1951         }
1952
1953         /* Parse the switch configuration elements */
1954         element = &(switch_config->element[0]);
1955         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1956                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1957                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1958         } else
1959                 PMD_DRV_LOG(INFO, "Unknown element type");
1960
1961 fail:
1962         rte_free(switch_config);
1963
1964         return ret;
1965 }
1966
1967 static int
1968 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1969                         uint32_t num)
1970 {
1971         struct pool_entry *entry;
1972
1973         if (pool == NULL || num == 0)
1974                 return -EINVAL;
1975
1976         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1977         if (entry == NULL) {
1978                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
1979                 return -ENOMEM;
1980         }
1981
1982         /* queue heap initialize */
1983         pool->num_free = num;
1984         pool->num_alloc = 0;
1985         pool->base = base;
1986         LIST_INIT(&pool->alloc_list);
1987         LIST_INIT(&pool->free_list);
1988
1989         /* Initialize element  */
1990         entry->base = 0;
1991         entry->len = num;
1992
1993         LIST_INSERT_HEAD(&pool->free_list, entry, next);
1994         return 0;
1995 }
1996
1997 static void
1998 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1999 {
2000         struct pool_entry *entry;
2001
2002         if (pool == NULL)
2003                 return;
2004
2005         LIST_FOREACH(entry, &pool->alloc_list, next) {
2006                 LIST_REMOVE(entry, next);
2007                 rte_free(entry);
2008         }
2009
2010         LIST_FOREACH(entry, &pool->free_list, next) {
2011                 LIST_REMOVE(entry, next);
2012                 rte_free(entry);
2013         }
2014
2015         pool->num_free = 0;
2016         pool->num_alloc = 0;
2017         pool->base = 0;
2018         LIST_INIT(&pool->alloc_list);
2019         LIST_INIT(&pool->free_list);
2020 }
2021
2022 static int
2023 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2024                        uint32_t base)
2025 {
2026         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2027         uint32_t pool_offset;
2028         int insert;
2029
2030         if (pool == NULL) {
2031                 PMD_DRV_LOG(ERR, "Invalid parameter");
2032                 return -EINVAL;
2033         }
2034
2035         pool_offset = base - pool->base;
2036         /* Lookup in alloc list */
2037         LIST_FOREACH(entry, &pool->alloc_list, next) {
2038                 if (entry->base == pool_offset) {
2039                         valid_entry = entry;
2040                         LIST_REMOVE(entry, next);
2041                         break;
2042                 }
2043         }
2044
2045         /* Not find, return */
2046         if (valid_entry == NULL) {
2047                 PMD_DRV_LOG(ERR, "Failed to find entry");
2048                 return -EINVAL;
2049         }
2050
2051         /**
2052          * Found it, move it to free list  and try to merge.
2053          * In order to make merge easier, always sort it by qbase.
2054          * Find adjacent prev and last entries.
2055          */
2056         prev = next = NULL;
2057         LIST_FOREACH(entry, &pool->free_list, next) {
2058                 if (entry->base > valid_entry->base) {
2059                         next = entry;
2060                         break;
2061                 }
2062                 prev = entry;
2063         }
2064
2065         insert = 0;
2066         /* Try to merge with next one*/
2067         if (next != NULL) {
2068                 /* Merge with next one */
2069                 if (valid_entry->base + valid_entry->len == next->base) {
2070                         next->base = valid_entry->base;
2071                         next->len += valid_entry->len;
2072                         rte_free(valid_entry);
2073                         valid_entry = next;
2074                         insert = 1;
2075                 }
2076         }
2077
2078         if (prev != NULL) {
2079                 /* Merge with previous one */
2080                 if (prev->base + prev->len == valid_entry->base) {
2081                         prev->len += valid_entry->len;
2082                         /* If it merge with next one, remove next node */
2083                         if (insert == 1) {
2084                                 LIST_REMOVE(valid_entry, next);
2085                                 rte_free(valid_entry);
2086                         } else {
2087                                 rte_free(valid_entry);
2088                                 insert = 1;
2089                         }
2090                 }
2091         }
2092
2093         /* Not find any entry to merge, insert */
2094         if (insert == 0) {
2095                 if (prev != NULL)
2096                         LIST_INSERT_AFTER(prev, valid_entry, next);
2097                 else if (next != NULL)
2098                         LIST_INSERT_BEFORE(next, valid_entry, next);
2099                 else /* It's empty list, insert to head */
2100                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2101         }
2102
2103         pool->num_free += valid_entry->len;
2104         pool->num_alloc -= valid_entry->len;
2105
2106         return 0;
2107 }
2108
2109 static int
2110 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2111                        uint16_t num)
2112 {
2113         struct pool_entry *entry, *valid_entry;
2114
2115         if (pool == NULL || num == 0) {
2116                 PMD_DRV_LOG(ERR, "Invalid parameter");
2117                 return -EINVAL;
2118         }
2119
2120         if (pool->num_free < num) {
2121                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2122                             num, pool->num_free);
2123                 return -ENOMEM;
2124         }
2125
2126         valid_entry = NULL;
2127         /* Lookup  in free list and find most fit one */
2128         LIST_FOREACH(entry, &pool->free_list, next) {
2129                 if (entry->len >= num) {
2130                         /* Find best one */
2131                         if (entry->len == num) {
2132                                 valid_entry = entry;
2133                                 break;
2134                         }
2135                         if (valid_entry == NULL || valid_entry->len > entry->len)
2136                                 valid_entry = entry;
2137                 }
2138         }
2139
2140         /* Not find one to satisfy the request, return */
2141         if (valid_entry == NULL) {
2142                 PMD_DRV_LOG(ERR, "No valid entry found");
2143                 return -ENOMEM;
2144         }
2145         /**
2146          * The entry have equal queue number as requested,
2147          * remove it from alloc_list.
2148          */
2149         if (valid_entry->len == num) {
2150                 LIST_REMOVE(valid_entry, next);
2151         } else {
2152                 /**
2153                  * The entry have more numbers than requested,
2154                  * create a new entry for alloc_list and minus its
2155                  * queue base and number in free_list.
2156                  */
2157                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2158                 if (entry == NULL) {
2159                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2160                                     "resource pool");
2161                         return -ENOMEM;
2162                 }
2163                 entry->base = valid_entry->base;
2164                 entry->len = num;
2165                 valid_entry->base += num;
2166                 valid_entry->len -= num;
2167                 valid_entry = entry;
2168         }
2169
2170         /* Insert it into alloc list, not sorted */
2171         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2172
2173         pool->num_free -= valid_entry->len;
2174         pool->num_alloc += valid_entry->len;
2175
2176         return (valid_entry->base + pool->base);
2177 }
2178
2179 /**
2180  * bitmap_is_subset - Check whether src2 is subset of src1
2181  **/
2182 static inline int
2183 bitmap_is_subset(uint8_t src1, uint8_t src2)
2184 {
2185         return !((src1 ^ src2) & src2);
2186 }
2187
2188 static int
2189 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2190 {
2191         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2192
2193         /* If DCB is not supported, only default TC is supported */
2194         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2195                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2196                 return -EINVAL;
2197         }
2198
2199         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2200                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2201                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2202                             enabled_tcmap);
2203                 return -EINVAL;
2204         }
2205         return I40E_SUCCESS;
2206 }
2207
2208 int
2209 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2210                                 struct i40e_vsi_vlan_pvid_info *info)
2211 {
2212         struct i40e_hw *hw;
2213         struct i40e_vsi_context ctxt;
2214         uint8_t vlan_flags = 0;
2215         int ret;
2216
2217         if (vsi == NULL || info == NULL) {
2218                 PMD_DRV_LOG(ERR, "invalid parameters");
2219                 return I40E_ERR_PARAM;
2220         }
2221
2222         if (info->on) {
2223                 vsi->info.pvid = info->config.pvid;
2224                 /**
2225                  * If insert pvid is enabled, only tagged pkts are
2226                  * allowed to be sent out.
2227                  */
2228                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2229                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2230         } else {
2231                 vsi->info.pvid = 0;
2232                 if (info->config.reject.tagged == 0)
2233                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2234
2235                 if (info->config.reject.untagged == 0)
2236                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2237         }
2238         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2239                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2240         vsi->info.port_vlan_flags |= vlan_flags;
2241         vsi->info.valid_sections =
2242                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2243         memset(&ctxt, 0, sizeof(ctxt));
2244         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2245         ctxt.seid = vsi->seid;
2246
2247         hw = I40E_VSI_TO_HW(vsi);
2248         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2249         if (ret != I40E_SUCCESS)
2250                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2251
2252         return ret;
2253 }
2254
2255 static int
2256 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2257 {
2258         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2259         int i, ret;
2260         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2261
2262         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2263         if (ret != I40E_SUCCESS)
2264                 return ret;
2265
2266         if (!vsi->seid) {
2267                 PMD_DRV_LOG(ERR, "seid not valid");
2268                 return -EINVAL;
2269         }
2270
2271         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2272         tc_bw_data.tc_valid_bits = enabled_tcmap;
2273         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2274                 tc_bw_data.tc_bw_credits[i] =
2275                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2276
2277         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2278         if (ret != I40E_SUCCESS) {
2279                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2280                 return ret;
2281         }
2282
2283         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2284                                         sizeof(vsi->info.qs_handle));
2285         return I40E_SUCCESS;
2286 }
2287
2288 static int
2289 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2290                                  struct i40e_aqc_vsi_properties_data *info,
2291                                  uint8_t enabled_tcmap)
2292 {
2293         int ret, total_tc = 0, i;
2294         uint16_t qpnum_per_tc, bsf, qp_idx;
2295
2296         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2297         if (ret != I40E_SUCCESS)
2298                 return ret;
2299
2300         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2301                 if (enabled_tcmap & (1 << i))
2302                         total_tc++;
2303         vsi->enabled_tc = enabled_tcmap;
2304
2305         /* Number of queues per enabled TC */
2306         qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2307         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2308         bsf = rte_bsf32(qpnum_per_tc);
2309
2310         /* Adjust the queue number to actual queues that can be applied */
2311         vsi->nb_qps = qpnum_per_tc * total_tc;
2312
2313         /**
2314          * Configure TC and queue mapping parameters, for enabled TC,
2315          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2316          * default queue will serve it.
2317          */
2318         qp_idx = 0;
2319         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2320                 if (vsi->enabled_tc & (1 << i)) {
2321                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2322                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2323                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2324                         qp_idx += qpnum_per_tc;
2325                 } else
2326                         info->tc_mapping[i] = 0;
2327         }
2328
2329         /* Associate queue number with VSI */
2330         if (vsi->type == I40E_VSI_SRIOV) {
2331                 info->mapping_flags |=
2332                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2333                 for (i = 0; i < vsi->nb_qps; i++)
2334                         info->queue_mapping[i] =
2335                                 rte_cpu_to_le_16(vsi->base_queue + i);
2336         } else {
2337                 info->mapping_flags |=
2338                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2339                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2340         }
2341         info->valid_sections =
2342                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2343
2344         return I40E_SUCCESS;
2345 }
2346
2347 static int
2348 i40e_veb_release(struct i40e_veb *veb)
2349 {
2350         struct i40e_vsi *vsi;
2351         struct i40e_hw *hw;
2352
2353         if (veb == NULL || veb->associate_vsi == NULL)
2354                 return -EINVAL;
2355
2356         if (!TAILQ_EMPTY(&veb->head)) {
2357                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2358                 return -EACCES;
2359         }
2360
2361         vsi = veb->associate_vsi;
2362         hw = I40E_VSI_TO_HW(vsi);
2363
2364         vsi->uplink_seid = veb->uplink_seid;
2365         i40e_aq_delete_element(hw, veb->seid, NULL);
2366         rte_free(veb);
2367         vsi->veb = NULL;
2368         return I40E_SUCCESS;
2369 }
2370
2371 /* Setup a veb */
2372 static struct i40e_veb *
2373 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2374 {
2375         struct i40e_veb *veb;
2376         int ret;
2377         struct i40e_hw *hw;
2378
2379         if (NULL == pf || vsi == NULL) {
2380                 PMD_DRV_LOG(ERR, "veb setup failed, "
2381                             "associated VSI shouldn't null");
2382                 return NULL;
2383         }
2384         hw = I40E_PF_TO_HW(pf);
2385
2386         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2387         if (!veb) {
2388                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2389                 goto fail;
2390         }
2391
2392         veb->associate_vsi = vsi;
2393         TAILQ_INIT(&veb->head);
2394         veb->uplink_seid = vsi->uplink_seid;
2395
2396         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2397                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2398
2399         if (ret != I40E_SUCCESS) {
2400                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2401                             hw->aq.asq_last_status);
2402                 goto fail;
2403         }
2404
2405         /* get statistics index */
2406         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2407                                 &veb->stats_idx, NULL, NULL, NULL);
2408         if (ret != I40E_SUCCESS) {
2409                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2410                             hw->aq.asq_last_status);
2411                 goto fail;
2412         }
2413
2414         /* Get VEB bandwidth, to be implemented */
2415         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2416         vsi->uplink_seid = veb->seid;
2417
2418         return veb;
2419 fail:
2420         rte_free(veb);
2421         return NULL;
2422 }
2423
2424 int
2425 i40e_vsi_release(struct i40e_vsi *vsi)
2426 {
2427         struct i40e_pf *pf;
2428         struct i40e_hw *hw;
2429         struct i40e_vsi_list *vsi_list;
2430         int ret;
2431         struct i40e_mac_filter *f;
2432
2433         if (!vsi)
2434                 return I40E_SUCCESS;
2435
2436         pf = I40E_VSI_TO_PF(vsi);
2437         hw = I40E_VSI_TO_HW(vsi);
2438
2439         /* VSI has child to attach, release child first */
2440         if (vsi->veb) {
2441                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2442                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2443                                 return -1;
2444                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2445                 }
2446                 i40e_veb_release(vsi->veb);
2447         }
2448
2449         /* Remove all macvlan filters of the VSI */
2450         i40e_vsi_remove_all_macvlan_filter(vsi);
2451         TAILQ_FOREACH(f, &vsi->mac_list, next)
2452                 rte_free(f);
2453
2454         if (vsi->type != I40E_VSI_MAIN) {
2455                 /* Remove vsi from parent's sibling list */
2456                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2457                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2458                         return I40E_ERR_PARAM;
2459                 }
2460                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2461                                 &vsi->sib_vsi_list, list);
2462
2463                 /* Remove all switch element of the VSI */
2464                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2465                 if (ret != I40E_SUCCESS)
2466                         PMD_DRV_LOG(ERR, "Failed to delete element");
2467         }
2468         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2469
2470         if (vsi->type != I40E_VSI_SRIOV)
2471                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2472         rte_free(vsi);
2473
2474         return I40E_SUCCESS;
2475 }
2476
2477 static int
2478 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2479 {
2480         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2481         struct i40e_aqc_remove_macvlan_element_data def_filter;
2482         int ret;
2483
2484         if (vsi->type != I40E_VSI_MAIN)
2485                 return I40E_ERR_CONFIG;
2486         memset(&def_filter, 0, sizeof(def_filter));
2487         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2488                                         ETH_ADDR_LEN);
2489         def_filter.vlan_tag = 0;
2490         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2491                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2492         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2493         if (ret != I40E_SUCCESS) {
2494                 struct i40e_mac_filter *f;
2495
2496                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2497                             "macvlan filter");
2498                 /* It needs to add the permanent mac into mac list */
2499                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2500                 if (f == NULL) {
2501                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2502                         return I40E_ERR_NO_MEMORY;
2503                 }
2504                 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2505                                 ETH_ADDR_LEN);
2506                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2507                 vsi->mac_num++;
2508
2509                 return ret;
2510         }
2511
2512         return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2513 }
2514
2515 static int
2516 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2517 {
2518         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2519         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2520         struct i40e_hw *hw = &vsi->adapter->hw;
2521         i40e_status ret;
2522         int i;
2523
2524         memset(&bw_config, 0, sizeof(bw_config));
2525         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2526         if (ret != I40E_SUCCESS) {
2527                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2528                             hw->aq.asq_last_status);
2529                 return ret;
2530         }
2531
2532         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2533         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2534                                         &ets_sla_config, NULL);
2535         if (ret != I40E_SUCCESS) {
2536                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2537                             "configuration %u", hw->aq.asq_last_status);
2538                 return ret;
2539         }
2540
2541         /* Not store the info yet, just print out */
2542         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2543         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2544         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2545                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2546                             ets_sla_config.share_credits[i]);
2547                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2548                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2549                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2550                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2551                             (i * 4));
2552         }
2553
2554         return 0;
2555 }
2556
2557 /* Setup a VSI */
2558 struct i40e_vsi *
2559 i40e_vsi_setup(struct i40e_pf *pf,
2560                enum i40e_vsi_type type,
2561                struct i40e_vsi *uplink_vsi,
2562                uint16_t user_param)
2563 {
2564         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2565         struct i40e_vsi *vsi;
2566         int ret;
2567         struct i40e_vsi_context ctxt;
2568         struct ether_addr broadcast =
2569                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2570
2571         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2572                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2573                             "VSI link shouldn't be NULL");
2574                 return NULL;
2575         }
2576
2577         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2578                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2579                             "uplink VSI should be NULL");
2580                 return NULL;
2581         }
2582
2583         /* If uplink vsi didn't setup VEB, create one first */
2584         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2585                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2586
2587                 if (NULL == uplink_vsi->veb) {
2588                         PMD_DRV_LOG(ERR, "VEB setup failed");
2589                         return NULL;
2590                 }
2591         }
2592
2593         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2594         if (!vsi) {
2595                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2596                 return NULL;
2597         }
2598         TAILQ_INIT(&vsi->mac_list);
2599         vsi->type = type;
2600         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2601         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2602         vsi->parent_vsi = uplink_vsi;
2603         vsi->user_param = user_param;
2604         /* Allocate queues */
2605         switch (vsi->type) {
2606         case I40E_VSI_MAIN  :
2607                 vsi->nb_qps = pf->lan_nb_qps;
2608                 break;
2609         case I40E_VSI_SRIOV :
2610                 vsi->nb_qps = pf->vf_nb_qps;
2611                 break;
2612         default:
2613                 goto fail_mem;
2614         }
2615         ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2616         if (ret < 0) {
2617                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2618                                 vsi->seid, ret);
2619                 goto fail_mem;
2620         }
2621         vsi->base_queue = ret;
2622
2623         /* VF has MSIX interrupt in VF range, don't allocate here */
2624         if (type != I40E_VSI_SRIOV) {
2625                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2626                 if (ret < 0) {
2627                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2628                         goto fail_queue_alloc;
2629                 }
2630                 vsi->msix_intr = ret;
2631         } else
2632                 vsi->msix_intr = 0;
2633         /* Add VSI */
2634         if (type == I40E_VSI_MAIN) {
2635                 /* For main VSI, no need to add since it's default one */
2636                 vsi->uplink_seid = pf->mac_seid;
2637                 vsi->seid = pf->main_vsi_seid;
2638                 /* Bind queues with specific MSIX interrupt */
2639                 /**
2640                  * Needs 2 interrupt at least, one for misc cause which will
2641                  * enabled from OS side, Another for queues binding the
2642                  * interrupt from device side only.
2643                  */
2644
2645                 /* Get default VSI parameters from hardware */
2646                 memset(&ctxt, 0, sizeof(ctxt));
2647                 ctxt.seid = vsi->seid;
2648                 ctxt.pf_num = hw->pf_id;
2649                 ctxt.uplink_seid = vsi->uplink_seid;
2650                 ctxt.vf_num = 0;
2651                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2652                 if (ret != I40E_SUCCESS) {
2653                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
2654                         goto fail_msix_alloc;
2655                 }
2656                 (void)rte_memcpy(&vsi->info, &ctxt.info,
2657                         sizeof(struct i40e_aqc_vsi_properties_data));
2658                 vsi->vsi_id = ctxt.vsi_number;
2659                 vsi->info.valid_sections = 0;
2660
2661                 /* Configure tc, enabled TC0 only */
2662                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2663                         I40E_SUCCESS) {
2664                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
2665                         goto fail_msix_alloc;
2666                 }
2667
2668                 /* TC, queue mapping */
2669                 memset(&ctxt, 0, sizeof(ctxt));
2670                 vsi->info.valid_sections |=
2671                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2672                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2673                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2674                 (void)rte_memcpy(&ctxt.info, &vsi->info,
2675                         sizeof(struct i40e_aqc_vsi_properties_data));
2676                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2677                                                 I40E_DEFAULT_TCMAP);
2678                 if (ret != I40E_SUCCESS) {
2679                         PMD_DRV_LOG(ERR, "Failed to configure "
2680                                     "TC queue mapping");
2681                         goto fail_msix_alloc;
2682                 }
2683                 ctxt.seid = vsi->seid;
2684                 ctxt.pf_num = hw->pf_id;
2685                 ctxt.uplink_seid = vsi->uplink_seid;
2686                 ctxt.vf_num = 0;
2687
2688                 /* Update VSI parameters */
2689                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2690                 if (ret != I40E_SUCCESS) {
2691                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
2692                         goto fail_msix_alloc;
2693                 }
2694
2695                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2696                                                 sizeof(vsi->info.tc_mapping));
2697                 (void)rte_memcpy(&vsi->info.queue_mapping,
2698                                 &ctxt.info.queue_mapping,
2699                         sizeof(vsi->info.queue_mapping));
2700                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2701                 vsi->info.valid_sections = 0;
2702
2703                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2704                                 ETH_ADDR_LEN);
2705
2706                 /**
2707                  * Updating default filter settings are necessary to prevent
2708                  * reception of tagged packets.
2709                  * Some old firmware configurations load a default macvlan
2710                  * filter which accepts both tagged and untagged packets.
2711                  * The updating is to use a normal filter instead if needed.
2712                  * For NVM 4.2.2 or after, the updating is not needed anymore.
2713                  * The firmware with correct configurations load the default
2714                  * macvlan filter which is expected and cannot be removed.
2715                  */
2716                 i40e_update_default_filter_setting(vsi);
2717         } else if (type == I40E_VSI_SRIOV) {
2718                 memset(&ctxt, 0, sizeof(ctxt));
2719                 /**
2720                  * For other VSI, the uplink_seid equals to uplink VSI's
2721                  * uplink_seid since they share same VEB
2722                  */
2723                 vsi->uplink_seid = uplink_vsi->uplink_seid;
2724                 ctxt.pf_num = hw->pf_id;
2725                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2726                 ctxt.uplink_seid = vsi->uplink_seid;
2727                 ctxt.connection_type = 0x1;
2728                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2729
2730                 /* Configure switch ID */
2731                 ctxt.info.valid_sections |=
2732                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2733                 ctxt.info.switch_id =
2734                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2735                 /* Configure port/vlan */
2736                 ctxt.info.valid_sections |=
2737                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2738                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2739                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2740                                                 I40E_DEFAULT_TCMAP);
2741                 if (ret != I40E_SUCCESS) {
2742                         PMD_DRV_LOG(ERR, "Failed to configure "
2743                                     "TC queue mapping");
2744                         goto fail_msix_alloc;
2745                 }
2746                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2747                 ctxt.info.valid_sections |=
2748                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2749                 /**
2750                  * Since VSI is not created yet, only configure parameter,
2751                  * will add vsi below.
2752                  */
2753         }
2754         else {
2755                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
2756                 goto fail_msix_alloc;
2757         }
2758
2759         if (vsi->type != I40E_VSI_MAIN) {
2760                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2761                 if (ret) {
2762                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
2763                                     hw->aq.asq_last_status);
2764                         goto fail_msix_alloc;
2765                 }
2766                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2767                 vsi->info.valid_sections = 0;
2768                 vsi->seid = ctxt.seid;
2769                 vsi->vsi_id = ctxt.vsi_number;
2770                 vsi->sib_vsi_list.vsi = vsi;
2771                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2772                                 &vsi->sib_vsi_list, list);
2773         }
2774
2775         /* MAC/VLAN configuration */
2776         ret = i40e_vsi_add_mac(vsi, &broadcast);
2777         if (ret != I40E_SUCCESS) {
2778                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2779                 goto fail_msix_alloc;
2780         }
2781
2782         /* Get VSI BW information */
2783         i40e_vsi_dump_bw_config(vsi);
2784         return vsi;
2785 fail_msix_alloc:
2786         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2787 fail_queue_alloc:
2788         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2789 fail_mem:
2790         rte_free(vsi);
2791         return NULL;
2792 }
2793
2794 /* Configure vlan stripping on or off */
2795 int
2796 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2797 {
2798         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2799         struct i40e_vsi_context ctxt;
2800         uint8_t vlan_flags;
2801         int ret = I40E_SUCCESS;
2802
2803         /* Check if it has been already on or off */
2804         if (vsi->info.valid_sections &
2805                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2806                 if (on) {
2807                         if ((vsi->info.port_vlan_flags &
2808                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2809                                 return 0; /* already on */
2810                 } else {
2811                         if ((vsi->info.port_vlan_flags &
2812                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2813                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2814                                 return 0; /* already off */
2815                 }
2816         }
2817
2818         if (on)
2819                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2820         else
2821                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2822         vsi->info.valid_sections =
2823                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2824         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2825         vsi->info.port_vlan_flags |= vlan_flags;
2826         ctxt.seid = vsi->seid;
2827         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2828         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2829         if (ret)
2830                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2831                             on ? "enable" : "disable");
2832
2833         return ret;
2834 }
2835
2836 static int
2837 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2838 {
2839         struct rte_eth_dev_data *data = dev->data;
2840         int ret;
2841
2842         /* Apply vlan offload setting */
2843         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2844
2845         /* Apply double-vlan setting, not implemented yet */
2846
2847         /* Apply pvid setting */
2848         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2849                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
2850         if (ret)
2851                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
2852
2853         return ret;
2854 }
2855
2856 static int
2857 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2858 {
2859         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2860
2861         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2862 }
2863
2864 static int
2865 i40e_update_flow_control(struct i40e_hw *hw)
2866 {
2867 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2868         struct i40e_link_status link_status;
2869         uint32_t rxfc = 0, txfc = 0, reg;
2870         uint8_t an_info;
2871         int ret;
2872
2873         memset(&link_status, 0, sizeof(link_status));
2874         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2875         if (ret != I40E_SUCCESS) {
2876                 PMD_DRV_LOG(ERR, "Failed to get link status information");
2877                 goto write_reg; /* Disable flow control */
2878         }
2879
2880         an_info = hw->phy.link_info.an_info;
2881         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2882                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
2883                 ret = I40E_ERR_NOT_READY;
2884                 goto write_reg; /* Disable flow control */
2885         }
2886         /**
2887          * If link auto negotiation is enabled, flow control needs to
2888          * be configured according to it
2889          */
2890         switch (an_info & I40E_LINK_PAUSE_RXTX) {
2891         case I40E_LINK_PAUSE_RXTX:
2892                 rxfc = 1;
2893                 txfc = 1;
2894                 hw->fc.current_mode = I40E_FC_FULL;
2895                 break;
2896         case I40E_AQ_LINK_PAUSE_RX:
2897                 rxfc = 1;
2898                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2899                 break;
2900         case I40E_AQ_LINK_PAUSE_TX:
2901                 txfc = 1;
2902                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2903                 break;
2904         default:
2905                 hw->fc.current_mode = I40E_FC_NONE;
2906                 break;
2907         }
2908
2909 write_reg:
2910         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2911                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2912         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2913         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2914         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2915         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2916
2917         return ret;
2918 }
2919
2920 /* PF setup */
2921 static int
2922 i40e_pf_setup(struct i40e_pf *pf)
2923 {
2924         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2925         struct i40e_filter_control_settings settings;
2926         struct rte_eth_dev_data *dev_data = pf->dev_data;
2927         struct i40e_vsi *vsi;
2928         int ret;
2929
2930         /* Clear all stats counters */
2931         pf->offset_loaded = FALSE;
2932         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2933         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2934
2935         ret = i40e_pf_get_switch_config(pf);
2936         if (ret != I40E_SUCCESS) {
2937                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2938                 return ret;
2939         }
2940
2941         /* VSI setup */
2942         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2943         if (!vsi) {
2944                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2945                 return I40E_ERR_NOT_READY;
2946         }
2947         pf->main_vsi = vsi;
2948         dev_data->nb_rx_queues = vsi->nb_qps;
2949         dev_data->nb_tx_queues = vsi->nb_qps;
2950
2951         /* Configure filter control */
2952         memset(&settings, 0, sizeof(settings));
2953         settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2954         /* Enable ethtype and macvlan filters */
2955         settings.enable_ethtype = TRUE;
2956         settings.enable_macvlan = TRUE;
2957         ret = i40e_set_filter_control(hw, &settings);
2958         if (ret)
2959                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2960                                                                 ret);
2961
2962         /* Update flow control according to the auto negotiation */
2963         i40e_update_flow_control(hw);
2964
2965         return I40E_SUCCESS;
2966 }
2967
2968 int
2969 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2970 {
2971         uint32_t reg;
2972         uint16_t j;
2973
2974         /**
2975          * Set or clear TX Queue Disable flags,
2976          * which is required by hardware.
2977          */
2978         i40e_pre_tx_queue_cfg(hw, q_idx, on);
2979         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2980
2981         /* Wait until the request is finished */
2982         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2983                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2984                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2985                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2986                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2987                                                         & 0x1))) {
2988                         break;
2989                 }
2990         }
2991         if (on) {
2992                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2993                         return I40E_SUCCESS; /* already on, skip next steps */
2994
2995                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2996                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2997         } else {
2998                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2999                         return I40E_SUCCESS; /* already off, skip next steps */
3000                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3001         }
3002         /* Write the register */
3003         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3004         /* Check the result */
3005         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3006                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3007                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3008                 if (on) {
3009                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3010                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3011                                 break;
3012                 } else {
3013                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3014                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3015                                 break;
3016                 }
3017         }
3018         /* Check if it is timeout */
3019         if (j >= I40E_CHK_Q_ENA_COUNT) {
3020                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3021                             (on ? "enable" : "disable"), q_idx);
3022                 return I40E_ERR_TIMEOUT;
3023         }
3024
3025         return I40E_SUCCESS;
3026 }
3027
3028 /* Swith on or off the tx queues */
3029 static int
3030 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
3031 {
3032         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3033         struct i40e_tx_queue *txq;
3034         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3035         uint16_t i;
3036         int ret;
3037
3038         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3039                 txq = dev_data->tx_queues[i];
3040                 /* Don't operate the queue if not configured or
3041                  * if starting only per queue */
3042                 if (!txq->q_set || (on && txq->tx_deferred_start))
3043                         continue;
3044                 if (on)
3045                         ret = i40e_dev_tx_queue_start(dev, i);
3046                 else
3047                         ret = i40e_dev_tx_queue_stop(dev, i);
3048                 if ( ret != I40E_SUCCESS)
3049                         return ret;
3050         }
3051
3052         return I40E_SUCCESS;
3053 }
3054
3055 int
3056 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3057 {
3058         uint32_t reg;
3059         uint16_t j;
3060
3061         /* Wait until the request is finished */
3062         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3063                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3064                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3065                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3066                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3067                         break;
3068         }
3069
3070         if (on) {
3071                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3072                         return I40E_SUCCESS; /* Already on, skip next steps */
3073                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3074         } else {
3075                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3076                         return I40E_SUCCESS; /* Already off, skip next steps */
3077                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3078         }
3079
3080         /* Write the register */
3081         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3082         /* Check the result */
3083         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3084                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3085                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3086                 if (on) {
3087                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3088                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3089                                 break;
3090                 } else {
3091                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3092                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3093                                 break;
3094                 }
3095         }
3096
3097         /* Check if it is timeout */
3098         if (j >= I40E_CHK_Q_ENA_COUNT) {
3099                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3100                             (on ? "enable" : "disable"), q_idx);
3101                 return I40E_ERR_TIMEOUT;
3102         }
3103
3104         return I40E_SUCCESS;
3105 }
3106 /* Switch on or off the rx queues */
3107 static int
3108 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3109 {
3110         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3111         struct i40e_rx_queue *rxq;
3112         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
3113         uint16_t i;
3114         int ret;
3115
3116         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3117                 rxq = dev_data->rx_queues[i];
3118                 /* Don't operate the queue if not configured or
3119                  * if starting only per queue */
3120                 if (!rxq->q_set || (on && rxq->rx_deferred_start))
3121                         continue;
3122                 if (on)
3123                         ret = i40e_dev_rx_queue_start(dev, i);
3124                 else
3125                         ret = i40e_dev_rx_queue_stop(dev, i);
3126                 if (ret != I40E_SUCCESS)
3127                         return ret;
3128         }
3129
3130         return I40E_SUCCESS;
3131 }
3132
3133 /* Switch on or off all the rx/tx queues */
3134 int
3135 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3136 {
3137         int ret;
3138
3139         if (on) {
3140                 /* enable rx queues before enabling tx queues */
3141                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3142                 if (ret) {
3143                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3144                         return ret;
3145                 }
3146                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3147         } else {
3148                 /* Stop tx queues before stopping rx queues */
3149                 ret = i40e_vsi_switch_tx_queues(vsi, on);
3150                 if (ret) {
3151                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3152                         return ret;
3153                 }
3154                 ret = i40e_vsi_switch_rx_queues(vsi, on);
3155         }
3156
3157         return ret;
3158 }
3159
3160 /* Initialize VSI for TX */
3161 static int
3162 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3163 {
3164         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3165         struct rte_eth_dev_data *data = pf->dev_data;
3166         uint16_t i;
3167         uint32_t ret = I40E_SUCCESS;
3168
3169         for (i = 0; i < data->nb_tx_queues; i++) {
3170                 ret = i40e_tx_queue_init(data->tx_queues[i]);
3171                 if (ret != I40E_SUCCESS)
3172                         break;
3173         }
3174
3175         return ret;
3176 }
3177
3178 /* Initialize VSI for RX */
3179 static int
3180 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3181 {
3182         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3183         struct rte_eth_dev_data *data = pf->dev_data;
3184         int ret = I40E_SUCCESS;
3185         uint16_t i;
3186
3187         i40e_pf_config_mq_rx(pf);
3188         for (i = 0; i < data->nb_rx_queues; i++) {
3189                 ret = i40e_rx_queue_init(data->rx_queues[i]);
3190                 if (ret != I40E_SUCCESS) {
3191                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3192                                     "initialization");
3193                         break;
3194                 }
3195         }
3196
3197         return ret;
3198 }
3199
3200 /* Initialize VSI */
3201 static int
3202 i40e_vsi_init(struct i40e_vsi *vsi)
3203 {
3204         int err;
3205
3206         err = i40e_vsi_tx_init(vsi);
3207         if (err) {
3208                 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization");
3209                 return err;
3210         }
3211         err = i40e_vsi_rx_init(vsi);
3212         if (err) {
3213                 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization");
3214                 return err;
3215         }
3216
3217         return err;
3218 }
3219
3220 static void
3221 i40e_stat_update_32(struct i40e_hw *hw,
3222                    uint32_t reg,
3223                    bool offset_loaded,
3224                    uint64_t *offset,
3225                    uint64_t *stat)
3226 {
3227         uint64_t new_data;
3228
3229         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3230         if (!offset_loaded)
3231                 *offset = new_data;
3232
3233         if (new_data >= *offset)
3234                 *stat = (uint64_t)(new_data - *offset);
3235         else
3236                 *stat = (uint64_t)((new_data +
3237                         ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3238 }
3239
3240 static void
3241 i40e_stat_update_48(struct i40e_hw *hw,
3242                    uint32_t hireg,
3243                    uint32_t loreg,
3244                    bool offset_loaded,
3245                    uint64_t *offset,
3246                    uint64_t *stat)
3247 {
3248         uint64_t new_data;
3249
3250         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3251         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3252                         I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3253
3254         if (!offset_loaded)
3255                 *offset = new_data;
3256
3257         if (new_data >= *offset)
3258                 *stat = new_data - *offset;
3259         else
3260                 *stat = (uint64_t)((new_data +
3261                         ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3262
3263         *stat &= I40E_48_BIT_MASK;
3264 }
3265
3266 /* Disable IRQ0 */
3267 void
3268 i40e_pf_disable_irq0(struct i40e_hw *hw)
3269 {
3270         /* Disable all interrupt types */
3271         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3272         I40E_WRITE_FLUSH(hw);
3273 }
3274
3275 /* Enable IRQ0 */
3276 void
3277 i40e_pf_enable_irq0(struct i40e_hw *hw)
3278 {
3279         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3280                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3281                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3282                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3283         I40E_WRITE_FLUSH(hw);
3284 }
3285
3286 static void
3287 i40e_pf_config_irq0(struct i40e_hw *hw)
3288 {
3289         uint32_t enable;
3290
3291         /* read pending request and disable first */
3292         i40e_pf_disable_irq0(hw);
3293         /**
3294          * Enable all interrupt error options to detect possible errors,
3295          * other informative int are ignored
3296          */
3297         enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3298                  I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3299                  I40E_PFINT_ICR0_ENA_GRST_MASK |
3300                  I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3301                  I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3302                  I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3303                  I40E_PFINT_ICR0_ENA_VFLR_MASK |
3304                  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3305
3306         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3307         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3308                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3309
3310         /* Link no queues with irq0 */
3311         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3312                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3313 }
3314
3315 static void
3316 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3317 {
3318         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320         int i;
3321         uint16_t abs_vf_id;
3322         uint32_t index, offset, val;
3323
3324         if (!pf->vfs)
3325                 return;
3326         /**
3327          * Try to find which VF trigger a reset, use absolute VF id to access
3328          * since the reg is global register.
3329          */
3330         for (i = 0; i < pf->vf_num; i++) {
3331                 abs_vf_id = hw->func_caps.vf_base_id + i;
3332                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3333                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3334                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3335                 /* VFR event occured */
3336                 if (val & (0x1 << offset)) {
3337                         int ret;
3338
3339                         /* Clear the event first */
3340                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3341                                                         (0x1 << offset));
3342                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3343                         /**
3344                          * Only notify a VF reset event occured,
3345                          * don't trigger another SW reset
3346                          */
3347                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3348                         if (ret != I40E_SUCCESS)
3349                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3350                 }
3351         }
3352 }
3353
3354 static void
3355 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3356 {
3357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358         struct i40e_arq_event_info info;
3359         uint16_t pending, opcode;
3360         int ret;
3361
3362         info.buf_len = I40E_AQ_BUF_SZ;
3363         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3364         if (!info.msg_buf) {
3365                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3366                 return;
3367         }
3368
3369         pending = 1;
3370         while (pending) {
3371                 ret = i40e_clean_arq_element(hw, &info, &pending);
3372
3373                 if (ret != I40E_SUCCESS) {
3374                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3375                                     "aq_err: %u", hw->aq.asq_last_status);
3376                         break;
3377                 }
3378                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3379
3380                 switch (opcode) {
3381                 case i40e_aqc_opc_send_msg_to_pf:
3382                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3383                         i40e_pf_host_handle_vf_msg(dev,
3384                                         rte_le_to_cpu_16(info.desc.retval),
3385                                         rte_le_to_cpu_32(info.desc.cookie_high),
3386                                         rte_le_to_cpu_32(info.desc.cookie_low),
3387                                         info.msg_buf,
3388                                         info.msg_len);
3389                         break;
3390                 default:
3391                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3392                                     opcode);
3393                         break;
3394                 }
3395         }
3396         rte_free(info.msg_buf);
3397 }
3398
3399 /**
3400  * Interrupt handler triggered by NIC  for handling
3401  * specific interrupt.
3402  *
3403  * @param handle
3404  *  Pointer to interrupt handle.
3405  * @param param
3406  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3407  *
3408  * @return
3409  *  void
3410  */
3411 static void
3412 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3413                            void *param)
3414 {
3415         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417         uint32_t cause, enable;
3418
3419         i40e_pf_disable_irq0(hw);
3420
3421         cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3422         enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3423
3424         /* Shared IRQ case, return */
3425         if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3426                 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3427                             "no INT event to process", hw->pf_id);
3428                 goto done;
3429         }
3430
3431         if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3432                 PMD_DRV_LOG(INFO, "INT:Link status changed");
3433                 i40e_dev_link_update(dev, 0);
3434         }
3435
3436         if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3437                 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error");
3438
3439         if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3440                 PMD_DRV_LOG(INFO, "INT:Malicious programming detected");
3441
3442         if (cause & I40E_PFINT_ICR0_GRST_MASK)
3443                 PMD_DRV_LOG(INFO, "INT:Global Resets Requested");
3444
3445         if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3446                 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured");
3447
3448         if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3449                 PMD_DRV_LOG(INFO, "INT:HMC error occured");
3450
3451         /* Add processing func to deal with VF reset vent */
3452         if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3453                 PMD_DRV_LOG(INFO, "INT:VF reset detected");
3454                 i40e_dev_handle_vfr_event(dev);
3455         }
3456         /* Find admin queue event */
3457         if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3458                 PMD_DRV_LOG(INFO, "INT:ADMINQ event");
3459                 i40e_dev_handle_aq_msg(dev);
3460         }
3461
3462 done:
3463         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3464         /* Re-enable interrupt from device side */
3465         i40e_pf_enable_irq0(hw);
3466         /* Re-enable interrupt from host side */
3467         rte_intr_enable(&(dev->pci_dev->intr_handle));
3468 }
3469
3470 static int
3471 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3472                          struct i40e_macvlan_filter *filter,
3473                          int total)
3474 {
3475         int ele_num, ele_buff_size;
3476         int num, actual_num, i;
3477         int ret = I40E_SUCCESS;
3478         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3479         struct i40e_aqc_add_macvlan_element_data *req_list;
3480
3481         if (filter == NULL  || total == 0)
3482                 return I40E_ERR_PARAM;
3483         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3484         ele_buff_size = hw->aq.asq_buf_size;
3485
3486         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3487         if (req_list == NULL) {
3488                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3489                 return I40E_ERR_NO_MEMORY;
3490         }
3491
3492         num = 0;
3493         do {
3494                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3495                 memset(req_list, 0, ele_buff_size);
3496
3497                 for (i = 0; i < actual_num; i++) {
3498                         (void)rte_memcpy(req_list[i].mac_addr,
3499                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3500                         req_list[i].vlan_tag =
3501                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3502                         req_list[i].flags = rte_cpu_to_le_16(\
3503                                 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3504                         req_list[i].queue_number = 0;
3505                 }
3506
3507                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3508                                                 actual_num, NULL);
3509                 if (ret != I40E_SUCCESS) {
3510                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
3511                         goto DONE;
3512                 }
3513                 num += actual_num;
3514         } while (num < total);
3515
3516 DONE:
3517         rte_free(req_list);
3518         return ret;
3519 }
3520
3521 static int
3522 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3523                             struct i40e_macvlan_filter *filter,
3524                             int total)
3525 {
3526         int ele_num, ele_buff_size;
3527         int num, actual_num, i;
3528         int ret = I40E_SUCCESS;
3529         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3530         struct i40e_aqc_remove_macvlan_element_data *req_list;
3531
3532         if (filter == NULL  || total == 0)
3533                 return I40E_ERR_PARAM;
3534
3535         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3536         ele_buff_size = hw->aq.asq_buf_size;
3537
3538         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3539         if (req_list == NULL) {
3540                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
3541                 return I40E_ERR_NO_MEMORY;
3542         }
3543
3544         num = 0;
3545         do {
3546                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3547                 memset(req_list, 0, ele_buff_size);
3548
3549                 for (i = 0; i < actual_num; i++) {
3550                         (void)rte_memcpy(req_list[i].mac_addr,
3551                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
3552                         req_list[i].vlan_tag =
3553                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
3554                         req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3555                 }
3556
3557                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3558                                                 actual_num, NULL);
3559                 if (ret != I40E_SUCCESS) {
3560                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
3561                         goto DONE;
3562                 }
3563                 num += actual_num;
3564         } while (num < total);
3565
3566 DONE:
3567         rte_free(req_list);
3568         return ret;
3569 }
3570
3571 /* Find out specific MAC filter */
3572 static struct i40e_mac_filter *
3573 i40e_find_mac_filter(struct i40e_vsi *vsi,
3574                          struct ether_addr *macaddr)
3575 {
3576         struct i40e_mac_filter *f;
3577
3578         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3579                 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3580                         return f;
3581         }
3582
3583         return NULL;
3584 }
3585
3586 static bool
3587 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3588                          uint16_t vlan_id)
3589 {
3590         uint32_t vid_idx, vid_bit;
3591
3592         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3593         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3594
3595         if (vsi->vfta[vid_idx] & vid_bit)
3596                 return 1;
3597         else
3598                 return 0;
3599 }
3600
3601 static void
3602 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3603                          uint16_t vlan_id, bool on)
3604 {
3605         uint32_t vid_idx, vid_bit;
3606
3607 #define UINT32_BIT_MASK      0x1F
3608 #define VALID_VLAN_BIT_MASK  0xFFF
3609         /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3610          *  element first, then find the bits it belongs to
3611          */
3612         vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3613                   sizeof(uint32_t));
3614         vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3615
3616         if (on)
3617                 vsi->vfta[vid_idx] |= vid_bit;
3618         else
3619                 vsi->vfta[vid_idx] &= ~vid_bit;
3620 }
3621
3622 /**
3623  * Find all vlan options for specific mac addr,
3624  * return with actual vlan found.
3625  */
3626 static inline int
3627 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3628                            struct i40e_macvlan_filter *mv_f,
3629                            int num, struct ether_addr *addr)
3630 {
3631         int i;
3632         uint32_t j, k;
3633
3634         /**
3635          * Not to use i40e_find_vlan_filter to decrease the loop time,
3636          * although the code looks complex.
3637           */
3638         if (num < vsi->vlan_num)
3639                 return I40E_ERR_PARAM;
3640
3641         i = 0;
3642         for (j = 0; j < I40E_VFTA_SIZE; j++) {
3643                 if (vsi->vfta[j]) {
3644                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3645                                 if (vsi->vfta[j] & (1 << k)) {
3646                                         if (i > num - 1) {
3647                                                 PMD_DRV_LOG(ERR, "vlan number "
3648                                                             "not match");
3649                                                 return I40E_ERR_PARAM;
3650                                         }
3651                                         (void)rte_memcpy(&mv_f[i].macaddr,
3652                                                         addr, ETH_ADDR_LEN);
3653                                         mv_f[i].vlan_id =
3654                                                 j * I40E_UINT32_BIT_SIZE + k;
3655                                         i++;
3656                                 }
3657                         }
3658                 }
3659         }
3660         return I40E_SUCCESS;
3661 }
3662
3663 static inline int
3664 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3665                            struct i40e_macvlan_filter *mv_f,
3666                            int num,
3667                            uint16_t vlan)
3668 {
3669         int i = 0;
3670         struct i40e_mac_filter *f;
3671
3672         if (num < vsi->mac_num)
3673                 return I40E_ERR_PARAM;
3674
3675         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3676                 if (i > num - 1) {
3677                         PMD_DRV_LOG(ERR, "buffer number not match");
3678                         return I40E_ERR_PARAM;
3679                 }
3680                 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3681                 mv_f[i].vlan_id = vlan;
3682                 i++;
3683         }
3684
3685         return I40E_SUCCESS;
3686 }
3687
3688 static int
3689 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3690 {
3691         int i, num;
3692         struct i40e_mac_filter *f;
3693         struct i40e_macvlan_filter *mv_f;
3694         int ret = I40E_SUCCESS;
3695
3696         if (vsi == NULL || vsi->mac_num == 0)
3697                 return I40E_ERR_PARAM;
3698
3699         /* Case that no vlan is set */
3700         if (vsi->vlan_num == 0)
3701                 num = vsi->mac_num;
3702         else
3703                 num = vsi->mac_num * vsi->vlan_num;
3704
3705         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3706         if (mv_f == NULL) {
3707                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3708                 return I40E_ERR_NO_MEMORY;
3709         }
3710
3711         i = 0;
3712         if (vsi->vlan_num == 0) {
3713                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3714                         (void)rte_memcpy(&mv_f[i].macaddr,
3715                                 &f->macaddr, ETH_ADDR_LEN);
3716                         mv_f[i].vlan_id = 0;
3717                         i++;
3718                 }
3719         } else {
3720                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3721                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3722                                         vsi->vlan_num, &f->macaddr);
3723                         if (ret != I40E_SUCCESS)
3724                                 goto DONE;
3725                         i += vsi->vlan_num;
3726                 }
3727         }
3728
3729         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3730 DONE:
3731         rte_free(mv_f);
3732
3733         return ret;
3734 }
3735
3736 int
3737 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3738 {
3739         struct i40e_macvlan_filter *mv_f;
3740         int mac_num;
3741         int ret = I40E_SUCCESS;
3742
3743         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3744                 return I40E_ERR_PARAM;
3745
3746         /* If it's already set, just return */
3747         if (i40e_find_vlan_filter(vsi,vlan))
3748                 return I40E_SUCCESS;
3749
3750         mac_num = vsi->mac_num;
3751
3752         if (mac_num == 0) {
3753                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3754                 return I40E_ERR_PARAM;
3755         }
3756
3757         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3758
3759         if (mv_f == NULL) {
3760                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3761                 return I40E_ERR_NO_MEMORY;
3762         }
3763
3764         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3765
3766         if (ret != I40E_SUCCESS)
3767                 goto DONE;
3768
3769         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3770
3771         if (ret != I40E_SUCCESS)
3772                 goto DONE;
3773
3774         i40e_set_vlan_filter(vsi, vlan, 1);
3775
3776         vsi->vlan_num++;
3777         ret = I40E_SUCCESS;
3778 DONE:
3779         rte_free(mv_f);
3780         return ret;
3781 }
3782
3783 int
3784 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3785 {
3786         struct i40e_macvlan_filter *mv_f;
3787         int mac_num;
3788         int ret = I40E_SUCCESS;
3789
3790         /**
3791          * Vlan 0 is the generic filter for untagged packets
3792          * and can't be removed.
3793          */
3794         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3795                 return I40E_ERR_PARAM;
3796
3797         /* If can't find it, just return */
3798         if (!i40e_find_vlan_filter(vsi, vlan))
3799                 return I40E_ERR_PARAM;
3800
3801         mac_num = vsi->mac_num;
3802
3803         if (mac_num == 0) {
3804                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
3805                 return I40E_ERR_PARAM;
3806         }
3807
3808         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3809
3810         if (mv_f == NULL) {
3811                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3812                 return I40E_ERR_NO_MEMORY;
3813         }
3814
3815         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3816
3817         if (ret != I40E_SUCCESS)
3818                 goto DONE;
3819
3820         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3821
3822         if (ret != I40E_SUCCESS)
3823                 goto DONE;
3824
3825         /* This is last vlan to remove, replace all mac filter with vlan 0 */
3826         if (vsi->vlan_num == 1) {
3827                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3828                 if (ret != I40E_SUCCESS)
3829                         goto DONE;
3830
3831                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3832                 if (ret != I40E_SUCCESS)
3833                         goto DONE;
3834         }
3835
3836         i40e_set_vlan_filter(vsi, vlan, 0);
3837
3838         vsi->vlan_num--;
3839         ret = I40E_SUCCESS;
3840 DONE:
3841         rte_free(mv_f);
3842         return ret;
3843 }
3844
3845 int
3846 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3847 {
3848         struct i40e_mac_filter *f;
3849         struct i40e_macvlan_filter *mv_f;
3850         int vlan_num;
3851         int ret = I40E_SUCCESS;
3852
3853         /* If it's add and we've config it, return */
3854         f = i40e_find_mac_filter(vsi, addr);
3855         if (f != NULL)
3856                 return I40E_SUCCESS;
3857
3858         /**
3859          * If vlan_num is 0, that's the first time to add mac,
3860          * set mask for vlan_id 0.
3861          */
3862         if (vsi->vlan_num == 0) {
3863                 i40e_set_vlan_filter(vsi, 0, 1);
3864                 vsi->vlan_num = 1;
3865         }
3866
3867         vlan_num = vsi->vlan_num;
3868
3869         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3870         if (mv_f == NULL) {
3871                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3872                 return I40E_ERR_NO_MEMORY;
3873         }
3874
3875         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3876         if (ret != I40E_SUCCESS)
3877                 goto DONE;
3878
3879         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3880         if (ret != I40E_SUCCESS)
3881                 goto DONE;
3882
3883         /* Add the mac addr into mac list */
3884         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3885         if (f == NULL) {
3886                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3887                 ret = I40E_ERR_NO_MEMORY;
3888                 goto DONE;
3889         }
3890         (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3891         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3892         vsi->mac_num++;
3893
3894         ret = I40E_SUCCESS;
3895 DONE:
3896         rte_free(mv_f);
3897
3898         return ret;
3899 }
3900
3901 int
3902 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3903 {
3904         struct i40e_mac_filter *f;
3905         struct i40e_macvlan_filter *mv_f;
3906         int vlan_num;
3907         int ret = I40E_SUCCESS;
3908
3909         /* Can't find it, return an error */
3910         f = i40e_find_mac_filter(vsi, addr);
3911         if (f == NULL)
3912                 return I40E_ERR_PARAM;
3913
3914         vlan_num = vsi->vlan_num;
3915         if (vlan_num == 0) {
3916                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
3917                 return I40E_ERR_PARAM;
3918         }
3919         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3920         if (mv_f == NULL) {
3921                 PMD_DRV_LOG(ERR, "failed to allocate memory");
3922                 return I40E_ERR_NO_MEMORY;
3923         }
3924
3925         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3926         if (ret != I40E_SUCCESS)
3927                 goto DONE;
3928
3929         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3930         if (ret != I40E_SUCCESS)
3931                 goto DONE;
3932
3933         /* Remove the mac addr into mac list */
3934         TAILQ_REMOVE(&vsi->mac_list, f, next);
3935         rte_free(f);
3936         vsi->mac_num--;
3937
3938         ret = I40E_SUCCESS;
3939 DONE:
3940         rte_free(mv_f);
3941         return ret;
3942 }
3943
3944 /* Configure hash enable flags for RSS */
3945 uint64_t
3946 i40e_config_hena(uint64_t flags)
3947 {
3948         uint64_t hena = 0;
3949
3950         if (!flags)
3951                 return hena;
3952
3953         if (flags & ETH_RSS_NONF_IPV4_UDP)
3954                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3955         if (flags & ETH_RSS_NONF_IPV4_TCP)
3956                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3957         if (flags & ETH_RSS_NONF_IPV4_SCTP)
3958                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3959         if (flags & ETH_RSS_NONF_IPV4_OTHER)
3960                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3961         if (flags & ETH_RSS_FRAG_IPV4)
3962                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3963         if (flags & ETH_RSS_NONF_IPV6_UDP)
3964                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3965         if (flags & ETH_RSS_NONF_IPV6_TCP)
3966                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3967         if (flags & ETH_RSS_NONF_IPV6_SCTP)
3968                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3969         if (flags & ETH_RSS_NONF_IPV6_OTHER)
3970                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3971         if (flags & ETH_RSS_FRAG_IPV6)
3972                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3973         if (flags & ETH_RSS_L2_PAYLOAD)
3974                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3975
3976         return hena;
3977 }
3978
3979 /* Parse the hash enable flags */
3980 uint64_t
3981 i40e_parse_hena(uint64_t flags)
3982 {
3983         uint64_t rss_hf = 0;
3984
3985         if (!flags)
3986                 return rss_hf;
3987
3988         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3989                 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3990         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3991                 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3992         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3993                 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3994         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3995                 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3996         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3997                 rss_hf |= ETH_RSS_FRAG_IPV4;
3998         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3999                 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
4000         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4001                 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
4002         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4003                 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
4004         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4005                 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
4006         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4007                 rss_hf |= ETH_RSS_FRAG_IPV6;
4008         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4009                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4010
4011         return rss_hf;
4012 }
4013
4014 /* Disable RSS */
4015 static void
4016 i40e_pf_disable_rss(struct i40e_pf *pf)
4017 {
4018         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4019         uint64_t hena;
4020
4021         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4022         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4023         hena &= ~I40E_RSS_HENA_ALL;
4024         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4025         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4026         I40E_WRITE_FLUSH(hw);
4027 }
4028
4029 static int
4030 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4031 {
4032         uint32_t *hash_key;
4033         uint8_t hash_key_len;
4034         uint64_t rss_hf;
4035         uint16_t i;
4036         uint64_t hena;
4037
4038         hash_key = (uint32_t *)(rss_conf->rss_key);
4039         hash_key_len = rss_conf->rss_key_len;
4040         if (hash_key != NULL && hash_key_len >=
4041                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4042                 /* Fill in RSS hash key */
4043                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4044                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4045         }
4046
4047         rss_hf = rss_conf->rss_hf;
4048         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4049         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4050         hena &= ~I40E_RSS_HENA_ALL;
4051         hena |= i40e_config_hena(rss_hf);
4052         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4053         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4054         I40E_WRITE_FLUSH(hw);
4055
4056         return 0;
4057 }
4058
4059 static int
4060 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4061                          struct rte_eth_rss_conf *rss_conf)
4062 {
4063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4064         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4065         uint64_t hena;
4066
4067         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4068         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4069         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4070                 if (rss_hf != 0) /* Enable RSS */
4071                         return -EINVAL;
4072                 return 0; /* Nothing to do */
4073         }
4074         /* RSS enabled */
4075         if (rss_hf == 0) /* Disable RSS */
4076                 return -EINVAL;
4077
4078         return i40e_hw_rss_hash_set(hw, rss_conf);
4079 }
4080
4081 static int
4082 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4083                            struct rte_eth_rss_conf *rss_conf)
4084 {
4085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4086         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4087         uint64_t hena;
4088         uint16_t i;
4089
4090         if (hash_key != NULL) {
4091                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4092                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4093                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4094         }
4095         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4096         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4097         rss_conf->rss_hf = i40e_parse_hena(hena);
4098
4099         return 0;
4100 }
4101
4102 static int
4103 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4104 {
4105         switch (filter_type) {
4106         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4107                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4108                 break;
4109         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4110                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4111                 break;
4112         case RTE_TUNNEL_FILTER_IMAC_TENID:
4113                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4114                 break;
4115         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4116                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4117                 break;
4118         case ETH_TUNNEL_FILTER_IMAC:
4119                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4120                 break;
4121         default:
4122                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4123                 return -EINVAL;
4124         }
4125
4126         return 0;
4127 }
4128
4129 static int
4130 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4131                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4132                         uint8_t add)
4133 {
4134         uint16_t ip_type;
4135         uint8_t tun_type = 0;
4136         int val, ret = 0;
4137         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4138         struct i40e_vsi *vsi = pf->main_vsi;
4139         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4140         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4141
4142         cld_filter = rte_zmalloc("tunnel_filter",
4143                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4144                 0);
4145
4146         if (NULL == cld_filter) {
4147                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4148                 return -EINVAL;
4149         }
4150         pfilter = cld_filter;
4151
4152         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4153                         sizeof(struct ether_addr));
4154         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4155                         sizeof(struct ether_addr));
4156
4157         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4158         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4159                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4160                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4161                                 &tunnel_filter->ip_addr,
4162                                 sizeof(pfilter->ipaddr.v4.data));
4163         } else {
4164                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4165                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4166                                 &tunnel_filter->ip_addr,
4167                                 sizeof(pfilter->ipaddr.v6.data));
4168         }
4169
4170         /* check tunneled type */
4171         switch (tunnel_filter->tunnel_type) {
4172         case RTE_TUNNEL_TYPE_VXLAN:
4173                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4174                 break;
4175         default:
4176                 /* Other tunnel types is not supported. */
4177                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4178                 rte_free(cld_filter);
4179                 return -EINVAL;
4180         }
4181
4182         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4183                                                 &pfilter->flags);
4184         if (val < 0) {
4185                 rte_free(cld_filter);
4186                 return -EINVAL;
4187         }
4188
4189         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4190                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4191         pfilter->tenant_id = tunnel_filter->tenant_id;
4192         pfilter->queue_number = tunnel_filter->queue_id;
4193
4194         if (add)
4195                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4196         else
4197                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4198                                                 cld_filter, 1);
4199
4200         rte_free(cld_filter);
4201         return ret;
4202 }
4203
4204 static int
4205 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4206 {
4207         uint8_t i;
4208
4209         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4210                 if (pf->vxlan_ports[i] == port)
4211                         return i;
4212         }
4213
4214         return -1;
4215 }
4216
4217 static int
4218 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4219 {
4220         int  idx, ret;
4221         uint8_t filter_idx;
4222         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4223
4224         idx = i40e_get_vxlan_port_idx(pf, port);
4225
4226         /* Check if port already exists */
4227         if (idx >= 0) {
4228                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4229                 return -EINVAL;
4230         }
4231
4232         /* Now check if there is space to add the new port */
4233         idx = i40e_get_vxlan_port_idx(pf, 0);
4234         if (idx < 0) {
4235                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4236                         "not adding port %d", port);
4237                 return -ENOSPC;
4238         }
4239
4240         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4241                                         &filter_idx, NULL);
4242         if (ret < 0) {
4243                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4244                 return -1;
4245         }
4246
4247         PMD_DRV_LOG(INFO, "Added %s port %d with AQ command with index %d",
4248                          port,  filter_index);
4249
4250         /* New port: add it and mark its index in the bitmap */
4251         pf->vxlan_ports[idx] = port;
4252         pf->vxlan_bitmap |= (1 << idx);
4253
4254         if (!(pf->flags & I40E_FLAG_VXLAN))
4255                 pf->flags |= I40E_FLAG_VXLAN;
4256
4257         return 0;
4258 }
4259
4260 static int
4261 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4262 {
4263         int idx;
4264         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4265
4266         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4267                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4268                 return -EINVAL;
4269         }
4270
4271         idx = i40e_get_vxlan_port_idx(pf, port);
4272
4273         if (idx < 0) {
4274                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4275                 return -EINVAL;
4276         }
4277
4278         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4279                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4280                 return -1;
4281         }
4282
4283         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4284                         port, idx);
4285
4286         pf->vxlan_ports[idx] = 0;
4287         pf->vxlan_bitmap &= ~(1 << idx);
4288
4289         if (!pf->vxlan_bitmap)
4290                 pf->flags &= ~I40E_FLAG_VXLAN;
4291
4292         return 0;
4293 }
4294
4295 /* Add UDP tunneling port */
4296 static int
4297 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4298                         struct rte_eth_udp_tunnel *udp_tunnel)
4299 {
4300         int ret = 0;
4301         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4302
4303         if (udp_tunnel == NULL)
4304                 return -EINVAL;
4305
4306         switch (udp_tunnel->prot_type) {
4307         case RTE_TUNNEL_TYPE_VXLAN:
4308                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4309                 break;
4310
4311         case RTE_TUNNEL_TYPE_GENEVE:
4312         case RTE_TUNNEL_TYPE_TEREDO:
4313                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4314                 ret = -1;
4315                 break;
4316
4317         default:
4318                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4319                 ret = -1;
4320                 break;
4321         }
4322
4323         return ret;
4324 }
4325
4326 /* Remove UDP tunneling port */
4327 static int
4328 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4329                         struct rte_eth_udp_tunnel *udp_tunnel)
4330 {
4331         int ret = 0;
4332         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4333
4334         if (udp_tunnel == NULL)
4335                 return -EINVAL;
4336
4337         switch (udp_tunnel->prot_type) {
4338         case RTE_TUNNEL_TYPE_VXLAN:
4339                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
4340                 break;
4341         case RTE_TUNNEL_TYPE_GENEVE:
4342         case RTE_TUNNEL_TYPE_TEREDO:
4343                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4344                 ret = -1;
4345                 break;
4346         default:
4347                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4348                 ret = -1;
4349                 break;
4350         }
4351
4352         return ret;
4353 }
4354
4355 /* Configure RSS */
4356 static int
4357 i40e_pf_config_rss(struct i40e_pf *pf)
4358 {
4359         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4360         struct rte_eth_rss_conf rss_conf;
4361         uint32_t i, lut = 0;
4362         uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4363
4364         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4365                 if (j == num)
4366                         j = 0;
4367                 lut = (lut << 8) | (j & ((0x1 <<
4368                         hw->func_caps.rss_table_entry_width) - 1));
4369                 if ((i & 3) == 3)
4370                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4371         }
4372
4373         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4374         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4375                 i40e_pf_disable_rss(pf);
4376                 return 0;
4377         }
4378         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4379                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4380                 /* Calculate the default hash key */
4381                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4382                         rss_key_default[i] = (uint32_t)rte_rand();
4383                 rss_conf.rss_key = (uint8_t *)rss_key_default;
4384                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4385                                                         sizeof(uint32_t);
4386         }
4387
4388         return i40e_hw_rss_hash_set(hw, &rss_conf);
4389 }
4390
4391 static int
4392 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
4393                         struct rte_eth_tunnel_filter_conf *filter)
4394 {
4395         if (pf == NULL || filter == NULL) {
4396                 PMD_DRV_LOG(ERR, "Invalid parameter");
4397                 return -EINVAL;
4398         }
4399
4400         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
4401                 PMD_DRV_LOG(ERR, "Invalid queue ID");
4402                 return -EINVAL;
4403         }
4404
4405         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
4406                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
4407                 return -EINVAL;
4408         }
4409
4410         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
4411                 (is_zero_ether_addr(filter->outer_mac))) {
4412                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
4413                 return -EINVAL;
4414         }
4415
4416         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
4417                 (is_zero_ether_addr(filter->inner_mac))) {
4418                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
4419                 return -EINVAL;
4420         }
4421
4422         return 0;
4423 }
4424
4425 static int
4426 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4427                         void *arg)
4428 {
4429         struct rte_eth_tunnel_filter_conf *filter;
4430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4431         int ret = I40E_SUCCESS;
4432
4433         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
4434
4435         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
4436                 return I40E_ERR_PARAM;
4437
4438         switch (filter_op) {
4439         case RTE_ETH_FILTER_NOP:
4440                 if (!(pf->flags & I40E_FLAG_VXLAN))
4441                         ret = I40E_NOT_SUPPORTED;
4442         case RTE_ETH_FILTER_ADD:
4443                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
4444                 break;
4445         case RTE_ETH_FILTER_DELETE:
4446                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
4447                 break;
4448         default:
4449                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4450                 ret = I40E_ERR_PARAM;
4451                 break;
4452         }
4453
4454         return ret;
4455 }
4456
4457 static int
4458 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4459 {
4460         if (!pf->dev_data->sriov.active) {
4461                 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4462                 case ETH_MQ_RX_RSS:
4463                         i40e_pf_config_rss(pf);
4464                         break;
4465                 default:
4466                         i40e_pf_disable_rss(pf);
4467                         break;
4468                 }
4469         }
4470
4471         return 0;
4472 }
4473
4474 static int
4475 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
4476                      enum rte_filter_type filter_type,
4477                      enum rte_filter_op filter_op,
4478                      void *arg)
4479 {
4480         int ret = 0;
4481
4482         if (dev == NULL)
4483                 return -EINVAL;
4484
4485         switch (filter_type) {
4486         case RTE_ETH_FILTER_TUNNEL:
4487                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
4488                 break;
4489         default:
4490                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4491                                                         filter_type);
4492                 ret = -EINVAL;
4493                 break;
4494         }
4495
4496         return ret;
4497 }